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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073ca5219sm13729371f8f.27.2025.04.29.06.22.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 06:22:02 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH v2 1/7] target/microblaze: Use 'obj' in DEVICE() casts in mb_cpu_initfn() Date: Tue, 29 Apr 2025 14:21:54 +0100 Message-ID: <20250429132200.605611-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429132200.605611-1-peter.maydell@linaro.org> References: <20250429132200.605611-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We're about to make a change that removes the only other use of the 'cpu' local variable in mb_cpu_initfn(); since the DEVICE() casts work fine with the Object*, use that instead, so that we can remove the local variable when we make the following change. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson --- target/microblaze/cpu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 00a2730de4d..d92a43191bd 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -333,11 +333,11 @@ static void mb_cpu_initfn(Object *obj) #ifndef CONFIG_USER_ONLY /* Inbound IRQ and FIR lines */ - qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); - qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1); - qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1); - qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); - qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); + qdev_init_gpio_in(DEVICE(obj), microblaze_cpu_set_irq, 2); + qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_dp, "ns_axi_dp", 1); + qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_ip, "ns_axi_ip", 1); + qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); + qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); #endif /* Restricted 'endianness' property is equivalent of 'little-endian' */ From patchwork Tue Apr 29 13:21:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 885724 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp321322wrq; Tue, 29 Apr 2025 06:24:09 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVuMkkrWQsaqIQtgJV5d9Ka56m07lklS6VRZc7A9Y0ejS7mTUkwC5JW326lr0XFJdtxgul+Qw==@linaro.org X-Google-Smtp-Source: AGHT+IE+VTYLXSVj2BeC322Od1rvrJBlGteDYmdQwZGHX9nODO8oGOJdx1F51WKKA5Kfn6gMMVEK X-Received: by 2002:a05:620a:424f:b0:7b6:d273:9b4f with SMTP id af79cd13be357-7cabe4a76abmr527375985a.11.1745933049419; Tue, 29 Apr 2025 06:24:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745933049; cv=none; d=google.com; s=arc-20240605; b=ayYUZcQs3kfPxAUaJ1UQFzfyH6Qi1bkyjwcW84en8+KAMqfdw0heZ6hWWTawsZaISn livcDsjs8I+ZP3HQm4Md+hFvDhgm/8hWD+P+e0pcCFcG5k+jODeySc7v+BzPiW0Tx8/f yTpya3QAEP2e2FKULSu0R9qS4hMVQ7TsveVv6aLj3IEQz8WBEIFBhcmytdztbr5nBe3C iYhFlbawGJK3H4JpJE7epvcV6ctluzNZa7bTF9JWQz5X3EmKtXZry4I0cC64LIjGXTcX PQXKqEXkOnXESD4gLTSL2vSVjERgasH5Gpa+4VUmuxtZlxIvKy8oXEie+oYy8+hn0Mfm 1fWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1K2H3VE4tCQOLcXEpqGHsbFF7wzsGTavlqzL6DY4PxQ=; fh=Yux02oYTyJuF8nAmaWd/1nIp5ZFES5h4Vshc1JxIXVs=; b=EDlckUml1YBNRI1AYSlHj8uP4NbAH3vTBTUBE7MZTF2mmjkRwfFbFsX/QI7eADBzyY Pgn7zXF8kER/zZpzlMSKoNSRr5ZjcXzR/mSq1M+pQVI5K3Ng1HaxkvpiLFaK+KxefetE hyHu+pdDGMdRyW9QrnX/u2wZlUSUJ5cQZ9re5GM39bkyaK4lBFJOI0Z5KoBisCBN2uzL 11syLegMWIhkkFilOqXsE+g7X9mnWCdNLpHdErOEEgo6t36In7s9Xu/C9ZO6N3o0TKhG bWNa/wDhYXwTi6odPKir+ugYZr7Jfi8r3Xpug6qvq2NG/FgxoeF1+DEd2TpRYtAwX2vf tuhg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f5Qah+i3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073ca5219sm13729371f8f.27.2025.04.29.06.22.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 06:22:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH v2 2/7] target/microblaze: Delay gdb_register_coprocessor() to realize Date: Tue, 29 Apr 2025 14:21:55 +0100 Message-ID: <20250429132200.605611-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429132200.605611-1-peter.maydell@linaro.org> References: <20250429132200.605611-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently the microblaze code calls gdb_register_coprocessor() in its initfn. This works, but we would like to delay setting up GDB registers until realize. All other target architectures only call gdb_register_coprocessor() in realize, after the call to cpu_exec_realizefn(). Move the microblaze gdb_register_coprocessor() use, bringing it in line with other targets. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/microblaze/cpu.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index d92a43191bd..b8dae83ce0c 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -252,6 +252,11 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) return; } + gdb_register_coprocessor(cs, mb_cpu_gdb_read_stack_protect, + mb_cpu_gdb_write_stack_protect, + gdb_find_static_feature("microblaze-stack-protect.xml"), + 0); + qemu_init_vcpu(cs); version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION; @@ -324,13 +329,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) static void mb_cpu_initfn(Object *obj) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); - - gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect, - mb_cpu_gdb_write_stack_protect, - gdb_find_static_feature("microblaze-stack-protect.xml"), - 0); - #ifndef CONFIG_USER_ONLY /* Inbound IRQ and FIR lines */ qdev_init_gpio_in(DEVICE(obj), microblaze_cpu_set_irq, 2); From patchwork Tue Apr 29 13:21:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 885725 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp321825wrq; Tue, 29 Apr 2025 06:25:16 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWheSByCJa7BM11ndmg+WbVsHIpZ25p6BGQUcQKR1uA1hD8gOk6uVQK/FXai5jQ7vgBAMqyJA==@linaro.org X-Google-Smtp-Source: AGHT+IFsgVnURVLrDTPRpKDvzS3DRU6U9cv0hV+PIjXjN9QZvTfKCoFb7ZvJe79zkH64e0WObUuG X-Received: by 2002:a05:620a:24c3:b0:7c5:6b15:1483 with SMTP id af79cd13be357-7cabdd71b9emr564652885a.6.1745933115844; Tue, 29 Apr 2025 06:25:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745933115; cv=none; d=google.com; s=arc-20240605; b=QJpVMIDBJl47B2yM/+yeVCazsVT+2utx5ZAV+HB+Ycfp3myhMIkGdct1du4BaLijW1 srN5sbeR3ix2culIDcI4OH/I7Fd6pR3vKHbDYzfEooim8bducXxj2ZaCEaxw8K4UCop3 KL5Hzq6Cpt9rn2Y/ThAdzqM0uXWzOgPz+6b1Oj8tvYLcjQ5tm0bmc5i1I2ghAzCQTU4w kk5+IK4YI8MAunnsc6DG331V6TG89dNmc2YmL+k7ug8SiNM3LLlnEyNMulHpc7M0GQaD N24lsHyU8xjHxO+VYctpX7JuJp0AnVbfwjgn5xBNPhqnkGiD48EUakb3JbO3Jfq7+1AA zqkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=U0MilJhhj9cXGSYSZ37HStWvLOYbPls0FXWBsHGtjT4=; fh=nRN/HwZLv7p7vwbUbsQ3NLtY4n8ciXv+fZlCB9sP1S0=; b=iXyXNKC7ZE1s8EUw6lxGDzEB4JcYsqHfVJMilA9ElqCoef2fROqQltUiuZuzS8MaZI K9DVD71wGcAiJbmgmr+fivBZXriB6vzqhAWpxmRDpMDXHD9UKY/dJ3hknWMwmCbD3Lh7 wL/gjJ0Vv0+lSZCor6FruLVyopx9JVVKiH9lNTQvg3ivLRZhAKcSnSiqXe14F/WsHZq1 L4bM9FM+W7/COoimYRc+Rnm1DWsv39ereq5ka7q6YmPg4pjAzLdwt1/3pc4w9Z7MknaG 4zwGt0s+rG/r3enHL9QGMAbbIaDCshHcp7o7y/SdDVBxVPFM27oYU9WdTSukOufVp4LR bM9w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Gs5Zr8t/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073ca5219sm13729371f8f.27.2025.04.29.06.22.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 06:22:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH v2 3/7] hw/core/cpu-common: Don't init gdbstub until cpu_exec_realizefn() Date: Tue, 29 Apr 2025 14:21:56 +0100 Message-ID: <20250429132200.605611-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429132200.605611-1-peter.maydell@linaro.org> References: <20250429132200.605611-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently we call gdb_init_cpu() in cpu_common_initfn(), which is very early in the CPU object's init->realize creation sequence. In particular this happens before the architecture-specific subclass's init fn has even run. This means that gdb_init_cpu() can only do things that depend strictly on the class, not on the object, because the CPUState* that it is passed is currently half-initialized. In commit a1f728ecc90cf6c6 we accidentally broke this rule, by adding a call to the gdb_get_core_xml_file method which takes the CPUState. At the moment we get away with this because the only implementation doesn't actually look at the pointer it is passed. However the whole reason we created that method was so that we could make the "which XML file?" decision based on a property of the CPU object, and we currently can't change the Arm implementation of the method to do what we want without causing wrong behaviour or a crash. The ordering restrictions here are: * we must call gdb_init_cpu before: - any call to gdb_register_coprocessor() - any use of the gdb_num_regs field (this is only used in code that's about to call gdb_register_coprocessor() and wants to know the first register number of the set of registers it's about to add) * we must call gdb_init_cpu after CPU properties have been set, which is to say somewhere in realize The function cpu_exec_realizefn() meets both of these requirements, as it is called by the architecture-specific CPU realize function early in realize, before any calls ot gdb_register_coprocessor(). Move the gdb_init_cpu() call to there. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- hw/core/cpu-common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 92c40b6bf83..39e674aca21 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -234,6 +234,8 @@ bool cpu_exec_realizefn(CPUState *cpu, Error **errp) return false; } + gdb_init_cpu(cpu); + /* Wait until cpu initialization complete before exposing cpu. */ cpu_list_add(cpu); @@ -304,7 +306,6 @@ static void cpu_common_initfn(Object *obj) /* cache the cpu class for the hotpath */ cpu->cc = CPU_GET_CLASS(cpu); - gdb_init_cpu(cpu); cpu->cpu_index = UNASSIGNED_CPU_INDEX; cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX; cpu->as = NULL; From patchwork Tue Apr 29 13:21:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 885722 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp321246wrq; Tue, 29 Apr 2025 06:24:00 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUjMsb8UrydcGmheS0OA4rOCBnczYpIFzJrJgk+R9gwvWi4QYYlAKtZCpk9EdryOIGQ45kTdQ==@linaro.org X-Google-Smtp-Source: AGHT+IG2ih666aEh0pyi6i/3C3HJMXoTZaXhEdoHlM6yi/6M1Vv16H0VW7UgWBwkiCMmh5Lfc6VF X-Received: by 2002:a05:622a:58c3:b0:476:75d0:a1e1 with SMTP id d75a77b69052e-488124cb727mr50428941cf.9.1745933039717; Tue, 29 Apr 2025 06:23:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745933039; cv=none; d=google.com; s=arc-20240605; b=LlD4h2z3A/axgcM2zWOlhQpddRG5EJY0ZqJMwnBQeXPJRiW33J71FO4gvspqoKBnLd HnvGCvE661TKul5dBfnNVAQIoUFHcHKYIAB/XssNdfb13WWE9dIXf+fB2RkR02mMmAGk Gl6rvMaQH5jImII13to3mJy3ZmcPyDqXPteEnjcTc5ns0F1UN36kNAvvrgUVQY69cqMS qQoK7yr3itpb7A1JpGOxXz5mHoGLlybHDFcuaXPNPLsNlqGosgiKyA+EYmc6OabwVvC4 sN+I+KBDIYAoDOlef5LxTThtYKTK9Lu6NTUH8r/GQjZ6dlzB7kEy4m18R4025NJDzjhN vCqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PW9jN2yS/TAOGn5xgs3qpwNb9whA0g2Y1AVjroSf5VQ=; fh=Jf09H9I4VaHbgN8mQ13fIEtUNqkBvOSdRrW68i91mfA=; b=ccDNRUSEpTn26cynN3x/mqp7EktzAMW66QbNpY+fi9jQyZSwek4PejDLv0XZVtK7oQ c/JNRk99SD0fZwP2j1hUcvUIMZkip3DC3C0Wqkn3qhRsqVUO8PBZbdN/rIKEiJWc3p7Y F2q+54wKaY55sXsLWMSCirD85E/PCQC7zen4/XgVP9DY38vn+aSsm8pF4RFdEGafbIiF FT7fyywaOBIMF0knv8Ei+wXPK3ZiNqs9+73nosWbNLK09zkLbMDP5+Azd6cKMXTgTTgu QJ8/0WK5MXoQDio+toU332ktxy4jZ74Z7sXYYrAz94I7yH/VSr9ZqThUNdU9nHkGzwBo Nq1Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=olAB2tiG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073ca5219sm13729371f8f.27.2025.04.29.06.22.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 06:22:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH v2 4/7] target/arm: Present AArch64 gdbstub based on ARM_FEATURE_AARCH64 Date: Tue, 29 Apr 2025 14:21:57 +0100 Message-ID: <20250429132200.605611-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429132200.605611-1-peter.maydell@linaro.org> References: <20250429132200.605611-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently we provide an AArch64 gdbstub for CPUs which are TYPE_AARCH64_CPU, and an AArch32 gdbstub for those which are only TYPE_ARM_CPU. This mostly does the right thing, except in the corner case of KVM with -cpu host,aarch64=off. That produces a CPU which is TYPE_AARCH64_CPU but which has ARM_FEATURE_AARCH64 removed and which to the guest is in AArch32 mode. Now we have moved all the handling of AArch64-vs-AArch32 gdbstub behaviour into TYPE_ARM_CPU we can change the condition we use for whether to select the AArch64 gdbstub to look at ARM_FEATURE_AARCH64. This will mean that we now correctly provide an AArch32 gdbstub for aarch64=off CPUs. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/internals.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 4d3d84ffebd..f1c06a3fd89 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1831,7 +1831,7 @@ void aarch64_add_sme_properties(Object *obj); /* Return true if the gdbstub is presenting an AArch64 CPU */ static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu) { - return object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU); + return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); } /* Read the CONTROL register as the MRS instruction would. */ From patchwork Tue Apr 29 13:21:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 885723 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp321284wrq; Tue, 29 Apr 2025 06:24:04 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUBi2JS6vR0zv0bSaKaqeN+Ak5ZJrga2IsQuWIXL+DOLt1tBtlLBiDTv8LnKJ+J6/yz6K5EHg==@linaro.org X-Google-Smtp-Source: AGHT+IHtQGjEoNRDNb85frhClArRQdX0HfkefpBKsDoq1j0AGc0UdpyU/mcKuABut7E3tGIss85j X-Received: by 2002:a05:620a:4710:b0:7c5:47c6:b888 with SMTP id af79cd13be357-7c9668c1e18mr2206110985a.40.1745933044186; Tue, 29 Apr 2025 06:24:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745933044; cv=none; d=google.com; s=arc-20240605; b=XXAcXBPdiqrEYQ90G75QkyMGgKmX5xu7v/FFXffTDAZFt/j1BBvyewprIkg1uEfyBi HkeBA7NRL6KS/nZSOnFxiC0DNy866U9F7mPANGwJd2QDP+Z8Uz22XGaeV+vb8mHBQKWl XMJwP6+DTj/hxLTq9uO37rBiHAuzbmxgjjO87SrelolvVKKZ+j0Fe/1OoJbYvBZAdAXP UtDEV9tlcuHNtEmydMFV8dO7AQzqfTqS0vG/A3WMu1CmRsD3ENkviK3/wgLEt4dBUWYh YSHe0dO3P+nwxMm1awIwq8IQe7reW6SzfgdvfH2C8Dig8UY4XF0+7SEl3GwRutuqQwoz l43A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DjSG1O4sqyvihfU4YBjpfGe20pFEFSZo62gLO5k4z4k=; fh=tTs/+Q/9VapTPyRNUBfitoxynJgLFWMl03vJGZls8JI=; b=lv6qIO8LDkivSfu50c+lGeykMqN9+zn1V7MB3O7paEOr03UiVkJHdK+oe6Ixk2mUei 5RY3FV5/DOp1u2InamVXLrONzPsQq6ikNhDWGZCNwVfvthPUFpUu/RrhCOxor44Mk9Ig ssB8PRo4VJ4qZot+Jn6NrZ8tK0JzVDhqqCvzSPIlW1K9HvQrcegY0hxzdmHrj/wvsWPK 5vJjJI4RFrf/vghArDygOXuWdWhKwXnos91Kh1ZCFRo/FeXGqFy4ysJrUjiIahRwPPe7 NyIg3tIQ0SrjNsX3olxakw2WB4xhlDRYJI812CQLbrZB0fnd8kE8aaTIKB0+kcMNUZD2 JyzQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SzhdpLNC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073ca5219sm13729371f8f.27.2025.04.29.06.22.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 06:22:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH v2 5/7] target/arm: Move aarch64 CPU property code to TYPE_ARM_CPU Date: Tue, 29 Apr 2025 14:21:58 +0100 Message-ID: <20250429132200.605611-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429132200.605611-1-peter.maydell@linaro.org> References: <20250429132200.605611-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The only thing we have left in the TYPE_AARCH64_CPU class that makes it different to TYPE_ARM_CPU is that we register the handling of the "aarch64" property there. Move the handling of this property to the base class, where we make it a property of the object rather than of the class, and add it to the CPU if it has the ARM_FEATURE_AARCH64 property present at init. This is in line with how we handle other Arm CPU properties, and should not change which CPUs it's visible for. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpu.c | 36 ++++++++++++++++++++++++++++++++++++ target/arm/cpu64.c | 33 --------------------------------- 2 files changed, 36 insertions(+), 33 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5e951675c60..73a2a197667 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1610,6 +1610,35 @@ static void arm_set_pmu(Object *obj, bool value, Error **errp) cpu->has_pmu = value; } +static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); +} + +static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + /* + * At this time, this property is only allowed if KVM is enabled. This + * restriction allows us to avoid fixing up functionality that assumes a + * uniform execution state like do_interrupt. + */ + if (value == false) { + if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { + error_setg(errp, "'aarch64' feature cannot be disabled " + "unless KVM is enabled and 32-bit EL1 " + "is supported"); + return; + } + unset_feature(&cpu->env, ARM_FEATURE_AARCH64); + } else { + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + } +} + unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) { /* @@ -1737,6 +1766,13 @@ void arm_cpu_post_init(Object *obj) */ arm_cpu_propagate_feature_implications(cpu); + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, + aarch64_cpu_set_aarch64); + object_property_set_description(obj, "aarch64", + "Set on/off to enable/disable aarch64 " + "execution state "); + } if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 00629a5d1d1..e527465a3ca 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -781,45 +781,12 @@ static const ARMCPUInfo aarch64_cpus[] = { #endif }; -static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) -{ - ARMCPU *cpu = ARM_CPU(obj); - - return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); -} - -static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) -{ - ARMCPU *cpu = ARM_CPU(obj); - - /* At this time, this property is only allowed if KVM is enabled. This - * restriction allows us to avoid fixing up functionality that assumes a - * uniform execution state like do_interrupt. - */ - if (value == false) { - if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { - error_setg(errp, "'aarch64' feature cannot be disabled " - "unless KVM is enabled and 32-bit EL1 " - "is supported"); - return; - } - unset_feature(&cpu->env, ARM_FEATURE_AARCH64); - } else { - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - } -} - static void aarch64_cpu_finalizefn(Object *obj) { } static void aarch64_cpu_class_init(ObjectClass *oc, const void *data) { - object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, - aarch64_cpu_set_aarch64); - object_class_property_set_description(oc, "aarch64", - "Set on/off to enable/disable aarch64 " - "execution state "); } static void aarch64_cpu_instance_init(Object *obj) From patchwork Tue Apr 29 13:21:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 885721 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp321193wrq; Tue, 29 Apr 2025 06:23:51 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWEeRg9g6agjcTgE43XinvPb0YGP6pLIBs8B7Ikg/vUY/TwBOiHwFb7CBQLhJwq02COjASLdQ==@linaro.org X-Google-Smtp-Source: AGHT+IE5IWBQCp0TixcOzm5HzVNnktrHEbBiIu+GgHK7F4f6MUj4mFkovTf/HocodI2sVUB4akNb X-Received: by 2002:ad4:5769:0:b0:6e8:903c:6e5b with SMTP id 6a1803df08f44-6f4f1b9a5c4mr48526026d6.9.1745933031617; Tue, 29 Apr 2025 06:23:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745933031; cv=none; d=google.com; s=arc-20240605; b=SSkVgCN99SX617pOjl9hgoRnKLLcKhkn0utT0y9xj5J95nPZiYCSrrgnZKWYmd+lrr 2cRvJnSS2lE1yy0i/tzOAvhA0qSk9Jo/wVaX0VIdRaHtKQZkp/HAVyN3nxzecjutrin8 83wLZId4m3aAM3PtUzwOSL9o1peLNkpnAaDQxl/DtHTmNizRVWXRkSCqu9i/mwG2d8D9 6nP2TYXyL8yukmCvost0e+TFmZabvbx1lGPStX72qYI2l+2MtQmsWtyx+Wtla6Q1IW+d SzNa0jFOxV90mLJ+FayHlKIKHP+mUla8+Xywz15D6Qk/e+kzr7HbFURPS0Mmvk2dcSwl 5c+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mr1QFeW43XnVmNc1okA19chi54m5Uhrocgufe8XGZeE=; fh=C6u+p2+vyrXPLm/zylHizVgAVQYXVoLn07diVK2RKS8=; b=MB0PjZnSpIq7ZI06ZQNRZRGYGkUlDVZMfthkumYyFNmHGyWB3HVh/ALyYmf180ZNLD AhGsSr9ODUhc3qM0T4doUQ6ftbt6hb6fsrayJ99dN1Vt+ZS92Upjgcqnt26TdO6bhwEd j4Drc11ocKCtkSNKajV9E10narKd1vJO+yGzLyHI1+o2lsnp3/0cPx/H7ssp1UtTlJJV dVrvDcX8MzX2ZHwO7y8zXUE7Ogrbc42jLj6/JcNKyYPbNd8yGoBx9Da2Gn16Lku6LuNR cXZzwrCi4NEWuxl00s4BWaVg6y6WZYYir5jkRNN+ABsZMFY0zxfx6Vv0fw2scBiXIHDh wZzA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Fimfy1hZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073ca5219sm13729371f8f.27.2025.04.29.06.22.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 06:22:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH v2 6/7] target/arm/kvm: don't check TYPE_AARCH64_CPU Date: Tue, 29 Apr 2025 14:21:59 +0100 Message-ID: <20250429132200.605611-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429132200.605611-1-peter.maydell@linaro.org> References: <20250429132200.605611-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We want to merge TYPE_AARCH64_CPU with TYPE_ARM_CPU, so enforcing in kvm_arch_init_vcpu() that the CPU class is a subclass of TYPE_AARCH64_CPU will no longer be possible. It's safe to just remove this test, because any purely-AArch32 CPU will fail the "kvm_target isn't set" check, because we no longer support the old AArch32-host KVM setup and so CPUs like the Cortex-A7 no longer set cpu->kvm_target. Only the 'host', 'max', and the odd special cases 'cortex-a53' and 'cortex-a57' set kvm_target. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/kvm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 97de8c7e939..6b2c788e0fa 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1882,8 +1882,7 @@ int kvm_arch_init_vcpu(CPUState *cs) CPUARMState *env = &cpu->env; uint64_t psciver; - if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE || - !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) { + if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) { error_report("KVM is not supported for this guest CPU type"); return -EINVAL; } From patchwork Tue Apr 29 13:22:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 885720 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:38f:210b:807b with SMTP id g4csp321131wrq; Tue, 29 Apr 2025 06:23:43 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVJ6VYZfIM7uVbbCgIMde4H3J8bFszz2qoSyNoWZWU7vL/X2SS1UjqiUWPlaVWioyCndKcVuQ==@linaro.org X-Google-Smtp-Source: AGHT+IGVdYvi4PRshlNhWOeA8Kcmi6ljfjrUkUEozaEUSjAt+fyJIGli4SUCUdpx4jOWfHrfvDFw X-Received: by 2002:a67:ffc5:0:b0:4c1:492a:d75b with SMTP id ada2fe7eead31-4da9434d4f0mr1685732137.2.1745933022860; Tue, 29 Apr 2025 06:23:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745933022; cv=none; d=google.com; s=arc-20240605; b=e4ODzODz75fUjgaPAmK52ooR3BKxH6Lx6qqOkZkZ8YmrnzVkRhKo5ECtfQFjbrjLN9 nBVIBNqZGQVmMlYFeGdRyRYHJeZlh8hinkh6JrUiSNiju0YFoXDfZ9aGn6hf3ZFn41Xu TgZLJV9ZEM3rQkeTrIr9KSSTf2U364eTXae2NLZpnEDbt4tZ8YG17k1Sqi1EhqiCgYOr LmbFGzENYi8u2OYQwwdhI8fUwMev0FrDgU1aW9OfItIGMNl611oUTEThrIQpss2mqNKP cxRB4PkVLy+i2HeyatPiVmxeTiKdeUs7TGKR4d9Kw00EfzIWVg/tZfQSrkhEkI3SBpWT 13Gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1ZwkigIUy0IIiAszFNbLpeUVLw4uBqn4OmPKEQckEf8=; fh=tk5MvO++wjoOhIPJ/I6GWQW5HAoqClvmen94l0rKdb4=; b=LJ3ZDqG5oAfiZ05YnJzNIX7ovx8TaiEd//SO5keL7v71v20nTdzp55bpdbfW+482dn ItRpc9s/1p5mlVVmu6S/30ymsvovgtbLwxWyOeo9cV+t8JIO5n1MkNUyarmGrsCitGUl X4XHyKbMhgehpOmRthtpVq4pDjjM8uqiVTlNfySne5U0Bb6Qi5lNMFccvBlJNDHLsxhv 9RvGod6keuG+LuZS9moh+4/ye7tbg8UuBd9QN4YqqC1zYhKOWMV8H5CwiUuV5HvmKnaB rT41i9vL62fimguJyhHioE4Q3iGAhmxCqGzVBYf+OKYf8Hev3ydk+nQxv61ILcYRGNk9 8LtA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OebY71w+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073ca5219sm13729371f8f.27.2025.04.29.06.22.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 06:22:08 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH v2 7/7] target/arm: Remove TYPE_AARCH64_CPU Date: Tue, 29 Apr 2025 14:22:00 +0100 Message-ID: <20250429132200.605611-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429132200.605611-1-peter.maydell@linaro.org> References: <20250429132200.605611-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The TYPE_AARCH64_CPU class is an abstract type that is the parent of all the AArch64 CPUs. It now has no special behaviour of its own, so we can eliminate it and make the AArch64 CPUs directly inherit from TYPE_ARM_CPU. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpu-qom.h | 5 ----- target/arm/cpu.h | 4 ---- target/arm/internals.h | 1 - target/arm/cpu64.c | 49 +----------------------------------------- target/arm/tcg/cpu64.c | 2 +- 5 files changed, 2 insertions(+), 59 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index b497667d61e..2fcb0e12525 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -28,11 +28,6 @@ OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU) #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU -#define TYPE_AARCH64_CPU "aarch64-cpu" -typedef struct AArch64CPUClass AArch64CPUClass; -DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, - TYPE_AARCH64_CPU) - #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fdcf8cd1ae0..a394c7d46d7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1141,10 +1141,6 @@ struct ARMCPUClass { ResettablePhases parent_phases; }; -struct AArch64CPUClass { - ARMCPUClass parent_class; -}; - /* Callback functions for the generic timer's timers. */ void arm_gt_ptimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque); diff --git a/target/arm/internals.h b/target/arm/internals.h index f1c06a3fd89..7be34388fc2 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -353,7 +353,6 @@ static inline int r14_bank_number(int mode) } void arm_cpu_register(const ARMCPUInfo *info); -void aarch64_cpu_register(const ARMCPUInfo *info); void register_cp_regs_for_features(ARMCPU *cpu); void init_cpreg_list(ARMCPU *cpu); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e527465a3ca..200da1c489b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -781,59 +781,12 @@ static const ARMCPUInfo aarch64_cpus[] = { #endif }; -static void aarch64_cpu_finalizefn(Object *obj) -{ -} - -static void aarch64_cpu_class_init(ObjectClass *oc, const void *data) -{ -} - -static void aarch64_cpu_instance_init(Object *obj) -{ - ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); - - acc->info->initfn(obj); - arm_cpu_post_init(obj); -} - -static void cpu_register_class_init(ObjectClass *oc, const void *data) -{ - ARMCPUClass *acc = ARM_CPU_CLASS(oc); - - acc->info = data; -} - -void aarch64_cpu_register(const ARMCPUInfo *info) -{ - TypeInfo type_info = { - .parent = TYPE_AARCH64_CPU, - .instance_init = aarch64_cpu_instance_init, - .class_init = info->class_init ?: cpu_register_class_init, - .class_data = info, - }; - - type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); - type_register_static(&type_info); - g_free((void *)type_info.name); -} - -static const TypeInfo aarch64_cpu_type_info = { - .name = TYPE_AARCH64_CPU, - .parent = TYPE_ARM_CPU, - .instance_finalize = aarch64_cpu_finalizefn, - .abstract = true, - .class_init = aarch64_cpu_class_init, -}; - static void aarch64_cpu_register_types(void) { size_t i; - type_register_static(&aarch64_cpu_type_info); - for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { - aarch64_cpu_register(&aarch64_cpus[i]); + arm_cpu_register(&aarch64_cpus[i]); } } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 29ab0ac79da..5d8ed2794d3 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1316,7 +1316,7 @@ static void aarch64_cpu_register_types(void) size_t i; for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { - aarch64_cpu_register(&aarch64_cpus[i]); + arm_cpu_register(&aarch64_cpus[i]); } }