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Fri, 25 Apr 2025 06:27:51 -0700 (PDT) Received: from localhost.localdomain ([110.44.101.8]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309f7752a03sm1564313a91.18.2025.04.25.06.27.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 06:27:51 -0700 (PDT) From: Anand Moon To: Chanwoo Choi , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alim Akhtar , linux-kernel@vger.kernel.org (open list:MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BO...), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-samsung-soc@vger.kernel.org (open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES) Cc: Anand Moon Subject: [PATCH v1 01/10] dt-bindings: clock: Add RTC clock binding for Maxim MAX77686 Date: Fri, 25 Apr 2025 18:56:21 +0530 Message-ID: <20250425132727.5160-2-linux.amoon@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250425132727.5160-1-linux.amoon@gmail.com> References: <20250425132727.5160-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add device tree schema for the RTC clock in the Maxim MAX77686 family of PMICs. This binding defines the 32k clock generator block, which includes three 32.768kHz crystal clock outputs controllable via I2C. The detailed binding information can be found in the MFD DT binding documentation at bindings/mfd/maxim,max77686.yaml. Signed-off-by: Anand Moon --- .../bindings/clock/maxim,max77686.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/maxim,max77686.yaml diff --git a/Documentation/devicetree/bindings/clock/maxim,max77686.yaml b/Documentation/devicetree/bindings/clock/maxim,max77686.yaml new file mode 100644 index 000000000000..72f11309f033 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/maxim,max77686.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/maxim,max77686.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX77686 family clock generator block + +maintainers: + - Anand Moon + +description: | + Binding for Maxim MAX77686 32k clock generator block + + This is a part of device tree bindings of MAX77686 multi-function + device. More information can be found in MFD DT binding + doc as follows: + bindings/mfd/maxim,max77686.yaml for MAX77686 + + The MAX77686 contains three 32.768khz crystal clock outputs that can + be controlled (gated/ungated) over I2C. Clocks are defined as + preprocessor macros in dt-bindings/clock/maxim,max77686.h. + +properties: + compatible: + enum: + - max77686-rtc + + "#clock-cells": + const: 1 + + clock-output-names: + maxItems: 3 + description: Names for AP, CP and BT clocks. + +required: + - compatible + - "#clock-cells" + +additionalProperties: false + +examples: + - | + max77686_osc: clocks { + compatible = "max77686-rtc"; + #clock-cells = <1>; + clock-output-names = "32khz_ap", "32khz_cp", "32khz_pmic"; + }; From patchwork Fri Apr 25 13:26:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 884720 Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE21424E4A4; Fri, 25 Apr 2025 13:28:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 25 Apr 2025 06:28:00 -0700 (PDT) Received: from localhost.localdomain ([110.44.101.8]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309f7752a03sm1564313a91.18.2025.04.25.06.27.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 06:28:00 -0700 (PDT) From: Anand Moon To: Chanwoo Choi , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alim Akhtar , linux-kernel@vger.kernel.org (open list:MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BO...), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-samsung-soc@vger.kernel.org (open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES) Cc: Anand Moon Subject: [PATCH v1 02/10] ARM: dts: exynos: Add rtc clock definitions for MAX77686 PMIC for Exynos4412 Odroid Date: Fri, 25 Apr 2025 18:56:22 +0530 Message-ID: <20250425132727.5160-3-linux.amoon@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250425132727.5160-1-linux.amoon@gmail.com> References: <20250425132727.5160-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The MAX77686A includes a crystal driver with an external load capacitance. When enabled, the crystal driver starts in low power mode. The LowJitterMode bit controls the crystal driver, allowing it to switch between low power mode and low jitter mode (high power mode). Setting the LowJitterMode bit to 1 activates low jitter mode on three channels simultaneously. These three 32khz buffer outputs (32KHAP, 32KHCP, P32KH) are independently enabled/disabled over I2C. The 32khz_ap output is typically routed to the AP Processor, while the 32khz_cp and 32khz_pmic outputs are intended for BT, WLAN, BB, or peripheral chipsets. Signed-off-by: Anand Moon --- arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi index 93ddbd4b0a18..03943c666d11 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi @@ -289,6 +289,13 @@ max77686: pmic@9 { reg = <0x09>; #clock-cells = <1>; + max77686_osc: clocks { + compatible = "max77686-rtc"; + #clock-cells = <1>; + clock-output-names = "32khz_ap", + "32khz_cp", "32khz_pmic"; + }; + voltage-regulators { ldo1_reg: LDO1 { regulator-name = "VDD_ALIVE_1.0V"; From patchwork Fri Apr 25 13:26:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 885399 Received: from mail-pg1-f170.google.com (mail-pg1-f170.google.com [209.85.215.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D01BC2528E5; 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Fri, 25 Apr 2025 06:28:09 -0700 (PDT) Received: from localhost.localdomain ([110.44.101.8]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309f7752a03sm1564313a91.18.2025.04.25.06.28.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 06:28:09 -0700 (PDT) From: Anand Moon To: Chanwoo Choi , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alim Akhtar , linux-kernel@vger.kernel.org (open list:MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BO...), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-samsung-soc@vger.kernel.org (open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES) Cc: Anand Moon Subject: [PATCH v1 03/10] ARM: dts: exynos: Add proper regulator states for suspend-to-mem for Exynos4412 Odroid Date: Fri, 25 Apr 2025 18:56:23 +0530 Message-ID: <20250425132727.5160-4-linux.amoon@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250425132727.5160-1-linux.amoon@gmail.com> References: <20250425132727.5160-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 MAX77686 PMCI is able to power down and up key core supplies and other voltage rails via PWRREQ signal to enter / exit (deep) sleep mode. PWRREQ status is ignored during initial power up and down processes. All programming must be done before the AP enterns the sleep mode by pulling PWRREQ low since the AP does not have programming capability in (deep) sleep mode. Add suspend-to-mem node to regulator core to be enabled or disabled during system suspend and also support changing the regulator operating mode during runtime and when the system enter sleep mode (stand by mode). Regulators which can be turned off during system suspend: -LDOn : 2, 6-8, 10-12, 14-16, -BUCKn : 1-4. Use standard regulator bindings for it ('regulator-off-in-suspend'). Signed-off-by: Anand Moon --- .../dts/samsung/exynos4412-odroid-common.dtsi | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi index 03943c666d11..3837e038c266 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi @@ -309,6 +309,10 @@ ldo2_reg: LDO2 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo3_reg: LDO3 { @@ -338,6 +342,10 @@ ldo6_reg: LDO6 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo7_reg: LDO7 { @@ -345,18 +353,30 @@ ldo7_reg: LDO7 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo8_reg: LDO8 { regulator-name = "VDD10_HDMI_1.0V"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo10_reg: LDO10 { regulator-name = "VDDQ_MIPIHSI_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo11_reg: LDO11 { @@ -364,6 +384,10 @@ ldo11_reg: LDO11 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo12_reg: LDO12 { @@ -372,6 +396,10 @@ ldo12_reg: LDO12 { regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo13_reg: LDO13 { @@ -388,6 +416,10 @@ ldo14_reg: LDO14 { regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo15_reg: LDO15 { @@ -396,6 +428,10 @@ ldo15_reg: LDO15 { regulator-max-microvolt = <1000000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo16_reg: LDO16 { @@ -404,6 +440,10 @@ ldo16_reg: LDO16 { regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo20_reg: LDO20 { @@ -442,6 +482,10 @@ buck1_reg: BUCK1 { regulator-max-microvolt = <1100000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck2_reg: BUCK2 { @@ -450,6 +494,10 @@ buck2_reg: BUCK2 { regulator-max-microvolt = <1350000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck3_reg: BUCK3 { @@ -458,6 +506,10 @@ buck3_reg: BUCK3 { regulator-max-microvolt = <1050000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck4_reg: BUCK4 { @@ -465,6 +517,10 @@ buck4_reg: BUCK4 { regulator-min-microvolt = <900000>; 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Fri, 25 Apr 2025 06:28:18 -0700 (PDT) Received: from localhost.localdomain ([110.44.101.8]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309f7752a03sm1564313a91.18.2025.04.25.06.28.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 06:28:18 -0700 (PDT) From: Anand Moon To: Chanwoo Choi , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alim Akhtar , linux-kernel@vger.kernel.org (open list:MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BO...), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-samsung-soc@vger.kernel.org (open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES) Cc: Anand Moon Subject: [PATCH v1 04/10] ARM: dts: exynos: Add rtc clock definitions for MAX77686 PMIC for Exynos4412 Midas Date: Fri, 25 Apr 2025 18:56:24 +0530 Message-ID: <20250425132727.5160-5-linux.amoon@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250425132727.5160-1-linux.amoon@gmail.com> References: <20250425132727.5160-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The MAX77686A includes a crystal driver with an external load capacitance. When enabled, the crystal driver starts in low power mode. The LowJitterMode bit controls the crystal driver, allowing it to switch between low power mode and low jitter mode (high power mode). Setting the LowJitterMode bit to 1 activates low jitter mode on three channels simultaneously. These three 32khz buffer outputs (32KHAP, 32KHCP, P32KH) are independently enabled/disabled over I2C. The 32khz_ap output is typically routed to the AP Processor, while the 32khz_cp and 32khz_pmic outputs are intended for BT, WLAN, BB, or peripheral chipsets. Signed-off-by: Anand Moon --- arch/arm/boot/dts/samsung/exynos4412-midas.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi b/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi index 3d5aace668dc..ad2c7ebfdc41 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi @@ -729,6 +729,13 @@ max77686: pmic@9 { reg = <0x09>; #clock-cells = <1>; + max77686_osc: clocks { + compatible = "max77686-rtc"; + #clock-cells = <1>; + clock-output-names = "32khz_ap", + "32khz_cp", "32khz_pmic"; + }; + voltage-regulators { ldo1_reg: LDO1 { regulator-name = "VALIVE_1.0V_AP"; From patchwork Fri Apr 25 13:26:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 885398 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE309253958; 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Fri, 25 Apr 2025 06:28:27 -0700 (PDT) Received: from localhost.localdomain ([110.44.101.8]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309f7752a03sm1564313a91.18.2025.04.25.06.28.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 06:28:27 -0700 (PDT) From: Anand Moon To: Chanwoo Choi , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alim Akhtar , linux-kernel@vger.kernel.org (open list:MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BO...), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-samsung-soc@vger.kernel.org (open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES) Cc: Anand Moon Subject: [PATCH v1 05/10] ARM: dts: exynos: Add rtc clock definitions for MAX77686 PMIC for Exynos4412 p4note Date: Fri, 25 Apr 2025 18:56:25 +0530 Message-ID: <20250425132727.5160-6-linux.amoon@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250425132727.5160-1-linux.amoon@gmail.com> References: <20250425132727.5160-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The MAX77686A includes a crystal driver with an external load capacitance. When enabled, the crystal driver starts in low power mode. The LowJitterMode bit controls the crystal driver, allowing it to switch between low power mode and low jitter mode (high power mode). Setting the LowJitterMode bit to 1 activates low jitter mode on three channels simultaneously. These three 32khz buffer outputs (32KHAP, 32KHCP, P32KH) are independently enabled/disabled over I2C. The 32khz_ap output is typically routed to the AP Processor, while the 32khz_cp and 32khz_pmic outputs are intended for BT, WLAN, BB, or peripheral chipsets. Signed-off-by: Anand Moon --- arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi b/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi index 28a605802733..ad0abe8d9e30 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi @@ -432,6 +432,13 @@ max77686: pmic@9 { reg = <0x09>; #clock-cells = <1>; + max77686_osc: clocks { + compatible = "max77686-rtc"; + #clock-cells = <1>; + clock-output-names = "32khz_ap", + "32khz_cp", "32khz_pmic"; + }; + voltage-regulators { ldo1_reg: LDO1 { regulator-name = "ldo1"; From patchwork Fri Apr 25 13:26:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 884718 Received: from mail-pj1-f44.google.com (mail-pj1-f44.google.com [209.85.216.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5C0B2522B8; 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Fri, 25 Apr 2025 06:28:36 -0700 (PDT) Received: from localhost.localdomain ([110.44.101.8]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309f7752a03sm1564313a91.18.2025.04.25.06.28.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 06:28:36 -0700 (PDT) From: Anand Moon To: Chanwoo Choi , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alim Akhtar , linux-kernel@vger.kernel.org (open list:MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BO...), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-samsung-soc@vger.kernel.org (open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES) Cc: Anand Moon Subject: [PATCH v1 06/10] ARM: dts: exynos: Update proper regulator states for suspend-to-mem for Exynos4412 p4node Date: Fri, 25 Apr 2025 18:56:26 +0530 Message-ID: <20250425132727.5160-7-linux.amoon@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250425132727.5160-1-linux.amoon@gmail.com> References: <20250425132727.5160-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The MAX77686 PMCI is able to power down and up key core supplies and other voltage rails via PWRREQ signal to enter / exit (deep) sleep mode. PWRREQ status is ignored during initial power up and down processes. All programming must be done before the AP enterns the sleep mode by pulling PWRREQ low since the AP does not have programming capability in (deep) sleep mode. Update few regulator node with support suspend-to-mem node to regulator. dropped suspend-to-mem as MAX77686 do not support these. Regulators which can be turned off during system suspend: -LDOn : 2, 6-8, 10-12, 14-16, -BUCKn : 1-4. Use standard regulator bindings for it ('regulator-off-in-suspend'). Signed-off-by: Anand Moon --- .../boot/dts/samsung/exynos4412-p4note.dtsi | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi b/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi index ad0abe8d9e30..d0ecb1c6a922 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi @@ -448,6 +448,10 @@ ldo1_reg: LDO1 { ldo2_reg: LDO2 { regulator-name = "ldo2"; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; /* WM8994 audio */ @@ -457,10 +461,6 @@ ldo3_reg: LDO3 { regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; }; ldo4_reg: LDO4 { @@ -472,20 +472,24 @@ ldo5_reg: LDO5 { regulator-name = "VCC_1.8V_IO"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; }; ldo6_reg: LDO6 { regulator-name = "ldo6"; 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Fri, 25 Apr 2025 06:28:45 -0700 (PDT) Received: from localhost.localdomain ([110.44.101.8]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309f7752a03sm1564313a91.18.2025.04.25.06.28.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 06:28:45 -0700 (PDT) From: Anand Moon To: Chanwoo Choi , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alim Akhtar , linux-kernel@vger.kernel.org (open list:MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BO...), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-samsung-soc@vger.kernel.org (open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES) Cc: Anand Moon Subject: [PATCH v1 07/10] ARM: dts: exynos: Add rtc clock definitions for MAX77686 PMIC for Exynos5250 smdk5250 Date: Fri, 25 Apr 2025 18:56:27 +0530 Message-ID: <20250425132727.5160-8-linux.amoon@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250425132727.5160-1-linux.amoon@gmail.com> References: <20250425132727.5160-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The MAX77686A includes a crystal driver with an external load capacitance. When enabled, the crystal driver starts in low power mode. The LowJitterMode bit controls the crystal driver, allowing it to switch between low power mode and low jitter mode (high power mode). Setting the LowJitterMode bit to 1 activates low jitter mode on three channels simultaneously. These three 32khz buffer outputs (32KHAP, 32KHCP, P32KH) are independently enabled/disabled over I2C. The 32khz_ap output is typically routed to the AP Processor, while the 32khz_cp and 32khz_pmic outputs are intended for BT, WLAN, BB, or peripheral chipsets. Signed-off-by: Anand Moon --- arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts b/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts index bb623726ef1e..d41409019671 100644 --- a/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts @@ -145,6 +145,13 @@ max77686: pmic@9 { #clock-cells = <1>; wakeup-source; + max77686_osc: clocks { + compatible = "max77686-rtc"; + #clock-cells = <1>; + clock-output-names = "32khz_ap", + "32khz_cp", "32khz_pmic"; + }; + voltage-regulators { ldo1_reg: LDO1 { regulator-name = "P1.0V_LDO_OUT1"; From patchwork Fri Apr 25 13:26:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 884717 Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE975253F2D; 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Fri, 25 Apr 2025 06:28:54 -0700 (PDT) Received: from localhost.localdomain ([110.44.101.8]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309f7752a03sm1564313a91.18.2025.04.25.06.28.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 06:28:54 -0700 (PDT) From: Anand Moon To: Chanwoo Choi , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alim Akhtar , linux-kernel@vger.kernel.org (open list:MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BO...), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-samsung-soc@vger.kernel.org (open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES) Cc: Anand Moon Subject: [PATCH v1 08/10] ARM: dts: exynos: Add proper regulator states for suspend-to-mem for Exyno5250 smdk5250 Date: Fri, 25 Apr 2025 18:56:28 +0530 Message-ID: <20250425132727.5160-9-linux.amoon@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250425132727.5160-1-linux.amoon@gmail.com> References: <20250425132727.5160-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The MAX77686 PMCI is able to power down and up key core supplies and other voltage rails via PWRREQ signal to enter / exit (deep) sleep mode. PWRREQ status is ignored during initial power up and down processes. All programming must be done before the AP enterns the sleep mode by pulling PWRREQ low since the AP does not have programming capability in (deep) sleep mode. Add suspend-to-mem node to regulator core to be enabled or disabled during system suspend and also support changing the regulator operating mode during runtime and when the system enter sleep mode (stand by mode). Regulators which can be turned off during system suspend: -LDOn : 2, 6-8, 10-12, 14-16, -BUCKn : 1-4. Use standard regulator bindings for it ('regulator-off-in-suspend'). Signed-off-by: Anand Moon --- .../boot/dts/samsung/exynos5250-smdk5250.dts | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts b/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts index d41409019671..866e56915a2a 100644 --- a/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts @@ -165,6 +165,10 @@ ldo2_reg: LDO2 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo3_reg: LDO3 { @@ -191,6 +195,10 @@ ldo6_reg: LDO6 { regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo7_reg: LDO7 { @@ -198,12 +206,20 @@ ldo7_reg: LDO7 { regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo8_reg: LDO8 { regulator-name = "P1.0V_LDO_OUT8"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo10_reg: LDO10 { @@ -211,18 +227,30 @@ ldo10_reg: LDO10 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo11_reg: LDO11 { regulator-name = "P1.8V_LDO_OUT11"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo12_reg: LDO12 { regulator-name = "P3.0V_LDO_OUT12"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo13_reg: LDO13 { @@ -235,18 +263,30 @@ ldo14_reg: LDO14 { regulator-name = "P1.8V_LDO_OUT14"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo15_reg: LDO15 { regulator-name = "P1.0V_LDO_OUT15"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo16_reg: LDO16 { regulator-name = "P1.8V_LDO_OUT16"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck1_reg: BUCK1 { @@ -255,6 +295,10 @@ buck1_reg: BUCK1 { regulator-max-microvolt = <1300000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck2_reg: BUCK2 { @@ -263,6 +307,10 @@ buck2_reg: BUCK2 { regulator-max-microvolt = <1350000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck3_reg: BUCK3 { @@ -271,6 +319,10 @@ buck3_reg: BUCK3 { regulator-max-microvolt = <1200000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck4_reg: BUCK4 { @@ -279,6 +331,10 @@ buck4_reg: BUCK4 { regulator-max-microvolt = <1300000>; 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Fri, 25 Apr 2025 06:29:03 -0700 (PDT) Received: from localhost.localdomain ([110.44.101.8]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309f7752a03sm1564313a91.18.2025.04.25.06.28.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 06:29:03 -0700 (PDT) From: Anand Moon To: Chanwoo Choi , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alim Akhtar , linux-kernel@vger.kernel.org (open list:MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BO...), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-samsung-soc@vger.kernel.org (open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES) Cc: Anand Moon Subject: [PATCH v1 09/10] ARM: dts: exynos: Add rtc clock definitions for MAX77686 PMIC for Exynos5250 snow Date: Fri, 25 Apr 2025 18:56:29 +0530 Message-ID: <20250425132727.5160-10-linux.amoon@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250425132727.5160-1-linux.amoon@gmail.com> References: <20250425132727.5160-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The MAX77686A includes a crystal driver with an external load capacitance. When enabled, the crystal driver starts in low power mode. The LowJitterMode bit controls the crystal driver, allowing it to switch between low power mode and low jitter mode (high power mode). Setting the LowJitterMode bit to 1 activates low jitter mode on three channels simultaneously. These three 32khz buffer outputs (32KHAP, 32KHCP, P32KH) are independently enabled/disabled over I2C. The 32khz_ap output is typically routed to the AP Processor, while the 32khz_cp and 32khz_pmic outputs are intended for BT, WLAN, BB, or peripheral chipsets. Signed-off-by: Anand Moon --- arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi index 65b000df176e..ca6ebd8a9d62 100644 --- a/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi @@ -298,6 +298,13 @@ max77686: pmic@9 { reg = <0x09>; #clock-cells = <1>; + max77686_osc: clocks { + compatible = "max77686-rtc"; + #clock-cells = <1>; + clock-output-names = "32khz_ap", + "32khz_cp", "32khz_pmic"; + }; + voltage-regulators { ldo1_reg: LDO1 { regulator-name = "P1.0V_LDO_OUT1"; From patchwork Fri Apr 25 13:26:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 884716 Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2A9C253946; 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Fri, 25 Apr 2025 06:29:12 -0700 (PDT) Received: from localhost.localdomain ([110.44.101.8]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309f7752a03sm1564313a91.18.2025.04.25.06.29.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 06:29:12 -0700 (PDT) From: Anand Moon To: Chanwoo Choi , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alim Akhtar , linux-kernel@vger.kernel.org (open list:MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BO...), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-samsung-soc@vger.kernel.org (open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES) Cc: Anand Moon Subject: [PATCH v1 10/10] ARM: dts: exynos: Add proper regulator states for suspend-to-mem for Exynos5250 snow Date: Fri, 25 Apr 2025 18:56:30 +0530 Message-ID: <20250425132727.5160-11-linux.amoon@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250425132727.5160-1-linux.amoon@gmail.com> References: <20250425132727.5160-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The MAX77686 PMCI is able to power down and up key core supplies and other voltage rails via PWRREQ signal to enter / exit (deep) sleep mode. PWRREQ status is ignored during initial power up and down processes. All programming must be done before the AP enterns the sleep mode by pulling PWRREQ low since the AP does not have programming capability in (deep) sleep mode. Add suspend-to-mem node to regulator core to be enabled or disabled during system suspend and also support changing the regulator operating mode during runtime and when the system enter sleep mode (stand by mode). Regulators which can be turned off during system suspend: -LDOn : 2, 6-8, 10-12, 14-16, -BUCKn : 1-4. Use standard regulator bindings for it ('regulator-off-in-suspend'). Signed-off-by: Anand Moon --- .../dts/samsung/exynos5250-snow-common.dtsi | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi index ca6ebd8a9d62..70c3e6da55b7 100644 --- a/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi @@ -318,6 +318,10 @@ ldo2_reg: LDO2 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo3_reg: LDO3 { @@ -332,6 +336,10 @@ ldo7_reg: LDO7 { regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo8_reg: LDO8 { @@ -339,6 +347,10 @@ ldo8_reg: LDO8 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo10_reg: LDO10 { @@ -346,6 +358,10 @@ ldo10_reg: LDO10 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo12_reg: LDO12 { @@ -353,6 +369,10 @@ ldo12_reg: LDO12 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo14_reg: LDO14 { @@ -360,6 +380,10 @@ ldo14_reg: LDO14 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo15_reg: LDO15 { @@ -367,6 +391,10 @@ ldo15_reg: LDO15 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo16_reg: LDO16 { @@ -374,6 +402,10 @@ ldo16_reg: LDO16 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck1_reg: BUCK1 { @@ -382,6 +414,10 @@ buck1_reg: BUCK1 { regulator-max-microvolt = <1300000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck2_reg: BUCK2 { @@ -390,6 +426,10 @@ buck2_reg: BUCK2 { regulator-max-microvolt = <1350000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck3_reg: BUCK3 { @@ -398,6 +438,10 @@ buck3_reg: BUCK3 { regulator-max-microvolt = <1200000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck4_reg: BUCK4 { @@ -406,6 +450,10 @@ buck4_reg: BUCK4 { regulator-max-microvolt = <1300000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck5_reg: BUCK5 {