From patchwork Wed Apr 23 01:46:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 884183 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AED1263C8A; Wed, 23 Apr 2025 01:46:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745372819; cv=none; b=tR/izZR24bp1zsTgS7vgNHqVgv65//B7x1ggWjh+JLce3OUVlUr+LIBtKKlG7skM87xsklrld8SUUhFJPvX/10TtgdZDA7ll6ZqloeJUlc5lyj9HlxQ2Bk7CRoP8tRF3SKQn/Twt1yg4dAf8NE7+vXBu3EmmPOhEmZVzanhFPuM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745372819; c=relaxed/simple; bh=C/DC4U7CqrN91iP2gD2mgE+3K0WuG/bWFWbZbz7y1R8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Qa4+nVBfcOMK6P8WihogBUEgydqh9LfM05349+ZeMm3CVcuR65FaEqpLcU/CPDVSMmfioNWvY5idU5R419eARD6frzERUDMqMK3Ha2ccUyMpZISU6e3LpVJkmIU6vJo30Dj+AadJe9MoWTv3BVcdKU1wDpI29jqB0faWwB3DKfA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fAkP27h7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fAkP27h7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 79FA7C4CEEC; Wed, 23 Apr 2025 01:46:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745372819; bh=C/DC4U7CqrN91iP2gD2mgE+3K0WuG/bWFWbZbz7y1R8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fAkP27h7hm3ZW8x84mQkTYcnMPF3xnnU+IsNlCT/4BkVA/o/kIs+OFxIJLUKvK3+N 9QhsRb/vj9kHBdPVt0UNQRozkEgnw80OZGZbLyu+J2jUtPXl5vP1UhfT+VLoyiHOcp V0XAGVMzPOJI9DR4gSMS/LxFCMRbIY9ex0b30h5tnMlzpyJmgmi3svgmI5qC2QoZji pB03vUJF0ouwA4UF2Gjq2nFUIKq9uYkLF3027gc/M7E+fBa/5JvR5OAMTelXqqrKiZ xtV9IlL+NgbBxHX97k5XEE9Eb6XN23Sj/dsHk3B+O5mq/dKJBN6cx4w5SQIU3CkiNs hUQRgy0zgnX4Q== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan , Bagas Sanjaya Subject: [PATCH v9 01/13] Documentation: x86: Add AMD Hardware Feedback Interface documentation Date: Tue, 22 Apr 2025 20:46:19 -0500 Message-ID: <20250423014631.3224338-2-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250423014631.3224338-1-superm1@kernel.org> References: <20250423014631.3224338-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Introduce a new documentation file, `amd_hfi.rst`, which delves into the implementation details of the AMD Hardware Feedback Interface and its associated driver, `amd_hfi`. This documentation describes how the driver provides hint to the OS scheduling which depends on the capability of core performance and efficiency ranking data. This documentation describes * The design of the driver * How the driver provides hints to the OS scheduling * How the driver interfaces with the kernel for efficiency ranking data. Reviewed-by: Bagas Sanjaya Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v9: * Reflow to ~80 characters * Move higher in the index * 2024->2025 --- Documentation/arch/x86/amd-hfi.rst | 133 +++++++++++++++++++++++++++++ Documentation/arch/x86/index.rst | 1 + 2 files changed, 134 insertions(+) create mode 100644 Documentation/arch/x86/amd-hfi.rst diff --git a/Documentation/arch/x86/amd-hfi.rst b/Documentation/arch/x86/amd-hfi.rst new file mode 100644 index 0000000000000..8c1799acb6fe6 --- /dev/null +++ b/Documentation/arch/x86/amd-hfi.rst @@ -0,0 +1,133 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================================================== +Hardware Feedback Interface For Hetero Core Scheduling On AMD Platform +====================================================================== + +:Copyright: 2025 Advanced Micro Devices, Inc. All Rights Reserved. + +:Author: Perry Yuan +:Author: Mario Limonciello + +Overview +-------- + +AMD Heterogeneous Core implementations are comprised of more than one +architectural class and CPUs are comprised of cores of various efficiency and +power capabilities: performance-oriented *classic cores* and power-efficient +*dense cores*. As such, power management strategies must be designed to +accommodate the complexities introduced by incorporating different core types. +Heterogeneous systems can also extend to more than two architectural classes +as well. The purpose of the scheduling feedback mechanism is to provide +information to the operating system scheduler in real time such that the +scheduler can direct threads to the optimal core. + +The goal of AMD's heterogeneous architecture is to attain power benefit by +sending background thread to the dense cores while sending high priority +threads to the classic cores. From a performance perspective, sending +background threads to dense cores can free up power headroom and allow the +classic cores to optimally service demanding threads. Furthermore, the area +optimized nature of the dense cores allows for an increasing number of +physical cores. This improved core density will have positive multithreaded +performance impact. + +AMD Heterogeneous Core Driver +----------------------------- + +The ``amd_hfi`` driver delivers the operating system a performance and energy +efficiency capability data for each CPU in the system. The scheduler can use +the ranking data from the HFI driver to make task placement decisions. + +Thread Classification and Ranking Table Interaction +---------------------------------------------------- + +The thread classification is used to select into a ranking table that +describes an efficiency and performance ranking for each classification. + +Threads are classified during runtime into enumerated classes. The classes +represent thread performance/power characteristics that may benefit from +special scheduling behaviors. The below table depicts an example of thread +classification and a preference where a given thread should be scheduled +based on its thread class. The real time thread classification is consumed +by the operating system and is used to inform the scheduler of where the +thread should be placed. + +Thread Classification Example Table +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ++----------+----------------+-------------------------------+---------------------+---------+ +| class ID | Classification | Preferred scheduling behavior | Preemption priority | Counter | ++----------+----------------+-------------------------------+---------------------+---------+ +| 0 | Default | Performant | Highest | | ++----------+----------------+-------------------------------+---------------------+---------+ +| 1 | Non-scalable | Efficient | Lowest | PMCx1A1 | ++----------+----------------+-------------------------------+---------------------+---------+ +| 2 | I/O bound | Efficient | Lowest | PMCx044 | ++----------+----------------+-------------------------------+---------------------+---------+ + +Thread classification is performed by the hardware each time that the thread is switched out. +Threads that don't meet any hardware specified criteria will be classified as "default". + +AMD Hardware Feedback Interface +-------------------------------- + +The Hardware Feedback Interface provides to the operating system information +about the performance and energy efficiency of each CPU in the system. Each +capability is given as a unit-less quantity in the range [0-255]. A higher +performance value indicates higher performance capability, and a higher +efficiency value indicates more efficiency. Energy efficiency and performance +are reported in separate capabilities in the shared memory based ranking table. + +These capabilities may change at runtime as a result of changes in the +operating conditions of the system or the action of external factors. +Power Management FW is responsible for detecting events that would require +a reordering of the performance and efficiency ranking. Table updates would +happen relatively infrequently and occur on the time scale of seconds or more. + +The following events trigger a table update: + * Thermal Stress Events + * Silent Compute + * Extreme Low Battery Scenarios + +The kernel or a userspace policy daemon can use these capabilities to modify +task placement decisions. For instance, if either the performance or energy +capabilities of a given logical processor becomes zero, it is an indication +that the hardware recommends to the operating system to not schedule any tasks +on that processor for performance or energy efficiency reasons, respectively. + +Implementation details for Linux +-------------------------------- + +The implementation of threads scheduling consists of the following steps: + +1. A thread is spawned and scheduled to the ideal core using the default + heterogeneous scheduling policy. +2. The processor profiles thread execution and assigns an enumerated + classification ID. + This classification is communicated to the OS via logical processor + scope MSR. +3. During the thread context switch out the operating system consumes the + workload(WL) classification which resides in a logical processor scope MSR. +4. The OS triggers the hardware to clear its history by writing to an MSR, + after consuming the WL classification and before switching in the new thread. +5. If due to the classification, ranking table, and processor availability, + the thread is not on its ideal processor, the OS will then consider + scheduling the thread on its ideal processor (if available). + +Ranking Table +------------- +The ranking table is a shared memory region that is used to communicate the +performance and energy efficiency capabilities of each CPU in the system. + +The ranking table design includes rankings for each APIC ID in the system and +rankings both for performance and efficiency for each workload classification. + +.. kernel-doc:: drivers/platform/x86/amd/hfi/hfi.c + :doc: amd_shmem_info + +Ranking Table update +--------------------------- +The power management firmware issues an platform interrupt after updating the +ranking table and is ready for the operating system to consume it. CPUs receive +such interrupt and read new ranking table from shared memory which PCCT table +has provided, then ``amd_hfi`` driver parse the new table to provide new +consume data for scheduling decisions. diff --git a/Documentation/arch/x86/index.rst b/Documentation/arch/x86/index.rst index 8ac64d7de4dc9..fb167e6bb9d52 100644 --- a/Documentation/arch/x86/index.rst +++ b/Documentation/arch/x86/index.rst @@ -27,6 +27,7 @@ x86-specific Documentation intel_txt amd-memory-encryption amd_hsmp + amd-hfi tdx pti mds From patchwork Wed Apr 23 01:46:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 884182 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D096C264A72; Wed, 23 Apr 2025 01:47:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745372823; cv=none; b=gBzi2hOSsKHr6K1ZQZrPl+EKVkXVvJ9nGP063f4Z0Q5TdNRCkcpWtGCA0EI6Sv8xsBRDVKuJTNV8vsMZ4XKorlnAQ3loHkN99oQiMhhlR4N65AF/x5JTAYgxbz/A3TfH0KwKZq2CfRLEEYxJBjnMPXK3McpXYRs97DGZmgagqoA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745372823; c=relaxed/simple; bh=UcQq1FFSIkxtUl0R2B0U9yrBSqRLeyIDteqW0GNuh/I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ihgn63tLI92mEmxCgcBF/zu6Kzm7qRFu8MgQg4BL0P7cQ18BF/uRHa4012DvKPN6ql1+pvtMP0oIUb46/NnecnfZ38rJSQJDcwMGdM18a4ngdVqPteR/lRvMQaR66avaSxdINkn45t+XJOMHvrPogz9BdJsP+UwqEzuLtrEgT1E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eMAzY9Pp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eMAzY9Pp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9B990C4CEED; Wed, 23 Apr 2025 01:47:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745372823; bh=UcQq1FFSIkxtUl0R2B0U9yrBSqRLeyIDteqW0GNuh/I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eMAzY9Ppey6y7/HLO4nPRmuCxvZhpD465dwB08aAXptGaY90P/3mPUKK8+zUGMYDK gIhVc3/vzfJxBUSeWzaQ6GzH9RC69vJXzO4eJ7iaC3J5WdTPlZ99TbWLoBUh/EoGMX hq5X5v6g8qCAhBiq4P+FRTnvy06WdVI7hNrbo9rRyssbNHBNFmW286gRjH/zsCGcbx 8yLXjlIVVxevh38vTqt+mSovpp4Pj1DTYc2fTAu3JrErDaRK6ceK68qMpTDkI27LWu KisFJrCZt/ExHk59165UxO2MzC1AKJVZUU5g0jgjmuaekWKG85QGmsz9Fo4cuMfVXh POgWn5yfavniA== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v9 03/13] x86/msr-index: define AMD heterogeneous CPU related MSR Date: Tue, 22 Apr 2025 20:46:21 -0500 Message-ID: <20250423014631.3224338-4-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250423014631.3224338-1-superm1@kernel.org> References: <20250423014631.3224338-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Introduces new MSR registers for AMD hardware feedback support. These registers enable the system to provide workload classification and configuration capabilities. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ac21dc19dde21..0c761033aa714 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -724,6 +724,11 @@ #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 +/* AMD Hardware Feedback Support MSRs */ +#define AMD_WORKLOAD_CLASS_CONFIG 0xc0000500 +#define AMD_WORKLOAD_CLASS_ID 0xc0000501 +#define AMD_WORKLOAD_HRST 0xc0000502 + /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e From patchwork Wed Apr 23 01:46:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 884181 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C514F262D02; Wed, 23 Apr 2025 01:47:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745372827; cv=none; b=asUpk7UK4IC+KcYpdxosi5vtOvq/4JxvqOJoDMysAbpb7sdJB0ZJLDzxoaWrBxTlsVCrUXccxYQNzSu6OWCnIBMXzRe6Bo4kIFu8vXUthptF761SoDdANDeqALzp6+krvoZ5c6SQOEc/rA/fZNiSVirw7IXTs1i7bxRoqP0mvcM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745372827; c=relaxed/simple; bh=S40MEZK0pLUKXOTwd62c9bwXnvtU/VjJmBVxHGDgLCI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=I5vjg9ZNmvh/oq9ud1IHcNARhfS4voDa3gRcxFGT4A7KkIhzMQY+4zStglzMQwVKFwGPZlHoD2nv3YNwnKar35q6ZEXhZKX3v1upgOW35b1dHSzp5gV/Jh8OO2ML3IOhpVnt3byMIuQOh2tpv4Vmk3m8qDJDkCBhfu9Kxq4AnW0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=X/HaNFKy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="X/HaNFKy" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C8506C4CEEC; Wed, 23 Apr 2025 01:47:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745372827; bh=S40MEZK0pLUKXOTwd62c9bwXnvtU/VjJmBVxHGDgLCI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X/HaNFKyRBCmMCwM11oKtaxP0bQ2W8C5aeSC0M7LUYSvNpCkpVactvy78Ul2NoeSg dCHo0QFGRQQOywsEh+QY4NoiE0zkAii3jdFKU+glCtWXyfJHp31VakS092fyeTk9ik JwnJl8IHuESjzEbvGD1XWIW0ntXDoxSlXZ31DctfeyTLWpPioooRPL9X2fATQsom4i 0oywUo4Ess5q3FHbv6AHLhpnXbu7zHBJBWP6y1t2LP4wFM2bL1oAI8DOGCgqcGGiIt UFwP6nSEKDHJ/yrtwoIrBQm4crffFBg9ZFMhrUWtDUJu+GZPZ7xxB/BaR1XwDjltvs NwV3WDaRVzZIQ== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan Subject: [PATCH v9 05/13] platform/x86: hfi: parse CPU core ranking data from shared memory Date: Tue, 22 Apr 2025 20:46:23 -0500 Message-ID: <20250423014631.3224338-6-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250423014631.3224338-1-superm1@kernel.org> References: <20250423014631.3224338-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan When `amd_hfi` driver is loaded, it will use PCCT subspace type 4 table to retrieve the shared memory address which contains the CPU core ranking table. This table includes a header that specifies the number of ranking data entries to be parsed and rank each CPU core with the Performance and Energy Efficiency capability as implemented by the CPU power management firmware. Once the table has been parsed, each CPU is assigned a ranking score within its class. Subsequently, when the scheduler selects cores, it chooses from the ranking list based on the assigned scores in each class, thereby ensuring the optimal selection of CPU cores according to their predefined classifications and priorities. Reviewed-by: Ilpo Järvinen Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v9 * Fix an indexing logic error in amd_hfi_fill_metadata() leading to wrong APIC IDs being used. * Add a missing space * use dev_err/dev_warn * pcct->PCCT * signed->unsigned --- drivers/platform/x86/amd/hfi/hfi.c | 197 +++++++++++++++++++++++++++++ 1 file changed, 197 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index e613bdf027b26..17ce5302cb531 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -18,21 +18,71 @@ #include #include #include +#include #include +#include #include #include +#include +#include + +#include + +#include +#include #define AMD_HFI_DRIVER "amd_hfi" +#define AMD_HFI_MAILBOX_COUNT 1 +#define AMD_HETERO_RANKING_TABLE_VER 2 #define AMD_HETERO_CPUID_27 0x80000027 static struct platform_device *device; +/** + * struct amd_shmem_info - Shared memory table for AMD HFI + * + * @header: The PCCT table header including signature, length flags and command. + * @version_number: Version number of the table + * @n_logical_processors: Number of logical processors + * @n_capabilities: Number of ranking dimensions (performance, efficiency, etc) + * @table_update_context: Command being sent over the subspace + * @n_bitmaps: Number of 32-bit bitmaps to enumerate all the APIC IDs + * This is based on the maximum APIC ID enumerated in the system + * @reserved: 24 bit spare + * @table_data: Bit Map(s) of enabled logical processors + * Followed by the ranking data for each logical processor + */ +struct amd_shmem_info { + struct acpi_pcct_ext_pcc_shared_memory header; + u32 version_number :8, + n_logical_processors :8, + n_capabilities :8, + table_update_context :8; + u32 n_bitmaps :8, + reserved :24; + u32 table_data[]; +}; + struct amd_hfi_data { const char *name; struct device *dev; + + /* PCCT table related */ + struct pcc_mbox_chan *pcc_chan; + void __iomem *pcc_comm_addr; + struct acpi_subtable_header *pcct_entry; + struct amd_shmem_info *shmem; }; +/** + * struct amd_hfi_classes - HFI class capabilities per CPU + * @perf: Performance capability + * @eff: Power efficiency capability + * + * Capabilities of a logical processor in the ranking table. These capabilities + * are unitless and specific to each HFI class. + */ struct amd_hfi_classes { u32 perf; u32 eff; @@ -41,21 +91,106 @@ struct amd_hfi_classes { /** * struct amd_hfi_cpuinfo - HFI workload class info per CPU * @cpu: cpu index + * @apic_id: apic id of the current cpu * @class_index: workload class ID index * @nr_class: max number of workload class supported + * @ipcc_scores: ipcc scores for each class * @amd_hfi_classes: current cpu workload class ranking data * * Parameters of a logical processor linked with hardware feedback class. */ struct amd_hfi_cpuinfo { int cpu; + u32 apic_id; s16 class_index; u8 nr_class; + int *ipcc_scores; struct amd_hfi_classes *amd_hfi_classes; }; static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = -1}; +static int find_cpu_index_by_apicid(unsigned int target_apicid) +{ + int cpu_index; + + for_each_possible_cpu(cpu_index) { + struct cpuinfo_x86 *info = &cpu_data(cpu_index); + + if (info->topo.apicid == target_apicid) { + pr_debug("match APIC id %u for CPU index: %d\n", + info->topo.apicid, cpu_index); + return cpu_index; + } + } + + return -ENODEV; +} + +static int amd_hfi_fill_metadata(struct amd_hfi_data *amd_hfi_data) +{ + struct acpi_pcct_ext_pcc_slave *pcct_ext = + (struct acpi_pcct_ext_pcc_slave *)amd_hfi_data->pcct_entry; + void __iomem *pcc_comm_addr; + u32 apic_start = 0; + + pcc_comm_addr = acpi_os_ioremap(amd_hfi_data->pcc_chan->shmem_base_addr, + amd_hfi_data->pcc_chan->shmem_size); + if (!pcc_comm_addr) { + dev_err(amd_hfi_data->dev, "failed to ioremap PCC common region mem\n"); + return -ENOMEM; + } + + memcpy_fromio(amd_hfi_data->shmem, pcc_comm_addr, pcct_ext->length); + iounmap(pcc_comm_addr); + + if (amd_hfi_data->shmem->header.signature != PCC_SIGNATURE) { + dev_err(amd_hfi_data->dev, "invalid signature in shared memory\n"); + return -EINVAL; + } + if (amd_hfi_data->shmem->version_number != AMD_HETERO_RANKING_TABLE_VER) { + dev_err(amd_hfi_data->dev, "invalid version %d\n", amd_hfi_data->shmem->version_number); + return -EINVAL; + } + + for (unsigned int i = 0; i < amd_hfi_data->shmem->n_bitmaps; i++) { + u32 bitmap = amd_hfi_data->shmem->table_data[i]; + + for (unsigned int j = 0; j < BITS_PER_TYPE(u32); j++) { + u32 apic_id = i * BITS_PER_TYPE(u32) + j; + struct amd_hfi_cpuinfo *info; + int cpu_index, apic_index; + + if (!(bitmap & BIT(j))) + continue; + + cpu_index = find_cpu_index_by_apicid(apic_id); + if (cpu_index < 0) { + dev_warn(amd_hfi_data->dev, "APIC ID %u not found\n", apic_id); + continue; + } + + info = per_cpu_ptr(&amd_hfi_cpuinfo, cpu_index); + info->apic_id = apic_id; + + /* Fill the ranking data for each logical processor */ + info = per_cpu_ptr(&amd_hfi_cpuinfo, cpu_index); + apic_index = apic_start * info->nr_class * 2; + for (unsigned int k = 0; k < info->nr_class; k++) { + u32 *table = amd_hfi_data->shmem->table_data + + amd_hfi_data->shmem->n_bitmaps + + i * info->nr_class; + + info->amd_hfi_classes[k].eff = table[apic_index + 2 * k]; + info->amd_hfi_classes[k].perf = table[apic_index + 2 * k + 1]; + } + apic_start++; + } + } + + return 0; +} + static int amd_hfi_alloc_class_data(struct platform_device *pdev) { struct amd_hfi_cpuinfo *hfi_cpuinfo; @@ -72,6 +207,7 @@ static int amd_hfi_alloc_class_data(struct platform_device *pdev) for_each_possible_cpu(idx) { struct amd_hfi_classes *classes; + int *ipcc_scores; classes = devm_kcalloc(dev, nr_class_id, @@ -79,14 +215,71 @@ static int amd_hfi_alloc_class_data(struct platform_device *pdev) GFP_KERNEL); if (!classes) return -ENOMEM; + ipcc_scores = devm_kcalloc(dev, nr_class_id, sizeof(int), GFP_KERNEL); + if (!ipcc_scores) + return -ENOMEM; hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, idx); hfi_cpuinfo->amd_hfi_classes = classes; + hfi_cpuinfo->ipcc_scores = ipcc_scores; hfi_cpuinfo->nr_class = nr_class_id; } return 0; } +static int amd_hfi_metadata_parser(struct platform_device *pdev, + struct amd_hfi_data *amd_hfi_data) +{ + struct acpi_pcct_ext_pcc_slave *pcct_ext; + struct acpi_subtable_header *pcct_entry; + struct mbox_chan *pcc_mbox_channels; + struct acpi_table_header *pcct_tbl; + struct pcc_mbox_chan *pcc_chan; + acpi_status status; + int ret; + + pcc_mbox_channels = devm_kcalloc(&pdev->dev, AMD_HFI_MAILBOX_COUNT, + sizeof(*pcc_mbox_channels), GFP_KERNEL); + if (!pcc_mbox_channels) + return -ENOMEM; + + pcc_chan = devm_kcalloc(&pdev->dev, AMD_HFI_MAILBOX_COUNT, + sizeof(*pcc_chan), GFP_KERNEL); + if (!pcc_chan) + return -ENOMEM; + + status = acpi_get_table(ACPI_SIG_PCCT, 0, &pcct_tbl); + if (ACPI_FAILURE(status) || !pcct_tbl) + return -ENODEV; + + /* get pointer to the first PCC subspace entry */ + pcct_entry = (struct acpi_subtable_header *) ( + (unsigned long)pcct_tbl + sizeof(struct acpi_table_pcct)); + + pcc_chan->mchan = &pcc_mbox_channels[0]; + + amd_hfi_data->pcc_chan = pcc_chan; + amd_hfi_data->pcct_entry = pcct_entry; + pcct_ext = (struct acpi_pcct_ext_pcc_slave *)pcct_entry; + + if (pcct_ext->length <= 0) + return -EINVAL; + + amd_hfi_data->shmem = devm_kzalloc(amd_hfi_data->dev, pcct_ext->length, GFP_KERNEL); + if (!amd_hfi_data->shmem) + return -ENOMEM; + + pcc_chan->shmem_base_addr = pcct_ext->base_address; + pcc_chan->shmem_size = pcct_ext->length; + + /* parse the shared memory info from the PCCT table */ + ret = amd_hfi_fill_metadata(amd_hfi_data); + + acpi_put_table(pcct_tbl); + + return ret; +} + static const struct acpi_device_id amd_hfi_platform_match[] = { {"AMDI0104", 0}, { } @@ -112,6 +305,10 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret) return ret; + ret = amd_hfi_metadata_parser(pdev, amd_hfi_data); + if (ret) + return ret; + return 0; } From patchwork Wed Apr 23 01:46:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 884180 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4858C266595; Wed, 23 Apr 2025 01:47:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745372832; cv=none; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745372831; bh=PvHbHKP9YT2R2ZmznP9QoSqr89VNI5yfDALL58/Fq1w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kSlvE3+yLwhVUZ+RyzrC9EeHpwpdr3QFe2OZ7oY/dHbEwbMgtHLHi0TdWeIwQdUHK S3pXyWpYd6+NR/D90RhH0PntpMLU8kGlW9byWR8YNFIO/jycbG089ptOqxd18PMLKv LFh4PaMEiJt9v366XhiS7/0c/7mm5Ser5WPrce3q0V7W5m9cI6POixZc2yXJZTtr0T /MgOYXNvwgYOrlHhmL6c02Zw1PWr0lDOvEEFOwRHaum2gOqwjPAeJBr9lfA7ZzuRjS zNiTAYF3AZFN9EzWq06W3RmOvAmSORxffmF+FtP6yMbYbAmnwH18PWD3QWmBHEbvpu B3jI2yzhI1QWA== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan Subject: [PATCH v9 07/13] platform/x86: hfi: add online and offline callback support Date: Tue, 22 Apr 2025 20:46:25 -0500 Message-ID: <20250423014631.3224338-8-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250423014631.3224338-1-superm1@kernel.org> References: <20250423014631.3224338-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan There are some firmware parameters that need to be configured when a CPU core is brought online or offline. when CPU is online, it will initialize the workload classification parameters to CPU firmware which will trigger the workload class ID updating function. Once the CPU is going to offline, it will need to disable the workload classification function and clear the history. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v9: * explicit conversion for bool * fix signed/unsigned for some prints * Update to wrmsrq_on_cpu --- drivers/platform/x86/amd/hfi/hfi.c | 88 ++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index f63c6098b7d92..1472214dc809f 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -92,6 +92,7 @@ struct amd_hfi_classes { * struct amd_hfi_cpuinfo - HFI workload class info per CPU * @cpu: cpu index * @apic_id: apic id of the current cpu + * @cpus: mask of cpus associated with amd_hfi_cpuinfo * @class_index: workload class ID index * @nr_class: max number of workload class supported * @ipcc_scores: ipcc scores for each class @@ -102,6 +103,7 @@ struct amd_hfi_classes { struct amd_hfi_cpuinfo { int cpu; u32 apic_id; + cpumask_var_t cpus; s16 class_index; u8 nr_class; int *ipcc_scores; @@ -110,6 +112,8 @@ struct amd_hfi_cpuinfo { static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = -1}; +static DEFINE_MUTEX(hfi_cpuinfo_lock); + static int find_cpu_index_by_apicid(unsigned int target_apicid) { int cpu_index; @@ -236,6 +240,81 @@ static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) return 0; } +static int amd_hfi_set_state(unsigned int cpu, bool state) +{ + int ret; + + ret = wrmsrq_on_cpu(cpu, AMD_WORKLOAD_CLASS_CONFIG, state ? 1 : 0); + if (ret) + return ret; + + return wrmsrq_on_cpu(cpu, AMD_WORKLOAD_HRST, 0x1); +} + +/** + * amd_hfi_online() - Enable workload classification on @cpu + * @cpu: CPU in which the workload classification will be enabled + * + * Return: 0 on success, negative error code on failure. + */ +static int amd_hfi_online(unsigned int cpu) +{ + struct amd_hfi_cpuinfo *hfi_info = per_cpu_ptr(&amd_hfi_cpuinfo, cpu); + struct amd_hfi_classes *hfi_classes; + int ret; + + if (WARN_ON_ONCE(!hfi_info)) + return -EINVAL; + + /* + * Check if @cpu as an associated, initialized and ranking data must + * be filled. + */ + hfi_classes = hfi_info->amd_hfi_classes; + if (!hfi_classes) + return -EINVAL; + + guard(mutex)(&hfi_cpuinfo_lock); + + if (!zalloc_cpumask_var(&hfi_info->cpus, GFP_KERNEL)) + return -ENOMEM; + + cpumask_set_cpu(cpu, hfi_info->cpus); + + ret = amd_hfi_set_state(cpu, true); + if (ret) + pr_err("WCT enable failed for CPU %u\n", cpu); + + return ret; +} + +/** + * amd_hfi_offline() - Disable workload classification on @cpu + * @cpu: CPU in which the workload classification will be disabled + * + * Remove @cpu from those covered by its HFI instance. + * + * Return: 0 on success, negative error code on failure + */ +static int amd_hfi_offline(unsigned int cpu) +{ + struct amd_hfi_cpuinfo *hfi_info = &per_cpu(amd_hfi_cpuinfo, cpu); + int ret; + + if (WARN_ON_ONCE(!hfi_info)) + return -EINVAL; + + guard(mutex)(&hfi_cpuinfo_lock); + + ret = amd_hfi_set_state(cpu, false); + if (ret) + pr_err("WCT disable failed for CPU %u\n", cpu); + + free_cpumask_var(hfi_info->cpus); + + return ret; +} + static int update_hfi_ipcc_scores(void) { int cpu; @@ -338,6 +417,15 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret) return ret; + /* + * Tasks will already be running at the time this happens. This is + * OK because rankings will be adjusted by the callbacks. + */ + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/amd_hfi:online", + amd_hfi_online, amd_hfi_offline); + if (ret < 0) + return ret; + return 0; } From patchwork Wed Apr 23 01:46:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 884179 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62E1C266EF8; Wed, 23 Apr 2025 01:47:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745372836; cv=none; b=Y81tswVwlXFP2ae8iuio8ZGSKEwwmXAKHWBMOx6Mcgvv6zAfpO/AVKD0AjSMF5nCdZf60U9Aa47pxAWpRHfesp3/uB1E26cHVtTCiRFrEHRI4bQJevSMAlD2wLrkAHohPia4kzNsH67OjbaazmmxB92aztcmqLkl3kdPLFH062M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745372836; c=relaxed/simple; bh=Do1426mrGV2LHA/HL/SD6shDSzpjPFUyAEjYA4UDuPU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EowuYIYvBQtgakZt/3LdRU7DMwXJxKarK9OXr6FUpm1htfQkiBD+vRkSO7vtRtR9CtD9wmBgbAIcZrmGO+IIJJ35Cm4KC73U8UGFbiLbFw75wC4UKo5C4oT9CFUow254ubyJV7sXUuL7n0RSLad5O7pVre+b5TJtzCAX7ClLUeg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JPnl1+3i; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JPnl1+3i" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 19BFFC4CEED; Wed, 23 Apr 2025 01:47:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745372835; bh=Do1426mrGV2LHA/HL/SD6shDSzpjPFUyAEjYA4UDuPU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JPnl1+3i7SWg98r+Ur9CpacIZYwkwyqeMjrLH7qauPQq8JjbI2E6NV2GKgtvlCIAv AJOmRHjn6OU25PE7QNgBoddyKfuc+oaaoY9PUCA/1s+6vqV2NVSAUme+FE6HiSvSfr 1+n/H0HsScozScYgEQt8hn2i0B9bfAKRVFZAgQ+IDH7JmRWQzmt51GkerTH7uqIDat TnoXpbdF12+tN8WK4MAplOsNHqMe9ZkWd8Mq+EAhxug1Zv5fAO9jycG6PpL/uhfL59 uTH/t/Mak5AaGT4r06uA5+GP0nEN3GybMMOWbsz9Y8EvaJz+lZfP6YJI4cAFoJyVNI EjzxT6uCQiOgQ== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v9 09/13] x86/process: Clear hardware feedback history for AMD processors Date: Tue, 22 Apr 2025 20:46:27 -0500 Message-ID: <20250423014631.3224338-10-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250423014631.3224338-1-superm1@kernel.org> References: <20250423014631.3224338-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Incorporate a mechanism within the context switching code to reset the hardware history for AMD processors. Specifically, when a task is switched in, the class ID was read and reset the hardware workload classification history of CPU firmware and then it start to trigger workload classification for the next running thread. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- arch/x86/kernel/process_64.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 24e1ccf229125..aba6d182a7d25 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -709,6 +709,10 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Load the Intel cache allocation PQR MSR. */ resctrl_sched_in(next_p); + /* Reset hw history on AMD CPUs */ + if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS)) + wrmsrl(AMD_WORKLOAD_HRST, 0x1); + return prev_p; } From patchwork Wed Apr 23 01:46:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 884178 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0283A2676F4; Wed, 23 Apr 2025 01:47:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745372840; cv=none; b=KGKYhpNKp3T0Gd+ThoXMVA3otafq0STBlSwB3oAFVox8/xTipUv8bZR9pS47KmNpFQg6XdSPOHDpgUR8v8gMXNKXCyZZVGHKui6ifUWc9rO1K/q3qF8nqj1Vd9akxDTeUz11lPLS1L9nvHugMiN40V1lFBGzJauod1Z9h8khZAI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745372840; c=relaxed/simple; bh=oHtRIsAptTXF54+4BJ34mKmBZlrungbNMyhnHWfvkmQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=f1fVgoab5fFnxGacph8B088XALRknki/ZAikf55CeMq1UxYJutRh6lEeF29LNsooPgh7+m+xWv5+hweuCv9M0Sy53yC7IvH4E4KsMuoAv99MPJjyJjapuD6asa3Wdyq/hIm8IbXiadcTLu4mQAXkO2+JyAfFgVOKBVVJQf/kZeY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MxkllRVI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MxkllRVI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 21F88C4CEEF; Wed, 23 Apr 2025 01:47:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745372839; bh=oHtRIsAptTXF54+4BJ34mKmBZlrungbNMyhnHWfvkmQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MxkllRVIR1L49NVQ5QWSnp3FHQl7uHEehZpLAPQktYeanFhRhycBxfmMvxeelxrGi LEDZDtxwSu+0NLw66eWwXnR3eLe75y9h3aNOd82x9MOyEOO3jzLeJ+aw9NLWAk9uij M55fi2i/YfPec3P2fgvbdiiUPyFlI3F+ZMzxSSl7RAicjSt+RK6f1A+6GHUOS+weZI sAdVBac+POYlO36pY5RS9KUKPJUqtlL8yJFMhTBKDxUQNMxz+crKYLvwwSWV0q5Xfh yJ/VBmpvdirfxxVrwLekcOiQqswbOCHIdKOzALcZ7G5BJC+lxMJ6/bp5ET3j2tYnFK +NgXPCittT0yw== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v9 11/13] platform/x86/amd: hfi: Set ITMT priority from ranking data Date: Tue, 22 Apr 2025 20:46:29 -0500 Message-ID: <20250423014631.3224338-12-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250423014631.3224338-1-superm1@kernel.org> References: <20250423014631.3224338-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello The static ranking data that is read at module load should be used to set up the priorities for the cores relative to the performance values. Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- drivers/platform/x86/amd/hfi/Kconfig | 1 + drivers/platform/x86/amd/hfi/hfi.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/Kconfig b/drivers/platform/x86/amd/hfi/Kconfig index 476e4a9ed67a9..75b0f73407047 100644 --- a/drivers/platform/x86/amd/hfi/Kconfig +++ b/drivers/platform/x86/amd/hfi/Kconfig @@ -7,6 +7,7 @@ config AMD_HFI bool "AMD Hetero Core Hardware Feedback Driver" depends on ACPI depends on CPU_SUP_AMD + depends on SCHED_MC_PRIO help Select this option to enable the AMD Heterogeneous Core Hardware Feedback Interface. If selected, hardware provides runtime thread diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 921e07acf2ff1..22a5bf977daf5 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -114,6 +114,12 @@ static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = static DEFINE_MUTEX(hfi_cpuinfo_lock); +static void amd_hfi_sched_itmt_work(struct work_struct *work) +{ + sched_set_itmt_support(); +} +static DECLARE_WORK(sched_amd_hfi_itmt_work, amd_hfi_sched_itmt_work); + static int find_cpu_index_by_apicid(unsigned int target_apicid) { int cpu_index; @@ -237,6 +243,8 @@ static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) WRITE_ONCE(hfi_cpuinfo->ipcc_scores[i], hfi_cpuinfo->amd_hfi_classes[i].perf); + sched_set_itmt_core_prio(hfi_cpuinfo->ipcc_scores[0], cpu); + return 0; } @@ -458,6 +466,8 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret < 0) return ret; + schedule_work(&sched_amd_hfi_itmt_work); + return 0; } From patchwork Wed Apr 23 01:46:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 884177 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FA43267AE4; Wed, 23 Apr 2025 01:47:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745372844; cv=none; b=X1ziPdTRT8bm5A+LGRjqWxBuOwE8ylZPL6/CEa4hGtqiZWeA+4JbqjWG1can/iFf2b+arRzzfsYXhikZk8SZv+dGkBujHblby3aEBmxZpln3xB6g6HnUgC4ZOtr3LpecgUGJCA8sxxQ0Sd/onQX+HwxA9VOz34qegjpnCJBi5UU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745372844; c=relaxed/simple; bh=ccxi92/CdYcFz5SRXc75fcFWq7DUZRAtA96LadU0vMs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jjXDs3dCXTRX61DMUTtkDQbUXTlrCYtKdO24PdQA9hG0XSkgR0KY75m8JUypu8lAG27761aPf2dV8dC3TqRs5FHPbTGHw0Rd16jAl4fmqCxyR4OqV6hNWoDeEasNa3tLvQKivvFg+k8ooD8/iJ9mtoWKeMcdAVAjiQSGn1y2LhA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ujR1UScJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ujR1UScJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1987BC4CEEE; Wed, 23 Apr 2025 01:47:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745372843; bh=ccxi92/CdYcFz5SRXc75fcFWq7DUZRAtA96LadU0vMs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ujR1UScJejlUs1alli6VXzUXGfUIDyMk9IrMKs1cxV+cMhuf1302e3ybpaVW3/CP4 q+C45d9L9JPn0ValsgWx/aXx+h8/xhDs6OwtLOaEsrLuxm/3pxpgm1abBuYKNlM07K Si1dQyIzS8XAiGXVpAaL1N3nzfb90A7t982bLeb2x4L4knXyvqAgRPh7FExkIir1/2 7vJiijOxV8idcCvI1lE9Vd5FW7/K1aY/M/isabS/DLFJYCgAfrljoAdF7HxfdbDhmG u6b4kJw9pUbgVc5RspMxATfTUoI5Q2JEsepYkQLejk3jxrbGoMZMcYSDNNW8xflCTD vZ+snsINadrQw== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v9 13/13] x86/itmt: Add debugfs file to show core priorities Date: Tue, 22 Apr 2025 20:46:31 -0500 Message-ID: <20250423014631.3224338-14-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250423014631.3224338-1-superm1@kernel.org> References: <20250423014631.3224338-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello Multiple drivers can report priorities to ITMT. To aid in debugging any issues with the values reported by drivers introduce a debugfs file to read out the values. Signed-off-by: Mario Limonciello --- arch/x86/kernel/itmt.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/x86/kernel/itmt.c b/arch/x86/kernel/itmt.c index 9cea1fc36c18f..243a769fdd97b 100644 --- a/arch/x86/kernel/itmt.c +++ b/arch/x86/kernel/itmt.c @@ -59,6 +59,18 @@ static ssize_t sched_itmt_enabled_write(struct file *filp, return result; } +static int sched_core_priority_show(struct seq_file *s, void *unused) +{ + int cpu; + + seq_puts(s, "CPU #\tPriority\n"); + for_each_possible_cpu(cpu) + seq_printf(s, "%d\t%d\n", cpu, arch_asym_cpu_priority(cpu)); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(sched_core_priority); + static const struct file_operations dfs_sched_itmt_fops = { .read = debugfs_read_file_bool, .write = sched_itmt_enabled_write, @@ -67,6 +79,7 @@ static const struct file_operations dfs_sched_itmt_fops = { }; static struct dentry *dfs_sched_itmt; +static struct dentry *dfs_sched_core_prio; /** * sched_set_itmt_support() - Indicate platform supports ITMT @@ -102,6 +115,14 @@ int sched_set_itmt_support(void) return -ENOMEM; } + dfs_sched_core_prio = debugfs_create_file("sched_core_priority", 0644, + arch_debugfs_dir, NULL, + &sched_core_priority_fops); + if (IS_ERR_OR_NULL(dfs_sched_core_prio)) { + dfs_sched_core_prio = NULL; + return -ENOMEM; + } + sched_itmt_capable = true; sysctl_sched_itmt_enabled = 1; @@ -133,6 +154,8 @@ void sched_clear_itmt_support(void) debugfs_remove(dfs_sched_itmt); dfs_sched_itmt = NULL; + debugfs_remove(dfs_sched_core_prio); + dfs_sched_core_prio = NULL; if (sysctl_sched_itmt_enabled) { /* disable sched_itmt if we are no longer ITMT capable */