From patchwork Tue Apr 22 08:21:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xin Li \(Intel\)" X-Patchwork-Id: 883456 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2660255229; Tue, 22 Apr 2025 08:23:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745310232; cv=none; b=rM+QaHae6Al7P8mNrdCtwS8Og5R7cemPSMAKsDpzPKQyW3jvjxYAOBstjcCgHhy4PE3f5kKmJl13ODv+1drKgFZlSGsSx3ARPGqfuiWkQQIR+QONo3Y+DonBdVjv1PrVi0Nc54iC85cXs3pB57cX2j9oeMNvLb6ihZcEGwPEgR4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745310232; c=relaxed/simple; bh=dSrOmsOGijxY8owXsHWDFLyZ+zqKO+vscqgd3I6Wg98=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CfHTqn7R+VTQ2cNESQGzQMkzwwuDYVn57sHZAaf37P3bME9i9BGZUazIt1Od1sUPJcsiC8vP/udhN+yHhQpVqtbj8N5aDNwJNDtiITklJ1QZdBNt9l4v8eBHY73DCX3TVk1uRFLP3Od9uaCGUs9yYfKLrHnTRnhHfrRRwu9npkQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com; spf=pass smtp.mailfrom=zytor.com; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b=C+FHL7l1; arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="C+FHL7l1" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 53M8MG9F1954391 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Tue, 22 Apr 2025 01:22:22 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53M8MG9F1954391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745310144; bh=gofr29Us7GJwE+ep+JSVtswMwKTsjSvf3ByH2Ru+lMY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C+FHL7l1DozIF9G3dyP8TJEkWL4mb+IbzggFlvUHen/RMc6m8raGVFoPqJTk1NloE dZEvycUnAXEB+wMZfgOQgp8M7ntf0J0NYGe5AWNwyKSvmonnj0D3+yR3eYhx6wihMv cbXC2V4zp5cqC6kq70UtDQC71N3d8i/2m8Yp2DtlJze9Ps9J0z6WDGvYaj8GYIO1E6 aFROF2AMz5JriybNNFSrbo4djA+VO/OFXxmQpoMKOQ9J9Y8vIl/Eda+WEtNJJYyOnv lpZh7KcgftJhdhV4JmJK/hirxkQJt4YDV8FOC/FXYUao/OGh7u3HXxEXgFRrimFNNO bUzyvFISvm1gQ== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Subject: [RFC PATCH v2 01/34] x86/msr: Move rdtsc{,_ordered}() to Date: Tue, 22 Apr 2025 01:21:42 -0700 Message-ID: <20250422082216.1954310-2-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250422082216.1954310-1-xin@zytor.com> References: <20250422082216.1954310-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Relocate rdtsc{,_ordered}() from to , and subsequently remove the inclusion of in . Consequently, must be included in several source files that previously did not require it. Signed-off-by: Xin Li (Intel) --- arch/x86/boot/startup/sme.c | 1 + arch/x86/events/msr.c | 3 + arch/x86/events/perf_event.h | 1 + arch/x86/events/probe.c | 2 + arch/x86/hyperv/ivm.c | 1 + arch/x86/include/asm/fred.h | 1 + arch/x86/include/asm/microcode.h | 2 + arch/x86/include/asm/mshyperv.h | 1 + arch/x86/include/asm/msr.h | 55 +------------- arch/x86/include/asm/suspend_32.h | 1 + arch/x86/include/asm/suspend_64.h | 1 + arch/x86/include/asm/switch_to.h | 2 + arch/x86/include/asm/tsc.h | 76 ++++++++++++++++++- arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 1 + arch/x86/kernel/fpu/xstate.h | 1 + arch/x86/kernel/hpet.c | 1 + arch/x86/kernel/process_64.c | 1 + arch/x86/kernel/trace_clock.c | 2 +- arch/x86/kernel/tsc_sync.c | 1 + arch/x86/lib/kaslr.c | 2 +- arch/x86/realmode/init.c | 1 + drivers/acpi/processor_perflib.c | 1 + drivers/acpi/processor_throttling.c | 3 +- drivers/cpufreq/amd-pstate-ut.c | 2 + drivers/hwmon/hwmon-vid.c | 4 + drivers/net/vmxnet3/vmxnet3_drv.c | 4 + .../intel/speed_select_if/isst_if_common.c | 1 + drivers/platform/x86/intel/turbo_max_3.c | 1 + 28 files changed, 115 insertions(+), 58 deletions(-) diff --git a/arch/x86/boot/startup/sme.c b/arch/x86/boot/startup/sme.c index 5738b31c8e60..591d6a4d2e59 100644 --- a/arch/x86/boot/startup/sme.c +++ b/arch/x86/boot/startup/sme.c @@ -44,6 +44,7 @@ #include #include #include +#include #define PGD_FLAGS _KERNPG_TABLE_NOENC #define P4D_FLAGS _KERNPG_TABLE_NOENC diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 8970ecef87c5..c39e49cecace 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -3,6 +3,9 @@ #include #include #include +#include +#include + #include "probe.h" enum perf_msr_id { diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index b29b452b1187..53ef48b4c65c 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -17,6 +17,7 @@ #include #include #include +#include /* To enable MSR tracing please use the generic trace points. */ diff --git a/arch/x86/events/probe.c b/arch/x86/events/probe.c index fda35cf25528..bb719d0d3f0b 100644 --- a/arch/x86/events/probe.c +++ b/arch/x86/events/probe.c @@ -2,6 +2,8 @@ #include #include #include + +#include #include "probe.h" static umode_t diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c index 1b8a2415183b..8209de792388 100644 --- a/arch/x86/hyperv/ivm.c +++ b/arch/x86/hyperv/ivm.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #ifdef CONFIG_AMD_MEM_ENCRYPT diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index 2a29e5216881..12b34d5b2953 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -9,6 +9,7 @@ #include #include +#include #include /* diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index 263ea3dd0001..107a1aaa211b 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -2,6 +2,8 @@ #ifndef _ASM_X86_MICROCODE_H #define _ASM_X86_MICROCODE_H +#include + struct cpu_signature { unsigned int sig; unsigned int pf; diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyperv.h index bab5ccfc60a7..15d00dace70f 100644 --- a/arch/x86/include/asm/mshyperv.h +++ b/arch/x86/include/asm/mshyperv.h @@ -8,6 +8,7 @@ #include #include #include +#include #include /* diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 2ccc78ebc3d7..2caa13830e11 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -12,6 +12,7 @@ #include #include +#include #include struct msr_info { @@ -169,60 +170,6 @@ native_write_msr_safe(u32 msr, u32 low, u32 high) extern int rdmsr_safe_regs(u32 regs[8]); extern int wrmsr_safe_regs(u32 regs[8]); -/** - * rdtsc() - returns the current TSC without ordering constraints - * - * rdtsc() returns the result of RDTSC as a 64-bit integer. The - * only ordering constraint it supplies is the ordering implied by - * "asm volatile": it will put the RDTSC in the place you expect. The - * CPU can and will speculatively execute that RDTSC, though, so the - * results can be non-monotonic if compared on different CPUs. - */ -static __always_inline u64 rdtsc(void) -{ - DECLARE_ARGS(val, low, high); - - asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); - - return EAX_EDX_VAL(val, low, high); -} - -/** - * rdtsc_ordered() - read the current TSC in program order - * - * rdtsc_ordered() returns the result of RDTSC as a 64-bit integer. - * It is ordered like a load to a global in-memory counter. It should - * be impossible to observe non-monotonic rdtsc_unordered() behavior - * across multiple CPUs as long as the TSC is synced. - */ -static __always_inline u64 rdtsc_ordered(void) -{ - DECLARE_ARGS(val, low, high); - - /* - * The RDTSC instruction is not ordered relative to memory - * access. The Intel SDM and the AMD APM are both vague on this - * point, but empirically an RDTSC instruction can be - * speculatively executed before prior loads. An RDTSC - * immediately after an appropriate barrier appears to be - * ordered as a normal load, that is, it provides the same - * ordering guarantees as reading from a global memory location - * that some other imaginary CPU is updating continuously with a - * time stamp. - * - * Thus, use the preferred barrier on the respective CPU, aiming for - * RDTSCP as the default. - */ - asm volatile(ALTERNATIVE_2("rdtsc", - "lfence; rdtsc", X86_FEATURE_LFENCE_RDTSC, - "rdtscp", X86_FEATURE_RDTSCP) - : EAX_EDX_RET(val, low, high) - /* RDTSCP clobbers ECX with MSR_TSC_AUX. */ - :: "ecx"); - - return EAX_EDX_VAL(val, low, high); -} - static inline u64 native_read_pmc(int counter) { DECLARE_ARGS(val, low, high); diff --git a/arch/x86/include/asm/suspend_32.h b/arch/x86/include/asm/suspend_32.h index d8416b3bf832..e8e5aab06255 100644 --- a/arch/x86/include/asm/suspend_32.h +++ b/arch/x86/include/asm/suspend_32.h @@ -9,6 +9,7 @@ #include #include +#include /* image of the saved processor state */ struct saved_context { diff --git a/arch/x86/include/asm/suspend_64.h b/arch/x86/include/asm/suspend_64.h index 54df06687d83..b512f9665f78 100644 --- a/arch/x86/include/asm/suspend_64.h +++ b/arch/x86/include/asm/suspend_64.h @@ -9,6 +9,7 @@ #include #include +#include /* * Image of the saved processor state, used by the low level ACPI suspend to diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h index 75248546403d..4f21df7af715 100644 --- a/arch/x86/include/asm/switch_to.h +++ b/arch/x86/include/asm/switch_to.h @@ -52,6 +52,8 @@ do { \ } while (0) #ifdef CONFIG_X86_32 +#include + static inline void refresh_sysenter_cs(struct thread_struct *thread) { /* Only happens when SEP is enabled, no need to test "SEP"arately: */ diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index 94408a784c8e..13335a130edf 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -7,7 +7,81 @@ #include #include -#include + +/* + * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" + * constraint has different meanings. For i386, "A" means exactly + * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, + * it means rax *or* rdx. + */ +#ifdef CONFIG_X86_64 +/* Using 64-bit values saves one instruction clearing the high half of low */ +#define DECLARE_ARGS(val, low, high) unsigned long low, high +#define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32) +#define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) +#else +#define DECLARE_ARGS(val, low, high) u64 val +#define EAX_EDX_VAL(val, low, high) (val) +#define EAX_EDX_RET(val, low, high) "=A" (val) +#endif + +/** + * rdtsc() - returns the current TSC without ordering constraints + * + * rdtsc() returns the result of RDTSC as a 64-bit integer. The + * only ordering constraint it supplies is the ordering implied by + * "asm volatile": it will put the RDTSC in the place you expect. The + * CPU can and will speculatively execute that RDTSC, though, so the + * results can be non-monotonic if compared on different CPUs. + */ +static __always_inline u64 rdtsc(void) +{ + DECLARE_ARGS(val, low, high); + + asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); + + return EAX_EDX_VAL(val, low, high); +} + +/** + * rdtsc_ordered() - read the current TSC in program order + * + * rdtsc_ordered() returns the result of RDTSC as a 64-bit integer. + * It is ordered like a load to a global in-memory counter. It should + * be impossible to observe non-monotonic rdtsc_unordered() behavior + * across multiple CPUs as long as the TSC is synced. + */ +static __always_inline u64 rdtsc_ordered(void) +{ + DECLARE_ARGS(val, low, high); + + /* + * The RDTSC instruction is not ordered relative to memory + * access. The Intel SDM and the AMD APM are both vague on this + * point, but empirically an RDTSC instruction can be + * speculatively executed before prior loads. An RDTSC + * immediately after an appropriate barrier appears to be + * ordered as a normal load, that is, it provides the same + * ordering guarantees as reading from a global memory location + * that some other imaginary CPU is updating continuously with a + * time stamp. + * + * Thus, use the preferred barrier on the respective CPU, aiming for + * RDTSCP as the default. + */ + asm volatile(ALTERNATIVE_2("rdtsc", + "lfence; rdtsc", X86_FEATURE_LFENCE_RDTSC, + "rdtscp", X86_FEATURE_RDTSCP) + : EAX_EDX_RET(val, low, high) + /* RDTSCP clobbers ECX with MSR_TSC_AUX. */ + :: "ecx"); + + return EAX_EDX_VAL(val, low, high); +} + +#undef DECLARE_ARGS +#undef EAX_EDX_VAL +#undef EAX_EDX_RET /* * Standard way to access the cycle counter. diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c index 2a82eb6a0376..26c354bdea07 100644 --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "../../events/perf_event.h" /* For X86_CONFIG() */ #include "internal.h" diff --git a/arch/x86/kernel/fpu/xstate.h b/arch/x86/kernel/fpu/xstate.h index a3b7dcbdb060..52ce19289989 100644 --- a/arch/x86/kernel/fpu/xstate.h +++ b/arch/x86/kernel/fpu/xstate.h @@ -5,6 +5,7 @@ #include #include #include +#include #ifdef CONFIG_X86_64 DECLARE_PER_CPU(u64, xfd_state); diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index cc5d12232216..c9982a7c9536 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -12,6 +12,7 @@ #include #include #include +#include #undef pr_fmt #define pr_fmt(fmt) "hpet: " fmt diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 24e1ccf22912..cfa9c031de91 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -57,6 +57,7 @@ #include #include #include +#include #ifdef CONFIG_IA32_EMULATION /* Not included via unistd.h */ #include diff --git a/arch/x86/kernel/trace_clock.c b/arch/x86/kernel/trace_clock.c index b8e7abe00b06..708d61743d15 100644 --- a/arch/x86/kernel/trace_clock.c +++ b/arch/x86/kernel/trace_clock.c @@ -4,7 +4,7 @@ */ #include #include -#include +#include /* * trace_clock_x86_tsc(): A clock that is just the cycle counter. diff --git a/arch/x86/kernel/tsc_sync.c b/arch/x86/kernel/tsc_sync.c index f1c7a86dbf49..ec3aa340d351 100644 --- a/arch/x86/kernel/tsc_sync.c +++ b/arch/x86/kernel/tsc_sync.c @@ -21,6 +21,7 @@ #include #include #include +#include #include struct tsc_adjust { diff --git a/arch/x86/lib/kaslr.c b/arch/x86/lib/kaslr.c index a58f451a7dd3..b5893928d55c 100644 --- a/arch/x86/lib/kaslr.c +++ b/arch/x86/lib/kaslr.c @@ -8,7 +8,7 @@ */ #include #include -#include +#include #include #include #include diff --git a/arch/x86/realmode/init.c b/arch/x86/realmode/init.c index 263787b4800c..ed5c63c0b4e5 100644 --- a/arch/x86/realmode/init.c +++ b/arch/x86/realmode/init.c @@ -9,6 +9,7 @@ #include #include #include +#include #include struct real_mode_header *real_mode_header; diff --git a/drivers/acpi/processor_perflib.c b/drivers/acpi/processor_perflib.c index 53996f1a2d80..64b8d1e19594 100644 --- a/drivers/acpi/processor_perflib.c +++ b/drivers/acpi/processor_perflib.c @@ -20,6 +20,7 @@ #include #ifdef CONFIG_X86 #include +#include #endif #define ACPI_PROCESSOR_FILE_PERFORMANCE "performance" diff --git a/drivers/acpi/processor_throttling.c b/drivers/acpi/processor_throttling.c index 00d045e5f524..8482e9a8a7aa 100644 --- a/drivers/acpi/processor_throttling.c +++ b/drivers/acpi/processor_throttling.c @@ -18,9 +18,10 @@ #include #include #include +#include #include #include -#include +#include /* ignore_tpc: * 0 -> acpi processor driver doesn't ignore _TPC values diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-ut.c index 707fa81c749f..c8d031b297d2 100644 --- a/drivers/cpufreq/amd-pstate-ut.c +++ b/drivers/cpufreq/amd-pstate-ut.c @@ -31,6 +31,8 @@ #include +#include + #include "amd-pstate.h" diff --git a/drivers/hwmon/hwmon-vid.c b/drivers/hwmon/hwmon-vid.c index 6d1175a51832..2df4956296ed 100644 --- a/drivers/hwmon/hwmon-vid.c +++ b/drivers/hwmon/hwmon-vid.c @@ -15,6 +15,10 @@ #include #include +#ifdef CONFIG_X86 +#include +#endif + /* * Common code for decoding VID pins. * diff --git a/drivers/net/vmxnet3/vmxnet3_drv.c b/drivers/net/vmxnet3/vmxnet3_drv.c index 3df6aabc7e33..7edd0b5e0e77 100644 --- a/drivers/net/vmxnet3/vmxnet3_drv.c +++ b/drivers/net/vmxnet3/vmxnet3_drv.c @@ -27,6 +27,10 @@ #include #include +#ifdef CONFIG_X86 +#include +#endif + #include "vmxnet3_int.h" #include "vmxnet3_xdp.h" diff --git a/drivers/platform/x86/intel/speed_select_if/isst_if_common.c b/drivers/platform/x86/intel/speed_select_if/isst_if_common.c index 44dcd165b4c0..8a5713593811 100644 --- a/drivers/platform/x86/intel/speed_select_if/isst_if_common.c +++ b/drivers/platform/x86/intel/speed_select_if/isst_if_common.c @@ -21,6 +21,7 @@ #include #include +#include #include "isst_if_common.h" diff --git a/drivers/platform/x86/intel/turbo_max_3.c b/drivers/platform/x86/intel/turbo_max_3.c index 7e538bbd5b50..b5af3e91ba04 100644 --- a/drivers/platform/x86/intel/turbo_max_3.c +++ b/drivers/platform/x86/intel/turbo_max_3.c @@ -17,6 +17,7 @@ #include #include +#include #define MSR_OC_MAILBOX 0x150 #define MSR_OC_MAILBOX_CMD_OFFSET 32 From patchwork Tue Apr 22 08:21:43 2025 Content-Type: text/plain; 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Tue, 22 Apr 2025 01:22:24 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53M8MG9G1954391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745310146; bh=IoPTRGWe2Y3cj4mu9rrTWSQjJVT8gGehrwqKDjIdcAQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=b1z8RlaqquIXeYBqIgAy+u/r/q47lKeO8pCBYXjerdwtNfjtGgxePxuKRH1G8q7Eg 3yr5aijpEOpIzQRR4VI95BAlBgsgxvAjMKpeoxc8AmYPQDI2WH7ESLigIPAoWSaJha lTiBdiyZXvX61dgoYdVd4h8eAdxh5SIPVz3MC8rQW9bkPs5PakJ7J11JQ1LIEovXF5 OE/aPM5jxUO7eRx2T5+gGxwuzqRYYxNf0xIOCyXWR6eEAXQ6FBb9vzoj5U+Lt3CyAd D4Pxs/8oSukBmPJ9BE/q/qb5j/rNcjBlzuv/7Iw8PZHjSubwTAJSuLzuPx2ys04J8n xkcnr5QGmv2YA== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Subject: [RFC PATCH v2 02/34] x86/msr: Remove rdpmc() Date: Tue, 22 Apr 2025 01:21:43 -0700 Message-ID: <20250422082216.1954310-3-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250422082216.1954310-1-xin@zytor.com> References: <20250422082216.1954310-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 rdpmc() is not used anywhere, remove it. Signed-off-by: Xin Li (Intel) --- arch/x86/include/asm/msr.h | 7 ------- arch/x86/include/asm/paravirt.h | 7 ------- 2 files changed, 14 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 2caa13830e11..e05466e486fc 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -234,13 +234,6 @@ static inline int rdmsrq_safe(u32 msr, u64 *p) return err; } -#define rdpmc(counter, low, high) \ -do { \ - u64 _l = native_read_pmc((counter)); \ - (low) = (u32)_l; \ - (high) = (u32)(_l >> 32); \ -} while (0) - #define rdpmcl(counter, val) ((val) = native_read_pmc(counter)) #endif /* !CONFIG_PARAVIRT_XXL */ diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h index 86a77528792d..c4dedb984735 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -244,13 +244,6 @@ static inline u64 paravirt_read_pmc(int counter) return PVOP_CALL1(u64, cpu.read_pmc, counter); } -#define rdpmc(counter, low, high) \ -do { \ - u64 _l = paravirt_read_pmc(counter); \ - low = (u32)_l; \ - high = _l >> 32; \ -} while (0) - #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter)) static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) From patchwork Tue Apr 22 08:21:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xin Li \(Intel\)" X-Patchwork-Id: 883447 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E22626B0A9; Tue, 22 Apr 2025 08:24:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745310245; cv=none; b=JVvA/V/rOeJ/djcbZfLI7IHnpGSmnXHWdhrNgLqsRhzD8n53oqhITlESqF8WfBecgSe0rvyLmyxvIQwC8x/B8yd8i5p/raxgOzQI4Ni8F5RGU0rGKR6eD4ygUeKnbYzvmo8x2bAr/U3R/CSbe/4FgiOzX/jpE0Y0zW2WVgf5vhc= ARC-Message-Signature: i=1; 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Tue, 22 Apr 2025 01:22:31 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53M8MG9J1954391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745310152; bh=2fX9OBA6uAgolGV2mwCjcajGTCrZX3UzmQx9++m7S8w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DWloroeBI0Xco+1f4PQTeYOR+vYxwQ6OWrLvdsoNKKSO7CBjg/hE29Yiga1DMWA6a 3vjJgLMxR6/Kq1B4f3AtI2es9FoJ5qy02eFKKKI96lyZVVL8RDLAlkYglcv8alS0Qf WcSregt3TEEKdcYBIPtoG6YGq2XfT7SY3xWvzXDaQnXgzRD4xy21W88jQ5y3uEu7b6 1pQ93SrdhPxcmqTgXqXEgwbVpDt1UW0nZ3vhjRNRm4Bz3ilkQ2KvD4xwcW5uo/xdRZ iWqoZnPrxYn/rhNZ4bGCGPJoZdnXc9udd1Mjqp99UFtk+G5UJNIl0iraeMYyl4BFtQ 7iVfP7LKBPL8Q== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Subject: [RFC PATCH v2 05/34] x86/msr: Return u64 consistently in Xen PMC read functions Date: Tue, 22 Apr 2025 01:21:46 -0700 Message-ID: <20250422082216.1954310-6-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250422082216.1954310-1-xin@zytor.com> References: <20250422082216.1954310-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The pv_ops PMC read API is defined as: u64 (*read_pmc)(int counter); But Xen PMC read functions return unsigned long long, make them return u64 consistently. Signed-off-by: Xin Li (Intel) --- arch/x86/xen/pmu.c | 6 +++--- arch/x86/xen/xen-ops.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c index f06987b0efc3..9c1682af620a 100644 --- a/arch/x86/xen/pmu.c +++ b/arch/x86/xen/pmu.c @@ -346,7 +346,7 @@ bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err) return true; } -static unsigned long long xen_amd_read_pmc(int counter) +static u64 xen_amd_read_pmc(int counter) { struct xen_pmu_amd_ctxt *ctxt; uint64_t *counter_regs; @@ -366,7 +366,7 @@ static unsigned long long xen_amd_read_pmc(int counter) return counter_regs[counter]; } -static unsigned long long xen_intel_read_pmc(int counter) +static u64 xen_intel_read_pmc(int counter) { struct xen_pmu_intel_ctxt *ctxt; uint64_t *fixed_counters; @@ -396,7 +396,7 @@ static unsigned long long xen_intel_read_pmc(int counter) return arch_cntr_pair[counter].counter; } -unsigned long long xen_read_pmc(int counter) +u64 xen_read_pmc(int counter) { if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) return xen_amd_read_pmc(counter); diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h index 25e318ef27d6..dc886c3cc24d 100644 --- a/arch/x86/xen/xen-ops.h +++ b/arch/x86/xen/xen-ops.h @@ -274,7 +274,7 @@ static inline void xen_pmu_finish(int cpu) {} bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err); bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err); int pmu_apic_update(uint32_t reg); -unsigned long long xen_read_pmc(int counter); +u64 xen_read_pmc(int counter); #ifdef CONFIG_SMP From patchwork Tue Apr 22 08:21:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xin Li \(Intel\)" X-Patchwork-Id: 883462 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 714231F0E34; Tue, 22 Apr 2025 08:23:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="hcEX0Oma" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 53M8MG9K1954391 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Tue, 22 Apr 2025 01:22:33 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53M8MG9K1954391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745310154; bh=hH40dRMC8icMs0Kq/gRLpfnhusccGZZqYtPjziXUIq0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hcEX0Oma3CVnkwxqS8bKBIm18tqvV7335h9MWMF4E8wAMoT4z1itaFgVa2bu1H7Lv Ga+u823XXqz9EiWUYA9XlCQeHFfgScC5iggnF6WJwS4CQfGeYOy+x+oIvnckcTBzB6 8V7NP2nGUmfkFx31xOhz6KwJe5WcJid/C9tfwl98yFuEFykSa3egLEr8WStBfP/6oh K8ADOv9Wdb6X6GRIlWoxPenpyB34mw1V1qvbQ8zIfGnVmMda21cc2+p+ghtOaC0a2V V8nAVloDomWCJYiVBeBOXpRIQBAsncCQrgBQ+uMQZJ1te/DZTdjVSMkiakmJECg5VO psDTTjszTfsAw== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Subject: [RFC PATCH v2 06/34] x86/msr: Use the alternatives mechanism to read PMC Date: Tue, 22 Apr 2025 01:21:47 -0700 Message-ID: <20250422082216.1954310-7-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250422082216.1954310-1-xin@zytor.com> References: <20250422082216.1954310-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 To eliminate the indirect call overhead introduced by the pv_ops API, use the alternatives mechanism to read PMC: 1) When built with !CONFIG_XEN_PV, X86_FEATURE_XENPV becomes a disabled feature, preventing the Xen PMC read code from being built and ensuring the native code is executed unconditionally. 2) When built with CONFIG_XEN_PV: 2.1) If not running on the Xen hypervisor (!X86_FEATURE_XENPV), the kernel runtime binary is patched to unconditionally jump to the native PMC read code. 2.2) If running on the Xen hypervisor (X86_FEATURE_XENPV), the kernel runtime binary is patched to unconditionally jump to the Xen PMC read code. Consequently, remove the pv_ops PMC read API. Signed-off-by: Xin Li (Intel) --- arch/x86/include/asm/msr.h | 31 ++++++++++++++++++++------- arch/x86/include/asm/paravirt.h | 5 ----- arch/x86/include/asm/paravirt_types.h | 2 -- arch/x86/kernel/paravirt.c | 1 - arch/x86/xen/enlighten_pv.c | 2 -- drivers/net/vmxnet3/vmxnet3_drv.c | 2 +- 6 files changed, 24 insertions(+), 19 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 01dc8e61ef97..33cf506e2fd6 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -73,6 +74,10 @@ static inline void do_trace_read_msr(u32 msr, u64 val, int failed) {} static inline void do_trace_rdpmc(u32 msr, u64 val, int failed) {} #endif +#ifdef CONFIG_XEN_PV +extern u64 xen_read_pmc(int counter); +#endif + /* * __rdmsr() and __wrmsr() are the two primitives which are the bare minimum MSR * accessors and should not have any tracing or other functionality piggybacking @@ -170,16 +175,32 @@ native_write_msr_safe(u32 msr, u32 low, u32 high) extern int rdmsr_safe_regs(u32 regs[8]); extern int wrmsr_safe_regs(u32 regs[8]); -static inline u64 native_read_pmc(int counter) +static __always_inline u64 native_rdpmcq(int counter) { DECLARE_ARGS(val, low, high); - asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); + asm_inline volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); + if (tracepoint_enabled(rdpmc)) do_trace_rdpmc(counter, EAX_EDX_VAL(val, low, high), 0); + return EAX_EDX_VAL(val, low, high); } +static __always_inline u64 rdpmcq(int counter) +{ +#ifdef CONFIG_XEN_PV + if (cpu_feature_enabled(X86_FEATURE_XENPV)) + return xen_read_pmc(counter); +#endif + + /* + * 1) When built with !CONFIG_XEN_PV. + * 2) When built with CONFIG_XEN_PV but not running on Xen hypervisor. + */ + return native_rdpmcq(counter); +} + #ifdef CONFIG_PARAVIRT_XXL #include #else @@ -233,12 +254,6 @@ static inline int rdmsrq_safe(u32 msr, u64 *p) *p = native_read_msr_safe(msr, &err); return err; } - -static __always_inline u64 rdpmcq(int counter) -{ - return native_read_pmc(counter); -} - #endif /* !CONFIG_PARAVIRT_XXL */ /* Instruction opcode for WRMSRNS supported in binutils >= 2.40 */ diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h index 590824916394..c7689f5f70d6 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -239,11 +239,6 @@ static inline int rdmsrq_safe(unsigned msr, u64 *p) return err; } -static __always_inline u64 rdpmcq(int counter) -{ - return PVOP_CALL1(u64, cpu.read_pmc, counter); -} - static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) { PVOP_VCALL2(cpu.alloc_ldt, ldt, entries); diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h index 631c306ce1ff..475f508531d6 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -101,8 +101,6 @@ struct pv_cpu_ops { u64 (*read_msr_safe)(unsigned int msr, int *err); int (*write_msr_safe)(unsigned int msr, unsigned low, unsigned high); - u64 (*read_pmc)(int counter); - void (*start_context_switch)(struct task_struct *prev); void (*end_context_switch)(struct task_struct *next); #endif diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 1ccd05d8999f..28d195ad7514 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -132,7 +132,6 @@ struct paravirt_patch_template pv_ops = { .cpu.write_msr = native_write_msr, .cpu.read_msr_safe = native_read_msr_safe, .cpu.write_msr_safe = native_write_msr_safe, - .cpu.read_pmc = native_read_pmc, .cpu.load_tr_desc = native_load_tr_desc, .cpu.set_ldt = native_set_ldt, .cpu.load_gdt = native_load_gdt, diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 846b5737d320..9fbe187aff00 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -1236,8 +1236,6 @@ static const typeof(pv_ops) xen_cpu_ops __initconst = { .read_msr_safe = xen_read_msr_safe, .write_msr_safe = xen_write_msr_safe, - .read_pmc = xen_read_pmc, - .load_tr_desc = paravirt_nop, .set_ldt = xen_set_ldt, .load_gdt = xen_load_gdt, diff --git a/drivers/net/vmxnet3/vmxnet3_drv.c b/drivers/net/vmxnet3/vmxnet3_drv.c index 7edd0b5e0e77..8af3b4d7ef4d 100644 --- a/drivers/net/vmxnet3/vmxnet3_drv.c +++ b/drivers/net/vmxnet3/vmxnet3_drv.c @@ -151,7 +151,7 @@ static u64 vmxnet3_get_cycles(int pmc) { #ifdef CONFIG_X86 - return native_read_pmc(pmc); + return native_rdpmcq(pmc); #else return 0; #endif From patchwork Tue Apr 22 08:21:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xin Li \(Intel\)" X-Patchwork-Id: 883452 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B1A5265610; Tue, 22 Apr 2025 08:23:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745310240; cv=none; b=PrLEIughFgrHEFmv0HnupyTSCWQW9b8uLkOppOjmp/iQINeffGyrPjCu2IHmFHSqDRbRdAamcqUwSvuMzsM4p5VSBxFngmd/mYIT9gRz6SRfNXwWjtxcKaF3hPQrhJPqFd7paWiuTmk7fJrPQJ28iX/A0cbmdxJ1Obhn1RFlC1k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745310240; c=relaxed/simple; bh=3Pqdz91wOPtPj7Rvl434EYhKe9LHGfmQ+A4+fcS+M4M=; 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Tue, 22 Apr 2025 01:22:49 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53M8MG9S1954391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745310171; bh=tgzUrlRfHVNmuhey2aHHRIY5ipoKFEwgpjfhEzZ9bZY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cSUq20FJ1es+IIhRb98fV1d5F5NvXSUm1EMpz1+tO0YnVvnuTJaFjsStronse55k5 YxZtOYxcfkDzQLV4kClq6Bh9fQSG39eicOmoWqumnSOinsUbwn6q998dOSYad0zsE1 XTVUr6fpYzuVa8qpsuccsUw3Ow+s/jyBTD5r2pg0D9UWVh301tVKqpsTK+wFXOiuaD N0eQT6AhQXD63t318ErncqLrfB5Jcz79t3Isvxia9piGM6jDV7ZfMM3vN8awrIAAmE baBmekkbHBPV6QEgBNF1TdwtwUqOlgXwgXJkAJ4oGprjAmWEMzvfq69Je187jfLeDB aWRCULSzY6RQw== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Subject: [RFC PATCH v2 14/34] x86/msr: refactor pv_cpu_ops.write_msr{_safe}() Date: Tue, 22 Apr 2025 01:21:55 -0700 Message-ID: <20250422082216.1954310-15-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250422082216.1954310-1-xin@zytor.com> References: <20250422082216.1954310-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 An MSR value is represented as a 64-bit unsigned integer, with existing MSR instructions storing it in EDX:EAX as two 32-bit segments. The new immediate form MSR instructions, however, utilize a 64-bit general-purpose register to store the MSR value. To unify the usage of all MSR instructions, let the default MSR access APIs accept an MSR value as a single 64-bit argument instead of two 32-bit segments. The dual 32-bit APIs are still available as convenient wrappers over the APIs that handle an MSR value as a single 64-bit argument. The following illustrates the updated derivation of the MSR write APIs: __wrmsrq(u32 msr, u64 val) / \ / \ native_wrmsrq(msr, val) native_wrmsr(msr, low, high) | | native_write_msr(msr, val) / \ / \ wrmsrq(msr, val) wrmsr(msr, low, high) When CONFIG_PARAVIRT is enabled, wrmsrq() and wrmsr() are defined on top of paravirt_write_msr(): paravirt_write_msr(u32 msr, u64 val) / \ / \ wrmsrq(msr, val) wrmsr(msr, low, high) paravirt_write_msr() invokes cpu.write_msr(msr, val), an indirect layer of pv_ops MSR write call: If on native: cpu.write_msr = native_write_msr If on Xen: cpu.write_msr = xen_write_msr Therefore, refactor pv_cpu_ops.write_msr{_safe}() to accept an MSR value in a single u64 argument, replacing the current dual u32 arguments. No functional change intended. Signed-off-by: Xin Li (Intel) --- Change in v2: * Spell out the reason why use a single u64 argument to pass the MSR value in the lowest level APIs (Andrew Cooper). --- arch/x86/include/asm/msr.h | 35 ++++++++++++--------------- arch/x86/include/asm/paravirt.h | 27 +++++++++++---------- arch/x86/include/asm/paravirt_types.h | 4 +-- arch/x86/kernel/kvmclock.c | 2 +- arch/x86/kvm/svm/svm.c | 15 +++--------- arch/x86/xen/enlighten_pv.c | 29 +++++++++------------- 6 files changed, 46 insertions(+), 66 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 2ab8effea4cd..dd1114053173 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -97,12 +97,12 @@ static __always_inline u64 __rdmsr(u32 msr) return EAX_EDX_VAL(val, low, high); } -static __always_inline void __wrmsr(u32 msr, u32 low, u32 high) +static __always_inline void __wrmsrq(u32 msr, u64 val) { asm volatile("1: wrmsr\n" "2:\n" _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR) - : : "c" (msr), "a"(low), "d" (high) : "memory"); + : : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32)) : "memory"); } #define native_rdmsr(msr, val1, val2) \ @@ -118,11 +118,10 @@ static __always_inline u64 native_rdmsrq(u32 msr) } #define native_wrmsr(msr, low, high) \ - __wrmsr(msr, low, high) + __wrmsrq((msr), (u64)(high) << 32 | (low)) #define native_wrmsrq(msr, val) \ - __wrmsr((msr), (u32)((u64)(val)), \ - (u32)((u64)(val) >> 32)) + __wrmsrq((msr), (val)) static inline u64 native_read_msr(u32 msr) { @@ -151,11 +150,8 @@ static inline u64 native_read_msr_safe(u32 msr, int *err) } /* Can be uninlined because referenced by paravirt */ -static inline void notrace -native_write_msr(u32 msr, u32 low, u32 high) +static inline void notrace native_write_msr(u32 msr, u64 val) { - u64 val = (u64)high << 32 | low; - native_wrmsrq(msr, val); if (tracepoint_enabled(write_msr)) @@ -163,8 +159,7 @@ native_write_msr(u32 msr, u32 low, u32 high) } /* Can be uninlined because referenced by paravirt */ -static inline int notrace -native_write_msr_safe(u32 msr, u32 low, u32 high) +static inline int notrace native_write_msr_safe(u32 msr, u64 val) { int err; @@ -172,10 +167,10 @@ native_write_msr_safe(u32 msr, u32 low, u32 high) "2:\n\t" _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_WRMSR_SAFE, %[err]) : [err] "=a" (err) - : "c" (msr), "0" (low), "d" (high) + : "c" (msr), "0" ((u32)val), "d" ((u32)(val >> 32)) : "memory"); if (tracepoint_enabled(write_msr)) - do_trace_write_msr(msr, ((u64)high << 32 | low), err); + do_trace_write_msr(msr, val, err); return err; } @@ -227,7 +222,7 @@ do { \ static inline void wrmsr(u32 msr, u32 low, u32 high) { - native_write_msr(msr, low, high); + native_write_msr(msr, (u64)high << 32 | low); } #define rdmsrq(msr, val) \ @@ -235,13 +230,13 @@ static inline void wrmsr(u32 msr, u32 low, u32 high) static inline void wrmsrq(u32 msr, u64 val) { - native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32)); + native_write_msr(msr, val); } /* wrmsr with exception handling */ -static inline int wrmsr_safe(u32 msr, u32 low, u32 high) +static inline int wrmsrq_safe(u32 msr, u64 val) { - return native_write_msr_safe(msr, low, high); + return native_write_msr_safe(msr, val); } /* rdmsr with exception handling */ @@ -279,11 +274,11 @@ static __always_inline void wrmsrns(u32 msr, u64 val) } /* - * 64-bit version of wrmsr_safe(): + * Dual u32 version of wrmsrq_safe(): */ -static inline int wrmsrq_safe(u32 msr, u64 val) +static inline int wrmsr_safe(u32 msr, u32 low, u32 high) { - return wrmsr_safe(msr, (u32)val, (u32)(val >> 32)); + return wrmsrq_safe(msr, (u64)high << 32 | low); } struct msr __percpu *msrs_alloc(void); diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h index c7689f5f70d6..1bd1dad8da5a 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -180,10 +180,9 @@ static inline u64 paravirt_read_msr(unsigned msr) return PVOP_CALL1(u64, cpu.read_msr, msr); } -static inline void paravirt_write_msr(unsigned msr, - unsigned low, unsigned high) +static inline void paravirt_write_msr(u32 msr, u64 val) { - PVOP_VCALL3(cpu.write_msr, msr, low, high); + PVOP_VCALL2(cpu.write_msr, msr, val); } static inline u64 paravirt_read_msr_safe(unsigned msr, int *err) @@ -191,10 +190,9 @@ static inline u64 paravirt_read_msr_safe(unsigned msr, int *err) return PVOP_CALL2(u64, cpu.read_msr_safe, msr, err); } -static inline int paravirt_write_msr_safe(unsigned msr, - unsigned low, unsigned high) +static inline int paravirt_write_msr_safe(u32 msr, u64 val) { - return PVOP_CALL3(int, cpu.write_msr_safe, msr, low, high); + return PVOP_CALL2(int, cpu.write_msr_safe, msr, val); } #define rdmsr(msr, val1, val2) \ @@ -204,22 +202,25 @@ do { \ val2 = _l >> 32; \ } while (0) -#define wrmsr(msr, val1, val2) \ -do { \ - paravirt_write_msr(msr, val1, val2); \ -} while (0) +static __always_inline void wrmsr(u32 msr, u32 low, u32 high) +{ + paravirt_write_msr(msr, (u64)high << 32 | low); +} #define rdmsrq(msr, val) \ do { \ val = paravirt_read_msr(msr); \ } while (0) -static inline void wrmsrq(unsigned msr, u64 val) +static inline void wrmsrq(u32 msr, u64 val) { - wrmsr(msr, (u32)val, (u32)(val>>32)); + paravirt_write_msr(msr, val); } -#define wrmsr_safe(msr, a, b) paravirt_write_msr_safe(msr, a, b) +static inline int wrmsrq_safe(u32 msr, u64 val) +{ + return paravirt_write_msr_safe(msr, val) +} /* rdmsr with exception handling */ #define rdmsr_safe(msr, a, b) \ diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h index 475f508531d6..91b3423d36ce 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -92,14 +92,14 @@ struct pv_cpu_ops { /* Unsafe MSR operations. These will warn or panic on failure. */ u64 (*read_msr)(unsigned int msr); - void (*write_msr)(unsigned int msr, unsigned low, unsigned high); + void (*write_msr)(u32 msr, u64 val); /* * Safe MSR operations. * read sets err to 0 or -EIO. write returns 0 or -EIO. */ u64 (*read_msr_safe)(unsigned int msr, int *err); - int (*write_msr_safe)(unsigned int msr, unsigned low, unsigned high); + int (*write_msr_safe)(u32 msr, u64 val); void (*start_context_switch)(struct task_struct *prev); void (*end_context_switch)(struct task_struct *next); diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c index 0af797930ccb..ca0a49eeac4a 100644 --- a/arch/x86/kernel/kvmclock.c +++ b/arch/x86/kernel/kvmclock.c @@ -196,7 +196,7 @@ static void kvm_setup_secondary_clock(void) void kvmclock_disable(void) { if (msr_kvm_system_time) - native_write_msr(msr_kvm_system_time, 0, 0); + native_write_msr(msr_kvm_system_time, 0); } static void __init kvmclock_init_mem(void) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 67657b3a36ce..4ef9978dce70 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -475,7 +475,6 @@ static void svm_inject_exception(struct kvm_vcpu *vcpu) static void svm_init_erratum_383(void) { - u32 low, high; int err; u64 val; @@ -489,10 +488,7 @@ static void svm_init_erratum_383(void) val |= (1ULL << 47); - low = lower_32_bits(val); - high = upper_32_bits(val); - - native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); + native_write_msr_safe(MSR_AMD64_DC_CFG, val); erratum_383_found = true; } @@ -2167,17 +2163,12 @@ static bool is_erratum_383(void) /* Clear MCi_STATUS registers */ for (i = 0; i < 6; ++i) - native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); + native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0); value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); if (!err) { - u32 low, high; - value &= ~(1ULL << 2); - low = lower_32_bits(value); - high = upper_32_bits(value); - - native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); + native_write_msr_safe(MSR_IA32_MCG_STATUS, value); } /* Flush tlb to evict multi-match entries */ diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 9a89cb29fa35..052f68c92111 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -1111,10 +1111,8 @@ static u64 xen_do_read_msr(unsigned int msr, int *err) return val; } -static void set_seg(u32 which, u32 low, u32 high) +static void set_seg(u32 which, u64 base) { - u64 base = ((u64)high << 32) | low; - if (HYPERVISOR_set_segment_base(which, base)) WARN(1, "Xen set_segment_base(%u, %llx) failed\n", which, base); } @@ -1124,23 +1122,21 @@ static void set_seg(u32 which, u32 low, u32 high) * With err == NULL write_msr() semantics are selected. * Supplying an err pointer requires err to be pre-initialized with 0. */ -static void xen_do_write_msr(unsigned int msr, unsigned int low, - unsigned int high, int *err) +static void xen_do_write_msr(u32 msr, u64 val, int *err) { - u64 val; bool emulated; switch (msr) { case MSR_FS_BASE: - set_seg(SEGBASE_FS, low, high); + set_seg(SEGBASE_FS, val); break; case MSR_KERNEL_GS_BASE: - set_seg(SEGBASE_GS_USER, low, high); + set_seg(SEGBASE_GS_USER, val); break; case MSR_GS_BASE: - set_seg(SEGBASE_GS_KERNEL, low, high); + set_seg(SEGBASE_GS_KERNEL, val); break; case MSR_STAR: @@ -1156,15 +1152,13 @@ static void xen_do_write_msr(unsigned int msr, unsigned int low, break; default: - val = (u64)high << 32 | low; - if (pmu_msr_chk_emulated(msr, &val, false, &emulated) && emulated) return; if (err) - *err = native_write_msr_safe(msr, low, high); + *err = native_write_msr_safe(msr, val); else - native_write_msr(msr, low, high); + native_write_msr(msr, val); } } @@ -1173,12 +1167,11 @@ static u64 xen_read_msr_safe(unsigned int msr, int *err) return xen_do_read_msr(msr, err); } -static int xen_write_msr_safe(unsigned int msr, unsigned int low, - unsigned int high) +static int xen_write_msr_safe(u32 msr, u64 val) { int err = 0; - xen_do_write_msr(msr, low, high, &err); + xen_do_write_msr(msr, val, &err); return err; } @@ -1190,11 +1183,11 @@ static u64 xen_read_msr(unsigned int msr) return xen_do_read_msr(msr, xen_msr_safe ? &err : NULL); } -static void xen_write_msr(unsigned int msr, unsigned low, unsigned high) +static void xen_write_msr(u32 msr, u64 val) { int err; - xen_do_write_msr(msr, low, high, xen_msr_safe ? &err : NULL); + xen_do_write_msr(msr, val, xen_msr_safe ? &err : NULL); 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Tue, 22 Apr 2025 01:22:51 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53M8MG9T1954391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745310173; bh=EmAyA4H2zym7MMXbzGaqyeyz7QXZZDV9O+Z4+Oh7wSA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P7TTfABuMHPAhcQRaJGoDAbjaTPcJUAkbZU5kypZHeWS/AMW1L/3K2v2yCDUtHiyF NSHf1DyvbWITNZpDRj5sbGWdR8CvrQ/XCywXQghInGFqOhC2P6JM/YbpnLVao7rZH6 JOvEZQjD0cdY/iFs0oG7WcdBLLgBjXxfuMVsbznGP+03gLNj6TryaD94VK6pPnRQhw Joqd+sPZhGyYu1MUzVX21z1/v/K3WlRsT8j6cO6IkXbUOaOBSw4YNml4XxSFGD01Oa ktEgcbhadMBm/y96Z1Qx2KggyySX9ZJLplswD7wOAepciggZt4HsF7uj0cuZFb4nqI JWhKcTqnwJerg== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Subject: [RFC PATCH v2 15/34] x86/msr: Replace wrmsr(msr, low, 0) with wrmsrq(msr, low) Date: Tue, 22 Apr 2025 01:21:56 -0700 Message-ID: <20250422082216.1954310-16-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250422082216.1954310-1-xin@zytor.com> References: <20250422082216.1954310-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Signed-off-by: Xin Li (Intel) --- arch/x86/hyperv/hv_apic.c | 6 +++--- arch/x86/include/asm/apic.h | 2 +- arch/x86/include/asm/switch_to.h | 2 +- arch/x86/kernel/cpu/amd.c | 2 +- arch/x86/kernel/cpu/common.c | 8 ++++---- arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 4 ++-- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 2 +- arch/x86/kernel/cpu/umwait.c | 4 ++-- arch/x86/kernel/kvm.c | 2 +- 9 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/x86/hyperv/hv_apic.c b/arch/x86/hyperv/hv_apic.c index c450e67cb0a4..4d617ee59377 100644 --- a/arch/x86/hyperv/hv_apic.c +++ b/arch/x86/hyperv/hv_apic.c @@ -75,10 +75,10 @@ static void hv_apic_write(u32 reg, u32 val) { switch (reg) { case APIC_EOI: - wrmsr(HV_X64_MSR_EOI, val, 0); + wrmsrq(HV_X64_MSR_EOI, val); break; case APIC_TASKPRI: - wrmsr(HV_X64_MSR_TPR, val, 0); + wrmsrq(HV_X64_MSR_TPR, val); break; default: native_apic_mem_write(reg, val); @@ -92,7 +92,7 @@ static void hv_apic_eoi_write(void) if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1)) return; - wrmsr(HV_X64_MSR_EOI, APIC_EOI_ACK, 0); + wrmsrq(HV_X64_MSR_EOI, APIC_EOI_ACK); } static bool cpu_is_self(int cpu) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 0174dd548327..68e10e30fe9b 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -209,7 +209,7 @@ static inline void native_apic_msr_write(u32 reg, u32 v) reg == APIC_LVR) return; - wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); + wrmsrq(APIC_BASE_MSR + (reg >> 4), v); } static inline void native_apic_msr_eoi(void) diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h index 4f21df7af715..499b1c15cc8b 100644 --- a/arch/x86/include/asm/switch_to.h +++ b/arch/x86/include/asm/switch_to.h @@ -61,7 +61,7 @@ static inline void refresh_sysenter_cs(struct thread_struct *thread) return; this_cpu_write(cpu_tss_rw.x86_tss.ss1, thread->sysenter_cs); - wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); + wrmsrq(MSR_IA32_SYSENTER_CS, thread->sysenter_cs); } #endif diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 1f7925e45b46..6132a3c529cc 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1206,7 +1206,7 @@ void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr) if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask) return; - wrmsr(amd_msr_dr_addr_masks[dr], mask, 0); + wrmsrq(amd_msr_dr_addr_masks[dr], mask); per_cpu(amd_dr_addr_mask, cpu)[dr] = mask; } diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 10da3da5b81f..99d8a8c15ba5 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2019,9 +2019,9 @@ void enable_sep_cpu(void) */ tss->x86_tss.ss1 = __KERNEL_CS; - wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); - wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); - wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); + wrmsrq(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1); + wrmsrq(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); + wrmsrq(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32); put_cpu(); } @@ -2235,7 +2235,7 @@ static inline void setup_getcpu(int cpu) struct desc_struct d = { }; if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) - wrmsr(MSR_TSC_AUX, cpudata, 0); + wrmsrq(MSR_TSC_AUX, cpudata); /* Store CPU and node number in limit. */ d.limit0 = cpudata; diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c index 185317c6b509..cc534a83f19d 100644 --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c @@ -905,7 +905,7 @@ int resctrl_arch_measure_cycles_lat_fn(void *_plr) * Disable hardware prefetchers. */ rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high); - wrmsr(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits, 0x0); + wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits); mem_r = READ_ONCE(plr->kmem); /* * Dummy execute of the time measurement to load the needed @@ -1001,7 +1001,7 @@ static int measure_residency_fn(struct perf_event_attr *miss_attr, * Disable hardware prefetchers. */ rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high); - wrmsr(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits, 0x0); + wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits); /* Initialize rest of local variables */ /* diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index f4a2ee2a6404..73ed83f1dff8 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1707,7 +1707,7 @@ void resctrl_arch_mon_event_config_write(void *_config_info) pr_warn_once("Invalid event id %d\n", config_info->evtid); return; } - wrmsr(MSR_IA32_EVT_CFG_BASE + index, config_info->mon_config, 0); + wrmsrq(MSR_IA32_EVT_CFG_BASE + index, config_info->mon_config); } static void mbm_config_write_domain(struct rdt_resource *r, diff --git a/arch/x86/kernel/cpu/umwait.c b/arch/x86/kernel/cpu/umwait.c index 0050eae153bb..933fcd7ff250 100644 --- a/arch/x86/kernel/cpu/umwait.c +++ b/arch/x86/kernel/cpu/umwait.c @@ -33,7 +33,7 @@ static DEFINE_MUTEX(umwait_lock); static void umwait_update_control_msr(void * unused) { lockdep_assert_irqs_disabled(); - wrmsr(MSR_IA32_UMWAIT_CONTROL, READ_ONCE(umwait_control_cached), 0); + wrmsrq(MSR_IA32_UMWAIT_CONTROL, READ_ONCE(umwait_control_cached)); } /* @@ -71,7 +71,7 @@ static int umwait_cpu_offline(unsigned int cpu) * the original control MSR value in umwait_init(). So there * is no race condition here. */ - wrmsr(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached, 0); + wrmsrq(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached); return 0; } diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c index 44a45df7200a..bc9d21d7395f 100644 --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -399,7 +399,7 @@ static void kvm_disable_steal_time(void) if (!has_steal_clock) return; - wrmsr(MSR_KVM_STEAL_TIME, 0, 0); + wrmsrq(MSR_KVM_STEAL_TIME, 0); } static u64 kvm_steal_clock(int cpu) From patchwork Tue Apr 22 08:21:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xin Li \(Intel\)" X-Patchwork-Id: 883453 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EFA2264F87; Tue, 22 Apr 2025 08:23:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745310239; cv=none; b=EpocUi1wmSrMIA+N90xjLxtwPSucEjtW6tr7KpiItQLr7WbQO6LfvcsV0VRECkAyvHVT1umwPUMQs2W9wXdpxhnzSjLJgPiF45RL+sEs6Jl/Wi5iSNS4WM5tf6Bnmpvdu1glKOUVJLm3spRGEN9IiAAuA4o+OeAq/qtE/mVUwXs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745310239; c=relaxed/simple; bh=MlzZP2PcWDZrFa9hDnXv30fqYMM04NkLvN5K6Ig/4KA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NYhg7QlYZaThwcjjM9sa68nzxWxD1T/qk2vgnlwi5qz/EKu9AEPPe0L1jvdMiWLEr0Y0YQZ1sL9g2lhzC6Y8rkxZFzr0QUitwXA2mPc0jmf9XciYrDOXz4r/u+pfQlR08bTkUULnMqyGjQJ0hVX5kNbXYUvQ/KlJJOs8Hn7p8x0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com; spf=pass smtp.mailfrom=zytor.com; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b=aNQDlhh2; arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="aNQDlhh2" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 53M8MG9W1954391 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Tue, 22 Apr 2025 01:22:57 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53M8MG9W1954391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745310178; bh=XaAm3SgdeuQpqxiLf3TgiBnvvEMb/sqRjazcaLW8DyU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aNQDlhh2xlWRbyeJukGWTC/vCCeQb6zitL4jNCcMF4/UqfnsnIPrjB234ggYDAm4n /OAUTUCS6m8svXdcAJEjhiXvD0bvb7pxXmCp56esSiGCgBDU/fm2+V6WjpHdn7ALNZ dqP/5qRa1S0+Lp3LRQ3WFTfiGwPFPXzUffyVlWhaYmG78Chtndnv8OFzZqmNpS7l6c ImhtFxmMTaZOLVSxB5DGLhb3HeAISjXz4cKumUDuLcQuWXuj7fm47baKL82vIov6cz 70aPro2cmGmDIDjFIgcRsQs+TcX09RekPiJ/6zWfrES6Aw+7U7SmR69YRnJ8YiJwsn YbU2jKXeJuZUg== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Subject: [RFC PATCH v2 18/34] x86/opcode: Add immediate form MSR instructions Date: Tue, 22 Apr 2025 01:21:59 -0700 Message-ID: <20250422082216.1954310-19-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250422082216.1954310-1-xin@zytor.com> References: <20250422082216.1954310-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the instruction opcodes used by the immediate form WRMSRNS/RDMSR to x86-opcode-map. Signed-off-by: Xin Li (Intel) --- arch/x86/lib/x86-opcode-map.txt | 5 +++-- tools/arch/x86/lib/x86-opcode-map.txt | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index caedb3ef6688..e64f52321d6d 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -839,7 +839,7 @@ f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) | CRC32 Gd,Ew (66&F2) f2: ANDN Gy,By,Ey (v) f3: Grp17 (1A) f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v) | WRUSSD/Q My,Gy (66) -f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD/Q My,Gy +f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD/Q My,Gy | RDMSR Rq,Gq (F2),(11B) | WRMSRNS Gq,Rq (F3),(11B) f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v) f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3) | URDMSR Rq,Gq (F2),(11B) | UWRMSR Gq,Rq (F3),(11B) f9: MOVDIRI My,Gy @@ -1014,7 +1014,7 @@ f1: CRC32 Gy,Ey (es) | CRC32 Gy,Ey (66),(es) | INVVPID Gy,Mdq (F3),(ev) f2: INVPCID Gy,Mdq (F3),(ev) f4: TZCNT Gv,Ev (es) | TZCNT Gv,Ev (66),(es) f5: LZCNT Gv,Ev (es) | LZCNT Gv,Ev (66),(es) -f6: Grp3_1 Eb (1A),(ev) +f6: Grp3_1 Eb (1A),(ev) | RDMSR Rq,Gq (F2),(11B),(ev) | WRMSRNS Gq,Rq (F3),(11B),(ev) f7: Grp3_2 Ev (1A),(es) f8: MOVDIR64B Gv,Mdqq (66),(ev) | ENQCMD Gv,Mdqq (F2),(ev) | ENQCMDS Gv,Mdqq (F3),(ev) | URDMSR Rq,Gq (F2),(11B),(ev) | UWRMSR Gq,Rq (F3),(11B),(ev) f9: MOVDIRI My,Gy (ev) @@ -1103,6 +1103,7 @@ EndTable Table: VEX map 7 Referrer: AVXcode: 7 +f6: RDMSR Rq,Id (F2),(v1),(11B) | WRMSRNS Id,Rq (F3),(v1),(11B) f8: URDMSR Rq,Id (F2),(v1),(11B) | UWRMSR Id,Rq (F3),(v1),(11B) EndTable diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt index caedb3ef6688..e64f52321d6d 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -839,7 +839,7 @@ f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) | CRC32 Gd,Ew (66&F2) f2: ANDN Gy,By,Ey (v) f3: Grp17 (1A) f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v) | WRUSSD/Q My,Gy (66) -f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD/Q My,Gy +f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD/Q My,Gy | RDMSR Rq,Gq (F2),(11B) | WRMSRNS Gq,Rq (F3),(11B) f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v) f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3) | URDMSR Rq,Gq (F2),(11B) | UWRMSR Gq,Rq (F3),(11B) f9: MOVDIRI My,Gy @@ -1014,7 +1014,7 @@ f1: CRC32 Gy,Ey (es) | CRC32 Gy,Ey (66),(es) | INVVPID Gy,Mdq (F3),(ev) f2: INVPCID Gy,Mdq (F3),(ev) f4: TZCNT Gv,Ev (es) | TZCNT Gv,Ev (66),(es) f5: LZCNT Gv,Ev (es) | LZCNT Gv,Ev (66),(es) -f6: Grp3_1 Eb (1A),(ev) +f6: Grp3_1 Eb (1A),(ev) | RDMSR Rq,Gq (F2),(11B),(ev) | WRMSRNS Gq,Rq (F3),(11B),(ev) f7: Grp3_2 Ev (1A),(es) f8: MOVDIR64B Gv,Mdqq (66),(ev) | ENQCMD Gv,Mdqq (F2),(ev) | ENQCMDS Gv,Mdqq (F3),(ev) | URDMSR Rq,Gq (F2),(11B),(ev) | UWRMSR Gq,Rq (F3),(11B),(ev) f9: MOVDIRI My,Gy (ev) @@ -1103,6 +1103,7 @@ EndTable Table: VEX map 7 Referrer: AVXcode: 7 +f6: RDMSR Rq,Id (F2),(v1),(11B) | WRMSRNS Id,Rq (F3),(v1),(11B) f8: URDMSR Rq,Id (F2),(v1),(11B) | UWRMSR Id,Rq (F3),(v1),(11B) EndTable From patchwork Tue Apr 22 08:22:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xin Li \(Intel\)" X-Patchwork-Id: 883460 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD64424888E; Tue, 22 Apr 2025 08:23:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745310230; cv=none; b=IdBjpFyCnkHeFGGWgNQoRgy49aLDlYEzsyrpntVWA88WTNzIk8AGmZVieE6O1VDiaY7P8vrg6bo5RWnb5Fj3Xjmym1Vu4nwBnkA8xRkEbrSbtq9ya5kTp6R5GChtvV9y58pw2PmROzZlHX4dywY5BEfRLRsM36nqLERdGK7dOPQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745310230; c=relaxed/simple; bh=A7Q4uoK84rHePUBM6dp9wvO4znc2GXZoSCPZjM8WRTY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Tue, 22 Apr 2025 01:23:01 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53M8MG9Y1954391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745310183; bh=C6RK2fGRo87/f3fhWDh3Rej6GAV9BaF6uT8JNGWqWns=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BHi1R6AyC9e0eh53/qDzjqBE+qQb4RzEZPU1rW+urzk4SW5zJKcQ990fyyFIzp3Ny +ZO85XRSMlAItHcKxgVVuJ6bIFtxLdCzXCHEgZWwiSSp0I8ycHoE0kJWCt5vzx+Pgh awTbjmxkSsaICsvEZ+f3G2x+NbMFPXt07P3uzry3qjGx+2+6ti08zGvKxuLOJ51QP+ Ze0/EZLEQhvkUUadlbZ9OJhPmV9dDJYOW9+dzQ1lM8BWN9kqIMaDRpHZAdWmrJFL7Y OlvBsHTB19+9i+iy38t2OKh1xVb6wdoxeXiicjINWboz+d3fS/QhnsGL7tMDSnNgRM ZbLi44P9yvsYw== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Subject: [RFC PATCH v2 20/34] x86/extable: Implement EX_TYPE_FUNC_REWIND Date: Tue, 22 Apr 2025 01:22:01 -0700 Message-ID: <20250422082216.1954310-21-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250422082216.1954310-1-xin@zytor.com> References: <20250422082216.1954310-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: "H. Peter Anvin (Intel)" Add a new exception type, which allows emulating an exception as if it had happened at or near the call site of a function. This allows a function call inside an alternative for instruction emulation to "kick back" the exception into the alternatives pattern, possibly invoking a different exception handling pattern there, or at least indicating the "real" location of the fault. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li (Intel) --- arch/x86/include/asm/asm.h | 6 + arch/x86/include/asm/extable_fixup_types.h | 1 + arch/x86/mm/extable.c | 135 +++++++++++++-------- 3 files changed, 91 insertions(+), 51 deletions(-) diff --git a/arch/x86/include/asm/asm.h b/arch/x86/include/asm/asm.h index a9f07799e337..722340d7c1af 100644 --- a/arch/x86/include/asm/asm.h +++ b/arch/x86/include/asm/asm.h @@ -243,5 +243,11 @@ register unsigned long current_stack_pointer asm(_ASM_SP); #define _ASM_EXTABLE_FAULT(from, to) \ _ASM_EXTABLE_TYPE(from, to, EX_TYPE_FAULT) +#define _ASM_EXTABLE_FUNC_REWIND(from, ipdelta, spdelta) \ + _ASM_EXTABLE_TYPE(from, from /* unused */, \ + EX_TYPE_FUNC_REWIND | \ + EX_DATA_REG(spdelta) | \ + EX_DATA_IMM(ipdelta)) + #endif /* __KERNEL__ */ #endif /* _ASM_X86_ASM_H */ diff --git a/arch/x86/include/asm/extable_fixup_types.h b/arch/x86/include/asm/extable_fixup_types.h index 906b0d5541e8..9cd1cea45052 100644 --- a/arch/x86/include/asm/extable_fixup_types.h +++ b/arch/x86/include/asm/extable_fixup_types.h @@ -67,5 +67,6 @@ #define EX_TYPE_ZEROPAD 20 /* longword load with zeropad on fault */ #define EX_TYPE_ERETU 21 +#define EX_TYPE_FUNC_REWIND 22 #endif diff --git a/arch/x86/mm/extable.c b/arch/x86/mm/extable.c index f1743babafc8..6bf4c2a43c2c 100644 --- a/arch/x86/mm/extable.c +++ b/arch/x86/mm/extable.c @@ -319,6 +319,27 @@ static bool ex_handler_eretu(const struct exception_table_entry *fixup, } #endif +/* + * Emulate a fault taken at the call site of a function. + * + * The combined reg and flags field are used as an unsigned number of + * machine words to pop off the stack before the return address, then + * the signed imm field is used as a delta from the return IP address. + */ +static bool ex_handler_func_rewind(struct pt_regs *regs, int data) +{ + const long ipdelta = FIELD_GET(EX_DATA_IMM_MASK, data); + const unsigned long pops = FIELD_GET(EX_DATA_REG_MASK | EX_DATA_FLAG_MASK, data); + unsigned long *sp; + + sp = (unsigned long *)regs->sp; + sp += pops; + regs->ip = *sp++ + ipdelta; + regs->sp = (unsigned long)sp; + + return true; +} + int ex_get_fixup_type(unsigned long ip) { const struct exception_table_entry *e = search_exception_tables(ip); @@ -331,6 +352,7 @@ int fixup_exception(struct pt_regs *regs, int trapnr, unsigned long error_code, { const struct exception_table_entry *e; int type, reg, imm; + bool again; #ifdef CONFIG_PNPBIOS if (unlikely(SEGMENT_IS_PNP_CODE(regs->cs))) { @@ -346,60 +368,71 @@ int fixup_exception(struct pt_regs *regs, int trapnr, unsigned long error_code, } #endif - e = search_exception_tables(regs->ip); - if (!e) - return 0; - - type = FIELD_GET(EX_DATA_TYPE_MASK, e->data); - reg = FIELD_GET(EX_DATA_REG_MASK, e->data); - imm = FIELD_GET(EX_DATA_IMM_MASK, e->data); - - switch (type) { - case EX_TYPE_DEFAULT: - case EX_TYPE_DEFAULT_MCE_SAFE: - return ex_handler_default(e, regs); - case EX_TYPE_FAULT: - case EX_TYPE_FAULT_MCE_SAFE: - return ex_handler_fault(e, regs, trapnr); - case EX_TYPE_UACCESS: - return ex_handler_uaccess(e, regs, trapnr, fault_addr); - case EX_TYPE_CLEAR_FS: - return ex_handler_clear_fs(e, regs); - case EX_TYPE_FPU_RESTORE: - return ex_handler_fprestore(e, regs); - case EX_TYPE_BPF: - return ex_handler_bpf(e, regs); - case EX_TYPE_WRMSR: - return ex_handler_msr(e, regs, true, false, reg); - case EX_TYPE_RDMSR: - return ex_handler_msr(e, regs, false, false, reg); - case EX_TYPE_WRMSR_SAFE: - return ex_handler_msr(e, regs, true, true, reg); - case EX_TYPE_RDMSR_SAFE: - return ex_handler_msr(e, regs, false, true, reg); - case EX_TYPE_WRMSR_IN_MCE: - ex_handler_msr_mce(regs, true); - break; - case EX_TYPE_RDMSR_IN_MCE: - ex_handler_msr_mce(regs, false); - break; - case EX_TYPE_POP_REG: - regs->sp += sizeof(long); - fallthrough; - case EX_TYPE_IMM_REG: - return ex_handler_imm_reg(e, regs, reg, imm); - case EX_TYPE_FAULT_SGX: - return ex_handler_sgx(e, regs, trapnr); - case EX_TYPE_UCOPY_LEN: - return ex_handler_ucopy_len(e, regs, trapnr, fault_addr, reg, imm); - case EX_TYPE_ZEROPAD: - return ex_handler_zeropad(e, regs, fault_addr); + do { + e = search_exception_tables(regs->ip); + if (!e) + return 0; + + again = false; + + type = FIELD_GET(EX_DATA_TYPE_MASK, e->data); + reg = FIELD_GET(EX_DATA_REG_MASK, e->data); + imm = FIELD_GET(EX_DATA_IMM_MASK, e->data); + + switch (type) { + case EX_TYPE_DEFAULT: + case EX_TYPE_DEFAULT_MCE_SAFE: + return ex_handler_default(e, regs); + case EX_TYPE_FAULT: + case EX_TYPE_FAULT_MCE_SAFE: + return ex_handler_fault(e, regs, trapnr); + case EX_TYPE_UACCESS: + return ex_handler_uaccess(e, regs, trapnr, fault_addr); + case EX_TYPE_CLEAR_FS: + return ex_handler_clear_fs(e, regs); + case EX_TYPE_FPU_RESTORE: + return ex_handler_fprestore(e, regs); + case EX_TYPE_BPF: + return ex_handler_bpf(e, regs); + case EX_TYPE_WRMSR: + return ex_handler_msr(e, regs, true, false, reg); + case EX_TYPE_RDMSR: + return ex_handler_msr(e, regs, false, false, reg); + case EX_TYPE_WRMSR_SAFE: + return ex_handler_msr(e, regs, true, true, reg); + case EX_TYPE_RDMSR_SAFE: + return ex_handler_msr(e, regs, false, true, reg); + case EX_TYPE_WRMSR_IN_MCE: + ex_handler_msr_mce(regs, true); + break; + case EX_TYPE_RDMSR_IN_MCE: + ex_handler_msr_mce(regs, false); + break; + case EX_TYPE_POP_REG: + regs->sp += sizeof(long); + fallthrough; + case EX_TYPE_IMM_REG: + return ex_handler_imm_reg(e, regs, reg, imm); + case EX_TYPE_FAULT_SGX: + return ex_handler_sgx(e, regs, trapnr); + case EX_TYPE_UCOPY_LEN: + return ex_handler_ucopy_len(e, regs, trapnr, fault_addr, reg, imm); + case EX_TYPE_ZEROPAD: + return ex_handler_zeropad(e, regs, fault_addr); #ifdef CONFIG_X86_FRED - case EX_TYPE_ERETU: - return ex_handler_eretu(e, regs, error_code); + case EX_TYPE_ERETU: + return ex_handler_eretu(e, regs, error_code); #endif - } + case EX_TYPE_FUNC_REWIND: + again = ex_handler_func_rewind(regs, e->data); + break; + default: + break; /* Will BUG() */ + } + } while (again); + BUG(); + return 0; } extern unsigned int early_recursion_flag; From patchwork Tue Apr 22 08:22:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xin Li \(Intel\)" X-Patchwork-Id: 883461 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D866F23AE96; Tue, 22 Apr 2025 08:23:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745310230; cv=none; b=TVw+gyUPWrSwSAwWWWxdnEnbo+h0r48SVeheapON4XMg/GycyHCLumHjRsw65cDUDvB+7Zekjp1LK+OTL3eBG4mjQHfsWu2mI33adEIZO4WQ2hnpgZFwmuFtjHyYV4mvE4cveNURTEoKdzWO5s3RMIdVRChCW7RGz5fUwHL63Lo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745310230; c=relaxed/simple; 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Tue, 22 Apr 2025 01:23:05 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53M8MG9a1954391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745310187; bh=kSMr7RD7HY/M1n+drsBYA+dTa0bsodjA/Xja0eKYtpA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dk8fSv+AkELIlRdpChMel9SZnbgJwXWLUal3Sr5HedtvF0oEaDqZZh6Mdxa7mmUOT pqQdxNOxwQ4ybP6YSHN2p3qgPm+AHwGHY6vRqs34rDOln9kiX04a8OVrfTSTyv9hBb 34WIeGV4sB3p1zaJqo+aOqc44RNU8Kq4ppqMimtdoBQAG7VGMAbMWiZKoImvIN0gSV OO41Y95uih4tueaVJRntAe4BEy85pl8eYbyQlzkndESIEuNB0Z85J+RvyIIkgLX7aw WNJLctduOI+9g2lQPfZSVT+8+Ar7uKwRHKuaPTStQaEsQaOM0C52LZpyqgNVVR8jQ/ 8Uzgb4Yr3XL9w== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Subject: [RFC PATCH v2 22/34] x86/msr: Utilize the alternatives mechanism to read MSR Date: Tue, 22 Apr 2025 01:22:03 -0700 Message-ID: <20250422082216.1954310-23-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250422082216.1954310-1-xin@zytor.com> References: <20250422082216.1954310-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 To eliminate the indirect call overhead introduced by the pv_ops API, utilize the alternatives mechanism to read MSR: 1) When built with !CONFIG_XEN_PV, X86_FEATURE_XENPV becomes a disabled feature, preventing the Xen code from being built and ensuring the native code is executed unconditionally. 2) When built with CONFIG_XEN_PV: 2.1) If not running on the Xen hypervisor (!X86_FEATURE_XENPV), the kernel runtime binary is patched to unconditionally jump to the native MSR read code. 2.2) If running on the Xen hypervisor (X86_FEATURE_XENPV), the kernel runtime binary is patched to unconditionally jump to the Xen MSR read code. The alternatives mechanism is also used to choose the new immediate form MSR read instruction when it's available. Consequently, remove the pv_ops MSR read APIs and the Xen callbacks. Suggested-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li (Intel) --- arch/x86/include/asm/msr.h | 277 +++++++++++++++++++------- arch/x86/include/asm/paravirt.h | 40 ---- arch/x86/include/asm/paravirt_types.h | 9 - arch/x86/kernel/paravirt.c | 2 - arch/x86/xen/enlighten_pv.c | 48 ++--- arch/x86/xen/xen-asm.S | 49 +++++ arch/x86/xen/xen-ops.h | 7 + 7 files changed, 279 insertions(+), 153 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index bd3bdb3c3d23..5271cb002b23 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -75,6 +75,7 @@ static inline void do_trace_rdpmc(u32 msr, u64 val, int failed) {} #endif #ifdef CONFIG_XEN_PV +extern void asm_xen_read_msr(void); extern void asm_xen_write_msr(void); extern u64 xen_read_pmc(int counter); #endif @@ -88,6 +89,8 @@ extern u64 xen_read_pmc(int counter); /* The GNU Assembler (Gas) with Binutils 2.41 adds the .insn directive support */ #if defined(CONFIG_AS_IS_GNU) && CONFIG_AS_VERSION >= 24100 +#define ASM_RDMSR_IMM \ + " .insn VEX.128.F2.M7.W0 0xf6 /0, %[msr]%{:u32}, %[val]\n\t" #define ASM_WRMSRNS_IMM \ " .insn VEX.128.F3.M7.W0 0xf6 /0, %[val], %[msr]%{:u32}\n\t" #else @@ -97,10 +100,17 @@ extern u64 xen_read_pmc(int counter); * The register operand is encoded as %rax because all uses of the immediate * form MSR access instructions reference %rax as the register operand. */ +#define ASM_RDMSR_IMM \ + " .byte 0xc4,0xe7,0x7b,0xf6,0xc0; .long %c[msr]" #define ASM_WRMSRNS_IMM \ " .byte 0xc4,0xe7,0x7a,0xf6,0xc0; .long %c[msr]" #endif +#define RDMSR_AND_SAVE_RESULT \ + "rdmsr\n\t" \ + "shl $0x20, %%rdx\n\t" \ + "or %%rdx, %%rax\n\t" + #define PREPARE_RDX_FOR_WRMSR \ "mov %%rax, %%rdx\n\t" \ "shr $0x20, %%rdx\n\t" @@ -127,35 +137,135 @@ static __always_inline bool is_msr_imm_insn(void *ip) #endif } -static __always_inline u64 __rdmsr(u32 msr) +/* + * There are two sets of APIs for MSR accesses: native APIs and generic APIs. + * Native MSR APIs execute MSR instructions directly, regardless of whether the + * CPU is paravirtualized or native. Generic MSR APIs determine the appropriate + * MSR access method at runtime, allowing them to be used generically on both + * paravirtualized and native CPUs. + * + * When the compiler can determine the MSR number at compile time, the APIs + * with the suffix _constant() are used to enable the immediate form MSR + * instructions when available. The APIs with the suffix _variable() are + * used when the MSR number is not known until run time. + * + * Below is a diagram illustrating the derivation of the MSR read APIs: + * + * __native_rdmsrq_variable() __native_rdmsrq_constant() + * \ / + * \ / + * __native_rdmsrq() ----------------------- + * / \ | + * / \ | + * native_rdmsrq() native_read_msr_safe() | + * / \ | + * / \ | + * native_rdmsr() native_read_msr() | + * | + * | + * | + * __xenpv_rdmsrq() | + * | | + * | | + * __rdmsrq() <-------------------------------- + * / \ + * / \ + * rdmsrq() rdmsrq_safe() + * / \ + * / \ + * rdmsr() rdmsr_safe() + */ + +static __always_inline bool __native_rdmsrq_variable(u32 msr, u64 *val, int type) { - DECLARE_ARGS(val, low, high); +#ifdef CONFIG_X86_64 + BUILD_BUG_ON(__builtin_constant_p(msr)); - asm volatile("1: rdmsr\n" - "2:\n" - _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR) - : EAX_EDX_RET(val, low, high) : "c" (msr)); + asm_inline volatile goto( + "1:\n" + RDMSR_AND_SAVE_RESULT + _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) /* For RDMSR */ - return EAX_EDX_VAL(val, low, high); + : [val] "=a" (*val) + : "c" (msr), [type] "i" (type) + : "rdx" + : badmsr); +#else + asm_inline volatile goto( + "1: rdmsr\n\t" + _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) /* For RDMSR */ + + : "=A" (*val) + : "c" (msr), [type] "i" (type) + : + : badmsr); +#endif + + return false; + +badmsr: + *val = 0; + + return true; } -#define native_rdmsr(msr, val1, val2) \ -do { \ - u64 __val = __rdmsr((msr)); \ - (void)((val1) = (u32)__val); \ - (void)((val2) = (u32)(__val >> 32)); \ -} while (0) +#ifdef CONFIG_X86_64 +static __always_inline bool __native_rdmsrq_constant(u32 msr, u64 *val, int type) +{ + BUILD_BUG_ON(!__builtin_constant_p(msr)); + + asm_inline volatile goto( + "1:\n" + ALTERNATIVE("mov %[msr], %%ecx\n\t" + "2:\n" + RDMSR_AND_SAVE_RESULT, + ASM_RDMSR_IMM, + X86_FEATURE_MSR_IMM) + _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) /* For RDMSR immediate */ + _ASM_EXTABLE_TYPE(2b, %l[badmsr], %c[type]) /* For RDMSR */ + + : [val] "=a" (*val) + : [msr] "i" (msr), [type] "i" (type) + : "ecx", "rdx" + : badmsr); + + return false; + +badmsr: + *val = 0; + + return true; +} +#endif + +static __always_inline bool __native_rdmsrq(u32 msr, u64 *val, int type) +{ +#ifdef CONFIG_X86_64 + if (__builtin_constant_p(msr)) + return __native_rdmsrq_constant(msr, val, type); +#endif + + return __native_rdmsrq_variable(msr, val, type); +} static __always_inline u64 native_rdmsrq(u32 msr) { - return __rdmsr(msr); + u64 val = 0; + + __native_rdmsrq(msr, &val, EX_TYPE_RDMSR); + return val; } +#define native_rdmsr(msr, low, high) \ +do { \ + u64 __val = native_rdmsrq(msr); \ + (void)((low) = (u32)__val); \ + (void)((high) = (u32)(__val >> 32)); \ +} while (0) + static inline u64 native_read_msr(u32 msr) { - u64 val; - - val = __rdmsr(msr); + u64 val = native_rdmsrq(msr); if (tracepoint_enabled(read_msr)) do_trace_read_msr(msr, val, 0); @@ -163,36 +273,91 @@ static inline u64 native_read_msr(u32 msr) return val; } -static inline int native_read_msr_safe(u32 msr, u64 *p) +static inline int native_read_msr_safe(u32 msr, u64 *val) { int err; - DECLARE_ARGS(val, low, high); - asm volatile("1: rdmsr ; xor %[err],%[err]\n" - "2:\n\t" - _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_RDMSR_SAFE, %[err]) - : [err] "=r" (err), EAX_EDX_RET(val, low, high) - : "c" (msr)); - if (tracepoint_enabled(read_msr)) - do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), err); + err = __native_rdmsrq(msr, val, EX_TYPE_RDMSR_SAFE) ? -EIO : 0; - *p = EAX_EDX_VAL(val, low, high); + if (tracepoint_enabled(read_msr)) + do_trace_read_msr(msr, *val, err); return err; } +#ifdef CONFIG_XEN_PV +/* No plan to support immediate form MSR instructions in Xen */ +static __always_inline bool __xenpv_rdmsrq(u32 msr, u64 *val, int type) +{ + asm_inline volatile goto( + "1: call asm_xen_read_msr\n\t" + _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) /* For CALL */ + + : [val] "=a" (*val), ASM_CALL_CONSTRAINT + : "c" (msr), [type] "i" (type) + : "rdx" + : badmsr); + + return false; + +badmsr: + *val = 0; + + return true; +} +#endif + +static __always_inline bool __rdmsrq(u32 msr, u64 *val, int type) +{ + bool ret; + +#ifdef CONFIG_XEN_PV + if (cpu_feature_enabled(X86_FEATURE_XENPV)) + return __xenpv_rdmsrq(msr, val, type); +#endif + + /* + * 1) When built with !CONFIG_XEN_PV. + * 2) When built with CONFIG_XEN_PV but not running on Xen hypervisor. + */ + ret = __native_rdmsrq(msr, val, type); + + if (tracepoint_enabled(read_msr)) + do_trace_read_msr(msr, *val, ret ? -EIO : 0); + + return ret; +} + +#define rdmsrq(msr, val) \ +do { \ + u64 ___val = 0; \ + __rdmsrq((msr), &___val, EX_TYPE_RDMSR); \ + (val) = ___val; \ +} while (0) + +#define rdmsr(msr, low, high) \ +do { \ + u64 __val = 0; \ + rdmsrq((msr), __val); \ + (void)((low) = (u32)__val); \ + (void)((high) = (u32)(__val >> 32)); \ +} while (0) + +static __always_inline int rdmsrq_safe(u32 msr, u64 *val) +{ + return __rdmsrq(msr, val, EX_TYPE_RDMSR_SAFE) ? -EIO : 0; +} + +#define rdmsr_safe(msr, low, high) \ +({ \ + u64 __val = 0; \ + int __err = rdmsrq_safe((msr), &__val); \ + (*low) = (u32)__val; \ + (*high) = (u32)(__val >> 32); \ + __err; \ +}) + /* - * There are two sets of APIs for MSR accesses: native APIs and generic APIs. - * Native MSR APIs execute MSR instructions directly, regardless of whether the - * CPU is paravirtualized or native. Generic MSR APIs determine the appropriate - * MSR access method at runtime, allowing them to be used generically on both - * paravirtualized and native CPUs. - * - * When the compiler can determine the MSR number at compile time, the APIs - * with the suffix _constant() are used to enable the immediate form MSR - * instructions when available. The APIs with the suffix _variable() are - * used when the MSR number is not known until run time. - * * Below is a diagram illustrating the derivation of the MSR write APIs: * * __native_wrmsrq_variable() __native_wrmsrq_constant() @@ -420,42 +585,6 @@ static __always_inline u64 rdpmcq(int counter) return native_rdpmcq(counter); } -#ifdef CONFIG_PARAVIRT_XXL -#include -#else -#include -/* - * Access to machine-specific registers (available on 586 and better only) - * Note: the rd* operations modify the parameters directly (without using - * pointer indirection), this allows gcc to optimize better - */ - -#define rdmsr(msr, low, high) \ -do { \ - u64 __val = native_read_msr((msr)); \ - (void)((low) = (u32)__val); \ - (void)((high) = (u32)(__val >> 32)); \ -} while (0) - -#define rdmsrq(msr, val) \ - ((val) = native_read_msr((msr))) - -/* rdmsr with exception handling */ -#define rdmsr_safe(msr, low, high) \ -({ \ - u64 __val; \ - int __err = native_read_msr_safe((msr), &__val); \ - (*low) = (u32)__val; \ - (*high) = (u32)(__val >> 32); \ - __err; \ -}) - -static inline int rdmsrq_safe(u32 msr, u64 *p) -{ - return native_read_msr_safe(msr, p); -} -#endif /* !CONFIG_PARAVIRT_XXL */ - struct msr __percpu *msrs_alloc(void); void msrs_free(struct msr __percpu *msrs); int msr_set_bit(u32 msr, u8 bit); diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h index 6634f6cf801f..e248a77b719f 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -175,46 +175,6 @@ static inline void __write_cr4(unsigned long x) PVOP_VCALL1(cpu.write_cr4, x); } -static inline u64 paravirt_read_msr(unsigned msr) -{ - return PVOP_CALL1(u64, cpu.read_msr, msr); -} - -static inline u64 paravirt_read_msr_safe(unsigned msr, int *err) -{ - return PVOP_CALL2(u64, cpu.read_msr_safe, msr, err); -} - -#define rdmsr(msr, val1, val2) \ -do { \ - u64 _l = paravirt_read_msr(msr); \ - val1 = (u32)_l; \ - val2 = _l >> 32; \ -} while (0) - -#define rdmsrq(msr, val) \ -do { \ - val = paravirt_read_msr(msr); \ -} while (0) - -/* rdmsr with exception handling */ -#define rdmsr_safe(msr, a, b) \ -({ \ - int _err; \ - u64 _l = paravirt_read_msr_safe(msr, &_err); \ - (*a) = (u32)_l; \ - (*b) = _l >> 32; \ - _err; \ -}) - -static inline int rdmsrq_safe(unsigned msr, u64 *p) -{ - int err; - - *p = paravirt_read_msr_safe(msr, &err); - return err; -} - static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) { PVOP_VCALL2(cpu.alloc_ldt, ldt, entries); diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h index 18bb0e5bd22f..ae31ecf08933 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -90,15 +90,6 @@ struct pv_cpu_ops { void (*cpuid)(unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx); - /* Unsafe MSR operations. These will warn or panic on failure. */ - u64 (*read_msr)(unsigned int msr); - - /* - * Safe MSR operations. - * Returns 0 or -EIO. - */ - int (*read_msr_safe)(unsigned int msr, u64 *val); - void (*start_context_switch)(struct task_struct *prev); void (*end_context_switch)(struct task_struct *next); #endif diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 62bf66f61821..9f5eb8a78040 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -128,8 +128,6 @@ struct paravirt_patch_template pv_ops = { .cpu.read_cr0 = native_read_cr0, .cpu.write_cr0 = native_write_cr0, .cpu.write_cr4 = native_write_cr4, - .cpu.read_msr = native_read_msr, - .cpu.read_msr_safe = native_read_msr_safe, .cpu.load_tr_desc = native_load_tr_desc, .cpu.set_ldt = native_set_ldt, .cpu.load_gdt = native_load_gdt, diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 4672de7fc084..267e241b9236 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -1086,19 +1086,26 @@ static void xen_write_cr4(unsigned long cr4) native_write_cr4(cr4); } -static u64 xen_do_read_msr(unsigned int msr, int *err) +/* + * Return true in xen_rdmsr_ret_type to indicate the requested MSR read has + * been done successfully. + */ +struct xen_rdmsr_ret_type xen_read_msr(u32 msr) { - u64 val = 0; /* Avoid uninitialized value for safe variant. */ - bool emulated; + struct xen_rdmsr_ret_type ret; - if (pmu_msr_chk_emulated(msr, &val, true, &emulated) && emulated) - return val; + ret.done = true; - if (err) - *err = native_read_msr_safe(msr, &val); - else - val = native_read_msr(msr); + if (pmu_msr_chk_emulated(msr, &ret.val, true, &ret.done) && ret.done) + return ret; + + ret.val = 0; + ret.done = false; + return ret; +} +u64 xen_read_msr_fixup(u32 msr, u64 val) +{ switch (msr) { case MSR_IA32_APICBASE: val &= ~X2APIC_ENABLE; @@ -1107,7 +1114,11 @@ static u64 xen_do_read_msr(unsigned int msr, int *err) else val &= ~MSR_IA32_APICBASE_BSP; break; + + default: + break; } + return val; } @@ -1159,21 +1170,6 @@ bool xen_write_msr(u32 msr, u64 val) } } -static int xen_read_msr_safe(unsigned int msr, u64 *val) -{ - int err; - - *val = xen_do_read_msr(msr, &err); - return err; -} - -static u64 xen_read_msr(unsigned int msr) -{ - int err; - - return xen_do_read_msr(msr, xen_msr_safe ? &err : NULL); -} - /* This is called once we have the cpu_possible_mask */ void __init xen_setup_vcpu_info_placement(void) { @@ -1208,10 +1204,6 @@ static const typeof(pv_ops) xen_cpu_ops __initconst = { .write_cr4 = xen_write_cr4, - .read_msr = xen_read_msr, - - .read_msr_safe = xen_read_msr_safe, - .load_tr_desc = paravirt_nop, .set_ldt = xen_set_ldt, .load_gdt = xen_load_gdt, diff --git a/arch/x86/xen/xen-asm.S b/arch/x86/xen/xen-asm.S index eecce47fbe49..62270ef85c56 100644 --- a/arch/x86/xen/xen-asm.S +++ b/arch/x86/xen/xen-asm.S @@ -406,3 +406,52 @@ SYM_CODE_END(xen_entry_SYSCALL_compat) RET SYM_FUNC_END(asm_xen_write_msr) EXPORT_SYMBOL_GPL(asm_xen_write_msr) + +/* + * MSR number in %ecx, MSR value will be returned in %rax. + * + * The prototype of the Xen C code: + * struct { u64 val, bool done } xen_read_msr(u32 msr) + */ +SYM_FUNC_START(asm_xen_read_msr) + ENDBR + FRAME_BEGIN + XEN_SAVE_CALLEE_REGS_FOR_MSR + mov %ecx, %edi /* MSR number */ + call xen_read_msr + test %dl, %dl /* %dl=1, i.e., ZF=0, meaning successfully done */ + XEN_RESTORE_CALLEE_REGS_FOR_MSR + jnz 2f + + /* + * Falls through to the native RDMSR instruction if xen_read_msr() failed, + * i.e., the MSR access should be executed natively, which will trigger a + * #GP fault... + */ +1: rdmsr + + /* + * Note, #GP on RDMSR is reflected to the caller of this function through + * EX_TYPE_FUNC_REWIND, which enforces a coupling between the caller and + * callee, IOW the callee is able to calculate the address of the CALL + * instruction in the caller that invoked it. + * + * The top of the stack points directly at the return address; + * back up by 5 bytes (length of the CALL instruction in the caller) from + * the return address. + */ + _ASM_EXTABLE_FUNC_REWIND(1b, -5, FRAME_OFFSET / (BITS_PER_LONG / 8)) + + shl $0x20, %rdx + or %rdx, %rax + + XEN_SAVE_CALLEE_REGS_FOR_MSR + mov %ecx, %edi + mov %rax, %rsi + call xen_read_msr_fixup + XEN_RESTORE_CALLEE_REGS_FOR_MSR + +2: FRAME_END + RET +SYM_FUNC_END(asm_xen_read_msr) +EXPORT_SYMBOL_GPL(asm_xen_read_msr) diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h index 56712242262a..483526ec13c6 100644 --- a/arch/x86/xen/xen-ops.h +++ b/arch/x86/xen/xen-ops.h @@ -146,7 +146,14 @@ __visible unsigned long xen_read_cr2_direct(void); /* These are not functions, and cannot be called normally */ __visible void xen_iret(void); +struct xen_rdmsr_ret_type { + u64 val; + bool done; +}; + extern bool xen_write_msr(u32 msr, u64 val); +extern struct xen_rdmsr_ret_type xen_read_msr(u32 msr); +extern u64 xen_read_msr_fixup(u32 msr, u64 val); extern int xen_panic_handler_init(void); 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Tue, 22 Apr 2025 01:23:07 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53M8MG9b1954391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745310189; bh=1txH+adcfOwIr5LH/ZlSlDHGsa/VNPa8LSISbt9l4Ro=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OxFRBToWvEqJ0D8+VHe17wCVzLMgXTwVfmryl84uMGCcCa1OR1gcYgk3F9JimIkEm Id/7hCRonS1tRSe3XbDtDY2rOOSRAECeUFgk8SnqUTUQVMI7fMsmlmLdA+V1Isnccx NyOxGoeye8+rFjFY7d/LaanWDAMzgutZnK7I8bQcQOzDgKbXuT2nLEFt3l17FoQjbN 0MBd1FBVWKYzzM4HdY+mKWx4rA3pjbiDgR4YfpiXTsRCo/G4/quQSJEIDnLLYiZ/pn +gaaR0PJHyRUhR9gBfrfjXO0nxpya9KvdRYx5dSosavK3jrRh2vDAAe1RpFOl3uFKb EUpT5J98djaIA== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Subject: [RFC PATCH v2 23/34] x86/extable: Remove new dead code in ex_handler_msr() Date: Tue, 22 Apr 2025 01:22:04 -0700 Message-ID: <20250422082216.1954310-24-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250422082216.1954310-1-xin@zytor.com> References: <20250422082216.1954310-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The MSR read APIs no longer expect RAX or EDX:EAX to be cleared upon returning from #GP caused by MSR read instructions. The MSR safe APIs no longer assume -EIO being returned in a register from #GP caused by MSR instructions. Remove new dead code due to above changes. Signed-off-by: Xin Li (Intel) --- arch/x86/mm/extable.c | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-) diff --git a/arch/x86/mm/extable.c b/arch/x86/mm/extable.c index 6bf4c2a43c2c..ea3fe7f32772 100644 --- a/arch/x86/mm/extable.c +++ b/arch/x86/mm/extable.c @@ -165,7 +165,7 @@ static bool ex_handler_uaccess(const struct exception_table_entry *fixup, } static bool ex_handler_msr(const struct exception_table_entry *fixup, - struct pt_regs *regs, bool wrmsr, bool safe, int reg) + struct pt_regs *regs, bool wrmsr, bool safe) { bool imm_insn = is_msr_imm_insn((void *)regs->ip); u32 msr; @@ -207,17 +207,6 @@ static bool ex_handler_msr(const struct exception_table_entry *fixup, show_stack_regs(regs); } - if (!wrmsr) { - /* Pretend that the read succeeded and returned 0. */ - regs->ax = 0; - - if (!imm_insn) - regs->dx = 0; - } - - if (safe) - *pt_regs_nr(regs, reg) = -EIO; - return ex_handler_default(fixup, regs); } @@ -395,13 +384,13 @@ int fixup_exception(struct pt_regs *regs, int trapnr, unsigned long error_code, case EX_TYPE_BPF: return ex_handler_bpf(e, regs); case EX_TYPE_WRMSR: - return ex_handler_msr(e, regs, true, false, reg); + return ex_handler_msr(e, regs, true, false); case EX_TYPE_RDMSR: - return ex_handler_msr(e, regs, false, false, reg); + return ex_handler_msr(e, regs, false, false); case EX_TYPE_WRMSR_SAFE: - return ex_handler_msr(e, regs, true, true, reg); + return ex_handler_msr(e, regs, true, true); case EX_TYPE_RDMSR_SAFE: - return ex_handler_msr(e, regs, false, true, reg); + return ex_handler_msr(e, regs, false, true); case EX_TYPE_WRMSR_IN_MCE: ex_handler_msr_mce(regs, true); break; From patchwork Tue Apr 22 08:22:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xin Li \(Intel\)" X-Patchwork-Id: 883458 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17BA525523A; Tue, 22 Apr 2025 08:23:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="MammLggy" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 53M8MG9g1954391 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Tue, 22 Apr 2025 01:23:18 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53M8MG9g1954391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745310199; bh=KjomXZ5P3Zbm1klfdzn3LReOwRDs2PdqfVOgUPEXtew=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MammLggyo/MjNNAwAcGt2FRRqSlsggJGU25zpYplrm30iO3Y/UZa+69mVrL7h5AdS +QF2vmuyoTUyD+PdpH0lcuLBEfsSmWJnEV4E43GwV3sP/7cQrcCY/s75xekunodRVa MBCN8M8aF0nhj0PDdRAf4MrLwGcINYVauVcmEuaMv8xJCquK+hO/zGDpXej860AYjg NOT8SBUSpQ3ULjUuZ/sIg7bsPjGu5PLZtigXd69vD9lGPI77KfO9GCa1dmtAwL41Tk B7LFh5ljq9pZHluYM3LgLnmCHGK++CYmGWll/VVGfqOlZWhC1wu5qdivPclw361f2G tQVJYMIZbWMzA== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Subject: [RFC PATCH v2 28/34] x86/msr: Rename native_write_msr_safe() to native_wrmsrq_safe() Date: Tue, 22 Apr 2025 01:22:09 -0700 Message-ID: <20250422082216.1954310-29-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250422082216.1954310-1-xin@zytor.com> References: <20250422082216.1954310-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Signed-off-by: Xin Li (Intel) --- arch/x86/include/asm/msr.h | 4 ++-- arch/x86/kvm/svm/svm.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 72a1c3301d46..a1c63bed14be 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -366,7 +366,7 @@ static __always_inline int rdmsrq_safe(u32 msr, u64 *val) * __native_wrmsrq() ----------------------- * / \ | * / \ | - * native_wrmsrq_no_trace() native_write_msr_safe() | + * native_wrmsrq_no_trace() native_wrmsrq_safe() | * / \ | * / \ | * native_wrmsr_no_trace() native_wrmsrq() | @@ -480,7 +480,7 @@ static inline void notrace native_wrmsrq(u32 msr, u64 val) do_trace_write_msr(msr, val, 0); } -static inline int notrace native_write_msr_safe(u32 msr, u64 val) +static inline int notrace native_wrmsrq_safe(u32 msr, u64 val) { int err = __native_wrmsrq(msr, val, EX_TYPE_WRMSR_SAFE) ? -EIO : 0; diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 838606f784c9..01dd3cd20730 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -486,7 +486,7 @@ static void svm_init_erratum_383(void) val |= (1ULL << 47); - native_write_msr_safe(MSR_AMD64_DC_CFG, val); + native_wrmsrq_safe(MSR_AMD64_DC_CFG, val); erratum_383_found = true; } @@ -2159,11 +2159,11 @@ static bool is_erratum_383(void) /* Clear MCi_STATUS registers */ for (i = 0; i < 6; ++i) - native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0); + native_wrmsrq_safe(MSR_IA32_MCx_STATUS(i), 0); if (!native_read_msr_safe(MSR_IA32_MCG_STATUS, &value)) { value &= ~(1ULL << 2); - native_write_msr_safe(MSR_IA32_MCG_STATUS, value); + native_wrmsrq_safe(MSR_IA32_MCG_STATUS, value); } /* Flush tlb to evict multi-match entries */ From patchwork Tue Apr 22 08:22:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xin Li \(Intel\)" X-Patchwork-Id: 883457 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E47F625522B; Tue, 22 Apr 2025 08:23:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745310232; cv=none; b=ZEdnFk75roxHJ3SKAioJmt+VAU1m/yWKWMnyUOGFDf+/dI4LBT6juJySA5h1yIhIILCWQMbVO1YHkK57YgYQeuWZB8veYkOIrfNwYy3Z5U0U3CV4VTHIQbWTfMNaBQ4JVQexv3EdQCvPbirGPahjmn4NimIWy8lwE9w4KEwip40= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745310232; c=relaxed/simple; bh=4cF3LV8TD/rxDoNqTzi8ac3u7KhUM/vZA/zD5XUm6E4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Tue, 22 Apr 2025 01:23:19 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53M8MG9h1954391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745310201; bh=HZ6mNNbZ7ulzph9dMmRPGpUoSI6d0gZZ7dCJYm/kVRo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bhOnyEJJ9eA/e2yJpfrvVgyfJSJRYVg7h8wU1lJUr8G7Pna/4/NLi+alPmNV+SLRK Uo8LDKcvd0Pk5gC6kAB15JJcOI7+0ixbYobSD9S0ZkC7VSMyiQmcJ67McllPf46ule Zo//0nO6Loi0Zm3hZIoJu5gSw+5ZCTgTLpB+N7vw24j4D7huPiDQAIXQ0mMYlE28Iu JM+TWlUg9eQw7SWWSKY+QaKd6tM1sIujXGDJmyW5dZHdNPzvi4RUSSLufTAC57nokH MNXZdSlARgUnRzsuDgzLRJT7LYVtmLxfbvHlFRDyLxwsptSQyd6JLbwRKWTnLYST6j R0HGqr7RcZJWA== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Subject: [RFC PATCH v2 29/34] x86/msr: Rename native_rdmsrq() to native_rdmsrq_no_trace() Date: Tue, 22 Apr 2025 01:22:10 -0700 Message-ID: <20250422082216.1954310-30-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250422082216.1954310-1-xin@zytor.com> References: <20250422082216.1954310-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 native_rdmsrq() doesn't do trace thus can be used in noinstr context, rename it to native_rdmsrq_no_trace() to make it explicit. Signed-off-by: Xin Li (Intel) --- arch/x86/boot/startup/sme.c | 4 ++-- arch/x86/events/amd/brs.c | 2 +- arch/x86/hyperv/hv_vtl.c | 4 ++-- arch/x86/hyperv/ivm.c | 2 +- arch/x86/include/asm/mshyperv.h | 2 +- arch/x86/include/asm/msr.h | 8 ++++---- arch/x86/include/asm/sev-internal.h | 2 +- arch/x86/kernel/cpu/common.c | 2 +- arch/x86/kernel/cpu/mce/core.c | 4 ++-- arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 2 +- arch/x86/kvm/vmx/vmx.c | 4 ++-- 11 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/x86/boot/startup/sme.c b/arch/x86/boot/startup/sme.c index 5e147bf5a0a8..859d92ad91a4 100644 --- a/arch/x86/boot/startup/sme.c +++ b/arch/x86/boot/startup/sme.c @@ -524,7 +524,7 @@ void __head sme_enable(struct boot_params *bp) me_mask = 1UL << (ebx & 0x3f); /* Check the SEV MSR whether SEV or SME is enabled */ - sev_status = msr = native_rdmsrq(MSR_AMD64_SEV); + sev_status = msr = native_rdmsrq_no_trace(MSR_AMD64_SEV); feature_mask = (msr & MSR_AMD64_SEV_ENABLED) ? AMD_SEV_BIT : AMD_SME_BIT; /* @@ -555,7 +555,7 @@ void __head sme_enable(struct boot_params *bp) return; /* For SME, check the SYSCFG MSR */ - msr = native_rdmsrq(MSR_AMD64_SYSCFG); + msr = native_rdmsrq_no_trace(MSR_AMD64_SYSCFG); if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) return; } diff --git a/arch/x86/events/amd/brs.c b/arch/x86/events/amd/brs.c index 0153616a97cd..0623b6d775fb 100644 --- a/arch/x86/events/amd/brs.c +++ b/arch/x86/events/amd/brs.c @@ -49,7 +49,7 @@ static __always_inline void set_debug_extn_cfg(u64 val) static __always_inline u64 get_debug_extn_cfg(void) { - return native_rdmsrq(MSR_AMD_DBG_EXTN_CFG); + return native_rdmsrq_no_trace(MSR_AMD_DBG_EXTN_CFG); } static bool __init amd_brs_detect(void) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index c6343e699154..9e41e380ad26 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -149,11 +149,11 @@ static int hv_vtl_bringup_vcpu(u32 target_vp_index, int cpu, u64 eip_ignored) input->vp_context.rip = rip; input->vp_context.rsp = rsp; input->vp_context.rflags = 0x0000000000000002; - input->vp_context.efer = native_rdmsrq(MSR_EFER); + input->vp_context.efer = native_rdmsrq_no_trace(MSR_EFER); input->vp_context.cr0 = native_read_cr0(); input->vp_context.cr3 = __native_read_cr3(); input->vp_context.cr4 = native_read_cr4(); - input->vp_context.msr_cr_pat = native_rdmsrq(MSR_IA32_CR_PAT); + input->vp_context.msr_cr_pat = native_rdmsrq_no_trace(MSR_IA32_CR_PAT); input->vp_context.idtr.limit = idt_ptr.size; input->vp_context.idtr.base = idt_ptr.address; input->vp_context.gdtr.limit = gdt_ptr.size; diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c index 821609af5bd2..dfddf522e838 100644 --- a/arch/x86/hyperv/ivm.c +++ b/arch/x86/hyperv/ivm.c @@ -111,7 +111,7 @@ u64 hv_ghcb_hypercall(u64 control, void *input, void *output, u32 input_size) static inline u64 rd_ghcb_msr(void) { - return native_rdmsrq(MSR_AMD64_SEV_ES_GHCB); + return native_rdmsrq_no_trace(MSR_AMD64_SEV_ES_GHCB); } static inline void wr_ghcb_msr(u64 val) diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyperv.h index 778444310cfb..ab94221ff38d 100644 --- a/arch/x86/include/asm/mshyperv.h +++ b/arch/x86/include/asm/mshyperv.h @@ -305,7 +305,7 @@ void hv_set_non_nested_msr(unsigned int reg, u64 value); static __always_inline u64 hv_raw_get_msr(unsigned int reg) { - return native_rdmsrq(reg); + return native_rdmsrq_no_trace(reg); } #else /* CONFIG_HYPERV */ diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index a1c63bed14be..050d750a5ab7 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -157,7 +157,7 @@ static __always_inline bool is_msr_imm_insn(void *ip) * __native_rdmsrq() ----------------------- * / \ | * / \ | - * native_rdmsrq() native_read_msr_safe() | + * native_rdmsrq_no_trace() native_read_msr_safe() | * / \ | * / \ | * native_rdmsr() native_read_msr() | @@ -248,7 +248,7 @@ static __always_inline bool __native_rdmsrq(u32 msr, u64 *val, int type) return __native_rdmsrq_variable(msr, val, type); } -static __always_inline u64 native_rdmsrq(u32 msr) +static __always_inline u64 native_rdmsrq_no_trace(u32 msr) { u64 val = 0; @@ -258,14 +258,14 @@ static __always_inline u64 native_rdmsrq(u32 msr) #define native_rdmsr(msr, low, high) \ do { \ - u64 __val = native_rdmsrq(msr); \ + u64 __val = native_rdmsrq_no_trace(msr); \ (void)((low) = (u32)__val); \ (void)((high) = (u32)(__val >> 32)); \ } while (0) static inline u64 native_read_msr(u32 msr) { - u64 val = native_rdmsrq(msr); + u64 val = native_rdmsrq_no_trace(msr); if (tracepoint_enabled(read_msr)) do_trace_read_msr(msr, val, 0); diff --git a/arch/x86/include/asm/sev-internal.h b/arch/x86/include/asm/sev-internal.h index 7eb030702435..743da9fc7454 100644 --- a/arch/x86/include/asm/sev-internal.h +++ b/arch/x86/include/asm/sev-internal.h @@ -96,7 +96,7 @@ int svsm_perform_call_protocol(struct svsm_call *call); static inline u64 sev_es_rd_ghcb_msr(void) { - return native_rdmsrq(MSR_AMD64_SEV_ES_GHCB); + return native_rdmsrq_no_trace(MSR_AMD64_SEV_ES_GHCB); } static __always_inline void sev_es_wr_ghcb_msr(u64 val) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 99d8a8c15ba5..9d2de568cb96 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -164,7 +164,7 @@ static void ppin_init(struct cpuinfo_x86 *c) /* Is the enable bit set? */ if (val & 2UL) { - c->ppin = native_rdmsrq(info->msr_ppin); + c->ppin = native_rdmsrq_no_trace(info->msr_ppin); set_cpu_cap(c, info->feature); return; } diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index bd3cb984ccb9..9f7538b9d2fa 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -121,7 +121,7 @@ void mce_prep_record_common(struct mce *m) { m->cpuid = cpuid_eax(1); m->cpuvendor = boot_cpu_data.x86_vendor; - m->mcgcap = native_rdmsrq(MSR_IA32_MCG_CAP); + m->mcgcap = native_rdmsrq_no_trace(MSR_IA32_MCG_CAP); /* need the internal __ version to avoid deadlocks */ m->time = __ktime_get_real_seconds(); } @@ -1313,7 +1313,7 @@ static noinstr bool mce_check_crashing_cpu(void) (crashing_cpu != -1 && crashing_cpu != cpu)) { u64 mcgstatus; - mcgstatus = native_rdmsrq(MSR_IA32_MCG_STATUS); + mcgstatus = native_rdmsrq_no_trace(MSR_IA32_MCG_STATUS); if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { if (mcgstatus & MCG_STATUS_LMCES) diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c index 184bc1b3fb02..819c07a23c6d 100644 --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c @@ -482,7 +482,7 @@ int resctrl_arch_pseudo_lock_fn(void *_plr) * the buffer and evict pseudo-locked memory read earlier from the * cache. */ - saved_msr = native_rdmsrq(MSR_MISC_FEATURE_CONTROL); + saved_msr = native_rdmsrq_no_trace(MSR_MISC_FEATURE_CONTROL); native_wrmsrq_no_trace(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits); closid_p = this_cpu_read(pqr_state.cur_closid); rmid_p = this_cpu_read(pqr_state.cur_rmid); diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index b53575dee64a..cdbbfa0b9851 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -380,7 +380,7 @@ static __always_inline void vmx_disable_fb_clear(struct vcpu_vmx *vmx) if (!vmx->disable_fb_clear) return; - msr = native_rdmsrq(MSR_IA32_MCU_OPT_CTRL); + msr = native_rdmsrq_no_trace(MSR_IA32_MCU_OPT_CTRL); msr |= FB_CLEAR_DIS; native_wrmsrq_no_trace(MSR_IA32_MCU_OPT_CTRL, msr); /* Cache the MSR value to avoid reading it later */ @@ -7307,7 +7307,7 @@ void noinstr vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx, return; if (flags & VMX_RUN_SAVE_SPEC_CTRL) - vmx->spec_ctrl = native_rdmsrq(MSR_IA32_SPEC_CTRL); + vmx->spec_ctrl = native_rdmsrq_no_trace(MSR_IA32_SPEC_CTRL); /* * If the guest/host SPEC_CTRL values differ, restore the host value. From patchwork Tue Apr 22 08:22:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xin Li \(Intel\)" X-Patchwork-Id: 883459 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93CF025484B; Tue, 22 Apr 2025 08:23:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745310232; cv=none; b=MJ2w1H0bcJw8XD0MSqWTd5uDwMUKBZ2hU4HqFz0il8EoWgBY+wfVnRIyvyXln3rHExlmIHnD5iPiJEKD0kQQnaJirzL6dCMUrwhPHhaPfUNuc2ep94YGKfaa0wUEAkOETbVZ4vwwkhrUCXZQW61Z9BvBg32G3Z+pCayWDcW+ozA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745310232; c=relaxed/simple; bh=pb7DxqE8fahU4/PYdnnj4sfsCEZ82VcTsq5O/G9NAD4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TzEFAUmOy5xULH3/nNIvNWUNj0bDfSIBhDs6rkuziSvfssW6Wy4LpFdRPf7UKiu/yxRE0k4F4CxHhlQ+9m6pXdQfmDmHh2xL+mb6QlA3V/9R7koNoaZz5cUrWGKVWGBJcF99pyMdsG/10Z79vC98TC7Kdx02k8QSeNVaNOMiiL0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com; spf=pass smtp.mailfrom=zytor.com; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b=N6j53RZd; arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="N6j53RZd" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 53M8MG9i1954391 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Tue, 22 Apr 2025 01:23:21 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53M8MG9i1954391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745310203; bh=KF9UoUhpkeUaxol5GmRaBP0wotoAE475jYCZa+6vJrk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N6j53RZda7Hnrm3Z8UyJWyl2m7EfT1Jh76ZttRjn46pCv8YaQQ+xpoMdgq0mPnpKT EwUMoOWhnYnb1/5hgNgmETHvL/rJmUEuW/oCXN9+U/55daY2aP+9r3mvUTRZj/8bsV Hiuiyy+A89g2q4kl9x9SYelhIwx/krb/rTlGpcOePi8Lcb7Yrrt0i5MwE/MwittSk8 DUwskE+3zk5l9DH1aLljDwGukqrX7eL9Kc94LgWeRGlyrPWt2CjUbcUdgwBwaB+ifk emZJByhMB2HFpmTeT9i0/P2Ha3s458mTGVQRX0DFn5l6yAdmgruipzB9tsCHO66Px/ QI5yU9wp4aydw== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Subject: [RFC PATCH v2 30/34] x86/msr: Rename native_rdmsr() to native_rdmsr_no_trace() Date: Tue, 22 Apr 2025 01:22:11 -0700 Message-ID: <20250422082216.1954310-31-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250422082216.1954310-1-xin@zytor.com> References: <20250422082216.1954310-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 native_rdmsr() doesn't do trace thus can be used in noinstr context, rename it to native_rdmsr_no_trace() to make it explicit. Signed-off-by: Xin Li (Intel) --- arch/x86/include/asm/microcode.h | 2 +- arch/x86/include/asm/msr.h | 8 ++++---- arch/x86/kernel/cpu/microcode/amd.c | 2 +- arch/x86/kernel/cpu/microcode/core.c | 2 +- arch/x86/kernel/cpu/microcode/intel.c | 2 +- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index da482f430d80..d581fdaf1f36 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -69,7 +69,7 @@ static inline u32 intel_get_microcode_revision(void) native_cpuid_eax(1); /* get the current revision from MSR 0x8B */ - native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev); + native_rdmsr_no_trace(MSR_IA32_UCODE_REV, dummy, rev); return rev; } diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 050d750a5ab7..dfaac42b6258 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -158,9 +158,9 @@ static __always_inline bool is_msr_imm_insn(void *ip) * / \ | * / \ | * native_rdmsrq_no_trace() native_read_msr_safe() | - * / \ | - * / \ | - * native_rdmsr() native_read_msr() | + * / \ | + * / \ | + * native_rdmsr_no_trace() native_read_msr() | * | * | * | @@ -256,7 +256,7 @@ static __always_inline u64 native_rdmsrq_no_trace(u32 msr) return val; } -#define native_rdmsr(msr, low, high) \ +#define native_rdmsr_no_trace(msr, low, high) \ do { \ u64 __val = native_rdmsrq_no_trace(msr); \ (void)((low) = (u32)__val); \ diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index 41c553396500..f1f275ddab57 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -256,7 +256,7 @@ static u32 get_patch_level(void) { u32 rev, dummy __always_unused; - native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); + native_rdmsr_no_trace(MSR_AMD64_PATCH_LEVEL, rev, dummy); return rev; } diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index b3658d11e7b6..9bda8fd987ab 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -84,7 +84,7 @@ static bool amd_check_current_patch_level(void) u32 lvl, dummy, i; u32 *levels; - native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy); + native_rdmsr_no_trace(MSR_AMD64_PATCH_LEVEL, lvl, dummy); levels = final_levels; diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 26e13dc4cedd..c0307b1ad63d 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -78,7 +78,7 @@ void intel_collect_cpu_info(struct cpu_signature *sig) unsigned int val[2]; /* get processor flags from MSR 0x17 */ - native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); + native_rdmsr_no_trace(MSR_IA32_PLATFORM_ID, val[0], val[1]); sig->pf = 1 << ((val[1] >> 18) & 7); } } From patchwork Tue Apr 22 08:22:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xin Li \(Intel\)" X-Patchwork-Id: 883446 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90A8026E160; Tue, 22 Apr 2025 08:24:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="JnWtZCem" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 53M8MG9j1954391 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Tue, 22 Apr 2025 01:23:24 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53M8MG9j1954391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745310205; bh=PfH0d70H/awMl+pIfi176SABhujHw41azze32+OJXmk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JnWtZCemkFX6NCD7mP/s8qoAFT3h3Gb+Fvc+J5Mk02eaVtZrWyrmVnlpXwmVAvy41 houfWnQz9wGOKn2yRaZanE3IjEltuS0f/5cW2rlJmBwVly9l6LLAqVurtWi3thuZcM ji5BPEgLgOQkXAsMX4hjSxG1dqBUP9qrDSURde+feL4tlBBsfHS0nQPq1ugkmkwkBm Qf94NiRrS85WPrGN0VWgL6mlH/GHv4SGGPAIIC3MsntY56esV8EU1L6d8KeTVhVlvC nqDxaHuS3Och/kSL44qglJbmmo1kO2jM0JXyCV2y6tezwHqg8Wal5lhgPQfwgfhBGG UQBpBNOph9P0Q== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Subject: [RFC PATCH v2 31/34] x86/msr: Rename native_read_msr() to native_rdmsrq() Date: Tue, 22 Apr 2025 01:22:12 -0700 Message-ID: <20250422082216.1954310-32-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250422082216.1954310-1-xin@zytor.com> References: <20250422082216.1954310-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Signed-off-by: Xin Li (Intel) --- arch/x86/hyperv/ivm.c | 2 +- arch/x86/include/asm/msr.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c index dfddf522e838..8860c6c0f013 100644 --- a/arch/x86/hyperv/ivm.c +++ b/arch/x86/hyperv/ivm.c @@ -319,7 +319,7 @@ int hv_snp_boot_ap(u32 cpu, unsigned long start_ip) asm volatile("movl %%ds, %%eax;" : "=a" (vmsa->ds.selector)); hv_populate_vmcb_seg(vmsa->ds, vmsa->gdtr.base); - vmsa->efer = native_read_msr(MSR_EFER); + vmsa->efer = native_rdmsrq(MSR_EFER); vmsa->cr4 = native_read_cr4(); vmsa->cr3 = __native_read_cr3(); diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index dfaac42b6258..4c7aa9e7fbac 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -160,7 +160,7 @@ static __always_inline bool is_msr_imm_insn(void *ip) * native_rdmsrq_no_trace() native_read_msr_safe() | * / \ | * / \ | - * native_rdmsr_no_trace() native_read_msr() | + * native_rdmsr_no_trace() native_rdmsrq() | * | * | * | @@ -263,7 +263,7 @@ do { \ (void)((high) = (u32)(__val >> 32)); \ } while (0) -static inline u64 native_read_msr(u32 msr) +static inline u64 native_rdmsrq(u32 msr) { u64 val = native_rdmsrq_no_trace(msr); From patchwork Tue Apr 22 08:22:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xin Li \(Intel\)" X-Patchwork-Id: 883450 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE383266B44; 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} -static inline int native_read_msr_safe(u32 msr, u64 *val) +static inline int native_rdmsrq_safe(u32 msr, u64 *val) { int err; diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 01dd3cd20730..251fd9366b35 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -481,7 +481,7 @@ static void svm_init_erratum_383(void) return; /* Use _safe variants to not break nested virtualization */ - if (native_read_msr_safe(MSR_AMD64_DC_CFG, &val)) + if (native_rdmsrq_safe(MSR_AMD64_DC_CFG, &val)) return; val |= (1ULL << 47); @@ -649,9 +649,9 @@ static int svm_enable_virtualization_cpu(void) u64 len, status = 0; int err; - err = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &len); + err = native_rdmsrq_safe(MSR_AMD64_OSVW_ID_LENGTH, &len); if (!err) - err = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, &status); + err = native_rdmsrq_safe(MSR_AMD64_OSVW_STATUS, &status); if (err) osvw_status = osvw_len = 0; @@ -2148,7 +2148,7 @@ static bool is_erratum_383(void) if (!erratum_383_found) return false; - if (native_read_msr_safe(MSR_IA32_MC0_STATUS, &value)) + if (native_rdmsrq_safe(MSR_IA32_MC0_STATUS, &value)) return false; /* Bit 62 may or may not be set for this mce */ @@ -2161,7 +2161,7 @@ static bool is_erratum_383(void) for (i = 0; i < 6; ++i) native_wrmsrq_safe(MSR_IA32_MCx_STATUS(i), 0); - if (!native_read_msr_safe(MSR_IA32_MCG_STATUS, &value)) { + if (!native_rdmsrq_safe(MSR_IA32_MCG_STATUS, &value)) { value &= ~(1ULL << 2); native_wrmsrq_safe(MSR_IA32_MCG_STATUS, value); } diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c index ee908dfcff48..66d2c6fc7bfa 100644 --- a/arch/x86/xen/pmu.c +++ b/arch/x86/xen/pmu.c @@ -323,7 +323,7 @@ static u64 xen_amd_read_pmc(int counter) u64 val; msr = amd_counters_base + (counter * amd_msr_step); - native_read_msr_safe(msr, &val); + native_rdmsrq_safe(msr, &val); return val; } @@ -349,7 +349,7 @@ static u64 xen_intel_read_pmc(int counter) else msr = MSR_IA32_PERFCTR0 + counter; - native_read_msr_safe(msr, &val); + native_rdmsrq_safe(msr, &val); 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Tue, 22 Apr 2025 01:23:28 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53M8MG9l1954391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745310210; bh=WuTf4DKpHMtSM1ra3KvkSmb+zvqoPj+dUC25U2G1occ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QKcrrs1CLj1GklRXrRY5aS2PCtwaEhGTlYpiDyTQTjEtLCtpGP6PF4lU6okTlCAxs YcOPgbljQyNdip4ad/TqaWX7E6oaZNhnbuHaO/9CAxKWtXtH5IcEpsPeCqrhCapA2j 7/sjlQ+echmy0OGy5x+sG8HYkRhBfTDD46yscv1eNtFvuMspT3EJZSfGIsXT9FuHEP lwGS4cuq9Pl52a1bmYOQrcwDRDzLfN6Hjtx3Y5PSt1EOkUcnE2fwjGxqtkl4sfrZ/e 1E4b3AKvled+9XSPax5BGjZyR4j5ep8Tvn55jTFJhcMHXdiudbJQjCPXUevI1KzTbM JdJzBLsp4NdOg== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Subject: [RFC PATCH v2 33/34] x86/msr: Move the ARGS macros after the MSR read/write APIs Date: Tue, 22 Apr 2025 01:22:14 -0700 Message-ID: <20250422082216.1954310-34-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250422082216.1954310-1-xin@zytor.com> References: <20250422082216.1954310-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Since the ARGS macros are no longer used in the MSR read/write API implementation, move them after their definitions. Signed-off-by: Xin Li (Intel) --- arch/x86/include/asm/msr.h | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index b4447ba4d6c2..be593a15a838 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -38,23 +38,6 @@ struct saved_msrs { struct saved_msr *array; }; -/* - * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" - * constraint has different meanings. For i386, "A" means exactly - * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, - * it means rax *or* rdx. - */ -#ifdef CONFIG_X86_64 -/* Using 64-bit values saves one instruction clearing the high half of low */ -#define DECLARE_ARGS(val, low, high) unsigned long low, high -#define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32) -#define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) -#else -#define DECLARE_ARGS(val, low, high) u64 val -#define EAX_EDX_VAL(val, low, high) (val) -#define EAX_EDX_RET(val, low, high) "=A" (val) -#endif - /* * Be very careful with includes. This header is prone to include loops. */ @@ -559,6 +542,23 @@ static __always_inline int wrmsr_safe(u32 msr, u32 low, u32 high) extern int rdmsr_safe_regs(u32 regs[8]); extern int wrmsr_safe_regs(u32 regs[8]); +/* + * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" + * constraint has different meanings. For i386, "A" means exactly + * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, + * it means rax *or* rdx. + */ +#ifdef CONFIG_X86_64 +/* Using 64-bit values saves one instruction clearing the high half of low */ +#define DECLARE_ARGS(val, low, high) unsigned long low, high +#define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32) +#define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) +#else +#define DECLARE_ARGS(val, low, high) u64 val +#define EAX_EDX_VAL(val, low, high) (val) +#define EAX_EDX_RET(val, low, high) "=A" (val) +#endif + static __always_inline u64 native_rdpmcq(int counter) { DECLARE_ARGS(val, low, high); @@ -571,6 +571,10 @@ static __always_inline u64 native_rdpmcq(int counter) return EAX_EDX_VAL(val, low, high); } +#undef DECLARE_ARGS +#undef EAX_EDX_VAL +#undef EAX_EDX_RET + static __always_inline u64 rdpmcq(int counter) { #ifdef CONFIG_XEN_PV From patchwork Tue Apr 22 08:22:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xin Li \(Intel\)" X-Patchwork-Id: 883451 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 665012566EA; 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arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="Uc1b2MMH" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 53M8MG9m1954391 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Tue, 22 Apr 2025 01:23:30 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53M8MG9m1954391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745310212; bh=qnYCpm2Cl6ZIZ5hId3xkbPkJqqrZQFZfyOkhGDhffqY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Uc1b2MMHUkmSSWkI2MOrRUT6ZGc7p2OK1RO57VTRGzrFk3nJp7mExF9yRLqhXwrcN BEEh5kJRgcNa0ORqLGKos3bgYft/LGNyer5Hj/VmrWBwEfN4bo5k4h7fYDJnj7l0iH x3KPzP8Y8/4VNpO8JH9Yfwzhho87jdCmeXcBpjzy/qaN1+VLUT/st/KMk2S7jIMbTL ErV/dz7vQ+VWICcFlhVd+X7D1ljAh8bI0Ed7Om76UDvHltu1oSI+3z4c9vWm1fO4pm 4dTYUhuIvfW4g6DD8/vRKD69Q3YVmGv0OG8qFORLYD4AB4LVkHungT3s69bi00Wvfu KweyIKTZ9esZQ== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Subject: [RFC PATCH v2 34/34] x86/msr: Convert native_rdmsr_no_trace() uses to native_rdmsrq_no_trace() uses Date: Tue, 22 Apr 2025 01:22:15 -0700 Message-ID: <20250422082216.1954310-35-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250422082216.1954310-1-xin@zytor.com> References: <20250422082216.1954310-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Convert native_rdmsr_no_trace() uses to native_rdmsrq_no_trace() uses cleanly with the use of struct msr, and remove native_rdmsr_no_trace(). Signed-off-by: Xin Li (Intel) --- arch/x86/include/asm/microcode.h | 6 +++--- arch/x86/include/asm/msr.h | 13 +++---------- arch/x86/kernel/cpu/microcode/amd.c | 8 ++------ arch/x86/kernel/cpu/microcode/core.c | 4 ++-- arch/x86/kernel/cpu/microcode/intel.c | 6 +++--- 5 files changed, 13 insertions(+), 24 deletions(-) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index d581fdaf1f36..1d9641349744 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -61,7 +61,7 @@ static inline int intel_microcode_get_datasize(struct microcode_header_intel *hd static inline u32 intel_get_microcode_revision(void) { - u32 rev, dummy; + struct msr val; native_wrmsrq_no_trace(MSR_IA32_UCODE_REV, 0); @@ -69,9 +69,9 @@ static inline u32 intel_get_microcode_revision(void) native_cpuid_eax(1); /* get the current revision from MSR 0x8B */ - native_rdmsr_no_trace(MSR_IA32_UCODE_REV, dummy, rev); + val.q = native_rdmsrq_no_trace(MSR_IA32_UCODE_REV); - return rev; + return val.h; } #endif /* !CONFIG_CPU_SUP_INTEL */ diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index be593a15a838..aebcd846af3e 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -141,9 +141,9 @@ static __always_inline bool is_msr_imm_insn(void *ip) * / \ | * / \ | * native_rdmsrq_no_trace() native_rdmsrq_safe() | - * / \ | - * / \ | - * native_rdmsr_no_trace() native_rdmsrq() | + * / | + * / | + * native_rdmsrq() | * | * | * | @@ -239,13 +239,6 @@ static __always_inline u64 native_rdmsrq_no_trace(u32 msr) return val; } -#define native_rdmsr_no_trace(msr, low, high) \ -do { \ - u64 __val = native_rdmsrq_no_trace(msr); \ - (void)((low) = (u32)__val); \ - (void)((high) = (u32)(__val >> 32)); \ -} while (0) - static inline u64 native_rdmsrq(u32 msr) { u64 val = native_rdmsrq_no_trace(msr); diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index f1f275ddab57..b4d66e79089c 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -254,11 +254,7 @@ static bool verify_sha256_digest(u32 patch_id, u32 cur_rev, const u8 *data, unsi static u32 get_patch_level(void) { - u32 rev, dummy __always_unused; - - native_rdmsr_no_trace(MSR_AMD64_PATCH_LEVEL, rev, dummy); - - return rev; + return native_rdmsrq_no_trace(MSR_AMD64_PATCH_LEVEL); } static union cpuid_1_eax ucode_rev_to_cpuid(unsigned int val) @@ -835,7 +831,7 @@ static struct ucode_patch *find_patch(unsigned int cpu) void reload_ucode_amd(unsigned int cpu) { - u32 rev, dummy __always_unused; + u32 rev; struct microcode_amd *mc; struct ucode_patch *p; diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 9bda8fd987ab..81b264373d3e 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -81,10 +81,10 @@ struct early_load_data early_data; */ static bool amd_check_current_patch_level(void) { - u32 lvl, dummy, i; + u32 lvl, i; u32 *levels; - native_rdmsr_no_trace(MSR_AMD64_PATCH_LEVEL, lvl, dummy); + lvl = native_rdmsrq_no_trace(MSR_AMD64_PATCH_LEVEL); levels = final_levels; diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index c0307b1ad63d..1b484214f3ee 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -75,11 +75,11 @@ void intel_collect_cpu_info(struct cpu_signature *sig) sig->rev = intel_get_microcode_revision(); if (IFM(x86_family(sig->sig), x86_model(sig->sig)) >= INTEL_PENTIUM_III_DESCHUTES) { - unsigned int val[2]; + struct msr val; /* get processor flags from MSR 0x17 */ - native_rdmsr_no_trace(MSR_IA32_PLATFORM_ID, val[0], val[1]); - sig->pf = 1 << ((val[1] >> 18) & 7); + val.q = native_rdmsrq_no_trace(MSR_IA32_PLATFORM_ID); + sig->pf = 1 << ((val.h >> 18) & 7); } } EXPORT_SYMBOL_GPL(intel_collect_cpu_info);