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[2001:470:142::17]) by mx.google.com with ESMTPS id 2si1288732qkp.253.2020.05.06.11.35.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 May 2020 11:35:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:470:142::17 as permitted sender) client-ip=2001:470:142::17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QdkekIIT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:470:142::17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35292 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jWOtF-0002EM-Tu for patch@linaro.org; Wed, 06 May 2020 14:35:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60824) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jWOo4-0004MQ-7y for qemu-devel@nongnu.org; Wed, 06 May 2020 14:30:08 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:46346) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jWOo2-0002my-W5 for qemu-devel@nongnu.org; Wed, 06 May 2020 14:30:07 -0400 Received: by mail-pg1-x52b.google.com with SMTP id q124so1163096pgq.13 for ; Wed, 06 May 2020 11:30:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BLcD9N9MlInNi6OgkZr1QrgaUSOVwaTdYcH5SM4Yl98=; b=QdkekIITCGsJJcE+GYs0/vyd5osLMdYMd9NVK0DA6FTzwdxoU3nvx9LMkhOfsD6ADj 50akld1Cq4Avv3AOQFQm7mZTga5MTpPLd/Bp5HW6vO8YqoyKBOoG4aLMerXUxA6zxgok 9WIhPwVAmrrUdeeY/4w8dJipFhmJho3Yjpudrk007Vdi9Tp4F9HqYuoiJq0RcF5HnOsL twREaol40FlWDrDTReTDgpWCRG358LxyvvhuHLETcF2hq6lXbJhcsrnGDUu1QDH4lix5 8r+HpwNIZq8zmJwchIb6D3RdkWBotXMPqMA8HrJO6lipKF/pNUOYbCuKENAW5KF435N5 mDVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BLcD9N9MlInNi6OgkZr1QrgaUSOVwaTdYcH5SM4Yl98=; b=BcGMCF40Cl4ikB5MyQGx04FNWg1oFxVuBJKOqWabhHtlExre2YIGo9LiPUNTiHjBN8 YdwiphqwfGqVs4wbv9maoE1t9eFLw/3ebIXPbFr0wdlSMowx3FJX3kHK2VvE3+z0eTK8 wuf0Or9U9SHZeCjH8bbHgO2iu8ne5eWuhYYW2Rr4+dT/516kZHjtRHaD7RBB+WOfdjVI D5cBi6bBDyx+7poWF4zyFK0hRcE4yG1RgsIiw1wk931CVmdiDuFpnKwjaXhJtdWAXLzO eIHQyW58S6oh/P04GpGbg2xiiqBAiZ+m03mcF/FmItuUSrNW50SvmnWU91Qr4CYLThtk FoOw== X-Gm-Message-State: AGi0Pubf6QU8qhv9xjYPtI+axya/E/Vs/9U71yshc+MX85tHG83tQ6gF ginbOX9ISS/Sqerl25NNTnyhhjJw0Z4= X-Received: by 2002:a62:1657:: with SMTP id 84mr9374082pfw.51.1588789805064; Wed, 06 May 2020 11:30:05 -0700 (PDT) Received: from localhost.localdomain (174-21-149-226.tukw.qwest.net. [174.21.149.226]) by smtp.gmail.com with ESMTPSA id w11sm2572589pfq.100.2020.05.06.11.30.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2020 11:30:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 01/10] tcg: Add tcg_gen_gvec_dup_imm Date: Wed, 6 May 2020 11:29:53 -0700 Message-Id: <20200506183002.3192-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200506183002.3192-1-richard.henderson@linaro.org> References: <20200506183002.3192-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= , LIU Zhiwei , David Hildenbrand Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a version of tcg_gen_dup_* that takes both immediate and a vector element size operand. This will replace the set of tcg_gen_gvec_dup{8,16,32,64}i functions that encode the element size within the function name. Reviewed-by: LIU Zhiwei Reviewed-by: David Hildenbrand Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 2 ++ tcg/tcg-op-gvec.c | 7 +++++++ 2 files changed, 9 insertions(+) -- 2.20.1 diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index 74534e2480..eb0d47a42b 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -313,6 +313,8 @@ void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t s, uint32_t m); +void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t s, + uint32_t m, uint64_t imm); void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s, uint32_t m, TCGv_i32); void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s, diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 327d9588e0..593bb4542e 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -1569,6 +1569,13 @@ void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz, do_dup(MO_8, dofs, oprsz, maxsz, NULL, NULL, x); } +void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t oprsz, + uint32_t maxsz, uint64_t x) +{ + check_size_align(oprsz, maxsz, dofs); + do_dup(vece, dofs, oprsz, maxsz, NULL, NULL, x); +} + void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz) { From patchwork Wed May 6 18:29:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186266 Delivered-To: patch@linaro.org Received: by 2002:a92:8d81:0:0:0:0:0 with SMTP id w1csp2407089ill; Wed, 6 May 2020 11:30:50 -0700 (PDT) X-Google-Smtp-Source: APiQypJTot3EFhIzx/AxzOUBFYdxW71pFpC4Z/QZyA+lY8Feik0HOiVRvmTiiSXfmyKe2a/63U/M X-Received: by 2002:ac8:4b4c:: with SMTP id e12mr9917680qts.78.1588789850291; Wed, 06 May 2020 11:30:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1588789850; cv=none; d=google.com; s=arc-20160816; b=OuDJpqAbz8XnCzBOskiWp0K39PlUsdZI0WS+KI/sfVdyyqAmxpVB258/sQCSODKwIM zFN5ywyCtqocqLuAmUDtabg/f4J4d1ub0uesffVmsxEDix2xdMXLaXEazc+qkptAfzir bQk8vxNAiQI/o12/S2fziAo/rix9epIKxHIuVimCgNTjqoiYf9lNLcmfz/MQyOXlaQBF AcpVHpbAhuXoi2VUQH994NbiYeo663VMgAD+oMhfOQgve44bjKan4fp1xvF8PHF5fi6G RpXiEvGLyPJ7L7xbOm1D+zwiI2UdoRM6k+OH6ZVU0m63q2CaTzgVVP7lMzQtt8Bskpr0 tdYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dOnBBGhmkNTpQUIqTasvNhE2MTWW7gI0dB3WMtwwkiQ=; b=Y14gSkLP6fgiWohHzsaufcbiouigub9th6WIwdf2afpLAiBOA+inoGCuek86OL+KPE KBuBlqCZtiyquPRUjwn/iqTsXviIrZmuap/FCJ6q45OlYFWxZdngzVsDuXYzE8pd8Psb LZnnqcQkruSQ55b9YwJkl3RkSx32dcv14424TNwllvmgGi2XlFio1FVVo1Ho4CjtQd+d kYWPdIVtoWMpxz0Yn/2GUMScdQ7ZkrzDBal5ptZkb6IWCZHZbgLiKXQaWCQP/ZOnGswH OUlgXoCMLCIP1cZwmZG+Ds+G4H6nPiM3zQanZg14EJsjMjcZU+fb751WVoFKRx5/DNgO fL8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=tq6brdX7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:470:142::17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id w11sm2572589pfq.100.2020.05.06.11.30.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2020 11:30:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 02/10] target/s390x: Use tcg_gen_gvec_dup_imm Date: Wed, 6 May 2020 11:29:54 -0700 Message-Id: <20200506183002.3192-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200506183002.3192-1-richard.henderson@linaro.org> References: <20200506183002.3192-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= , David Hildenbrand Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The gen_gvec_dupi switch is unnecessary with the new function. Replace it with a local gen_gvec_dup_imm that takes care of the register to offset conversion and length arguments. Drop zero_vec and use use gen_gvec_dup_imm with 0. Reviewed-by: David Hildenbrand Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/s390x/translate_vx.inc.c | 41 +++++++-------------------------- 1 file changed, 8 insertions(+), 33 deletions(-) -- 2.20.1 diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c index 24558cce80..12347f8a03 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -231,8 +231,8 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr, #define gen_gvec_mov(v1, v2) \ tcg_gen_gvec_mov(0, vec_full_reg_offset(v1), vec_full_reg_offset(v2), 16, \ 16) -#define gen_gvec_dup64i(v1, c) \ - tcg_gen_gvec_dup64i(vec_full_reg_offset(v1), 16, 16, c) +#define gen_gvec_dup_imm(es, v1, c) \ + tcg_gen_gvec_dup_imm(es, vec_full_reg_offset(v1), 16, 16, c); #define gen_gvec_fn_2(fn, es, v1, v2) \ tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ 16, 16) @@ -316,31 +316,6 @@ static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a, tcg_temp_free_i64(cl); } -static void gen_gvec_dupi(uint8_t es, uint8_t reg, uint64_t c) -{ - switch (es) { - case ES_8: - tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, c); - break; - case ES_16: - tcg_gen_gvec_dup16i(vec_full_reg_offset(reg), 16, 16, c); - break; - case ES_32: - tcg_gen_gvec_dup32i(vec_full_reg_offset(reg), 16, 16, c); - break; - case ES_64: - gen_gvec_dup64i(reg, c); - break; - default: - g_assert_not_reached(); - } -} - -static void zero_vec(uint8_t reg) -{ - tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, 0); -} - static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, uint64_t b) { @@ -396,8 +371,8 @@ static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o) * Masks for both 64 bit elements of the vector are the same. * Trust tcg to produce a good constant loading. */ - gen_gvec_dup64i(get_field(s, v1), - generate_byte_mask(i2 & 0xff)); + gen_gvec_dup_imm(ES_64, get_field(s, v1), + generate_byte_mask(i2 & 0xff)); } else { TCGv_i64 t = tcg_temp_new_i64(); @@ -432,7 +407,7 @@ static DisasJumpType op_vgm(DisasContext *s, DisasOps *o) } } - gen_gvec_dupi(es, get_field(s, v1), mask); + gen_gvec_dup_imm(es, get_field(s, v1), mask); return DISAS_NEXT; } @@ -585,7 +560,7 @@ static DisasJumpType op_vllez(DisasContext *s, DisasOps *o) t = tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es); - zero_vec(get_field(s, v1)); + gen_gvec_dup_imm(es, get_field(s, v1), 0); write_vec_element_i64(t, get_field(s, v1), enr, es); tcg_temp_free_i64(t); return DISAS_NEXT; @@ -892,7 +867,7 @@ static DisasJumpType op_vrepi(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - gen_gvec_dupi(es, get_field(s, v1), data); + gen_gvec_dup_imm(es, get_field(s, v1), data); return DISAS_NEXT; } @@ -1372,7 +1347,7 @@ static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o) read_vec_element_i32(tmp, get_field(s, v2), i, ES_32); tcg_gen_add2_i32(tmp, sum, sum, sum, tmp, tmp); } - zero_vec(get_field(s, v1)); + gen_gvec_dup_imm(ES_32, get_field(s, v1), 0); write_vec_element_i32(sum, get_field(s, v1), 1, ES_32); tcg_temp_free_i32(tmp); From patchwork Wed May 6 18:29:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186268 Delivered-To: patch@linaro.org Received: by 2002:a92:8d81:0:0:0:0:0 with SMTP id w1csp2408957ill; Wed, 6 May 2020 11:32:47 -0700 (PDT) X-Google-Smtp-Source: APiQypKvkEkomOhsfvKCxJEDf7xKrRHv4ChTBrLQr2DKQWUzi5MFsSC3e6+IGyVtV0fIOCn2u4/Z X-Received: by 2002:a05:620a:4f0:: with SMTP id b16mr10128044qkh.165.1588789967566; Wed, 06 May 2020 11:32:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1588789967; cv=none; d=google.com; s=arc-20160816; b=JGqizijUFbVPCl6+shAZI7ztbZC+fDarkXn08V2c7IaZmtTUBMQFepSwFEBtH5UtAc a4If2RAokIr5kAEw/FvLwhfKlALMEhO9zfi+gkJAEpWUHjQY4wz4v0nCY62MWDK+TBwq J5TjVtPZltr33eKAKor4cJRSiq+H6poghoajxnqK/WLEaahGV24qUF6xHTdA5+dnJqAE Q5FELIsT2ew+Kb5wOZuIfRs+P57cBNa4pfEwoDuvAML/4UcTvqu5A6p/Bo7bZxnosFRQ q4W4tR2bevTR7B3umAWpkwHSU0QZwKAu0U5xkKUBR4b/iWGbbXEwnzSE7YZ11iz+Oyrs vOPA== ARC-Message-Signature: i=1; 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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id w11sm2572589pfq.100.2020.05.06.11.30.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2020 11:30:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 03/10] target/ppc: Use tcg_gen_gvec_dup_imm Date: Wed, 6 May 2020 11:29:55 -0700 Message-Id: <20200506183002.3192-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200506183002.3192-1-richard.henderson@linaro.org> References: <20200506183002.3192-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can now unify the implementation of the 3 VSPLTI instructions. Acked-by: David Gibson Signed-off-by: Richard Henderson --- target/ppc/translate/vmx-impl.inc.c | 32 ++++++++++++++++------------- target/ppc/translate/vsx-impl.inc.c | 2 +- 2 files changed, 19 insertions(+), 15 deletions(-) -- 2.20.1 diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c index 81d5a7a341..403ed3a01c 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -1035,21 +1035,25 @@ GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \ GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \ vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207) -#define GEN_VXFORM_DUPI(name, tcg_op, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) \ - { \ - int simm; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - simm = SIMM5(ctx->opcode); \ - tcg_op(avr_full_offset(rD(ctx->opcode)), 16, 16, simm); \ +static void gen_vsplti(DisasContext *ctx, int vece) +{ + int simm; + + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; } -GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12); -GEN_VXFORM_DUPI(vspltish, tcg_gen_gvec_dup16i, 6, 13); -GEN_VXFORM_DUPI(vspltisw, tcg_gen_gvec_dup32i, 6, 14); + simm = SIMM5(ctx->opcode); + tcg_gen_gvec_dup_imm(vece, avr_full_offset(rD(ctx->opcode)), 16, 16, simm); +} + +#define GEN_VXFORM_VSPLTI(name, vece, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) { gen_vsplti(ctx, vece); } + +GEN_VXFORM_VSPLTI(vspltisb, MO_8, 6, 12); +GEN_VXFORM_VSPLTI(vspltish, MO_16, 6, 13); +GEN_VXFORM_VSPLTI(vspltisw, MO_32, 6, 14); #define GEN_VXFORM_NOA(name, opc2, opc3) \ static void glue(gen_, name)(DisasContext *ctx) \ @@ -1559,7 +1563,7 @@ GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE, #undef GEN_VXRFORM_DUAL #undef GEN_VXRFORM1 #undef GEN_VXRFORM -#undef GEN_VXFORM_DUPI +#undef GEN_VXFORM_VSPLTI #undef GEN_VXFORM_NOA #undef GEN_VXFORM_UIMM #undef GEN_VAFORM_PAIRED diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 8287e272f5..b518de46db 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1579,7 +1579,7 @@ static void gen_xxspltib(DisasContext *ctx) return; } } - tcg_gen_gvec_dup8i(vsr_full_offset(rt), 16, 16, uim8); + tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(rt), 16, 16, uim8); } static void gen_xxsldwi(DisasContext *ctx) From patchwork Wed May 6 18:29:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186264 Delivered-To: patch@linaro.org Received: by 2002:a92:8d81:0:0:0:0:0 with SMTP id w1csp2406760ill; Wed, 6 May 2020 11:30:27 -0700 (PDT) X-Google-Smtp-Source: APiQypI/3F7eR0CMeQ7xskUAUoyhxlskU/nTar0ajeJtm2emzjrQIvxtJ/0B6af5sib0BjcsqIg7 X-Received: by 2002:ac8:4809:: with SMTP id g9mr9893021qtq.33.1588789826913; Wed, 06 May 2020 11:30:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1588789826; cv=none; d=google.com; s=arc-20160816; b=TV2+nyTlIvAnpih0I8TPUDNAmKcR1m854yrEm4wRPb3DlKpUgjSIA811zAN8p92a1u De2kye1kY1FDA93jTNoVXhdPYP/0vucCian3+Un4DOZASo79nwq6wESMoWH5nPT1jzUD G0ecyOjOJbVrcR6a9T8kghhsT1G+7U6NI2Pjl2vRwkGV/ibR0juOQ3QcQXp5QjCWPqHo Wq65L9ilefOG8fvQWBFL/ysUU6tvxzsegK/SqKkJpYk+pdyol7YKkpaVZY17VpuSJ7nU kriQAISqXmfl7gbcO/nB0nW54dy0e1+ov2GYFDj9PrUdwwzXEx/yRluUOR8PtJW96dru GEog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5E0pEn1U5VJfEC9GIolsazf+hdnyrEpcxC1RvioT0xA=; b=tEHibTRnBynbvMZRfc+vOkCXsfHXDp1fWFkRzQBcJLPRVzvNNYYCR01BMqwqEbakxu cy0Fq4yW/dH2Nuf3w+DnH52QL6ANuBWHaUNkCsvP+ILMlAF0igmHAMCYQQiAAwBgKOtb Ui45i9RHmHBC2QS4PCjoGYD2qWIeK38SGbpR81fl611EqFZQtkhJ4UkN4g2h5WR1q8jJ TQGjzGb/EGkAstcBB0+UhKuAnZIQv9uywYhs/k+rVm+yQGxc5RAYmFfYLG5apUmS2945 KgUElpejva0z25E3GzODIhWEqGqwh48qkSrAoeQo7zPXmRlc4mL+HGTr2oE8uejdmbMM oQJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jFLvcqiY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:470:142::17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id w11sm2572589pfq.100.2020.05.06.11.30.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2020 11:30:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 04/10] target/arm: Use tcg_gen_gvec_dup_imm Date: Wed, 6 May 2020 11:29:56 -0700 Message-Id: <20200506183002.3192-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200506183002.3192-1-richard.henderson@linaro.org> References: <20200506183002.3192-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In a few cases, we're able to remove some manual replication. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 10 +++++----- target/arm/translate-sve.c | 12 +++++------- target/arm/translate.c | 9 ++++++--- 3 files changed, 16 insertions(+), 15 deletions(-) -- 2.20.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a896f9c4b8..62e5729904 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -502,7 +502,7 @@ static void clear_vec_high(DisasContext *s, bool is_q, int rd) tcg_temp_free_i64(tcg_zero); } if (vsz > 16) { - tcg_gen_gvec_dup8i(ofs + 16, vsz - 16, vsz - 16, 0); + tcg_gen_gvec_dup_imm(MO_64, ofs + 16, vsz - 16, vsz - 16, 0); } } @@ -7785,8 +7785,8 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) { /* MOVI or MVNI, with MVNI negation handled above. */ - tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), is_q ? 16 : 8, - vec_full_reg_size(s), imm); + tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), is_q ? 16 : 8, + vec_full_reg_size(s), imm); } else { /* ORR or BIC, with BIC negation to AND handled above. */ if (is_neg) { @@ -10214,8 +10214,8 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, if (is_u) { if (shift == 8 << size) { /* Shift count the same size as element size produces zero. */ - tcg_gen_gvec_dup8i(vec_full_reg_offset(s, rd), - is_q ? 16 : 8, vec_full_reg_size(s), 0); + tcg_gen_gvec_dup_imm(size, vec_full_reg_offset(s, rd), + is_q ? 16 : 8, vec_full_reg_size(s), 0); } else { gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shri, size); } diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index b35bad245e..6c8bda4e4c 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -177,7 +177,7 @@ static bool do_mov_z(DisasContext *s, int rd, int rn) static void do_dupi_z(DisasContext *s, int rd, uint64_t word) { unsigned vsz = vec_full_reg_size(s); - tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), vsz, vsz, word); + tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), vsz, vsz, word); } /* Invoke a vector expander on two Pregs. */ @@ -1453,7 +1453,7 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag) unsigned oprsz = size_for_gvec(setsz / 8); if (oprsz * 8 == setsz) { - tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word); + tcg_gen_gvec_dup_imm(MO_64, ofs, oprsz, maxsz, word); goto done; } } @@ -2044,7 +2044,7 @@ static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a) unsigned nofs = vec_reg_offset(s, a->rn, index, esz); tcg_gen_gvec_dup_mem(esz, dofs, nofs, vsz, vsz); } else { - tcg_gen_gvec_dup64i(dofs, vsz, vsz, 0); + tcg_gen_gvec_dup_imm(esz, dofs, vsz, vsz, 0); } } return true; @@ -3260,9 +3260,7 @@ static bool trans_FDUP(DisasContext *s, arg_FDUP *a) /* Decode the VFP immediate. */ imm = vfp_expand_imm(a->esz, a->imm); - imm = dup_const(a->esz, imm); - - tcg_gen_gvec_dup64i(dofs, vsz, vsz, imm); + tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, imm); } return true; } @@ -3276,7 +3274,7 @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a) unsigned vsz = vec_full_reg_size(s); int dofs = vec_full_reg_offset(s, a->rd); - tcg_gen_gvec_dup64i(dofs, vsz, vsz, dup_const(a->esz, a->imm)); + tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, a->imm); } return true; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 025747c0bd..74fac1d09c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5209,7 +5209,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) MIN(shift, (8 << size) - 1), vec_size, vec_size); } else if (shift >= 8 << size) { - tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0); + tcg_gen_gvec_dup_imm(MO_8, rd_ofs, vec_size, + vec_size, 0); } else { tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift, vec_size, vec_size); @@ -5260,7 +5261,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) * architecturally valid and results in zero. */ if (shift >= 8 << size) { - tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0); + tcg_gen_gvec_dup_imm(size, rd_ofs, + vec_size, vec_size, 0); } else { tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift, vec_size, vec_size); @@ -5606,7 +5608,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } tcg_temp_free_i64(t64); } else { - tcg_gen_gvec_dup32i(reg_ofs, vec_size, vec_size, imm); + tcg_gen_gvec_dup_imm(MO_32, reg_ofs, vec_size, + vec_size, imm); } } } From patchwork Wed May 6 18:29:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186269 Delivered-To: patch@linaro.org Received: by 2002:a92:8d81:0:0:0:0:0 with SMTP id w1csp2409137ill; Wed, 6 May 2020 11:33:00 -0700 (PDT) X-Google-Smtp-Source: APiQypKpv4kyVaTSNDC/kJf++x42BsaAngxpjtqNotddto9qUIn5fWxQwfTbdllhmPaYAOWL5SjC X-Received: by 2002:a0c:b5dd:: with SMTP id o29mr9807982qvf.87.1588789980439; Wed, 06 May 2020 11:33:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1588789980; cv=none; d=google.com; s=arc-20160816; b=Z4ER1h9cMulZyOlKuqkEZcfFzXn4EBX65JpxZshUySE31N3tNsthdl5Xd5GsBp9zMO pE0PkbG2r41opsQtMWNcw6RV1T6zzJg+qfLM3JIfxCGTaBwb6VvELj4yEN4WDP22hCIb lIguHNlnS6VUna81X3vC5HC0LQAcnTIVTO1zt/kOOe5nWNU57A5vbusF1w1I0Qm5Geo2 X1wxc4h7OzyaMO3pSFrEvs4Tky5nCXpHqRlpgdZxq9WsqfKFnvRDGHmRdn2iRGt91xgV sotEE26mVmdEclkJdjps6MOZZI88vwT8QDgrbHowQOC5QZCp7IEsoZCa8zOia0q5+IqI /U/Q== ARC-Message-Signature: i=1; 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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id w11sm2572589pfq.100.2020.05.06.11.30.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2020 11:30:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 05/10] tcg: Use tcg_gen_gvec_dup_imm in logical simplifications Date: Wed, 6 May 2020 11:29:57 -0700 Message-Id: <20200506183002.3192-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200506183002.3192-1-richard.henderson@linaro.org> References: <20200506183002.3192-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= , LIU Zhiwei Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Replace the outgoing interface. Reviewed-by: LIU Zhiwei Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 593bb4542e..de16c027b3 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2326,7 +2326,7 @@ void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs, }; if (aofs == bofs) { - tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0); + tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0); } else { tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); } @@ -2343,7 +2343,7 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs, }; if (aofs == bofs) { - tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0); + tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0); } else { tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); } @@ -2360,7 +2360,7 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs, }; if (aofs == bofs) { - tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, -1); + tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, -1); } else { tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); } @@ -2411,7 +2411,7 @@ void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs, }; if (aofs == bofs) { - tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, -1); + tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, -1); } else { tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); } From patchwork Wed May 6 18:29:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186265 Delivered-To: patch@linaro.org Received: by 2002:a92:8d81:0:0:0:0:0 with SMTP id w1csp2406807ill; Wed, 6 May 2020 11:30:30 -0700 (PDT) X-Google-Smtp-Source: APiQypK6C/NBdfsV58bGTgGMMUCygjh1OsGBmVY0Itxw+L8jQUWb9jL3VV9hUux5j7+u5ZVIipxS X-Received: by 2002:a37:49d5:: with SMTP id w204mr9984104qka.335.1588789830634; Wed, 06 May 2020 11:30:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1588789830; cv=none; d=google.com; s=arc-20160816; b=J2IvQu4LGRVuo1O7aXSEeNbEWaK3mXoayb4JoJ7XG8XDPZIjZPhCRe0zMxnCFEOSaL HP/TDXMxxVE28jccBYR53wqa984RP7EI4x9PsCxSZixNdJhBp0ntSwwF9yS0xPmxfepj VTvqylB1o9QlEuh8yCrwykF6fIq9hAg2RRfOqbxd1KNodXW5wwPQfBIjMZbf/iS+EWQV uEtk09QvxK51cwKqVOtYdN3nOY5v59fE6l/KXgUHh+dyrTUsvIfNPhPJ0sui1ypPGQNM BHhe+sVLnBZGT2B4njFskVj+wxNk/2Av9Wtinw96aydTJizdkci32k8+qmZwfzzQRN5Q MkpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZhM8WFsngVW12JNtP5Ld2uYK1gRgB1Q32WgIlT7XOUI=; b=qskHQ0QNUxeZg9v1hGML2I+6xvHHJwyUHX77PMwOL7+7rICo7LRc4boriBElB+zmCn tDgzUEbubX9rzBnDub7gFPsvKD5ona/sSeN+oZ5VTlrOhEG+lcVWvX2hiuc8ZI+bBMeM 1WAoBzt24E6nWsLGoi4sn5dBzYO+aq4366yYbjGhVmmCPvQiX2aa/WfmgFOY++6Vg9RB 9Wwl3UGGe2/Dp03Z5+aAjo67tPrNyMJ0lc0u/mXaJ21nHjTL36WIazs6HolLaCV5qsuu ALca7tDivsC8D5Y9BU704ofBJms/R/d1t90lJVorFCPWG0obA+iTr3jM7wMtBsd5KuN5 ESLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=InUzyKQm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:470:142::17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id w11sm2572589pfq.100.2020.05.06.11.30.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2020 11:30:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 06/10] tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i Date: Wed, 6 May 2020 11:29:58 -0700 Message-Id: <20200506183002.3192-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200506183002.3192-1-richard.henderson@linaro.org> References: <20200506183002.3192-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= , LIU Zhiwei , David Hildenbrand Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These interfaces are now unused. Reviewed-by: LIU Zhiwei Reviewed-by: David Hildenbrand Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 5 ----- tcg/tcg-op-gvec.c | 28 ---------------------------- 2 files changed, 33 deletions(-) -- 2.20.1 diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index eb0d47a42b..fa8a0c8d03 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -320,11 +320,6 @@ void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s, void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s, uint32_t m, TCGv_i64); -void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t s, uint32_t m, uint8_t x); -void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t s, uint32_t m, uint16_t x); -void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t s, uint32_t m, uint32_t x); -void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t s, uint32_t m, uint64_t x); - void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index de16c027b3..5a6cc19812 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -1541,34 +1541,6 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs, } } -void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t oprsz, - uint32_t maxsz, uint64_t x) -{ - check_size_align(oprsz, maxsz, dofs); - do_dup(MO_64, dofs, oprsz, maxsz, NULL, NULL, x); -} - -void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t oprsz, - uint32_t maxsz, uint32_t x) -{ - check_size_align(oprsz, maxsz, dofs); - do_dup(MO_32, dofs, oprsz, maxsz, NULL, NULL, x); -} - -void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t oprsz, - uint32_t maxsz, uint16_t x) -{ - check_size_align(oprsz, maxsz, dofs); - do_dup(MO_16, dofs, oprsz, maxsz, NULL, NULL, x); -} - -void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz, - uint32_t maxsz, uint8_t x) -{ - check_size_align(oprsz, maxsz, dofs); - do_dup(MO_8, dofs, oprsz, maxsz, NULL, NULL, x); -} - void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t oprsz, uint32_t maxsz, uint64_t x) { From patchwork Wed May 6 18:29:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186273 Delivered-To: patch@linaro.org Received: by 2002:a92:8d81:0:0:0:0:0 with SMTP id w1csp2411584ill; Wed, 6 May 2020 11:36:01 -0700 (PDT) X-Google-Smtp-Source: APiQypJhR1ybTPimgJajTaTFeibH+uqh/TdWiASKjquSEET2U1ymDVu/uJzILXA0cmV1gSA/ltcp X-Received: by 2002:a37:e117:: with SMTP id c23mr10506556qkm.207.1588790161578; Wed, 06 May 2020 11:36:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1588790161; cv=none; d=google.com; s=arc-20160816; b=Xg+rCCU7MNCe0Nm1VNyA2CgCwwONuqL4qfr10kAeKei1m1V/yMwO3Oy631/tegAiak l1nYvnQSSb3WxbXTsxJr658RySn35Lpid3Ktczxizui+ONao4IV8Bu7Y23UZlj1gXQDq /E7TTD1QpOg1Tf+tCLXl89G0ANrP5D3qJylMsm5zlaz9qNP/DC3nswzHQkyfrmB1tsE/ KRlIzCyuoyTqv3XNhPccLQVIecse6Bvda7k8R0MsWXBNnjagJqMgOlfpstT70T+4w3eM nmCq79G8haYzEudsq5i4aIWDoQ3iYOD+RoDyFkU8iW+k0lu0Lk8qXvsmz6+j4opnOpFC yopQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NV6lL8g5TLJgWVXBQ3cW0c77O/M78yXELJw+3HhuoJg=; b=gf/U2RARS8Kv0qg0DpTduNRK+TOWe4ncLPuMjOgOEhKNPfgcrBM2GAiiuiY+Y7pt7w zXU+leS9ox2ZFnZDOVsB0b+vx1vgxiMKltvEe7a9H7ecFLLmFdF2lYQd8tGlh2AI5Xj/ RkexG8CftWT8Lmq+njSObNZcjDomoUc4A5V7ZZhvQJoPGPyaiOqqvJN4OelPtZVt7x3d D9c6/OeVQPqo5kNWi0gRYbY/acpgOffI5BkbaoYYTPM6dknL5KuEjGu7CANeA6PMI1Rr RWoARxm2qKb6UH6kkX6BjYwmlvgJFcc7D9fxmYEiKMOSQ+PTuqzwLA/w1TfQUJIFAptV pZCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QcVUoOMy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:470:142::17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id w11sm2572589pfq.100.2020.05.06.11.30.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2020 11:30:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 07/10] tcg: Add tcg_gen_gvec_dup_tl Date: Wed, 6 May 2020 11:29:59 -0700 Message-Id: <20200506183002.3192-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200506183002.3192-1-richard.henderson@linaro.org> References: <20200506183002.3192-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= , LIU Zhiwei , David Hildenbrand Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For use when a target needs to pass a configure-specific target_ulong value to duplicate. Reviewed-by: LIU Zhiwei Reviewed-by: David Hildenbrand Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.20.1 diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index fa8a0c8d03..d89f91f40e 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -320,6 +320,12 @@ void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s, void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s, uint32_t m, TCGv_i64); +#if TARGET_LONG_BITS == 64 +# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i64 +#else +# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i32 +#endif + void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, From patchwork Wed May 6 18:30:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186272 Delivered-To: patch@linaro.org Received: by 2002:a92:8d81:0:0:0:0:0 with SMTP id w1csp2411448ill; Wed, 6 May 2020 11:35:52 -0700 (PDT) X-Google-Smtp-Source: APiQypIUfXo64N0zHnpgj6dR/bNnkyX7sNxdsdy7/I/CxmgKvVVxhKyUdMzsh+MnaCsJ6dCrlrMh X-Received: by 2002:a05:6214:414:: with SMTP id z20mr9383343qvx.242.1588790152144; Wed, 06 May 2020 11:35:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1588790152; cv=none; d=google.com; s=arc-20160816; b=QXYAUWAbxYZJunWulpLSMGJtt23Ld9g7G9eXbFjMz39Jk33oV5L5o4wgm2jr/iHDou gh0LvA3VccX66SLn/qfDo29mcxXdO3XpTj9uHIVmdA/AGx/gxd5HFwsxBFtQYJfguRD8 yVJqHH0A8ck7mNYh2h8qTnCBvszti0WpIuw4vSAa+zNJ56bOLKXmvkEM14tiFy4jMXCq 5tPlKKj6DrmpV9Sxc7QjeZgAjwgMHIBddMIh7NIUpB7udmDnX3P++VQ6B1sebLStqlVI mfE4a9G7VitZ8YP2A2Ocx81LIAgnA+0/I+Xp1WLjn+eJF7RYhQ6QvpRKZj6U7PsPK9Be JNNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5T7KJt0fc54mlBnT3n+g8HKCVqPFI5bG2HmAN7UzeMM=; b=Vm0540aXqfKFwacpO0xf2Hm7StpmIPerJV2eapOUAC1L5AluLrIgOIyadqZSXM0N56 JhYnfq3cdRpPLbUbYvOb1jMHhT2UZHtW4sEB+qhpzxJ+PDSMa7iaFUYw6/mWVC7EOd2m 799eneWYj1YT7DliYTUrSr+R9HbNIWmFBBptSfwzQwS1+Jz5fV8dvTgfTqhLrPlsKLxv ERAmFFCm8+m51sqZnN2tXKvii/qme0RJSlP6I1zCTWrlWQ0bopOGsF7+H6MBpBegsx1x 7byEO2suv4UO44WRZ78MWt1v06jGMgGcVfTNfUjX5ZmjNjFLl5THPIs4gcJG36Zzbvgp MveQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ni0ndTOT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:470:142::17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id w11sm2572589pfq.100.2020.05.06.11.30.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2020 11:30:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 08/10] tcg: Improve vector tail clearing Date: Wed, 6 May 2020 11:30:00 -0700 Message-Id: <20200506183002.3192-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200506183002.3192-1-richard.henderson@linaro.org> References: <20200506183002.3192-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Better handling of non-power-of-2 tails as seen with Arm 8-byte vector operations. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 82 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 63 insertions(+), 19 deletions(-) -- 2.20.1 diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 5a6cc19812..43cac1a0bf 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -326,11 +326,34 @@ void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, in units of LNSZ. This limits the expansion of inline code. */ static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz) { - if (oprsz % lnsz == 0) { - uint32_t lnct = oprsz / lnsz; - return lnct >= 1 && lnct <= MAX_UNROLL; + uint32_t q, r; + + if (oprsz < lnsz) { + return false; } - return false; + + q = oprsz / lnsz; + r = oprsz % lnsz; + tcg_debug_assert((r & 7) == 0); + + if (lnsz < 16) { + /* For sizes below 16, accept no remainder. */ + if (r != 0) { + return false; + } + } else { + /* + * Recall that ARM SVE allows vector sizes that are not a + * power of 2, but always a multiple of 16. The intent is + * that e.g. size == 80 would be expanded with 2x32 + 1x16. + * In addition, expand_clr needs to handle a multiple of 8. + * Thus we can handle the tail with one more operation per + * diminishing power of 2. + */ + q += ctpop32(r); + } + + return q <= MAX_UNROLL; } static void expand_clr(uint32_t dofs, uint32_t maxsz); @@ -402,22 +425,31 @@ static void gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in) static TCGType choose_vector_type(const TCGOpcode *list, unsigned vece, uint32_t size, bool prefer_i64) { - if (TCG_TARGET_HAS_v256 && check_size_impl(size, 32)) { - /* - * Recall that ARM SVE allows vector sizes that are not a - * power of 2, but always a multiple of 16. The intent is - * that e.g. size == 80 would be expanded with 2x32 + 1x16. - * It is hard to imagine a case in which v256 is supported - * but v128 is not, but check anyway. - */ - if (tcg_can_emit_vecop_list(list, TCG_TYPE_V256, vece) - && (size % 32 == 0 - || tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece))) { - return TCG_TYPE_V256; - } + /* + * Recall that ARM SVE allows vector sizes that are not a + * power of 2, but always a multiple of 16. The intent is + * that e.g. size == 80 would be expanded with 2x32 + 1x16. + * It is hard to imagine a case in which v256 is supported + * but v128 is not, but check anyway. + * In addition, expand_clr needs to handle a multiple of 8. + */ + if (TCG_TARGET_HAS_v256 && + check_size_impl(size, 32) && + tcg_can_emit_vecop_list(list, TCG_TYPE_V256, vece) && + (!(size & 16) || + (TCG_TARGET_HAS_v128 && + tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece))) && + (!(size & 8) || + (TCG_TARGET_HAS_v64 && + tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)))) { + return TCG_TYPE_V256; } - if (TCG_TARGET_HAS_v128 && check_size_impl(size, 16) - && tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece)) { + if (TCG_TARGET_HAS_v128 && + check_size_impl(size, 16) && + tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece) && + (!(size & 8) || + (TCG_TARGET_HAS_v64 && + tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)))) { return TCG_TYPE_V128; } if (TCG_TARGET_HAS_v64 && !prefer_i64 && check_size_impl(size, 8) @@ -432,6 +464,18 @@ static void do_dup_store(TCGType type, uint32_t dofs, uint32_t oprsz, { uint32_t i = 0; + tcg_debug_assert(oprsz >= 8); + + /* + * This may be expand_clr for the tail of an operation, e.g. + * oprsz == 8 && maxsz == 64. The first 8 bytes of this store + * are misaligned wrt the maximum vector size, so do that first. + */ + if (dofs & 8) { + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); + i += 8; + } + switch (type) { case TCG_TYPE_V256: /* From patchwork Wed May 6 18:30:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186270 Delivered-To: patch@linaro.org Received: by 2002:a92:8d81:0:0:0:0:0 with SMTP id w1csp2409347ill; Wed, 6 May 2020 11:33:14 -0700 (PDT) X-Google-Smtp-Source: APiQypK05cxzLMz2L/qKJRcemstmAN0Q6KaUWtJnCp0KfQ1egRCV+XoblczIP1+DIg2caYW93VP+ X-Received: by 2002:a37:7ac2:: with SMTP id v185mr9890735qkc.386.1588789993979; Wed, 06 May 2020 11:33:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1588789993; cv=none; d=google.com; s=arc-20160816; b=YxPch5TJCfEMmbuDow44ufWio6qfK7q29j+ZgYH1SOnSck1NaUpT8c4JRGjkLRFRRB svd93LTwuSPGjzU/KxfMDzcLw63xvfguIO0mLsSqxHxMBx7lK5x3snmqBQGz1XxiaG4Z c2ZroNSs7zEzINB8DMm61ek5Y5pZUIeeeIX1a/mgA2tZsO1FJcwEQcBMfqwWvDT79M+L jbRSofb9XcJWZhKdGB23r+pqIKCrWsPizHb82w0RDxO+atRShtWgDY+GVh/84CJ2OQth bPSz2h8/o6sP3EHAJ+TwHBBFp8/INMbhp2bMWf+5EWeu37nl4TkV0Zw+GZx4+7K9IhId m4sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hktRCt+zPcMLEnvaBC38jKwfPbiQdX/9XB+JNDn/fPU=; b=uROYryywg3km6GwU9HoOPOedHr2iPNglo54aKZEIUPZwZJ1VBDAJUIFhqdlZe3Hzw3 l97g19Bje+LjMWpMcO2BZONV6bg9w5mFUcFFHaEpO14/yNgGD109Jl9w9ad5Es63BPvJ XUIqy6F+KXKvxdZlBVvFd8su0BgbrLMei2uPup7PmftzBzr1+PWbwPihRo4b+OTAj1jF cpQ60y6ZguDm2wjPYnB1VGQM9fEmrG9hC4dsEhDne/s3izmPbTlVzWUNZLPPWvQShkhv IiNDsfh+mqXOpUMncrfK1FsfoI73sfWJWhS4e+U1wOBYaFoOS7QTKx9NPP+gzjDbiorK xbhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uJmz11sO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:470:142::17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id w11sm2572589pfq.100.2020.05.06.11.30.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2020 11:30:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 09/10] tcg: Add load_dest parameter to GVecGen2 Date: Wed, 6 May 2020 11:30:01 -0700 Message-Id: <20200506183002.3192-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200506183002.3192-1-richard.henderson@linaro.org> References: <20200506183002.3192-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have this same parameter for GVecGen2i, GVecGen3, and GVecGen3i. This will make some SVE2 insns easier to parameterize. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 2 ++ tcg/tcg-op-gvec.c | 45 ++++++++++++++++++++++++++++----------- 2 files changed, 34 insertions(+), 13 deletions(-) -- 2.20.1 diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index d89f91f40e..cea6497341 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -109,6 +109,8 @@ typedef struct { uint8_t vece; /* Prefer i64 to v64. */ bool prefer_i64; + /* Load dest as a 2nd source operand. */ + bool load_dest; } GVecGen2; typedef struct { diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 43cac1a0bf..049a55e700 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -663,17 +663,22 @@ static void expand_clr(uint32_t dofs, uint32_t maxsz) /* Expand OPSZ bytes worth of two-operand operations using i32 elements. */ static void expand_2_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz, - void (*fni)(TCGv_i32, TCGv_i32)) + bool load_dest, void (*fni)(TCGv_i32, TCGv_i32)) { TCGv_i32 t0 = tcg_temp_new_i32(); + TCGv_i32 t1 = tcg_temp_new_i32(); uint32_t i; for (i = 0; i < oprsz; i += 4) { tcg_gen_ld_i32(t0, cpu_env, aofs + i); - fni(t0, t0); - tcg_gen_st_i32(t0, cpu_env, dofs + i); + if (load_dest) { + tcg_gen_ld_i32(t1, cpu_env, dofs + i); + } + fni(t1, t0); + tcg_gen_st_i32(t1, cpu_env, dofs + i); } tcg_temp_free_i32(t0); + tcg_temp_free_i32(t1); } static void expand_2i_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz, @@ -793,17 +798,22 @@ static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, /* Expand OPSZ bytes worth of two-operand operations using i64 elements. */ static void expand_2_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz, - void (*fni)(TCGv_i64, TCGv_i64)) + bool load_dest, void (*fni)(TCGv_i64, TCGv_i64)) { TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); uint32_t i; for (i = 0; i < oprsz; i += 8) { tcg_gen_ld_i64(t0, cpu_env, aofs + i); - fni(t0, t0); - tcg_gen_st_i64(t0, cpu_env, dofs + i); + if (load_dest) { + tcg_gen_ld_i64(t1, cpu_env, dofs + i); + } + fni(t1, t0); + tcg_gen_st_i64(t1, cpu_env, dofs + i); } tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } static void expand_2i_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz, @@ -924,17 +934,23 @@ static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, /* Expand OPSZ bytes worth of two-operand operations using host vectors. */ static void expand_2_vec(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t tysz, TCGType type, + bool load_dest, void (*fni)(unsigned, TCGv_vec, TCGv_vec)) { TCGv_vec t0 = tcg_temp_new_vec(type); + TCGv_vec t1 = tcg_temp_new_vec(type); uint32_t i; for (i = 0; i < oprsz; i += tysz) { tcg_gen_ld_vec(t0, cpu_env, aofs + i); - fni(vece, t0, t0); - tcg_gen_st_vec(t0, cpu_env, dofs + i); + if (load_dest) { + tcg_gen_ld_vec(t1, cpu_env, dofs + i); + } + fni(vece, t1, t0); + tcg_gen_st_vec(t1, cpu_env, dofs + i); } tcg_temp_free_vec(t0); + tcg_temp_free_vec(t1); } /* Expand OPSZ bytes worth of two-vector operands and an immediate operand @@ -1088,7 +1104,8 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, * that e.g. size == 80 would be expanded with 2x32 + 1x16. */ some = QEMU_ALIGN_DOWN(oprsz, 32); - expand_2_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, g->fniv); + expand_2_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, + g->load_dest, g->fniv); if (some == oprsz) { break; } @@ -1098,17 +1115,19 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, maxsz -= some; /* fallthru */ case TCG_TYPE_V128: - expand_2_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, g->fniv); + expand_2_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, + g->load_dest, g->fniv); break; case TCG_TYPE_V64: - expand_2_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, g->fniv); + expand_2_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, + g->load_dest, g->fniv); break; case 0: if (g->fni8 && check_size_impl(oprsz, 8)) { - expand_2_i64(dofs, aofs, oprsz, g->fni8); + expand_2_i64(dofs, aofs, oprsz, g->load_dest, g->fni8); } else if (g->fni4 && check_size_impl(oprsz, 4)) { - expand_2_i32(dofs, aofs, oprsz, g->fni4); + expand_2_i32(dofs, aofs, oprsz, g->load_dest, g->fni4); } else { assert(g->fno != NULL); tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, g->data, g->fno); From patchwork Wed May 6 18:30:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186274 Delivered-To: patch@linaro.org Received: by 2002:a92:8d81:0:0:0:0:0 with SMTP id w1csp2411643ill; Wed, 6 May 2020 11:36:06 -0700 (PDT) X-Google-Smtp-Source: APiQypKXDQa5uGejjJd0sFpedII+3HytzL3uPTFeidiB8vNXjl1OufwSdyZMl++Jezw67x6IuPyq X-Received: by 2002:aed:2f25:: with SMTP id l34mr9600578qtd.339.1588790166068; Wed, 06 May 2020 11:36:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1588790166; cv=none; d=google.com; s=arc-20160816; b=rZEbkCc3KKEVBT/bw0AJGLN6hTTyQUoh9a1cIre8/GP9EovSz/ANmxT+XqGhHuWdf3 wpREzNFDy6fB+0hUlUG7rtDG1G6ryi2PzaMhwVlJEH4ZE3GpXPJTaDCehFpNZS1ERmne 4zDc4ttA5imSmvkMJH5mN3yEfCL6PM0Bg5omHmHV7Yk764FW3uRFO4ZMCAdLiBm0Mgeq XGURZYg08MFsYbBH0ZKi9vrPKFRed9HLeZFcHFOl0KhLYU+QivOVizdPDNZHC/D3uU+d vO8lG7f2LYxWK0f0AQhOiW+UOauj4aZHw5bwcdAUWL7U44hqR0lkCIqDqWAFSVF3S9fe 4ndg== ARC-Message-Signature: i=1; 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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id w11sm2572589pfq.100.2020.05.06.11.30.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2020 11:30:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 10/10] tcg: Fix integral argument type to tcg_gen_rot[rl]i_i{32, 64} Date: Wed, 6 May 2020 11:30:02 -0700 Message-Id: <20200506183002.3192-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200506183002.3192-1-richard.henderson@linaro.org> References: <20200506183002.3192-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For the benefit of compatibility of function pointer types, we have standardized on int32_t and int64_t as the integral argument to tcg expanders. We converted most of them in 474b2e8f0f7, but missed the rotates. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 8 ++++---- tcg/tcg-op.c | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) -- 2.20.1 diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 230db6e022..e3399d6a5e 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -297,9 +297,9 @@ void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2); void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); +void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); +void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, unsigned int ofs, unsigned int len); void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, @@ -493,9 +493,9 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2); void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); +void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); +void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, unsigned int ofs, unsigned int len); void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index e2e25ebf7d..e60b74fb82 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -540,9 +540,9 @@ void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2) +void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { - tcg_debug_assert(arg2 < 32); + tcg_debug_assert(arg2 >= 0 && arg2 < 32); /* some cases can be optimized here */ if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); @@ -580,9 +580,9 @@ void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } -void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2) +void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { - tcg_debug_assert(arg2 < 32); + tcg_debug_assert(arg2 >= 0 && arg2 < 32); /* some cases can be optimized here */ if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); @@ -1962,9 +1962,9 @@ void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } } -void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2) +void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - tcg_debug_assert(arg2 < 64); + tcg_debug_assert(arg2 >= 0 && arg2 < 64); /* some cases can be optimized here */ if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); @@ -2001,9 +2001,9 @@ void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } } -void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2) +void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - tcg_debug_assert(arg2 < 64); + tcg_debug_assert(arg2 >= 0 && arg2 < 64); /* some cases can be optimized here */ if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1);