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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4405b4f3df8sm61241055e9.24.2025.04.17.09.54.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 17 Apr 2025 09:54:36 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Yanan Wang , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Zhao Liu , Marcel Apfelbaum , =?utf-8?q?Daniel_P=2E_Berran?= =?utf-8?q?g=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Richard Henderson , Pierrick Bouvier Subject: [PATCH 1/7] qemu: Introduce target_cpu_type() Date: Thu, 17 Apr 2025 18:54:24 +0200 Message-ID: <20250417165430.58213-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250417165430.58213-1-philmd@linaro.org> References: <20250417165430.58213-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduce the target_cpu_type() helper to access the CPU_RESOLVING_TYPE target-specific definition from target-agnostic code. Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 2 ++ meson.build | 2 ++ include/qemu/target_info.h | 19 +++++++++++++++++++ target_info-defs.c | 16 ++++++++++++++++ 4 files changed, 39 insertions(+) create mode 100644 include/qemu/target_info.h create mode 100644 target_info-defs.c diff --git a/MAINTAINERS b/MAINTAINERS index c7083ab1d93..07ca088f7e8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -495,6 +495,7 @@ F: include/exec/cpu*.h F: include/exec/exec-all.h F: include/exec/target_long.h F: include/qemu/accel.h +F: include/qemu/target_info.h F: include/system/accel-*.h F: include/system/cpus.h F: include/accel/accel-cpu-target.h @@ -503,6 +504,7 @@ F: accel/Makefile.objs F: accel/stubs/Makefile.objs F: cpu-common.c F: cpu-target.c +F: target_info-defs.c F: system/cpus.c Apple Silicon HVF CPUs diff --git a/meson.build b/meson.build index bcb9d39a387..ad324d46428 100644 --- a/meson.build +++ b/meson.build @@ -3807,6 +3807,8 @@ endif common_ss.add(pagevary) specific_ss.add(files('page-target.c', 'page-vary-target.c')) +specific_ss.add(files('target_info-defs.c')) + subdir('backends') subdir('disas') subdir('migration') diff --git a/include/qemu/target_info.h b/include/qemu/target_info.h new file mode 100644 index 00000000000..a53e632e735 --- /dev/null +++ b/include/qemu/target_info.h @@ -0,0 +1,19 @@ +/* + * QEMU binary/target helpers + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef QEMU_TARGET_INFO_H +#define QEMU_TARGET_INFO_H + +/** + * target_cpu_type: + * + * Returns: target CPU base QOM type name (i.e. TYPE_X86_CPU). + */ +const char *target_cpu_type(void); + +#endif diff --git a/target_info-defs.c b/target_info-defs.c new file mode 100644 index 00000000000..3ee89469855 --- /dev/null +++ b/target_info-defs.c @@ -0,0 +1,16 @@ +/* + * QEMU binary/target helpers (target specific) + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target_info.h" +#include "cpu.h" + +const char *target_cpu_type(void) +{ + return CPU_RESOLVING_TYPE; +} From patchwork Thu Apr 17 16:54:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 881866 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp421151wrs; Thu, 17 Apr 2025 09:55:24 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWnVlkt3Fml0l6/+ahFj+AcZFmCWmmn36jmyotlzZi4ejOLDFb3FLpMQ53sEK6pSvfcgXtpHA==@linaro.org X-Google-Smtp-Source: AGHT+IGuUcGZm07RwmqNiOR48PT8Hr+BT20Fcyhwp8qvMYhLasQL82sGqY3je5i5g79aPwaIpHSD X-Received: by 2002:a05:6214:508b:b0:6e2:485d:fddd with SMTP id 6a1803df08f44-6f2c2975ebbmr9337666d6.1.1744908923751; Thu, 17 Apr 2025 09:55:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1744908923; cv=none; d=google.com; s=arc-20240605; b=RHRMwAW95nn3o8UGwZksDbbFomCeTDuG4VRzqsHkqNW6Edw0MeKreYFGYwN9bK92ea PwCq8LyZMuWHjBNz8Swat9azMCcQGd68fZ82XH8ZqWrqfKiCWWwHEYRkrqUJ4LIqA1wn qp7nlWMxDmUsNo6YW4W2qGn7kGAUHZVud8lfULWOloFs3RrON3B9Co31y5eVW9MvmAEB wMSckewUvarauak33voG3/7b1lVb2flLsTntDP4/OfuBjpB+2Kw/tpNm8AcSGt3LRncf Z7TSqI1ZDEAZ7BMvv2vYV1NGKMqGiQkvouFQaNGgSHnFAaOfNYPzJn9641aAuHbGp9+z qGEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=CCtxW/YXYxc5X52XHJaBnnxo+Dcm7u6ycMuvffFjq6Q=; fh=648YH0ympC0GO1R9X4VUyDuabGl/p48Phw6ajjzDgmU=; b=EMLJMTvJKlW4gYJxwwuBbQFChq70pPpVAptUyz5+eJ1NTf9o373Jsv76ZGgzwrwORd 6I+MFTkZB6rD+s7e/whrHz1su96ex0QIO1CSz8y/fJLWQvWaqpNtxYarHhPq2yRSkDh/ 9JjRgDA+1E+LLNR29piwnd1jN/2DvttknPDpSlnq0rLNIEy/4ykoak4YNKI6S3LZlFZO CHnOqz34MIc1SgzlNeuymYT0xya2lvhM3NvDKwTaLT2aOE9JPI7JS7VkCga3ZfezKmnh 2acSLv8YAIoaGencRxCiG0Xv2SMCgXtuu9HyYl/MyJNLO1z0BtCiSM/3qo6wz9MliBEQ rXrw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="QmvNRD/N"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931e7sm119904f8f.67.2025.04.17.09.54.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 17 Apr 2025 09:54:41 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Yanan Wang , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Zhao Liu , Marcel Apfelbaum , =?utf-8?q?Daniel_P=2E_Berran?= =?utf-8?q?g=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Richard Henderson , Pierrick Bouvier Subject: [PATCH 2/7] cpus: Replace CPU_RESOLVING_TYPE -> target_cpu_type() Date: Thu, 17 Apr 2025 18:54:25 +0200 Message-ID: <20250417165430.58213-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250417165430.58213-1-philmd@linaro.org> References: <20250417165430.58213-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the target-specific CPU_RESOLVING_TYPE definition by a call to the target-agnostic target_cpu_type() runtime helper. Since the big "cpu.h" is not required anymore in tcg-all.c, remove it, using the tinier "cpu-param.h" header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- accel/accel-target.c | 6 ++++-- accel/tcg/tcg-all.c | 5 +++-- cpu-target.c | 7 ++++--- 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/accel/accel-target.c b/accel/accel-target.c index 33a539b4cbb..9e9e70be876 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "qemu/accel.h" +#include "qemu/target_info.h" #include "cpu.h" #include "accel/accel-cpu-target.h" @@ -88,17 +89,18 @@ static void accel_init_cpu_interfaces(AccelClass *ac) const char *ac_name; /* AccelClass name */ char *acc_name; /* AccelCPUClass name */ ObjectClass *acc; /* AccelCPUClass */ + const char *cpu_resolving_type = target_cpu_type(); ac_name = object_class_get_name(OBJECT_CLASS(ac)); g_assert(ac_name != NULL); - acc_name = g_strdup_printf("%s-%s", ac_name, CPU_RESOLVING_TYPE); + acc_name = g_strdup_printf("%s-%s", ac_name, cpu_resolving_type); acc = object_class_by_name(acc_name); g_free(acc_name); if (acc) { object_class_foreach(accel_init_cpu_int_aux, - CPU_RESOLVING_TYPE, false, acc); + cpu_resolving_type, false, acc); } } diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index b0d4e3e1362..25df7db5026 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -35,6 +35,7 @@ #include "qapi/qapi-types-common.h" #include "qapi/qapi-builtin-visit.h" #include "qemu/units.h" +#include "qemu/target_info.h" #if defined(CONFIG_USER_ONLY) #include "hw/qdev-core.h" #else @@ -43,7 +44,7 @@ #endif #include "accel/tcg/cpu-ops.h" #include "internal-common.h" -#include "cpu.h" +#include "cpu-param.h" struct TCGState { @@ -89,7 +90,7 @@ static int tcg_init_machine(MachineState *ms) unsigned max_threads = 1; #ifndef CONFIG_USER_ONLY - CPUClass *cc = CPU_CLASS(object_class_by_name(CPU_RESOLVING_TYPE)); + CPUClass *cc = CPU_CLASS(object_class_by_name(target_cpu_type())); bool mttcg_supported = cc->tcg_ops->mttcg_supported; switch (s->mttcg_enabled) { diff --git a/cpu-target.c b/cpu-target.c index c99d208a7c4..1779bb5337d 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -22,6 +22,7 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" +#include "qemu/target_info.h" #include "system/accel-ops.h" #include "system/cpus.h" #include "exec/cpu-common.h" @@ -37,7 +38,7 @@ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState)); char *cpu_model_from_type(const char *typename) { - const char *suffix = "-" CPU_RESOLVING_TYPE; + g_autofree char *suffix = g_strdup_printf("-%s", target_cpu_type()); if (!object_class_by_name(typename)) { return NULL; @@ -63,7 +64,7 @@ const char *parse_cpu_option(const char *cpu_option) exit(1); } - oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]); + oc = cpu_class_by_name(target_cpu_type(), model_pieces[0]); if (oc == NULL) { error_report("unable to find CPU model '%s'", model_pieces[0]); g_strfreev(model_pieces); @@ -92,7 +93,7 @@ static void cpu_list_entry(gpointer data, gpointer user_data) void list_cpus(void) { - CPUClass *cc = CPU_CLASS(object_class_by_name(CPU_RESOLVING_TYPE)); + CPUClass *cc = CPU_CLASS(object_class_by_name(target_cpu_type())); if (cc->list_cpus) { cc->list_cpus(); From patchwork Thu Apr 17 16:54:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 881870 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp421444wrs; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406994a362sm4801995e9.16.2025.04.17.09.54.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 17 Apr 2025 09:54:46 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Yanan Wang , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Zhao Liu , Marcel Apfelbaum , =?utf-8?q?Daniel_P=2E_Berran?= =?utf-8?q?g=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Richard Henderson , Pierrick Bouvier Subject: [PATCH 3/7] cpus: Move target-agnostic methods out of cpu-target.c Date: Thu, 17 Apr 2025 18:54:26 +0200 Message-ID: <20250417165430.58213-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250417165430.58213-1-philmd@linaro.org> References: <20250417165430.58213-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Various methods of cpu-target.c don't use any target-specific knowledge at all and can be built once in the target-agnostic cpu-common.c file. Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé --- cpu-target.c | 77 +------------------------------------------- hw/core/cpu-common.c | 74 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+), 76 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index 1779bb5337d..e018acbf71a 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -19,94 +19,19 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "qapi/error.h" -#include "qemu/error-report.h" -#include "qemu/qemu-print.h" -#include "qemu/target_info.h" #include "system/accel-ops.h" #include "system/cpus.h" #include "exec/cpu-common.h" #include "exec/tswap.h" #include "exec/replay-core.h" #include "exec/log.h" -#include "accel/accel-cpu-target.h" +#include "hw/core/cpu.h" #include "trace/trace-root.h" /* Validate correct placement of CPUArchState. */ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0); QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState)); -char *cpu_model_from_type(const char *typename) -{ - g_autofree char *suffix = g_strdup_printf("-%s", target_cpu_type()); - - if (!object_class_by_name(typename)) { - return NULL; - } - - if (g_str_has_suffix(typename, suffix)) { - return g_strndup(typename, strlen(typename) - strlen(suffix)); - } - - return g_strdup(typename); -} - -const char *parse_cpu_option(const char *cpu_option) -{ - ObjectClass *oc; - CPUClass *cc; - gchar **model_pieces; - const char *cpu_type; - - model_pieces = g_strsplit(cpu_option, ",", 2); - if (!model_pieces[0]) { - error_report("-cpu option cannot be empty"); - exit(1); - } - - oc = cpu_class_by_name(target_cpu_type(), model_pieces[0]); - if (oc == NULL) { - error_report("unable to find CPU model '%s'", model_pieces[0]); - g_strfreev(model_pieces); - exit(EXIT_FAILURE); - } - - cpu_type = object_class_get_name(oc); - cc = CPU_CLASS(oc); - cc->parse_features(cpu_type, model_pieces[1], &error_fatal); - g_strfreev(model_pieces); - return cpu_type; -} - -static void cpu_list_entry(gpointer data, gpointer user_data) -{ - CPUClass *cc = CPU_CLASS(OBJECT_CLASS(data)); - const char *typename = object_class_get_name(OBJECT_CLASS(data)); - g_autofree char *model = cpu_model_from_type(typename); - - if (cc->deprecation_note) { - qemu_printf(" %s (deprecated)\n", model); - } else { - qemu_printf(" %s\n", model); - } -} - -void list_cpus(void) -{ - CPUClass *cc = CPU_CLASS(object_class_by_name(target_cpu_type())); - - if (cc->list_cpus) { - cc->list_cpus(); - } else { - GSList *list; - - list = object_class_get_list_sorted(TYPE_CPU, false); - qemu_printf("Available CPUs:\n"); - g_slist_foreach(list, cpu_list_entry, NULL); - g_slist_free(list); - } -} - /* enable or disable single step mode. EXCP_DEBUG is returned by the CPU loop after each instruction */ void cpu_single_step(CPUState *cpu, int enabled) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 9064dd24f82..6d0788331c7 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -25,6 +25,9 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "qemu/lockcnt.h" +#include "qemu/error-report.h" +#include "qemu/qemu-print.h" +#include "qemu/target_info.h" #include "exec/log.h" #include "exec/gdbstub.h" #include "system/tcg.h" @@ -152,6 +155,21 @@ ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model) return NULL; } +char *cpu_model_from_type(const char *typename) +{ + g_autofree char *suffix = g_strdup_printf("-%s", target_cpu_type()); + + if (!object_class_by_name(typename)) { + return NULL; + } + + if (g_str_has_suffix(typename, suffix)) { + return g_strndup(typename, strlen(typename) - strlen(suffix)); + } + + return g_strdup(typename); +} + static void cpu_common_parse_features(const char *typename, char *features, Error **errp) { @@ -183,6 +201,33 @@ static void cpu_common_parse_features(const char *typename, char *features, } } +const char *parse_cpu_option(const char *cpu_option) +{ + ObjectClass *oc; + CPUClass *cc; + gchar **model_pieces; + const char *cpu_type; + + model_pieces = g_strsplit(cpu_option, ",", 2); + if (!model_pieces[0]) { + error_report("-cpu option cannot be empty"); + exit(1); + } + + oc = cpu_class_by_name(target_cpu_type(), model_pieces[0]); + if (oc == NULL) { + error_report("unable to find CPU model '%s'", model_pieces[0]); + g_strfreev(model_pieces); + exit(EXIT_FAILURE); + } + + cpu_type = object_class_get_name(oc); + cc = CPU_CLASS(oc); + cc->parse_features(cpu_type, model_pieces[1], &error_fatal); + g_strfreev(model_pieces); + return cpu_type; +} + bool cpu_exec_realizefn(CPUState *cpu, Error **errp) { if (!accel_cpu_common_realize(cpu, errp)) { @@ -359,3 +404,32 @@ static void cpu_register_types(void) } type_init(cpu_register_types) + +static void cpu_list_entry(gpointer data, gpointer user_data) +{ + CPUClass *cc = CPU_CLASS(OBJECT_CLASS(data)); + const char *typename = object_class_get_name(OBJECT_CLASS(data)); + g_autofree char *model = cpu_model_from_type(typename); + + if (cc->deprecation_note) { + qemu_printf(" %s (deprecated)\n", model); + } else { + qemu_printf(" %s\n", model); + } +} + +void list_cpus(void) +{ + CPUClass *cc = CPU_CLASS(object_class_by_name(target_cpu_type())); + + if (cc->list_cpus) { + cc->list_cpus(); + } else { + GSList *list; + + list = object_class_get_list_sorted(TYPE_CPU, false); + qemu_printf("Available CPUs:\n"); + g_slist_foreach(list, cpu_list_entry, NULL); + g_slist_free(list); + } +} From patchwork Thu Apr 17 16:54:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 881872 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp421579wrs; Thu, 17 Apr 2025 09:56:21 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXuqxabHreiit1bS7+JqjNlQw595aFVrFbMaCNa1DNEXxsM0RPQokFdL5vi3UgIqQEdDhAD0w==@linaro.org X-Google-Smtp-Source: AGHT+IFj+nxLjn6qCGDxkbYI4WGXr2caVrepEL2oYiLxFgUtVhzq9GXOREmn+BpeA2flpEDO1Nq6 X-Received: by 2002:ac8:584b:0:b0:477:6f6d:607a with SMTP id d75a77b69052e-47ad8097044mr85780091cf.7.1744908980878; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-44069953823sm4736265e9.19.2025.04.17.09.54.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 17 Apr 2025 09:54:51 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Yanan Wang , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Zhao Liu , Marcel Apfelbaum , =?utf-8?q?Daniel_P=2E_Berran?= =?utf-8?q?g=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Richard Henderson , Pierrick Bouvier Subject: [PATCH 4/7] accel: Implement accel_init_ops_interfaces() for both system/user mode Date: Thu, 17 Apr 2025 18:54:27 +0200 Message-ID: <20250417165430.58213-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250417165430.58213-1-philmd@linaro.org> References: <20250417165430.58213-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We want to build more common code, moving objects from meson's specific_ss[] set to common_ss[]. Since the CONFIG_USER_ONLY definitions isn't applied on the common_ss[] set, it is simpler to add an empty accel_init_ops_interfaces() stub on user emulation, removing any CONFIG_USER_ONLY use in accel-target.c. Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 2 +- accel/{accel-system.h => accel-internal.h} | 8 ++++---- accel/accel-system.c | 4 ++-- accel/accel-target.c | 10 ++-------- accel/accel-user.c | 6 ++++++ 5 files changed, 15 insertions(+), 15 deletions(-) rename accel/{accel-system.h => accel-internal.h} (56%) diff --git a/MAINTAINERS b/MAINTAINERS index 07ca088f7e8..9bd7e63c6cd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -499,7 +499,7 @@ F: include/qemu/target_info.h F: include/system/accel-*.h F: include/system/cpus.h F: include/accel/accel-cpu-target.h -F: accel/accel-*.c +F: accel/accel-*.? F: accel/Makefile.objs F: accel/stubs/Makefile.objs F: cpu-common.c diff --git a/accel/accel-system.h b/accel/accel-internal.h similarity index 56% rename from accel/accel-system.h rename to accel/accel-internal.h index 2d37c73c97b..03426aa21ee 100644 --- a/accel/accel-system.h +++ b/accel/accel-internal.h @@ -1,5 +1,5 @@ /* - * QEMU System Emulation accel internal functions + * QEMU accel internal functions * * Copyright 2021 SUSE LLC * @@ -7,9 +7,9 @@ * See the COPYING file in the top-level directory. */ -#ifndef ACCEL_SYSTEM_H -#define ACCEL_SYSTEM_H +#ifndef ACCEL_INTERNAL_H +#define ACCEL_INTERNAL_H -void accel_system_init_ops_interfaces(AccelClass *ac); +void accel_init_ops_interfaces(AccelClass *ac); #endif /* ACCEL_SYSTEM_H */ diff --git a/accel/accel-system.c b/accel/accel-system.c index 5df49fbe831..a0f562ae9ff 100644 --- a/accel/accel-system.c +++ b/accel/accel-system.c @@ -29,7 +29,7 @@ #include "system/accel-ops.h" #include "system/cpus.h" #include "qemu/error-report.h" -#include "accel-system.h" +#include "accel-internal.h" int accel_init_machine(AccelState *accel, MachineState *ms) { @@ -63,7 +63,7 @@ void accel_setup_post(MachineState *ms) } /* initialize the arch-independent accel operation interfaces */ -void accel_system_init_ops_interfaces(AccelClass *ac) +void accel_init_ops_interfaces(AccelClass *ac) { const char *ac_name; char *ops_name; diff --git a/accel/accel-target.c b/accel/accel-target.c index 9e9e70be876..6fa5c3ef04e 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -29,10 +29,7 @@ #include "cpu.h" #include "accel/accel-cpu-target.h" - -#ifndef CONFIG_USER_ONLY -#include "accel-system.h" -#endif /* !CONFIG_USER_ONLY */ +#include "accel-internal.h" static const TypeInfo accel_type = { .name = TYPE_ACCEL, @@ -106,10 +103,7 @@ static void accel_init_cpu_interfaces(AccelClass *ac) void accel_init_interfaces(AccelClass *ac) { -#ifndef CONFIG_USER_ONLY - accel_system_init_ops_interfaces(ac); -#endif /* !CONFIG_USER_ONLY */ - + accel_init_ops_interfaces(ac); accel_init_cpu_interfaces(ac); } diff --git a/accel/accel-user.c b/accel/accel-user.c index 22b6a1a1a89..7d192306a65 100644 --- a/accel/accel-user.c +++ b/accel/accel-user.c @@ -9,6 +9,12 @@ #include "qemu/osdep.h" #include "qemu/accel.h" +#include "accel-internal.h" + +void accel_init_ops_interfaces(AccelClass *ac) +{ + /* nothing */ +} AccelState *current_accel(void) { From patchwork Thu Apr 17 16:54:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 881873 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp421657wrs; Thu, 17 Apr 2025 09:56:31 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUTxIu0tn00sd6+RtNpOvpS1BOpCrS7utAxTC749JljTzXtZhyvOJy5jtqAYsPcBjbGhl8cLg==@linaro.org X-Google-Smtp-Source: AGHT+IGsjXZgnTT+opcRq11E7tJYYDNh3OjzFbHRrDiJWxKvUGtNW+uanlt8wCZZWFTu2ck+MNZc X-Received: by 2002:a05:620a:8006:b0:7c5:d72b:1a00 with SMTP id af79cd13be357-7c918feab42mr1036301685a.15.1744908991319; Thu, 17 Apr 2025 09:56:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1744908991; cv=none; d=google.com; s=arc-20240605; b=a7eXB7/PNR8zWcAMfk7WebPdZkSrsbrJzgY55g7w/3xVU1T/o6dJ/YGVuEw8Rrc9xu lfwmt6PFqhdeVuXEItf+7eU8Kfir68QNMCffjjx4lUVwNT0ErqOocMYN7Tx+SlKEbb1m ZerTGKmAhcyC9BKvKDYFeCCFNseyA4Mm5wT0zyJiQcvyE8hGJqVP/ohV2XNti+Al92FO qFrj9yf2M9tpP7+vka+V8QtAzjZ2D8RhijxtXfrRW5SP5yGKpEMIDJsaJ5ocRoSxkkdD kvVxbZAsGoL+eHk2wyd+RwnRff0Yc1f16f+iFVBYNhYGgka0kFPsI1nZKDfO0OLfqoie DAiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZuMPts4lp59PTenHXoFrRtrrX/gN06WnA+unwyU0N4c=; fh=648YH0ympC0GO1R9X4VUyDuabGl/p48Phw6ajjzDgmU=; b=T0bQDPpX/xe0bBz1sPGBcx1YD2J3tyDq9mY6gAp+OrlPjMIIxe9FVfhbKUcoPAaHei cEYJKl8ixSHnY4awZ4xWkHvDrI6/1yq9eQq9Jagfp6MEBQ1tO56apAlekk2IY9HZVmOZ aqDbGD6SmWPTRVqF3QTYraT5R+94xlmuff/T36bd2qqmposldnVMXg4igRl2EhRHZ3EJ rlB31JT89MVkZnmEmy6ucJB/XInhe/BxKj8j2Yx6pQUQUPSdufigGxHs2DE2B08hpiMT 285MFnNW2Wp4Ale5BdNhW286whRSdUVx1S0gh110hKsq3j5wflm4xqUPZ82Lhdy9zAU3 p/Yw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jJFx0GwI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-440699d106csm4068305e9.34.2025.04.17.09.54.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 17 Apr 2025 09:54:55 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Yanan Wang , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Zhao Liu , Marcel Apfelbaum , =?utf-8?q?Daniel_P=2E_Berran?= =?utf-8?q?g=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Richard Henderson , Pierrick Bouvier Subject: [PATCH 5/7] accel: Include missing 'qemu/accel.h' header in accel-internal.h Date: Thu, 17 Apr 2025 18:54:28 +0200 Message-ID: <20250417165430.58213-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250417165430.58213-1-philmd@linaro.org> References: <20250417165430.58213-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The "qemu/accel.h" header is implicitly pulled in. Include it explicitly in order to avoid when refactoring unrelated headers: accel/accel-internal.h:13:32: error: unknown type name 'AccelClass' 13 | void accel_init_ops_interfaces(AccelClass *ac); | ^ Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé --- accel/accel-internal.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/accel/accel-internal.h b/accel/accel-internal.h index 03426aa21ee..d3a4422cbf7 100644 --- a/accel/accel-internal.h +++ b/accel/accel-internal.h @@ -10,6 +10,8 @@ #ifndef ACCEL_INTERNAL_H #define ACCEL_INTERNAL_H +#include "qemu/accel.h" + void accel_init_ops_interfaces(AccelClass *ac); #endif /* ACCEL_SYSTEM_H */ From patchwork Thu Apr 17 16:54:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 881869 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp421388wrs; Thu, 17 Apr 2025 09:55:58 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXK7RGglJptojGnRg6khOhig7/7b8zminwkj4oSXAZXnB0R+1+929EKeiSCWiQiuRqgnFztmA==@linaro.org X-Google-Smtp-Source: AGHT+IE9ZdC1DQAVJ6c6SC4JrnAEcHY2ljvUnEVyh48mhOvWP2fPYw7ntsklRdPT+yHcTYui/3uj X-Received: by 2002:a05:6214:19c8:b0:6e8:ee68:b4a1 with SMTP id 6a1803df08f44-6f2b2f22a1fmr107988796d6.8.1744908957935; Thu, 17 Apr 2025 09:55:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1744908957; cv=none; d=google.com; s=arc-20240605; b=EngqdSbf6BTOiO3nUxghhx9Ty6OjsP205avSaKqGhdQo7GrkQnB9MrB7Yag6FpIqZQ GDxd16LGnUv/w70iY7wxBKRxBvZuU99ctIJnEgF3kTSTDJJRWn5PGEshzbRGE1Yb62y0 P8g+boTPVIRzTQBsOzSb9ffi5PiGB7LpgLSy96v31W9tapqhBTtClZl9dMcEdta7Cc3J BVqLD1fr0tOWwgdWmPqsDB0LK7y6+EZCHhBnu/GoiIz7WOCXWSiAsxp7dJpJN0fCqYyJ gQ3m695mELNfnbOp4OCextJ2JkhjAGspDTBXYiwppEZGgC/jr3uQdb5z5Z6DuRVVWJHh 9AMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=uJ8iU5RvZsXIn9yVLIzKm4nuSmrz0M49050hDPScekQ=; fh=648YH0ympC0GO1R9X4VUyDuabGl/p48Phw6ajjzDgmU=; b=eH08GGannCBhfPGvCbSRhmsozxn0kmI30/fEwBwBeMhBpx+nWe+kgfjKpQF4jqDT33 P1G0dMWWszal0cZolBvGtxF33Zx6TJJUxhwNNEIqRFYXPdp3ss8a+enUhbIibuGKePFy B/0CwVQtxvYmcmWNPn7TvdqwSoCrV6gjTEYZ94TefdFayKzlHV3U0bYbbEKSlmtixKf5 Llj7QVS0x19Aua1BPhLNddYotvMeqFIG6/Gr3EvvxPsc7jcQdgcr+y+O6whxR2iRT0Vp j/Z5edQMt1/wPqVwDAYI5X19TMzblBfnho0G1tfFuQ1PFL7I6hP6ITGs868iK8NTeLMY /LXw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WTbpOeZe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4405b4f2444sm62438605e9.17.2025.04.17.09.55.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 17 Apr 2025 09:55:00 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Yanan Wang , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Zhao Liu , Marcel Apfelbaum , =?utf-8?q?Daniel_P=2E_Berran?= =?utf-8?q?g=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Richard Henderson , Pierrick Bouvier Subject: [PATCH 6/7] accel: Make AccelCPUClass structure target-agnostic Date: Thu, 17 Apr 2025 18:54:29 +0200 Message-ID: <20250417165430.58213-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250417165430.58213-1-philmd@linaro.org> References: <20250417165430.58213-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move the target-agnostic parts of "accel/accel-cpu-target.h" to "accel/accel-cpu.h". Doing so we need to include missing "hw/core/cpu.h" header in "accel/accel-cpu.h" otherwise we get: include/accel/accel-cpu-target.h:39:28: error: unknown type name 'CPUClass' 39 | void (*cpu_class_init)(CPUClass *cc); | ^ Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé --- include/accel/accel-cpu-target.h | 12 +----------- include/accel/accel-cpu.h | 23 +++++++++++++++++++++++ accel/accel-target.c | 1 - 3 files changed, 24 insertions(+), 12 deletions(-) create mode 100644 include/accel/accel-cpu.h diff --git a/include/accel/accel-cpu-target.h b/include/accel/accel-cpu-target.h index 37dde7fae3e..6feb344e29b 100644 --- a/include/accel/accel-cpu-target.h +++ b/include/accel/accel-cpu-target.h @@ -21,21 +21,11 @@ */ #include "qom/object.h" +#include "accel/accel-cpu.h" #include "cpu.h" #define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE #define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU) -typedef struct AccelCPUClass AccelCPUClass; DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU) -typedef struct AccelCPUClass { - /*< private >*/ - ObjectClass parent_class; - /*< public >*/ - - void (*cpu_class_init)(CPUClass *cc); - void (*cpu_instance_init)(CPUState *cpu); - bool (*cpu_target_realize)(CPUState *cpu, Error **errp); -} AccelCPUClass; - #endif /* ACCEL_CPU_H */ diff --git a/include/accel/accel-cpu.h b/include/accel/accel-cpu.h new file mode 100644 index 00000000000..9e7eede7c3c --- /dev/null +++ b/include/accel/accel-cpu.h @@ -0,0 +1,23 @@ +/* + * Accelerator interface, specializes CPUClass + * + * Copyright 2021 SUSE LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef ACCEL_CPU_H +#define ACCEL_CPU_H + +#include "qom/object.h" +#include "hw/core/cpu.h" + +typedef struct AccelCPUClass { + ObjectClass parent_class; + + void (*cpu_class_init)(CPUClass *cc); + void (*cpu_instance_init)(CPUState *cpu); + bool (*cpu_target_realize)(CPUState *cpu, Error **errp); +} AccelCPUClass; + +#endif /* ACCEL_CPU_H */ diff --git a/accel/accel-target.c b/accel/accel-target.c index 6fa5c3ef04e..769a90230bf 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -27,7 +27,6 @@ #include "qemu/accel.h" #include "qemu/target_info.h" -#include "cpu.h" #include "accel/accel-cpu-target.h" #include "accel-internal.h" From patchwork Thu Apr 17 16:54:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 881868 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp421360wrs; Thu, 17 Apr 2025 09:55:52 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX4Qp70e4nPXMjTylwfTFVZwOTWffSYbSpPVVWw4EJmebZpYS1lcmHzmlf9sVq9wVEE907uVw==@linaro.org X-Google-Smtp-Source: AGHT+IHOznnRDhkNhfmpsMLTsd5EYPvq0h0VBgZSs5qd5cm4hzPD4G1PHQ0/5XHdEfRnK/EDgPUd X-Received: by 2002:a05:6102:745:b0:4c5:1c0b:4ee9 with SMTP id ada2fe7eead31-4cb59319ac2mr4974064137.22.1744908952719; Thu, 17 Apr 2025 09:55:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1744908952; cv=none; d=google.com; s=arc-20240605; b=IZEVGf9nZOLh77rLgU4caYvXrXi3iODQSFGt0Kb1zRSA7xxV3FdD5zH5Si69ylFBVa utlLE1X470+7MtTtRK7w5RAIx9zqBMWoeHVOxEYG1MZITF+2Y1jh5WmAmcM8U251Xxxv deDBloRv/m78IU2XkobbCAZB5Q0DgST3hrr3KHKNZdOxF0lm0EPZc7VVs2V9+SJHsiE2 OZZcwdurqZfe5LWkZJmVkc7po/UWClcuhO0cQnYZ31fchL0vmjVU2oBRSHfWJfM93MKI Zgdg4X54sUtFvKh60XklfuDB40jLRBVzs/m+q6dyP9j7SkXair37n3SImphfXSbNOySC FCjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jysnHSLV8epANTA9h+/N0cIGwX54iTNV542u38RlNio=; fh=648YH0ympC0GO1R9X4VUyDuabGl/p48Phw6ajjzDgmU=; b=B6ytFomyCPBvSrdcBPnZe7eDcsndw4uTDN7RUnMiHdPCF5r+t2JsYXuHw3P/k/irO3 A7e1ksP1i8tjz/8MgvANdl2N9ufmvJhLbx38NjtKW1YHrx8qZb7Sl7cdq6+dyqOp40HT VkVzHz9ZMxzZ0GTuNX4rHOEWXS3Ed5gTcIerP6ZfToLDjJCeQsBIfU7s7Ls2clWlOtS4 4mCnyiLGGnuYu6djGRIOP9NY0UBxckUZ9KTKDepdKrM5tRTMqpeRjGweTT3v13KtUWYv efxd9c7sy6dQJdbcYKyKw513QceNDZpE5k99VZ2kRAQ7i+tk3XsHEKPj2Op6WbuS3HX4 5hfg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=toDfPKrB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-440699454ccsm4508595e9.7.2025.04.17.09.55.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 17 Apr 2025 09:55:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Yanan Wang , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Zhao Liu , Marcel Apfelbaum , =?utf-8?q?Daniel_P=2E_Berran?= =?utf-8?q?g=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Richard Henderson , Pierrick Bouvier Subject: [PATCH 7/7] accel: Move target-agnostic code from accel-target.c -> accel-common.c Date: Thu, 17 Apr 2025 18:54:30 +0200 Message-ID: <20250417165430.58213-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250417165430.58213-1-philmd@linaro.org> References: <20250417165430.58213-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Various methods of accel-target.c don't use any target-specific knowledge at all and can be built once in the target-agnostic accel-common.c file. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- accel/accel-common.c | 142 +++++++++++++++++++++++++++++++++++++++++++ accel/accel-target.c | 129 --------------------------------------- accel/meson.build | 1 + 3 files changed, 143 insertions(+), 129 deletions(-) create mode 100644 accel/accel-common.c diff --git a/accel/accel-common.c b/accel/accel-common.c new file mode 100644 index 00000000000..f505461fc88 --- /dev/null +++ b/accel/accel-common.c @@ -0,0 +1,142 @@ +/* + * QEMU accel class, components common to system emulation and user mode + * + * Copyright (c) 2003-2008 Fabrice Bellard + * Copyright (c) 2014 Red Hat Inc. + * + * SPDX-License-Identifier: MIT + */ + +#include "qemu/osdep.h" +#include "qemu/accel.h" +#include "qemu/target_info.h" +#include "accel/accel-cpu.h" +#include "accel-internal.h" + +/* Lookup AccelClass from opt_name. Returns NULL if not found */ +AccelClass *accel_find(const char *opt_name) +{ + char *class_name = g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name); + AccelClass *ac = ACCEL_CLASS(module_object_class_by_name(class_name)); + g_free(class_name); + return ac; +} + +/* Return the name of the current accelerator */ +const char *current_accel_name(void) +{ + AccelClass *ac = ACCEL_GET_CLASS(current_accel()); + + return ac->name; +} + +static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque) +{ + CPUClass *cc = CPU_CLASS(klass); + AccelCPUClass *accel_cpu = opaque; + + /* + * The first callback allows accel-cpu to run initializations + * for the CPU, customizing CPU behavior according to the accelerator. + * + * The second one allows the CPU to customize the accel-cpu + * behavior according to the CPU. + * + * The second is currently only used by TCG, to specialize the + * TCGCPUOps depending on the CPU type. + */ + cc->accel_cpu = accel_cpu; + if (accel_cpu->cpu_class_init) { + accel_cpu->cpu_class_init(cc); + } + if (cc->init_accel_cpu) { + cc->init_accel_cpu(accel_cpu, cc); + } +} + +/* initialize the arch-specific accel CpuClass interfaces */ +static void accel_init_cpu_interfaces(AccelClass *ac) +{ + const char *ac_name; /* AccelClass name */ + char *acc_name; /* AccelCPUClass name */ + ObjectClass *acc; /* AccelCPUClass */ + const char *cpu_resolving_type = target_cpu_type(); + + ac_name = object_class_get_name(OBJECT_CLASS(ac)); + g_assert(ac_name != NULL); + + acc_name = g_strdup_printf("%s-%s", ac_name, cpu_resolving_type); + acc = object_class_by_name(acc_name); + g_free(acc_name); + + if (acc) { + object_class_foreach(accel_init_cpu_int_aux, + cpu_resolving_type, false, acc); + } +} + +void accel_init_interfaces(AccelClass *ac) +{ + accel_init_ops_interfaces(ac); + accel_init_cpu_interfaces(ac); +} + +void accel_cpu_instance_init(CPUState *cpu) +{ + if (cpu->cc->accel_cpu && cpu->cc->accel_cpu->cpu_instance_init) { + cpu->cc->accel_cpu->cpu_instance_init(cpu); + } +} + +bool accel_cpu_common_realize(CPUState *cpu, Error **errp) +{ + AccelState *accel = current_accel(); + AccelClass *acc = ACCEL_GET_CLASS(accel); + + /* target specific realization */ + if (cpu->cc->accel_cpu + && cpu->cc->accel_cpu->cpu_target_realize + && !cpu->cc->accel_cpu->cpu_target_realize(cpu, errp)) { + return false; + } + + /* generic realization */ + if (acc->cpu_common_realize && !acc->cpu_common_realize(cpu, errp)) { + return false; + } + + return true; +} + +void accel_cpu_common_unrealize(CPUState *cpu) +{ + AccelState *accel = current_accel(); + AccelClass *acc = ACCEL_GET_CLASS(accel); + + /* generic unrealization */ + if (acc->cpu_common_unrealize) { + acc->cpu_common_unrealize(cpu); + } +} + +int accel_supported_gdbstub_sstep_flags(void) +{ + AccelState *accel = current_accel(); + AccelClass *acc = ACCEL_GET_CLASS(accel); + if (acc->gdbstub_supported_sstep_flags) { + return acc->gdbstub_supported_sstep_flags(); + } + return 0; +} + +static const TypeInfo accel_types[] = { + { + .name = TYPE_ACCEL, + .parent = TYPE_OBJECT, + .class_size = sizeof(AccelClass), + .instance_size = sizeof(AccelState), + .abstract = true, + }, +}; + +DEFINE_TYPES(accel_types) diff --git a/accel/accel-target.c b/accel/accel-target.c index 769a90230bf..7fd392fbc4a 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -24,135 +24,7 @@ */ #include "qemu/osdep.h" -#include "qemu/accel.h" -#include "qemu/target_info.h" - #include "accel/accel-cpu-target.h" -#include "accel-internal.h" - -static const TypeInfo accel_type = { - .name = TYPE_ACCEL, - .parent = TYPE_OBJECT, - .class_size = sizeof(AccelClass), - .instance_size = sizeof(AccelState), - .abstract = true, -}; - -/* Lookup AccelClass from opt_name. Returns NULL if not found */ -AccelClass *accel_find(const char *opt_name) -{ - char *class_name = g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name); - AccelClass *ac = ACCEL_CLASS(module_object_class_by_name(class_name)); - g_free(class_name); - return ac; -} - -/* Return the name of the current accelerator */ -const char *current_accel_name(void) -{ - AccelClass *ac = ACCEL_GET_CLASS(current_accel()); - - return ac->name; -} - -static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque) -{ - CPUClass *cc = CPU_CLASS(klass); - AccelCPUClass *accel_cpu = opaque; - - /* - * The first callback allows accel-cpu to run initializations - * for the CPU, customizing CPU behavior according to the accelerator. - * - * The second one allows the CPU to customize the accel-cpu - * behavior according to the CPU. - * - * The second is currently only used by TCG, to specialize the - * TCGCPUOps depending on the CPU type. - */ - cc->accel_cpu = accel_cpu; - if (accel_cpu->cpu_class_init) { - accel_cpu->cpu_class_init(cc); - } - if (cc->init_accel_cpu) { - cc->init_accel_cpu(accel_cpu, cc); - } -} - -/* initialize the arch-specific accel CpuClass interfaces */ -static void accel_init_cpu_interfaces(AccelClass *ac) -{ - const char *ac_name; /* AccelClass name */ - char *acc_name; /* AccelCPUClass name */ - ObjectClass *acc; /* AccelCPUClass */ - const char *cpu_resolving_type = target_cpu_type(); - - ac_name = object_class_get_name(OBJECT_CLASS(ac)); - g_assert(ac_name != NULL); - - acc_name = g_strdup_printf("%s-%s", ac_name, cpu_resolving_type); - acc = object_class_by_name(acc_name); - g_free(acc_name); - - if (acc) { - object_class_foreach(accel_init_cpu_int_aux, - cpu_resolving_type, false, acc); - } -} - -void accel_init_interfaces(AccelClass *ac) -{ - accel_init_ops_interfaces(ac); - accel_init_cpu_interfaces(ac); -} - -void accel_cpu_instance_init(CPUState *cpu) -{ - if (cpu->cc->accel_cpu && cpu->cc->accel_cpu->cpu_instance_init) { - cpu->cc->accel_cpu->cpu_instance_init(cpu); - } -} - -bool accel_cpu_common_realize(CPUState *cpu, Error **errp) -{ - AccelState *accel = current_accel(); - AccelClass *acc = ACCEL_GET_CLASS(accel); - - /* target specific realization */ - if (cpu->cc->accel_cpu - && cpu->cc->accel_cpu->cpu_target_realize - && !cpu->cc->accel_cpu->cpu_target_realize(cpu, errp)) { - return false; - } - - /* generic realization */ - if (acc->cpu_common_realize && !acc->cpu_common_realize(cpu, errp)) { - return false; - } - - return true; -} - -void accel_cpu_common_unrealize(CPUState *cpu) -{ - AccelState *accel = current_accel(); - AccelClass *acc = ACCEL_GET_CLASS(accel); - - /* generic unrealization */ - if (acc->cpu_common_unrealize) { - acc->cpu_common_unrealize(cpu); - } -} - -int accel_supported_gdbstub_sstep_flags(void) -{ - AccelState *accel = current_accel(); - AccelClass *acc = ACCEL_GET_CLASS(accel); - if (acc->gdbstub_supported_sstep_flags) { - return acc->gdbstub_supported_sstep_flags(); - } - return 0; -} static const TypeInfo accel_cpu_type = { .name = TYPE_ACCEL_CPU, @@ -163,7 +35,6 @@ static const TypeInfo accel_cpu_type = { static void register_accel_types(void) { - type_register_static(&accel_type); type_register_static(&accel_cpu_type); } diff --git a/accel/meson.build b/accel/meson.build index 5eaeb683385..52909314bfa 100644 --- a/accel/meson.build +++ b/accel/meson.build @@ -1,3 +1,4 @@ +common_ss.add(files('accel-common.c')) specific_ss.add(files('accel-target.c')) system_ss.add(files('accel-system.c', 'accel-blocker.c')) user_ss.add(files('accel-user.c'))