From patchwork Wed Apr 16 11:06:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vishwaroop A X-Patchwork-Id: 881810 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2081.outbound.protection.outlook.com [40.107.92.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA1E31EF380; Wed, 16 Apr 2025 11:06:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.81 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744801601; cv=fail; b=DrFLz+Q5YkD6jqG7f3xvtcvStNweBV7T/biJ+2beCSG8BKEefnzFCcANWcV+q0A9Z87mZojweyk050p1JKp4DEF87uGRtFVglslc6SpDA0832oWM5PVlSoJW1gGJBDDWgE85GWZFrb2HozW70P+042czsf1o+r+JePpFsnX/aRA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744801601; c=relaxed/simple; bh=499x3GbmQ7WBz6PTbm2Ravm6OmWRIXeBjQX9ZAWOu14=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZXlPzQk3fLi7dGdt/43tjTdaddM3VhXDGbrtQO4Fx8CSvKCpVkJQq4/GAg5BTTaOG3h7nTH70/HBaIpFRpXLeIVyGWzphJnncrlQCY1cuNpn+x/ebbWcsBKWY3b2LcMcjEdl+gdrzdyZ5lK1tGz0ezJuaewsX32p/9XFqujnKl8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Y1Gtqfor; arc=fail smtp.client-ip=40.107.92.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Y1Gtqfor" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=g0Q3rW0SFqiGUP5F5/BK3uLQCV8S2YV8BVOr3gIFYmy3QDOJOvDSZogLqTz9b1gxjehHzfPRYmx8B821dwdLEtNGe0nx+xL0YnrBt+CXLayn1zgpi55T5HpqDBybAa7BY8h5MyYW7lCb8SJKbBM9Tv8LmhT3AAFUN1SVwxMnVivaHw59grCYUqhzrBq5pLBtUnOp21GPWrw7HqjU8nAjDctUuEMRDcaQMbXc4ac1q1b3PYTa3Ad3RVT7NqfzVgprRXrVJigSUx3RH7bT06s6Sj0GA4eUVNwuTtU5hiacXGiY6rV1jESe4TCp+Zx6eZ9AaH+DeeBviBT7tFkhrY86eA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=KDUQeJ9H4ROsmvM0YwlCi90TytoxzVSqQIUTwrKGLFQ=; b=ywx8LIhOIOOFzhkhqsrIou0HLmCdIH2kh3eczJ6HjLBTYBkk/SUAE6BwKqBCi75C+gxqIoMzv4WCw0COi3xKFSMfl4HJRdZutebzE/kGTPuaZk4+qFy9CphGY/yzldWmD5qqAQ052TStIRp7K2gbDzQeyeexW0gYT2G6Igwunx1fSCavM6EzU8h0xMa8LPb2+tzMeOBgf1TMz2fTdUmxfhHqiUSjIMmRSV2qGa/Yduf3/M0CkjFbhmguwtsLP1VRPR/jxGK5srExUnwfzc0D3hqPE1QaNLVFiloNpBqR0ntrVSRAmkhTBvmXr22DHuolaNB3LUDlcXqjzE+vg/o0xA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KDUQeJ9H4ROsmvM0YwlCi90TytoxzVSqQIUTwrKGLFQ=; b=Y1Gtqforklce6LOk2KFFJduMY5GArrX/b34qRHPXBS+A2YoBdJinE7R7NekQ15ERAe5R+owkhf4drFfFIMMB5QNNuQHCQzT/08Qh+gWWOkwbJXHSt0ZnlGfTqK+nqpJRSs0twCbfpuWD/u+T18wxYfNemIOCoeeHKXvem3AZzu+zh74Wx9LhDA56v4QnC65dxF6FjW3p/oxuoh3uxUa4sw311r2OF14iaWAQ9eWUAdSOwSofcvSv4rvcbTRq1rvQm6gijNlrG0Iimroswma0T8QR3gatco5VYcWTCl/S8ZLcxTzQnIhCRHxxWEnmkp0em/0mRC0Z+EKC6XeXW2kR7A== Received: from DM6PR06CA0099.namprd06.prod.outlook.com (2603:10b6:5:336::32) by SA3PR12MB7949.namprd12.prod.outlook.com (2603:10b6:806:31a::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8606.46; Wed, 16 Apr 2025 11:06:33 +0000 Received: from DS1PEPF0001709D.namprd05.prod.outlook.com (2603:10b6:5:336:cafe::34) by DM6PR06CA0099.outlook.office365.com (2603:10b6:5:336::32) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8632.34 via Frontend Transport; Wed, 16 Apr 2025 11:06:32 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS1PEPF0001709D.mail.protection.outlook.com (10.167.18.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8655.12 via Frontend Transport; Wed, 16 Apr 2025 11:06:32 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 16 Apr 2025 04:06:19 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 16 Apr 2025 04:06:18 -0700 Received: from build-va-bionic-20241022.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Wed, 16 Apr 2025 04:06:14 -0700 From: Vishwaroop A To: , , , , , , , , , CC: Subject: [PATCH v3 1/6] spi: tegra210-quad: Fix X1_X2_X4 encoding and support x4 transfers Date: Wed, 16 Apr 2025 11:06:01 +0000 Message-ID: <20250416110606.2737315-2-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250416110606.2737315-1-va@nvidia.com> References: <20250416110606.2737315-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709D:EE_|SA3PR12MB7949:EE_ X-MS-Office365-Filtering-Correlation-Id: 60a1701f-8a0d-40c8-c99b-08dd7cd6bf19 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026|921020; X-Microsoft-Antispam-Message-Info: 4pgdpvQgvkS7PfDbF5MWJZIy4qLthi0Gnd3mcJoz6XmA+MCwyBZrNku29RKwUOXFtLKSMfe1gpHBcGXSM73glXqKS4eyawCvoyxbzmpJVRwe1dZiPq12BfxSJyxzdFFmvr3fPKu0mBsph4W1oP4wTTf0qWSZcrdCJRuPDTxkSzccKOkEQwAsiXLK1U1DBwLEoM2XWytwrl8s7Bl/jDV6+HqZSkVOxkP0O/AI5gbGLwIjdxeWNUiae5W1swIhPSfS9lRCYzxAngdcGWUsD2OjGFK4pdN4Kte/Dd5x041/1CtiiDJPZ2Xxxvyx2yx02oWQTYAG1oglK0076YsitX36awEFAP4wDrMaIZDSt5pXykqtQlBUM217T3xYGoxtBKPHvvcOmQ911QSRZLxzqeT369cgCitnrZQlpKU2FepHgCOOJOT1f6TP/ZGVXNYvxcNeqUOPG/mw060WCCU/2TBQot0CZGUZfMfjOgXXsgQFQjLQnJrTd3XNyPOlGXs/u7ZkifzxctDzxHTby/+F6lothzkh4HiYRrhUfumFu2aHhnN30wMSGnMD+o9Bk7Z/bnZ0Mb+q79Tnmpo7arUgLGNp6C1SOpbanKNE7LC5TNELzx8bHuQajcnIc4cnrsJ+978ANnhvzVAlRa4SOn4AnaPa65CrX4mrV009KZZlBuzEBTsas093vqvUMt3tmzYo9e5MoEPKeV/cJ2BPpjBqGqX+PgFAOY3ETe3vwZ/T1V4XaTMCAtpuwxEdWWjrbi5IklOo7Q3Y+r8OwgC9QmSy9vtKPKThQB/+sk0Fvoo42GNlciY38SYeLDL5YSW+UNx8at5FUl+YbHPDP8JybRx3lFWq8MDSM9ef9P9zjUFm3piJ7iWzvmLN+GLOAiD4/cpN2kBqXu3rwFryouo6lKAqivI8+CAFMoZBeOlTmbUdU+Iq+e1zFkP6BJujQcVBy70aGvhGUma3SWnm21R46/HJhNGO67FDEMkx0CKsOR8pNDQknL8ezJWWoCBSRO1e0HmpLbiS+zZOvy6xjqhUOw26brEMMNDR1KJ1JLEJfDgwciLTuKUEfnrOx2Ws1yGSRFD1fnaHkWxElJcWaretSxleXIjTXu2SMrmyWVdlcW8VcfxHG/vgQ5sntUBUznHQ4zTygXOoLhvFHfVepHxo55QneuBf+6aXuMWUd+IhkA9lIOF7L9QyRR7S0Cw3phGMnCKQEaFxysjGwx/Wopxc+X/1ik1iLGvb7NoDth97ZTqVMeKhJWieEKeUfwCKEOCjvJT5UU/gQYeIRKsT54owG10chlLgLvRDcJ2rDMqD26foodvQTVHwv9L6DI3wOd1po6sw9G11KQq+Hkfp7BQ9r/NUnrhkNn2fDgmbY0grjYJVW4r7DJUEYtrseIxXUEDLgYzNIg3DMPg+F6jisGOf/tXnXlp4vG5/SnX9VMFIXAhzBQGWejuZ1B7Ut05/YQL9ayb6Xjyf+mnWeSfimhyCDBIlAVbnKRZIno0A2JeXYfCl2Nt2PKY+j7PSYAQtjdaY8fezi/dMSM/R4tgjvUXcGL4vXWGrVA== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2025 11:06:32.5431 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60a1701f-8a0d-40c8-c99b-08dd7cd6bf19 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7949 This patch corrects the QSPI_COMMAND_X1_X2_X4 and QSPI_ADDRESS_X1_X2_X4 macros to properly encode the bus width for x1, x2, and x4 transfers. Although these macros were previously incorrect, they were not being used in the driver, so no functionality was affected. The patch updates tegra_qspi_cmd_config() and tegra_qspi_addr_config() function calls to use the actual bus width from the transfer, instead of hardcoding it to 0 (which implied x1 mode). This change enables proper support for x1, x2, and x4 data transfers by correctly configuring the interface width for commands and addresses. These modifications improve the QSPI driver's flexibility and prepare it for future use cases that may require different bus widths for commands and addresses. Fixes: 1b8342cc4a38 ("spi: tegra210-quad: combined sequence mode") Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 08e49a876894..4983b1f705b8 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -134,7 +134,7 @@ #define QSPI_COMMAND_VALUE_SET(X) (((x) & 0xFF) << 0) #define QSPI_CMB_SEQ_CMD_CFG 0x1a0 -#define QSPI_COMMAND_X1_X2_X4(x) (((x) & 0x3) << 13) +#define QSPI_COMMAND_X1_X2_X4(x) ((((x) >> 1) & 0x3) << 13) #define QSPI_COMMAND_X1_X2_X4_MASK (0x03 << 13) #define QSPI_COMMAND_SDR_DDR BIT(12) #define QSPI_COMMAND_SIZE_SET(x) (((x) & 0xFF) << 0) @@ -147,7 +147,7 @@ #define QSPI_ADDRESS_VALUE_SET(X) (((x) & 0xFFFF) << 0) #define QSPI_CMB_SEQ_ADDR_CFG 0x1ac -#define QSPI_ADDRESS_X1_X2_X4(x) (((x) & 0x3) << 13) +#define QSPI_ADDRESS_X1_X2_X4(x) ((((x) >> 1) & 0x3) << 13) #define QSPI_ADDRESS_X1_X2_X4_MASK (0x03 << 13) #define QSPI_ADDRESS_SDR_DDR BIT(12) #define QSPI_ADDRESS_SIZE_SET(x) (((x) & 0xFF) << 0) @@ -1036,10 +1036,6 @@ static u32 tegra_qspi_addr_config(bool is_ddr, u8 bus_width, u8 len) { u32 addr_config = 0; - /* Extract Address configuration and value */ - is_ddr = 0; //Only SDR mode supported - bus_width = 0; //X1 mode - if (is_ddr) addr_config |= QSPI_ADDRESS_SDR_DDR; else @@ -1079,13 +1075,13 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, switch (transfer_phase) { case CMD_TRANSFER: /* X1 SDR mode */ - cmd_config = tegra_qspi_cmd_config(false, 0, + cmd_config = tegra_qspi_cmd_config(false, xfer->tx_nbits, xfer->len); cmd_value = *((const u8 *)(xfer->tx_buf)); break; case ADDR_TRANSFER: /* X1 SDR mode */ - addr_config = tegra_qspi_addr_config(false, 0, + addr_config = tegra_qspi_addr_config(false, xfer->tx_nbits, xfer->len); address_value = *((const u32 *)(xfer->tx_buf)); break; From patchwork Wed Apr 16 11:06:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vishwaroop A X-Patchwork-Id: 882236 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2069.outbound.protection.outlook.com [40.107.243.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA34B23BCEF; Wed, 16 Apr 2025 11:06:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.243.69 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744801606; cv=fail; b=bmjJudX2GsGfADwjAqyCZ/Ngf40PyGBgeg2Tu3jrK+o/e+EGrH/I0x4YgU9fV26RXF/5e9mWsjL04DtcPwuIJgEow+UaqQtP2rAmRprd5DIB10bBBzjohCjsTan33ew7u+Sbn47t5+jLnJggF4VLncH6BUEw5ySSnh62WVvsLzI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744801606; c=relaxed/simple; bh=UNy+mPzmKjsbJtk8a0Ul3KjBngS8ly8q87LJCgqfhy8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TN5YSwJeQwnBewysoow8f9d+G0IMvPsc+/DLgrhSMN4oweJCifBFT4qgVzWEXsfcjKTWaSlzTR6rbmqKdHPsrtyslor5rV7Fz3+mKD/ikq2ZjnDaXundnr1WdAGoTMLmJ06OJEo/C0MTyUyokDMxF8gUMusDlNazI3mk/XXsDGQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=dR49k8e+; arc=fail smtp.client-ip=40.107.243.69 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="dR49k8e+" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=OEqcNlg4e/UU4/0YWEI2IzE7MqmraTU8Hv90j41Hko1PTZk+5951JfIIFKd4aLIfXXoVIVFyLY3WmbTXnIE0yxWu6NL7ia3u8t5SLNb6Lg5Q3voQy6GAFmnRKWXKN5QSyuayXlwBtN3Yy/LLXuCeXoPOL3dx3Ol6LTYSKVY5oT9mC3zaqm+JS8lbFoO+E0qqge1Fa589T1EOdyg9QToTLen2HDg5MC0mvHsKC70PbXt/f4zbzVNV2eLOS9bVY786eZ04pEUmehc7BehnwvJixQiOl1JZb3Hj8J6bsVksVtd6QrM9Xa0vV4bMzvZRV+eMPM8bvuY7MPu//EsCNGiFWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=HTiGAvaW8FskL4xStQPXREwoZwcQA6Q1vDFXBlgrusA=; b=RFh09B0UxCytEmcCp4PI7yhmVLho7tMs6E77ae8LC/k2oB1cyShWFzflimTqBZNmup/d68nBAP+qcuyQ23cFct8ddcZIhc6nM9DdhNsqVY49uEvV3BdfmPTKFLhQXSkdlYqCn0NwujQ1OYElcmcSFvPj73hbLAXWqTksUYW7x75dRzCigxBkcWnl9wySRzIdGzDBD1A6Xx5BGTG7IB/w6zv0mRQFq9NLV6PheWxYyszha6BD888oX0znsoUfdOtavWnqkmsM/KcX+QRczumg/4eUu//J8ViBGRy/0cPZdSlCAJ6sa5uaiTY9AjVuVTgiDx2Vf5CTy+Ju8wE0Ccf7CQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HTiGAvaW8FskL4xStQPXREwoZwcQA6Q1vDFXBlgrusA=; b=dR49k8e+C96QujBa6es08EX7PZSJIHxhczqRYzWlfMKPwG0vMGhXVKGzulBpbUzMFOeaGUQXK4Ri2hG9uNsgMsB1fRmsbX5hi1j0mphK/CsljjzPfXRkUKEuVew5gmKo8KTd4OYx6NTzwhVz3csEBBHUgR4pSMi1j8k2QI7wUErkdYGz07q6vJ3cJvdxXVdEix/z8e8G2t8twtTED+dj3HwhZHm9vG7VaEi3IKzCn+huFx2aZoy1ExdKGMNdmOgh6syUShXgkX9W8abkXJjV69eDsgW47/VDFPlsyQeeQStZnq01PfSnW8r9Q0Whn4EUdJ6rzcG9YgUTqyLKseqcEw== Received: from CH0PR03CA0119.namprd03.prod.outlook.com (2603:10b6:610:cd::34) by PH7PR12MB7939.namprd12.prod.outlook.com (2603:10b6:510:278::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8632.27; Wed, 16 Apr 2025 11:06:39 +0000 Received: from DS2PEPF0000343A.namprd02.prod.outlook.com (2603:10b6:610:cd:cafe::6c) by CH0PR03CA0119.outlook.office365.com (2603:10b6:610:cd::34) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8632.35 via Frontend Transport; Wed, 16 Apr 2025 11:06:39 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DS2PEPF0000343A.mail.protection.outlook.com (10.167.18.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8655.12 via Frontend Transport; Wed, 16 Apr 2025 11:06:39 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 16 Apr 2025 04:06:23 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 16 Apr 2025 04:06:23 -0700 Received: from build-va-bionic-20241022.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Wed, 16 Apr 2025 04:06:20 -0700 From: Vishwaroop A To: , , , , , , , , , CC: Subject: [PATCH v3 2/6] spi: tegra210-quad: remove redundant error handling code Date: Wed, 16 Apr 2025 11:06:02 +0000 Message-ID: <20250416110606.2737315-3-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250416110606.2737315-1-va@nvidia.com> References: <20250416110606.2737315-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343A:EE_|PH7PR12MB7939:EE_ X-MS-Office365-Filtering-Correlation-Id: 95e2f307-89f4-4f67-57d7-08dd7cd6c306 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026|921020; X-Microsoft-Antispam-Message-Info: CjJAsRD4QGExWkxJXrs7iucLgx63/HM4cCxMsEkjsWMLXZJWi9nIHHqAMx79/ims2ZIYXlHeYUMPZU3BEPzA1yvuY5CU8mnvQSHNeHjli489oAcTJv6YonNcRG3vFV9mfPOWq5hK0FlIkHxId3vs6jJWdPwMi/ZELgB+5X2AYzYAtflp6AoSYpgsrYziBeFXkl3+Qf2wo88ANnCWbAs6Bt11tKFguNRMjo9cPSM/3UbVcTMDIYGMr0lHSGZnSeayGztrCdV210gnbbV1YpcZCiWMXpN2LPxh13wdTrc40uz3xdXqNfQv2KX4ykhimJYm1FDemc7ccd2Zt8ckkkESVht1Qi4DsSj3YCLAwp+DyXxnZPx3yNwGxJ2kPA4FMQGDvrrCtrVNa5NlpnPw9gqNwZMQTv5PpxRVj22WihQgn4X5F3weGEmPsfa+UWkEXAlJKQKC9P5TWeW/FLYlRlTJYm0/03brqZn3Rb7MNcH0WVsZ7hsvDmrAz8zNgLJuVYQz99wef/RiLGDb1Gfn+Msr2Xcw2r0MOyUzJDQTnfGokusngLQ4aIdvEDVQLA5p3hKiV4g+H+NWxZgrasHfDgiJK+9fsYaamXc+CfsRHbodxDVA8LRys5YKDSnsy0aTrbJsVPFmU9ZI6xEgbBvzC+MCdFG2F1hKy+nSTH0OkKoGdtcmZeSkjjBFrQt+tZ+4vpCB7yXJS4Gb1L8tekqjYxtwYbzychso3/5Mm/8PaiLHU5NcgjBLcCnBEwlI2+F1Q+Kd5vtw4GxkgKJCY51iMQAeHspVfQKMJTI+aLMbIFjPHJ0cks0MPMHXlEL2rFkXmSbdKBGFru1Eg0ulzPKAtyayBQ21zT5/JaEF8V+QVXJQ+oKG8x7BDK4MX3zij2UPlDXrkadP4wJqVd/EvXoOt4pmc/+bB5esusowelwIdRhzuRtpv/JbPUZ+zQ8MDqGa8ZLrQL/5sl1k4PYxeHY8auMhtROslyxpobMCDBh8jLZYt5D4SgMDdhoW9VE1Hw8teH3uQNftoARMI+v2isn4NQz7QEZmanIY3btM5ylZyrM2p6NWIHt981YtP/xgxAL8CdHksTisLlPMnaEztVkCcVAgpVpSuTmSOM35fQFux6NoW8s344G+ZQGARiuVuzpvPnhlRDFD/D5KeY7ELe7a92X4vMlslCi1bmwdUPt6j5uHbzbU/xeXGUlZMX4cZwOSrjPrYf1RVQi461hVXBO+zgLTarRzLBOQjdtF2weSRwa3GUebJK1FDxXrvCL8E2VwXzQ1boIg3C1t6/EJdAa0idHQBHDTI4XPpAZVFXsihw0JPxzCFKFTLflO6mT71f7hE5BCuNfzcN/HYBxgmfp3oTDj1IybkMPsYSokXeMddtacJTckkCuS+y83aA35QB2mS8mIr4Ah9BZtcSWZ1r2lF7MQaKXGYLu9T16++97UGyv2/D1afzL7s5Id5rc6cSP44tfQ2X0kc6Xh/m7tjMFEmStzfILv9yxfZupHHTGWQ9vb48ieMmhfWNY33x+1vyyhpV6dsjZkN1H/ZrzH0MdSVupFGw== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2025 11:06:39.1890 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95e2f307-89f4-4f67-57d7-08dd7cd6c306 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7939 Remove unnecessary error handling code that terminated transfers and executed delay on errors. This code was redundant as error handling is already done at a higher level in the SPI core. Fixes: 1b8342cc4a38 ("spi: tegra210-quad: combined sequence mode") Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 4983b1f705b8..a9359b005ee8 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1175,10 +1175,6 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, exit: msg->status = ret; - if (ret < 0) { - tegra_qspi_transfer_end(spi); - spi_transfer_delay_exec(xfer); - } return ret; } From patchwork Wed Apr 16 11:06:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vishwaroop A X-Patchwork-Id: 881809 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2043.outbound.protection.outlook.com [40.107.220.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 871632441A0; Wed, 16 Apr 2025 11:06:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.220.43 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744801611; cv=fail; b=s+pIwNEbDJaYY+S8mrayclABLsdwSxPpTxOQk3jiQBkeDbk5je//DSZ6mSsupWHDF6wR4s/YqfQ4WRrSscE1caO5K+zN2mOrhpMd7rQI7mJ/+zxFktBDaBN5RRV1V6aVujxc93tR4wtXJ0APU6e3mUXe6EGj0HJAOOKxBbGHDF0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744801611; c=relaxed/simple; bh=Y5583duQuHmRpHaRDNWhgEf1ZpRumPRNbCcjr459/h8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QECvVh7KxUzyO/IlX2pVW49BreGmn6F01HX9jyjZGhu63ZWjB1nzwhjp2geil3REkcdxFUKpmzEaNRjb2jd2tA/jgTw1Ulu3/1kSyFrL6GPWm17fBgbsj/MUWzecWt6SjqCIVJNlpliCh2NjvmyxpuqLHw6OAWTSihfpJX9tlEE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=nPT6wzEB; arc=fail smtp.client-ip=40.107.220.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="nPT6wzEB" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=gmoCEOEZOEd/Q77aJkZpEPOQic/RZ0yqTxubHUb8KmY9kJl01hnZVozvSTg2PUOs9SRs6uBpQxJGpcb4omEcjM7pbyWtS+yOnWz90Q9ahV3tIRnPCTYh/pMBRhtduLuBTHSiPmIcbhr89/eM7Nqo9dZ8lXp9CRs6nG8tQ7zaOcIX9SFN+kw+fWZzZ6n0nOilZhmZQHHfo//LdgeaBiUw+HqybfKqE8gYJypqG1PoPzoWCQYoazNTJdG/QbXW3mwN/H7pmSQXWfFaMDNLwoZej5JI1serRizX4crdvzxb/2wqLstQ6TVQUpZFsNA+vR/3Nu5TsxwCoJFQK3559iTkzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=YaKh4umcN8wTJOFm7OLxlTzd/qVFw6y2MfaHSbRCI2Y=; b=Qrz2VTcSGLJRy9j70qH7e9gMGjzqmhXVjUbkQa4rGNcGX6JlnK/6lShR3s9MKluk56DNuXwaZpKR5iDXn2r2qWBSVpfo/3bRlCuSvM3AAXTtQtQDLiEt2hJvwe1n7/qrHAR/1UVl1z4N7VSxR/2VCoZCuyimbKY/0RFAmc6IwCuJ3FbnEIPB50Su2XoQ9xAqTwf6P+3psKFGCvvKezCOqyvI8m/i96GqFIXJ6tWAPFrPLTP3dY8fpHyun97U1KaBN5TnllqsEH6SkvSKpC90nF7TjUBNpuMsyD32sqe2HgPuw3rwvcGJeQ3WpMmJ98ZtzJQa71/oHtByilxi0ku+IQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YaKh4umcN8wTJOFm7OLxlTzd/qVFw6y2MfaHSbRCI2Y=; b=nPT6wzEBiPrb+7M10TAMmKpO/8jnJn65VHrqKBThbv0EMfEVDyfQTCEwQe41F7ChLcfY5/dynUDFClMQrPzqIHtL49GgISDEhkB6KO44uQgWJzA9LX3ghKoGcVmmnfUu35j2aH8ouyedtPotMXfNCWnIXwRswPcjVyXEwtO4UgEQARtXqJzygSKIL2cOokcxT0i5M+NTKXrjSY2d9wn+33shtgfD1yN529HWf2fkzEVW9H+iOX/fk4KGxJQlAM2TnK325iRAhoyixbSLcoFDr+QK3xANrU90c+EU2lfCRQ2xjvlyy2Ewit82AeCmfB5BK/UpFW7F9M8zg2TU04NSoQ== Received: from DS7PR06CA0020.namprd06.prod.outlook.com (2603:10b6:8:2a::21) by DS0PR12MB6654.namprd12.prod.outlook.com (2603:10b6:8:d1::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8632.35; Wed, 16 Apr 2025 11:06:43 +0000 Received: from DS2PEPF0000343D.namprd02.prod.outlook.com (2603:10b6:8:2a:cafe::9d) by DS7PR06CA0020.outlook.office365.com (2603:10b6:8:2a::21) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8632.35 via Frontend Transport; Wed, 16 Apr 2025 11:06:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DS2PEPF0000343D.mail.protection.outlook.com (10.167.18.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8655.12 via Frontend Transport; Wed, 16 Apr 2025 11:06:43 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 16 Apr 2025 04:06:28 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 16 Apr 2025 04:06:28 -0700 Received: from build-va-bionic-20241022.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Wed, 16 Apr 2025 04:06:25 -0700 From: Vishwaroop A To: , , , , , , , , , CC: Subject: [PATCH v3 3/6] spi: tegra210-quad: modify chip select (CS) deactivation Date: Wed, 16 Apr 2025 11:06:03 +0000 Message-ID: <20250416110606.2737315-4-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250416110606.2737315-1-va@nvidia.com> References: <20250416110606.2737315-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343D:EE_|DS0PR12MB6654:EE_ X-MS-Office365-Filtering-Correlation-Id: a388fa61-881e-415e-1394-08dd7cd6c58e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700013|1800799024|376014|921020; X-Microsoft-Antispam-Message-Info: WjnCa5hwWpdWHKozXc2LGChfe8dywqRTaSnmksZu0OKvZEvi6yZh8wVHgJ68zCm8mDfNd0seKqJwZQSqUQcQpkqBYB6wzgdpZM0gHWjX/oMgEEMOeTBysYBiFyMSlJDu+kj7VPGU5EjN0o+XSIsSCYCoocFLR+NGAFjrfs6Uwd0wm+o1m3xvWW1NWi2Jwm309ulLlf2LklS24j9v5GLe8iXOVGKq7mXG7EmHBU5fljEoXhbnCRJOJL/N1nywhnhkJ6UskKYPG5Nb9JpKogIEsGQKwYSmNwX+E4PU8SwFAT+fGrXz0uHeacRVYtPXxjnktZlLmugYrDvW8wqD14zkcpNL120p/tjwsEsW20HsET9FdRHMCqrbktgMFYOeYalcM7qTIL5Y1rFcWbdTbGzbj1gkIlg9P0soL/LyhjSwQR17ZIMN3Xt3twG8Nd19XaOlhNQ0MPRxbcHrdV++FZ7c592yF+gTT6ZeQht9ERszfHRx8mL65+flbAdlcdByHVQJCV0MG37RQDuYbpahCoK7gH7BhuZQHtWNnmZmCN8mYOuisf5kG0UQzTgyRUaSHmmNCmdk8inXB5AwgFZg3d6bY7htRxv0VeFbcDt4ZcJtEXDl6w0Lz/RW8VEvi1XIGV8XhF7ZgAJ2yEhPu+ZRJT6yJGxr50ZooDw7EHCap/WeHhaild2k2N1Yq80kVdGerOFmdOME04oDO+lHTB1HFkPLOce/BqFo0j23xl1qb5bDj/HorkGNvcbwQAv0vyF9pmLwJNXK2yqYeHYtmb8kp+eaMpJjzp4Y4RfBOXZEwpmdWyskvCOXbLz4efxksne8sZK+ba+VB0uNGqtApOuJZxNIw25oz4xoA+TvdGf5P0J0CsAsdp8gtYTE+qzBebBsNt8PQkDZBajA+zkbLR2Hj/hG+wQ5v3j2dq2VNhQp8OE09+HiKwRpYqakuM+6wQAAVl1hDw+U0TsLtNeEfJ0wCAarTmFYmd6Nb1S1P9xtjfRnifx33ctxwrKULiGc4x5lBKqHzRxNq3I9bkobgCseCziY4fGDL7YfdIdQsg4K1COEYmz6IhxniTuSGEssndHHhL1eiFkFoWPmhxD15E1wZ3Eut0NaeMQHGDO3kIE4g+1vowdxXGnTHw55V72yB662WVH8Z9NQmm18RGVdFca4bS0lZiKnAjPjqq4O+A8XreQ8wJFR6HGM+YjeKvng0/8FeCyoWnQtG22Le4RZJzkjMpqZJUMejxDz6tUxUCeLDte7Rfvk1p0uE4o11ZSntImt6ChNxtIx77tUmQ9cmS32pvP0eu9dm0SqDaB7IUUA/rS6sYXApOKU8e2Kl2839qi6gLiR5tElrFFwWE3FXCaldvVuBGWN0Lo3058nziDo+R6V2xL9xUq1zgzF2JUtX6gTtwVy+2V1KWNAz4QMRLB7QyD17DUvWTdVQ5DtnKEmeDGD5Pt6poDfBh1v3PUX7Fxnlncq1QfYp0zD0Xa/BFLGtpY5yH+FaS/juG/A20FcKSUgnZzSe4Ww9+O0U6rpvUBgNVpi3Ai47+lglgwZHetF5+S3mg== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2025 11:06:43.4340 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a388fa61-881e-415e-1394-08dd7cd6c58e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6654 Modify the chip select (CS) deactivation and inter-transfer delay execution only during the DATA_TRANSFER phase when the cs_change flag is not set. This ensures proper CS handling and timing between transfers while eliminating redundant operations. Fixes: 1b8342cc4a38 ("spi: tegra210-quad: combined sequence mode") Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index a9359b005ee8..159fbbfd4a38 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1159,16 +1159,16 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, ret = -EIO; goto exit; } - if (!xfer->cs_change) { - tegra_qspi_transfer_end(spi); - spi_transfer_delay_exec(xfer); - } break; default: ret = -EINVAL; goto exit; } msg->actual_length += xfer->len; + if (!xfer->cs_change && transfer_phase == DATA_TRANSFER) { + tegra_qspi_transfer_end(spi); + spi_transfer_delay_exec(xfer); + } transfer_phase++; } ret = 0; From patchwork Wed Apr 16 11:06:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vishwaroop A X-Patchwork-Id: 882235 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2044.outbound.protection.outlook.com [40.107.236.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C040247299; Wed, 16 Apr 2025 11:06:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.236.44 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744801614; cv=fail; b=HO6HI0c6viDf53rAZL3J+5irF+FF838JbXo0bAc1CZJZNEvcncSYW1qx4BHGX6QPtdQ+HVXB/WxLf39RP+q8LvtJSTcqbxzWEiOd0WR4eiXyKwIUoeWreVd+ngEO6WedZg6P7A+RmrK/0dy9Shmkt+1VeF5nJXSTqgq23ah3y0s= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744801614; c=relaxed/simple; bh=xMMw0+lHw3nq+d7GcY9QATkbTJoMWTg99IeOX7wBRt4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=t3ATvqQWPaxtCChn5LcGcnh/Mtr34Ne+DUsuOY8Ddlq6Md4RkjwE48STnBjDB4wX1EfYWv9GaStRGOsAeTlC+YGhqVCT24ULNXhgyhf4X7iQkPi5xBaQu5Yjo2IYIHZTTgvFY3ZhTI0Dy/z61BfxndI9e1ZwqHctvRtSMHnMVx8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=d8GZTX6C; arc=fail smtp.client-ip=40.107.236.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="d8GZTX6C" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=u7fwmVEKsgnXZF/KMewg6wj7NhXtz7A+JT8ZkHqwNMB+X7wEfX96tQby0y8B/Fo4gFxmt5VjNnmpaObzGlzc3Mej0XnsinRLg9IpunByg0j7crpJOvJq7P9Er3V9wNiYtBMFOWTnOiAzDgn0qQe76A8z4lTvqjGjMPXfjamhVMIUnxnscgmwlNZPdjdnyL2dGzMlVDLR8prBvxaSOg8VgsiNG5gadAse1NvwGf4uRCVuC0FvKDQ2kY7OodVIqMbk+cBRBMOxoSrja7kGdN31MOr0nvV5GKIjtOqKdp3eJVqE0xql/kOGFSmhBsGZ8sLfG+76aSrIXIImS5fdEkfWUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vLWZv6EeCRhZCYQz6kBGQrdAQxVxyRJ6sIwv0WeYZ8w=; b=XWjNKhMKcnwSCJMkwng16X5M65VXgHwnvdvJ+7zfsZmrYcPM4TuDtfGV6MnaJ5UeYjFWEpw/lJhtf/RUqw+/U6ak3JeduvSNf8pqpclIxt3vFW2hHT/PEILjl34ia5/YCfD8kQkjCHvS10I3pmIB4PSNN7PMjnd6BdqXuju6+Ki+kgob4ABrCX1Tv3b8v+s6i4a1truN+2owewcudofW7QVgEXk3wdH/rI0Icxq8JU2zlhMrS8JBqe0WHZUVXBHZplKCHh6ziWyfYQ7myZDP4hYWNCGR8OY7Eg0ug1Cw1kBK3nOZKKcU2oYBYR0P7mV6NTjTDfqCh5aXp7hp8iII7w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vLWZv6EeCRhZCYQz6kBGQrdAQxVxyRJ6sIwv0WeYZ8w=; b=d8GZTX6Cgi66Ys2jLqdEB/ziAFz7OWJmu1WDROfHjaU9LEVLRuZJfxO/KxZmDwz4yOWUojdDr3nB72YRnbI5fPGiSirVXIMhFDGjvDKsf6VFE4BRzfszkGmi3HFdJnqilk6O5wbW4cdaKwBKoNWJ1slpfNEc6IfkwyCiJfU5x9kiPCis0J5msP+unL1PiBOSUkHrqIeBotYD0WW5bXML5JzM4OMPqMIWLMsSnRy9Z/KoANdMbaZ1vIMZlscdp1d1KL9DrKyYjFYfEPU5CsEWJwiMWH+37SIOqoQtIkngNvZ04h6PWIbhRBps739JqaEAvus8JruUI+GsUxGcEPnt5A== Received: from CH2PR15CA0024.namprd15.prod.outlook.com (2603:10b6:610:51::34) by PH8PR12MB6868.namprd12.prod.outlook.com (2603:10b6:510:1cb::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8632.28; Wed, 16 Apr 2025 11:06:47 +0000 Received: from DS2PEPF0000343E.namprd02.prod.outlook.com (2603:10b6:610:51:cafe::92) by CH2PR15CA0024.outlook.office365.com (2603:10b6:610:51::34) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8632.34 via Frontend Transport; Wed, 16 Apr 2025 11:06:46 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DS2PEPF0000343E.mail.protection.outlook.com (10.167.18.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8655.12 via Frontend Transport; Wed, 16 Apr 2025 11:06:46 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 16 Apr 2025 04:06:33 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 16 Apr 2025 04:06:33 -0700 Received: from build-va-bionic-20241022.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Wed, 16 Apr 2025 04:06:29 -0700 From: Vishwaroop A To: , , , , , , , , , CC: Subject: [PATCH v3 4/6] arm64: tegra: Configure QSPI clocks and add DMA Date: Wed, 16 Apr 2025 11:06:04 +0000 Message-ID: <20250416110606.2737315-5-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250416110606.2737315-1-va@nvidia.com> References: <20250416110606.2737315-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343E:EE_|PH8PR12MB6868:EE_ X-MS-Office365-Filtering-Correlation-Id: 513343d6-5241-4628-a755-08dd7cd6c764 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|1800799024|36860700013|82310400026|921020; X-Microsoft-Antispam-Message-Info: 9+TnWaDrMSHjC5GN4PpJ+tYO8V/okMdp1rBnS9l9qdOOxC3Fv6dWxIgMaVRSMkl8Y/n/rJ4ALjD3YGXxEoXaXo6l1QkbscAdo+DkoHlgV/3B0hN7QfsNEuXX/URPIcdXuxjeVoGO2jN9d6Qoyii7R0YsWTHEEY5ZtN4zPkWx4oY58WQaTnxhr1LTJ2DjAOKtd1b3UbzcDenL5t+7/3ASH0dxGJMccT5UeRhJYhBxuWem01YfJBdYsntO5omJ2psZIONl+Nwy7oqbdabxauzA8HQrQlIFR9Nqf4GtSzGjnI+Rkh3JCCGxyCRQQiSHgVIJXpP35BVaMa0d9knvplYTBq5/si8FVowxGHoGzpNxWn4u9DXkL8wyO7vqY56tcfpRofkLcDmI09aXDdNweZNl3JI8gdyZbZG2pVfkjPQGvNGICkHIAzz1uzO/xQZQ4PeEiO6HFxM5fvHuc7y3jn6AWgPzi7oDtGEaxXi1VCFIEc46s5wJPqS/tZU6Ovpf0xS4nFaHHo43WRdjmEPav6ozWN5uj20pq5LMJ4JryOaKTQxc8dNLJZ8LS6vgdClp+6jRQLMhb4/kuNGvQw9qr7uClzH2PRgmqUoKrmbid60Zc4FgVq8XSS5IkNi+v9vSLaYdv4IvxlQZfsqodiU1fwRkdMlwe0XX+fkXsNcGTJf7leJlgCtw4+enYstOKTPGACO3ismO77PkJ9lfKDjmlDUrT61qeOtEjUMyXAxwhdVmscFlSPPh28JnTda4X/NPdp+ktDQKMmhF1jdUsWUPh4GYM5Qz6WkBmVXYJS5Tz1YF4Cp1qg/zEtQTY1+EK0dt9Lkv3mCWJ2Dn7CVikB2lX4BQgekx189TfdwuVW/pCZPOy8d/riKCcW9Y20j6sf3LGFMylut28bQqpyqzxL5k+qzF0pphhXoi8/1a+BITyFzxpluUU0S8R2L5NMNOYaH3P7K7XI3z4Bu0idEuzeMrmuWc4H2UPgS++VWxozJ7wdLQIZs6MMr7kv9vb4cggSauhCGkJg+SHihF+ExjYmdoUCEb3EhPlZLwtXuQyDHYZnfYVrITO2ER7CvB6DSXaO/gFEPkp6/6qrnuGdzJky57/W7wQFcdSXeXXSIwJ6XolXC4C6fqwxkutJxsEqfglWB9xGKzM2oIFxxnYBSZ02wJt4i4P4M+Wri+YcXfjJJjbSQ9fV7vBm+kZ881yZ0zHy3jXq58oBzdjE4OoXU0auQIidodKllrv25vLJRYaNvyXzOMEoCjK9FhzlpOSQBekP2GGcVGPrmvy98GSeXRGja9xiyGbP2gNKk2ibSVdvUVAIkcMAPfDF1IWmI0kR15mlYE0v4JLMG5T5WcFXuDVHaAyJdtbQZFuzgtPl3B37TTIRti1hn/ow+95TGt1QGQHodl118209sMJ1G/rZoItpTNPZhAvVDG3lFaBkUxh09gUZzh6EK+nCqEEZsO0P5+AVwgDEBMSDVHOdLIr+4Nn+1Y9MXhGCXOTApWlLlzVhewGnl7g858fbliNALFT9cKN6cQ2fCVT/1xqpvZ3agSueYc3fJuQQ== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2025 11:06:46.5023 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 513343d6-5241-4628-a755-08dd7cd6c764 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6868 For Tegra234 devices, set QSPI0_2X_PM to 199.99 MHz and QSPI0_PM to 99.99 MHz using PLLC as the parent clock. These frequencies enable Quad IO reads at up to 99.99 MHz, the maximum achievable given PLL and clock divider limitations. Signed-off-by: Vishwaroop A --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 2601b43b2d8c..419dde2bfdf9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -2948,6 +2948,11 @@ <&bpmp TEGRA234_CLK_QSPI0_PM>; clock-names = "qspi", "qspi_out"; resets = <&bpmp TEGRA234_RESET_QSPI0>; + iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>; + assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, + <&bpmp TEGRA234_CLK_QSPI0_PM>; + assigned-clock-rates = <199999999 99999999>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>; status = "disabled"; }; @@ -3031,6 +3036,11 @@ <&bpmp TEGRA234_CLK_QSPI1_PM>; clock-names = "qspi", "qspi_out"; resets = <&bpmp TEGRA234_RESET_QSPI1>; + assigned-clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, + <&bpmp TEGRA234_CLK_QSPI1_PM>; + assigned-clock-rates = <199999999 99999999>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>; + iommus = <&smmu_niso1 TEGRA234_SID_QSPI1>; status = "disabled"; }; From patchwork Wed Apr 16 11:06:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vishwaroop A X-Patchwork-Id: 881808 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2088.outbound.protection.outlook.com [40.107.236.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A49DF23C8CD; Wed, 16 Apr 2025 11:07:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.236.88 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744801625; cv=fail; b=CISikV9pafZtaM4/ie/sx1823FzVbhA1cnjBvCUQdsDMpBN43sgWctQ69sls9V3apdjWl7c2tPQsSe3SZSi/q60ekbcFRkuNaY5IZmlQ9+xrgW7LA1rJdFci/1rfPltwy3SRZRIHY9Cj6+zLR38T94Hw2l23ejXL/zj/XKcZbmc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744801625; c=relaxed/simple; bh=s6aIeev3yjJw5DMoplNGlYFxTjsy2JoMzQuTkI10m38=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qCbipjeg37XeWlh5o1yo0MEd/Dm+2a8mdnS9oC6sKddJWBEavJECDsr9uGUFf/FSuPIvj5BgBFx1nOVakZesM9kFXiR6FGFO/OjXTmifWV/dzdU4sbhFxxot2e2rS7h5wD6R0fG24GsGKVOCT2wL71fWEvf+Ik2ZksBSLYOkV+c= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=FWSfSxZk; arc=fail smtp.client-ip=40.107.236.88 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="FWSfSxZk" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=tfZNt1Tyn+U92iKW4eoOO/+/5ujqTanzPFdC3wK5vl2kA6arFFZdYw+sqKYwpY4hSAJ2kA4kJZS0RcoIEdQPKPdO5M5QUT5Qni0H8wmgZ+27318CRiFArqkQWG7bctLl4OiH1VXk84Fi9+nC4/upv1/mu2Sjxg3XU2Lp/0WKo0WGPAyZGDu7jgDvWQmvFwPZxeNpYnqYJn0isimUGG5Xqryjc+bqkatTZf6yw1bEeRaQFSPjfv6RohgILL6eHaQ5TtaywqUgAfWTFOiOxKEIiRXE1gj8H+S8jjRyuQ54j0sjpUksDhsvtUg788gfTQyXOhxJaTvz0twiCuoXXWfr3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fHsefJNBufNJoCmWmZbqtWSm/Y8kIMX6JMbv36h5hLQ=; b=E12wE5KnH3pLZnBARKVjl+UWYR2BC2NOwpWk/2sRY7Hd7kc6TWPbz9qni1Uqb7OuBJRTNtSUEFWIcVn00PEbmKF2wJz7TmI7q/MsUtmpAHdYakQ81kC2ZIYmfUC5chWshcKUgH76/uelCceG7asrKWK95znUVR0LThBPFvYnpb1Y1Q7ZnRxGlCSnNdaT8+kG7aG/Bt4BT38SbEzMj9qQIbTPzXSoUZW5Xca7UILff6V7G1VqAFWEs+RZBPdsrpUupLJtDvWvQz73Sx688aHNd/+HH6FlCDLxXMwv5zOmtA6AwXZZF3clyGQRoe0mZxCi4nN4YwAsnplT7HmB4iRHqQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fHsefJNBufNJoCmWmZbqtWSm/Y8kIMX6JMbv36h5hLQ=; b=FWSfSxZksVRxp0LY2BPCbHgV5/SAV1H9QlOcaBUhAdh1xLtKpCl98S5W8XyZNMz/pw2UVIr11WLEmdSXFyb7olw+716iGL8hTBJzMJsPR1hPPSECABn7SorUFFCW/igMZJhmBCUS2qSH7/rCUG3BiRrbJcvGb5XubcK0OOkFiPLE2cbiIY+9zAMysdsudzFhw8UAFbzPC422dFRpu526SIB0lhexgypsbZ+X/pIJP7xN35mJGpVX8PRnZJCADahnMLTjPaBMaVbeQ7B0Vw6lUdodIrzKYvwv+U6CW60VdtuAd0pcfJRcK43PwPxtIBXgij+Zu2gVYpSWep3XbzAwow== Received: from DS7PR03CA0037.namprd03.prod.outlook.com (2603:10b6:5:3b5::12) by BL3PR12MB6594.namprd12.prod.outlook.com (2603:10b6:208:38d::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8632.37; Wed, 16 Apr 2025 11:06:57 +0000 Received: from DS2PEPF0000343C.namprd02.prod.outlook.com (2603:10b6:5:3b5:cafe::bf) by DS7PR03CA0037.outlook.office365.com (2603:10b6:5:3b5::12) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8632.32 via Frontend Transport; Wed, 16 Apr 2025 11:06:56 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DS2PEPF0000343C.mail.protection.outlook.com (10.167.18.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8655.12 via Frontend Transport; Wed, 16 Apr 2025 11:06:56 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 16 Apr 2025 04:06:41 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 16 Apr 2025 04:06:41 -0700 Received: from build-va-bionic-20241022.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Wed, 16 Apr 2025 04:06:38 -0700 From: Vishwaroop A To: , , , , , , , , , CC: Subject: [PATCH v3 5/6] spi: tegra210-quad: Update dummy sequence configuration Date: Wed, 16 Apr 2025 11:06:05 +0000 Message-ID: <20250416110606.2737315-6-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250416110606.2737315-1-va@nvidia.com> References: <20250416110606.2737315-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343C:EE_|BL3PR12MB6594:EE_ X-MS-Office365-Filtering-Correlation-Id: ff736bf0-0b59-42f5-85e9-08dd7cd6cd85 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|1800799024|36860700013|921020; X-Microsoft-Antispam-Message-Info: 4azlvpX7Fi1+mgdS30Kjy8L3plBnPICd3WKAaaJ5jijF5S3GpeUhtsvNsnkEG4Wd8OJ+UUFimVeQsODlyRjRv0eKXD6c77x2dnNOHMAewrwGEbjmBBS5tFnpez1C3/scImjjWhoZ0/SKERis5g9EcRV2ZgPV8g770xzFs/IiEYZWEAUWH4YSMJJz6cuY344XlyGTGimw7TTikpInFtMyziZ1nPl0RrUyINBNnZFL5svXd3+gNGKRJ2M8GbejgymiRanse3sUNYnXa6qIOuNY+CGJst+lijpLyrwBJLXIcJrmfTMFojHxY0wp8KCmkufry9dlKd+wqvOc4JUMgUZfMbsCv6+jWuRe8E1fSi2GVLMz5re4H6l6Ec2ou+bqRsjhv+LXBk5DRIGgmAvTSGb+ScEVVGCQPnmeDGw7SjCalbVoLkRv8RB+O+6Hx36pld3WszbcxmNsFEnNQsAIn4eTTwMV4ug8QjKFHz56sf1gkcfbOZQ4EOaTyZz2YX8tUVRrWKilYhZ4JgnKwbTO/ltK72CzFQzRXvyRAwF4FJMhpk9pH2HuXpRQfO709otV88X2CFHoCWbVD1z5ThNGyvxWc4pU/8U/PxYD+QYr5u0dyplmrDVvXPB6JQnMFW6yVE2TA0y4SNwO204kxy+v/wo7Ytr64urJRtzXAlcn27PgyNhOzh93MMk4iVP1hT+3blNeHxsl3sQj4ETp7qmbZfRlptaETTcpJNL0CAMXvWv9sqj1q/lCmagxNt2uu5HW5+CWFFeIgeNcSE4Fw9XjzDwdxfHmrV/8IwDwQz1sjQrBIcyhJncbNgm4tE3CDZPJXzF72I3FbykWmfJGa7XbnmF8Vmg+mwmqOHrcoZVS5BtTHKZhBI13kK0dzXUHIP+zdE3AXMtoi/O+WvfKv12rx2oKZAtDec2fjxHEPapFKeO7/IxwHt2hvnxh3UFuQgyNM1WKTdZVe3bVrC2x6QIQDx+R32FORPBzs0eb1baUYqKpI4/Jhl1GBZSnoyxQ1LmtC+/5yC3JFW2XrBzAkRsRIYltCma/aFBVSarPY4Fy/FF/f2raCAp0r7mWGvk8uW8J6+pEE5IDj7vfRY089jSIAsQX8O6e8zWW1iR4e3jQsMeItAgamo0zlN84/FkGdaodZ3d0rIcl2pE8nvFk3/VbZWgOKqxVcSNn9VcRhW71VXAnak4DhcAsjpfVDlVUj6yzBBw+UwdUVi0U6hQbBIYcBQhlViTBZgUVoNxqWKsazOhz1HdKVqbSGdLDnSt1eU0iCyMGK79AEsVldeCX064+Ty3C9Lptg/M3JPLgIo79ZPW7ceImLkb6TX5YaxKuz3UXUyNU6A4FH89iV+SuREHId/dUJs1NsYBeyQJYMAaxEiqc2oeaaR8YUH34qgQUYymnESUvEYPjrNK5WlAwbxswwp1t51zWCbQNZkTnGPKKuJ9jH3KY7PxEI0IWgUJJwXPNyrlAqn2LN+CkH471WRav9jkVpwaLuvrizim0aElaMWdJkKgHsT+cVXVWxXYjKZGf2/57FV/lJOlgtN3LHaKqswLgpA== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2025 11:06:56.8310 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff736bf0-0b59-42f5-85e9-08dd7cd6cd85 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6594 Adding support for the dummy sequence configuration. The dummy sequence introduces a delay between the command and the data phases of a transfer. This delay, measured in clock cycles, allows the slave device to prepare for data transmission, ensuring data integrity and proper synchronization. Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 159fbbfd4a38..04f41e92c1e2 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -22,6 +22,7 @@ #include #include #include +#include #define QSPI_COMMAND1 0x000 #define QSPI_BIT_LENGTH(x) (((x) & 0x1f) << 0) @@ -156,10 +157,14 @@ #define DATA_DIR_RX BIT(1) #define QSPI_DMA_TIMEOUT (msecs_to_jiffies(1000)) -#define DEFAULT_QSPI_DMA_BUF_LEN (64 * 1024) -#define CMD_TRANSFER 0 -#define ADDR_TRANSFER 1 -#define DATA_TRANSFER 2 +#define DEFAULT_QSPI_DMA_BUF_LEN SZ_64K + +enum tegra_qspi_transfer_type { + CMD_TRANSFER = 0, + ADDR_TRANSFER = 1, + DUMMY_TRANSFER = 2, + DATA_TRANSFER = 3 +}; struct tegra_qspi_soc_data { bool has_dma; @@ -1085,6 +1090,13 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, xfer->len); address_value = *((const u32 *)(xfer->tx_buf)); break; + case DUMMY_TRANSFER: + if (xfer->dummy_data) { + tqspi->dummy_cycles = xfer->len * 8 / xfer->tx_nbits; + break; + } + transfer_phase++; + fallthrough; case DATA_TRANSFER: /* Program Command, Address value in register */ tegra_qspi_writel(tqspi, cmd_value, QSPI_CMB_SEQ_CMD); @@ -1292,7 +1304,9 @@ static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi, list_for_each_entry(xfer, &msg->transfers, transfer_list) { transfer_count++; } - if (!tqspi->soc_data->cmb_xfer_capable || transfer_count != 3) + if (!tqspi->soc_data->cmb_xfer_capable) + return false; + if (transfer_count > 4 || transfer_count < 3) return false; xfer = list_first_entry(&msg->transfers, typeof(*xfer), transfer_list); @@ -1302,6 +1316,13 @@ static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi, if (xfer->len > 4 || xfer->len < 3) return false; xfer = list_next_entry(xfer, transfer_list); + if (transfer_count == 4) { + if (xfer->dummy_data != 1) + return false; + if ((xfer->len * 8 / xfer->tx_nbits) > QSPI_DUMMY_CYCLES_MAX) + return false; + xfer = list_next_entry(xfer, transfer_list); + } if (!tqspi->soc_data->has_dma && xfer->len > (QSPI_FIFO_DEPTH << 2)) return false; From patchwork Wed Apr 16 11:06:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vishwaroop A X-Patchwork-Id: 882234 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2072.outbound.protection.outlook.com [40.107.92.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5628224A05C; Wed, 16 Apr 2025 11:07:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.72 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744801631; cv=fail; b=HFnbYwzsERtjjMqO+xcTOdsWFbMYhxCDM9MRvM9YbWZ0YyEpsqpgZkH8pw31+bNZBY9LSQBYNzAfTzGN9FsEiWSgo2pmH+0Vcqn4/IVVzs2mhEQ1Au9F5CCyzpUyg4m7z1lHiS3FiBiEN0JChkwJvS6Rh72Y8QcNOrk5Jv9H+Qc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744801631; c=relaxed/simple; bh=o7Vq6zLbC2NwgEMD+P52qo8f9b97BbVhX6rfP/WYd6Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Cc+WxZb1fWfKx5CSFjifffg0dRb9aiiMcASqJmLs8u0RgG9h5mwlcftjXFLvHbNINmIaiUXDWh914RWUNoCaBB2cu1QIQH3I188LSXVKfCYfApierUNsqZcXYyAAAxFsjklfd2O4zYhto7+xTgHdf5mULc1SzCfyUmEaUxwpBg8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=gU/hZWVi; arc=fail smtp.client-ip=40.107.92.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="gU/hZWVi" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=QFDEMJZARcxGVL3z+ypW49CShl77/cyFf63GIeKaanZSxcs52vlkdWSzXq5puJof4fxKOkF4UEGpIudcmSu39cvxbNsYADxfxsBX1wUO5sxVpPRQIhK+CAfuk+TggGxHacaPXn1E6jtflb/JsUx3VLvoohUMuFjw9f1TtH8VpI/uPmRuuI6V0hLEUd+h1SYLoKACCXNUQzRJMHd5naQs3dganfx/RXx9jEixNBZyOnX3dx1vaW0s+ei0IeTliRG2/07Vju6w2VtltHwqNjgH/UMnFvJ7bky39+jhVaSxZguDgpECLpXt2Z/ikmkIR2n5yCMj6SVou6FdeejeJJjfPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UNd5dwXqUMH4HQ9YkDC7nVTRvwbJctwqPDTOqeCYkhQ=; b=l16ERRPaOPi3YSRRY2n2uEk4wy1qgGHBDVMYYQ0xfW25W34I3ZT2WCrILr5hRo388oc3h2+YymyqekSh1IoKhcGHRCGQYBaeXl4NYb7/MzeLprozZRZRaNzb4Q9Kni/rNPltiNt+GdC/D7hhTA9HhjTkQMRuwYdNTpVepBBFnqPFr0liwRatb2HLC7TiZ3ntWzuf/xR2xOAhzX+haUZIip/76T/JiPUQtxzqIIuNGPTRGgw0O2c0OE+5xclgadC9i37HJT6nNNII0mxQTwfN2VF7GqChp0iw6jMr57p1lCOS4iceT05R0YXzK7jpw2qSE9uVVkRq7x4BK2hUYmIVYA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UNd5dwXqUMH4HQ9YkDC7nVTRvwbJctwqPDTOqeCYkhQ=; b=gU/hZWViTV0bi3mXcp8EWQXd9q1C0CTe8HUNd0mCBX45SqcAlyNj5MdXSJVdi63DpVjDW8+YnSGjXpuiAad4QqaE4OfoGzN+q8/mDKeX8arllF/vnAUodwU2VAmzaJ6UHebwWp0LLxeBeQPIcABUWapONZw4/O9C8Soq/oBqI9O2fK3NFBN9u9egMKesfpZenPTZ2CxqLbAWl2J6cL1mZIPdMSZ3Ck5qetcO84jv74kNTVlv2FoARzaGg2paZjxIQlul3WlHxuGbPExuTdEy7/1UgRMvNhA33IA1hVwakzyU7CIVl6fxuOV1qVn1s+D2cvZ7Q/oLBLl0DxdzBhHB6A== Received: from DM6PR11CA0047.namprd11.prod.outlook.com (2603:10b6:5:14c::24) by PH7PR12MB7872.namprd12.prod.outlook.com (2603:10b6:510:27c::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8632.32; Wed, 16 Apr 2025 11:07:00 +0000 Received: from DS2PEPF0000343E.namprd02.prod.outlook.com (2603:10b6:5:14c:cafe::14) by DM6PR11CA0047.outlook.office365.com (2603:10b6:5:14c::24) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8655.15 via Frontend Transport; Wed, 16 Apr 2025 11:07:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DS2PEPF0000343E.mail.protection.outlook.com (10.167.18.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8655.12 via Frontend Transport; Wed, 16 Apr 2025 11:07:00 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 16 Apr 2025 04:06:46 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 16 Apr 2025 04:06:46 -0700 Received: from build-va-bionic-20241022.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Wed, 16 Apr 2025 04:06:42 -0700 From: Vishwaroop A To: , , , , , , , , , CC: Subject: [PATCH v3 6/6] spi: tegra210-quad: Add support for internal DMA Date: Wed, 16 Apr 2025 11:06:06 +0000 Message-ID: <20250416110606.2737315-7-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250416110606.2737315-1-va@nvidia.com> References: <20250416110606.2737315-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343E:EE_|PH7PR12MB7872:EE_ X-MS-Office365-Filtering-Correlation-Id: ffe60241-4ab5-4234-1ea7-08dd7cd6cfb8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|82310400026|376014|1800799024|921020; X-Microsoft-Antispam-Message-Info: VB/b42ujL7McbQwR5kEU+6rkBf2KoDH6128Uh/BlOY1fWIUgs45EeIsOw7KIQdbDOlOjt0NBrHSN8rSgBSSA6DyufoV8Bg0S+zsUYPZFU/DwsmANRirFS+WEIW34lUn7XXrnh/ofwNDQtLniuezTWkPgBOfgynjBeV/25dVd/gsyUi1CGOpLxRhaTv0P7ooZlEpaM9vKOW5r73CgJ3B6IUCS+V/q3guoUycVKR9u1bvJnStmMeTPHImTUJ48Lhz555oqyIqVgAokfUImiEJWYPYFZAsIBMBPOECP1v3KLnyM3+PqrSiiuU1FPOw1XUG4PUi/gFbVLgra0KErPC5qg8rL8fJc0Zjh2zARlxkHpPxzRlpVKQHoqXWG3PkOfM8mjQVGOHj0STbm7tDAOs06yT4zIU5AXXxJ+b3v5spfjUTDY0MvOtHZXCwUqBAzSM8aB3GbyqnnQ/XCOgMtoGxlvOtOHzg0P5uNHAUY/ovB6I0VW0MkWzSoSwTfzWkJPOmjVSVIstFaLKNReMJuytmnu3BruymuXN9sxxQqGTU9XKwbP+lBYaRNJlnakzAK3c/nolhkfHfV2/KOOmQbcslml1j1OhCDTAFYuIfXBVaoemw3mmvUYbS3N2ShrgnSAHFFqI4CGqCAxrEHAG3VqC3ATym4SPhJvE3Hn5UKV+IFjyXZ2WFDHDJLeWNKoWN2I6OduZYUeJkjloVMXEq/GedYqGCv9S9cX/oMjwAbl4h4XzOEXItafGFE9ifFCB2p81ANNyNoM9wdutfzPV39tBAM0It9d43uB8tVMOV9PHyetLIO9Gq8ox259UHWYxDPe3jCOa6E4MpvpbBW9hKlHAmIOsMupuc+zWnJa+w0i1jaBjKjjXBp9aYOSio3eMEdzY6Szb27jVK7LWpCQipwrsRtGtV4JEKg+1CEy5WG+Jh7DkMX5BIWaXcsEUNWL+l9lpQZMp6fP27xSiYPeLrAf5sOgtZM4mtCAYtWbVrhoTh0dwS/sRlppXPUL8MuqUssfW3rSmMHh8ojHKBSAQACn6rSNUJKw9oG5KlB3OJBj3cQLcjp5Dp6FZHO56rUNW4berF/eEA8SY+EzigA+gZ2l6iWQsWEM+6PcgKhfCybofHRK2C3qVT6lph1aMuh82b8et7r0/a7qFip+KOfeHt7PSAm6x4V2lEldu67ASQ+CMwXZ0NjjpAoNtvdoQSlTGIKW3ni8cVu/B52XsP3VnaRbD7SdoOF59GJKCVYhownuTUpo/G5lhaByZXS8OZpUGWoG95HTFvbR4nro90Vdo6lnwFVaCLa1ZFsuq2zyxrhokb0EHfU3gdY/gkU4glgpHwyhN6bKRQE2ceEoSZV1IcavxDnhY89O+4Hb/IrQNmE56UcIEsADN2jUfA3n5D3cMuaxoGK3hUSr0qGChFbO20VKM7D3hQbON0ob+lk4FLxWhwWlONtiBlxaMQ5aEUnkg2CpAUglVJfHHsVlAQtP7qaI/Dnr0KN0WQm4RmffvAx6iSV7CgmZ+8x/M8Jd7AGSDlBXPXqH6D6sznWHcbq8xbvayKyPA== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2025 11:07:00.4711 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ffe60241-4ab5-4234-1ea7-08dd7cd6cfb8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7872 Previous generations of Tegra supported DMA operations by an external DMA controller, but the QSPI on Tegra234 devices now have an internal DMA controller. Introduce routines to initialize and configure internal DMA channels for both transmit and receive paths. Set up DMA mapping functions to manage buffer addresses effectively. The variable err is changed to num_errors to more accurately represent its purpose in the code. The updated name clarifies that the variable tracks the number of errors encountered during execution, rather than serving as a generic error flag or code. Tegra241 device supports DMA via an external DMA controller (GPCDMA), so enable this. Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 227 +++++++++++++++++++------------- 1 file changed, 132 insertions(+), 95 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 04f41e92c1e2..e80a0850d07e 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -111,6 +111,9 @@ #define QSPI_DMA_BLK 0x024 #define QSPI_DMA_BLK_SET(x) (((x) & 0xffff) << 0) +#define QSPI_DMA_MEM_ADDRESS 0x028 +#define QSPI_DMA_HI_ADDRESS 0x02c + #define QSPI_TX_FIFO 0x108 #define QSPI_RX_FIFO 0x188 @@ -167,9 +170,9 @@ enum tegra_qspi_transfer_type { }; struct tegra_qspi_soc_data { - bool has_dma; bool cmb_xfer_capable; bool supports_tpm; + bool has_ext_dma; unsigned int cs_count; }; @@ -605,17 +608,21 @@ static void tegra_qspi_dma_unmap_xfer(struct tegra_qspi *tqspi, struct spi_trans len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; - dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); - dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE); + if (t->tx_buf) + dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); + if (t->rx_buf) + dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE); } static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct spi_transfer *t) { struct dma_slave_config dma_sconfig = { 0 }; + dma_addr_t rx_dma_phys, tx_dma_phys; unsigned int len; u8 dma_burst; int ret = 0; u32 val; + bool has_ext_dma = tqspi->soc_data->has_ext_dma; if (tqspi->is_packed) { ret = tegra_qspi_dma_map_xfer(tqspi, t); @@ -634,60 +641,86 @@ static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct len = tqspi->curr_dma_words * 4; /* set attention level based on length of transfer */ - val = 0; - if (len & 0xf) { - val |= QSPI_TX_TRIG_1 | QSPI_RX_TRIG_1; - dma_burst = 1; - } else if (((len) >> 4) & 0x1) { - val |= QSPI_TX_TRIG_4 | QSPI_RX_TRIG_4; - dma_burst = 4; - } else { - val |= QSPI_TX_TRIG_8 | QSPI_RX_TRIG_8; - dma_burst = 8; + if (has_ext_dma) { + val = 0; + if (len & 0xf) { + val |= QSPI_TX_TRIG_1 | QSPI_RX_TRIG_1; + dma_burst = 1; + } else if (((len) >> 4) & 0x1) { + val |= QSPI_TX_TRIG_4 | QSPI_RX_TRIG_4; + dma_burst = 4; + } else { + val |= QSPI_TX_TRIG_8 | QSPI_RX_TRIG_8; + dma_burst = 8; + } + + tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL); } - tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL); tqspi->dma_control_reg = val; dma_sconfig.device_fc = true; - if (tqspi->cur_direction & DATA_DIR_TX) { - dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO; - dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - dma_sconfig.dst_maxburst = dma_burst; - ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig); - if (ret < 0) { - dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); - return ret; - } - tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); - ret = tegra_qspi_start_tx_dma(tqspi, t, len); - if (ret < 0) { - dev_err(tqspi->dev, "failed to starting TX DMA: %d\n", ret); - return ret; + if ((tqspi->cur_direction & DATA_DIR_TX)) { + if (tqspi->tx_dma_chan) { + dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO; + dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + dma_sconfig.dst_maxburst = dma_burst; + ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig); + if (ret < 0) { + dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); + return ret; + } + + tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); + ret = tegra_qspi_start_tx_dma(tqspi, t, len); + if (ret < 0) { + dev_err(tqspi->dev, "failed to starting TX DMA: %d\n", ret); + return ret; + } + } else { + if (tqspi->is_packed) + tx_dma_phys = t->tx_dma; + else + tx_dma_phys = tqspi->tx_dma_phys; + tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); + tegra_qspi_writel(tqspi, lower_32_bits(tx_dma_phys), + QSPI_DMA_MEM_ADDRESS); + tegra_qspi_writel(tqspi, (upper_32_bits(tx_dma_phys) & 0xff), + QSPI_DMA_HI_ADDRESS); } } if (tqspi->cur_direction & DATA_DIR_RX) { - dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO; - dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - dma_sconfig.src_maxburst = dma_burst; - ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig); - if (ret < 0) { - dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); - return ret; - } - - dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, - tqspi->dma_buf_size, - DMA_FROM_DEVICE); + if (tqspi->rx_dma_chan) { + dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO; + dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + dma_sconfig.src_maxburst = dma_burst; + ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig); + if (ret < 0) { + dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); + return ret; + } + dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, + tqspi->dma_buf_size, DMA_FROM_DEVICE); + ret = tegra_qspi_start_rx_dma(tqspi, t, len); + if (ret < 0) { + dev_err(tqspi->dev, "failed to start RX DMA: %d\n", ret); + if (tqspi->cur_direction & DATA_DIR_TX) + dmaengine_terminate_all(tqspi->tx_dma_chan); + return ret; + } - ret = tegra_qspi_start_rx_dma(tqspi, t, len); - if (ret < 0) { - dev_err(tqspi->dev, "failed to start RX DMA: %d\n", ret); - if (tqspi->cur_direction & DATA_DIR_TX) - dmaengine_terminate_all(tqspi->tx_dma_chan); - return ret; + } else { + if (tqspi->is_packed) + rx_dma_phys = t->rx_dma; + else + rx_dma_phys = tqspi->rx_dma_phys; + + tegra_qspi_writel(tqspi, lower_32_bits(rx_dma_phys), + QSPI_DMA_MEM_ADDRESS); + tegra_qspi_writel(tqspi, (upper_32_bits(rx_dma_phys) & 0xff), + QSPI_DMA_HI_ADDRESS); } } @@ -726,9 +759,6 @@ static int tegra_qspi_start_cpu_based_transfer(struct tegra_qspi *qspi, struct s static void tegra_qspi_deinit_dma(struct tegra_qspi *tqspi) { - if (!tqspi->soc_data->has_dma) - return; - if (tqspi->tx_dma_buf) { dma_free_coherent(tqspi->dev, tqspi->dma_buf_size, tqspi->tx_dma_buf, tqspi->tx_dma_phys); @@ -759,16 +789,26 @@ static int tegra_qspi_init_dma(struct tegra_qspi *tqspi) u32 *dma_buf; int err; - if (!tqspi->soc_data->has_dma) - return 0; + if (tqspi->soc_data->has_ext_dma) { + dma_chan = dma_request_chan(tqspi->dev, "rx"); + if (IS_ERR(dma_chan)) { + err = PTR_ERR(dma_chan); + goto err_out; + } - dma_chan = dma_request_chan(tqspi->dev, "rx"); - if (IS_ERR(dma_chan)) { - err = PTR_ERR(dma_chan); - goto err_out; - } + tqspi->rx_dma_chan = dma_chan; - tqspi->rx_dma_chan = dma_chan; + dma_chan = dma_request_chan(tqspi->dev, "tx"); + if (IS_ERR(dma_chan)) { + err = PTR_ERR(dma_chan); + goto err_out; + } + + tqspi->tx_dma_chan = dma_chan; + } else { + tqspi->rx_dma_chan = NULL; + tqspi->tx_dma_chan = NULL; + } dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL); if (!dma_buf) { @@ -779,14 +819,6 @@ static int tegra_qspi_init_dma(struct tegra_qspi *tqspi) tqspi->rx_dma_buf = dma_buf; tqspi->rx_dma_phys = dma_phys; - dma_chan = dma_request_chan(tqspi->dev, "tx"); - if (IS_ERR(dma_chan)) { - err = PTR_ERR(dma_chan); - goto err_out; - } - - tqspi->tx_dma_chan = dma_chan; - dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL); if (!dma_buf) { err = -ENOMEM; @@ -1056,6 +1088,7 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, struct spi_message *msg) { bool is_first_msg = true; + bool has_ext_dma = tqspi->soc_data->has_ext_dma; struct spi_transfer *xfer; struct spi_device *spi = msg->spi; u8 transfer_phase = 0; @@ -1128,15 +1161,14 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, if (WARN_ON(ret == 0)) { dev_err(tqspi->dev, "QSPI Transfer failed with timeout: %d\n", ret); - if (tqspi->is_curr_dma_xfer && - (tqspi->cur_direction & DATA_DIR_TX)) - dmaengine_terminate_all - (tqspi->tx_dma_chan); - - if (tqspi->is_curr_dma_xfer && - (tqspi->cur_direction & DATA_DIR_RX)) - dmaengine_terminate_all - (tqspi->rx_dma_chan); + if (tqspi->is_curr_dma_xfer) { + if ((tqspi->cur_direction & DATA_DIR_TX) && + tqspi->tx_dma_chan) + dmaengine_terminate_all(tqspi->tx_dma_chan); + if ((tqspi->cur_direction & DATA_DIR_RX) && + tqspi->rx_dma_chan) + dmaengine_terminate_all(tqspi->rx_dma_chan); + } /* Abort transfer by resetting pio/dma bit */ if (!tqspi->is_curr_dma_xfer) { @@ -1197,6 +1229,7 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, struct spi_device *spi = msg->spi; struct spi_transfer *transfer; bool is_first_msg = true; + bool has_ext_dma = tqspi->soc_data->has_ext_dma; int ret = 0, val = 0; msg->status = 0; @@ -1251,10 +1284,12 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, QSPI_DMA_TIMEOUT); if (WARN_ON(ret == 0)) { dev_err(tqspi->dev, "transfer timeout\n"); - if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_TX)) - dmaengine_terminate_all(tqspi->tx_dma_chan); - if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_RX)) - dmaengine_terminate_all(tqspi->rx_dma_chan); + if (tqspi->is_curr_dma_xfer) { + if ((tqspi->cur_direction & DATA_DIR_TX) && tqspi->tx_dma_chan) + dmaengine_terminate_all(tqspi->tx_dma_chan); + if ((tqspi->cur_direction & DATA_DIR_RX) && tqspi->rx_dma_chan) + dmaengine_terminate_all(tqspi->rx_dma_chan); + } tegra_qspi_handle_error(tqspi); ret = -EIO; goto complete_xfer; @@ -1323,7 +1358,7 @@ static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi, return false; xfer = list_next_entry(xfer, transfer_list); } - if (!tqspi->soc_data->has_dma && xfer->len > (QSPI_FIFO_DEPTH << 2)) + if (!tqspi->soc_data->has_ext_dma && xfer->len > (QSPI_FIFO_DEPTH << 2)) return false; return true; @@ -1384,41 +1419,43 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi) unsigned int total_fifo_words; unsigned long flags; long wait_status; - int err = 0; + int num_errors = 0; if (tqspi->cur_direction & DATA_DIR_TX) { if (tqspi->tx_status) { - dmaengine_terminate_all(tqspi->tx_dma_chan); - err += 1; - } else { + if (tqspi->tx_dma_chan) + dmaengine_terminate_all(tqspi->tx_dma_chan); + num_errors++; + } else if (tqspi->tx_dma_chan) { wait_status = wait_for_completion_interruptible_timeout( &tqspi->tx_dma_complete, QSPI_DMA_TIMEOUT); if (wait_status <= 0) { dmaengine_terminate_all(tqspi->tx_dma_chan); dev_err(tqspi->dev, "failed TX DMA transfer\n"); - err += 1; + num_errors++; } } } if (tqspi->cur_direction & DATA_DIR_RX) { if (tqspi->rx_status) { - dmaengine_terminate_all(tqspi->rx_dma_chan); - err += 2; - } else { + if (tqspi->rx_dma_chan) + dmaengine_terminate_all(tqspi->rx_dma_chan); + num_errors++; + } else if (tqspi->rx_dma_chan) { wait_status = wait_for_completion_interruptible_timeout( &tqspi->rx_dma_complete, QSPI_DMA_TIMEOUT); if (wait_status <= 0) { dmaengine_terminate_all(tqspi->rx_dma_chan); dev_err(tqspi->dev, "failed RX DMA transfer\n"); - err += 2; + num_errors++; } } } spin_lock_irqsave(&tqspi->lock, flags); - if (err) { + if (num_errors) { tegra_qspi_dma_unmap_xfer(tqspi, t); tegra_qspi_handle_error(tqspi); complete(&tqspi->xfer_completion); @@ -1444,9 +1481,9 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi) /* continue transfer in current message */ total_fifo_words = tegra_qspi_calculate_curr_xfer_param(tqspi, t); if (total_fifo_words > QSPI_FIFO_DEPTH) - err = tegra_qspi_start_dma_based_transfer(tqspi, t); + num_errors = tegra_qspi_start_dma_based_transfer(tqspi, t); else - err = tegra_qspi_start_cpu_based_transfer(tqspi, t); + num_errors = tegra_qspi_start_cpu_based_transfer(tqspi, t); exit: spin_unlock_irqrestore(&tqspi->lock, flags); @@ -1474,28 +1511,28 @@ static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data) } static struct tegra_qspi_soc_data tegra210_qspi_soc_data = { - .has_dma = true, + .has_ext_dma = true, .cmb_xfer_capable = false, .supports_tpm = false, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra186_qspi_soc_data = { - .has_dma = true, + .has_ext_dma = true, .cmb_xfer_capable = true, .supports_tpm = false, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra234_qspi_soc_data = { - .has_dma = false, + .has_ext_dma = false, .cmb_xfer_capable = true, .supports_tpm = true, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra241_qspi_soc_data = { - .has_dma = false, + .has_ext_dma = true, .cmb_xfer_capable = true, .supports_tpm = true, .cs_count = 4,