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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0001709A.mail.protection.outlook.com (10.167.18.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8632.13 via Frontend Transport; Wed, 9 Apr 2025 03:00:31 +0000 Received: from BLRKPRNAYAK.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 8 Apr 2025 22:00:27 -0500 From: K Prateek Nayak To: "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , "Viresh Kumar" , , CC: Dhananjay Ugwekar , Huang Rui , Perry Yuan , Meng Li Subject: [PATCH] cpufreq/amd-pstate: Enable ITMT support after initializing core rankings Date: Wed, 9 Apr 2025 03:00:04 +0000 Message-ID: <20250409030004.23008-1-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709A:EE_|MN0PR12MB5787:EE_ X-MS-Office365-Filtering-Correlation-Id: e5b460d4-03b3-4c00-3234-08dd7712b0ab X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: zw+hizmaEB88RqArBIGUgw+z62fC+XYgm6DCnvywdazSCnYWaRKrSnuXGa7ZX2vX5VTlwOhFq+iY0LHU/Y2r7w5eCN8atOJJ7IRwdADrWw9UsfiUrjxBCdWmGc0+c6pd+wWoALslhraiDt8hJmIyRsG8BIzK0aFKYrXQEhkf+npj9msCPpJvjq1NaH7+1Bylxs/pvAS3CdptVgSuz+3WKjj7yIvRRjs2AT7P2+jYgFWEMYSFOwO9cS4/VTeIT47rfZoIxhDv0h1CznK6gr5h+uswghtiihHnKoLijb0NQPsEwQEwq8B+LohXDQRfgKCLQZRlWZ/QnQr3laTN99syc7o5uveouZEbm+sQ3xhNkjOO/yrHEBpIOyK+XS7v5u5729hscE9uQ+TMevWq74BJWJBPVI5J4OMNHC6P2d5PF6x4bYRXDGXWtAZkCEgO8E+8L6d1EoM9nF44R9xBenpiC+28eIYUVuFqs2BquexoCePPC3BxAIzQrL+Bye3jeaN917kno/UJWSxW5Qwtj/HTz1rIfpKgXW37SAPTn5YfWknIMVclVgkmB0dfyX5aDwgETcU0OINfXb8KKahJ1xBofhW+4W2moXfmTxRmH6KO+M8ebzuxSFK+maHiYnYG/+oDxbjQQNpH6JEIJxBVoyxLbATub3UVY1ElE3qxW0ZcqJGXgnWAFUxDvxouEpITlQnFzqvAH38skt7B5YGj3M4pAkdPQ9TatPy+N4k4cekgfj+9KJep8a4RyZ2i93yea9LuIVgho9qZ1Gb5EYKnHeFqx/ngwHNnn+J6nAp6y6mptPAqGoQFJ/yqzuE70w+WNSV7gWC3iXdqtk08rmFkdVo6eLNn9J2YGODIhbY7pRRcyBzRiR6BGN/CaAV1Z66/1batn2Nz1ERo1EmBjfcBfz/NPOlZdGcfLSKC7/TiwaaY8uyIcL8+pHHfA0DiwVU9R7cafXDZste6X9kK27gvwBGdGcTK0+C7cmVrerSzniDRmOMIM6fz6PCpe3lvOyL48VpZIXkbNa/25Hfgk7cL4SzB5OSV/PKwl098VCuYFICBBcS9lqc/ep46UkLUG1nAD0FeLyOZ/5BUy1YrYB/P6jwshTdp7C2PZ0r1U08L3ommYlJAkFGNH1HhF0RpCPx3BQH1ZlMBOKWtkgnIF+9/OX9e1X9w9H4Wpw7VYzow72HC8VnBTZMBjfWQ1IwKC3C9gcLETBzjgkZls/h0r5UTgIY5IX4iFMp+aQWQefI+wGvZJK2K0Bm7XPeCAole6OtPbO13sA3KdB67WodZy6Q2icM+wne+CkTVqKfQrIxF9nz/FR9iynmv/STGdQcQCmiHIc1K/Cvsb3WGmo4iSOLk1X3cDM0BY1DP4TdX3prG8UjyqjaLI0vLHT+R3HxRHUPDa6jkgD4Pt1F3bBAazYxnrUJBSNdPUKD0YsrZAenTLWpiWMQ4sjb58rRywS9sONKEo8JT7X1HPnA30yp5LLp4+1Cs6xLbbIXbIEwkcKoNga6t0nU= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2025 03:00:31.2667 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e5b460d4-03b3-4c00-3234-08dd7712b0ab X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5787 When working on dynamic asym priority support, it was observed that "asym_prefer_cpu" on AMD systems supporting Preferred Core ranking was always the first CPU in the sched group after boot even though it was not the CPU with the highest asym priority. "asym_prefer_cpu" is cached when the sched domain hierarchy is constructed. On AMD systems that support Preferred Core rankings, sched domains are rebuilt when ITMT support is enabled for the first time from amd_pstate*_cpu_init(). Since amd_pstate*_cpu_init() is called to initialize the cpudata for each CPU, the ITMT support is enabled after the first CPU initializes its asym priority but this is too early since other CPUs have not yet initialized their asym priorities and the sched domain is rebuilt when the ITMT support is toggled on for the first time. Initialize the asym priorities first in amd_pstate*_cpu_init() and then enable ITMT support only after amd_pstate_register_driver() is finished to ensure all CPUs have correctly initialized their asym priorities before sched domain hierarchy is rebuilt and "asym_prefer_cpu" is cached. Remove the delayed work mechanism now that ITMT support is only toggled from the driver init path which is outside the cpuhp critical section. Fixes: f3a052391822 ("cpufreq: amd-pstate: Enable amd-pstate preferred core support") Signed-off-by: K Prateek Nayak --- drivers/cpufreq/amd-pstate.c | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) base-commit: 56a49e19e1aea1374e9ba58cfd40260587bb7355 diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index c54c031939c8..ee638589f5f9 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -794,19 +794,9 @@ static void amd_perf_ctl_reset(unsigned int cpu) wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); } -/* - * Set amd-pstate preferred core enable can't be done directly from cpufreq callbacks - * due to locking, so queue the work for later. - */ -static void amd_pstste_sched_prefcore_workfn(struct work_struct *work) -{ - sched_set_itmt_support(); -} -static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn); - #define CPPC_MAX_PERF U8_MAX -static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) +static void amd_pstate_init_asym_prio(struct amd_cpudata *cpudata) { /* user disabled or not detected */ if (!amd_pstate_prefcore) @@ -814,14 +804,8 @@ static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) cpudata->hw_prefcore = true; - /* - * The priorities can be set regardless of whether or not - * sched_set_itmt_support(true) has been called and it is valid to - * update them at any time after it has been called. - */ + /* The priorities must be initialized before ITMT support can be toggled on. */ sched_set_itmt_core_prio((int)READ_ONCE(cpudata->prefcore_ranking), cpudata->cpu); - - schedule_work(&sched_prefcore_work); } static void amd_pstate_update_limits(unsigned int cpu) @@ -974,7 +958,7 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) if (ret) goto free_cpudata1; - amd_pstate_init_prefcore(cpudata); + amd_pstate_init_asym_prio(cpudata); ret = amd_pstate_init_freq(cpudata); if (ret) @@ -1450,7 +1434,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) if (ret) goto free_cpudata1; - amd_pstate_init_prefcore(cpudata); + amd_pstate_init_asym_prio(cpudata); ret = amd_pstate_init_freq(cpudata); if (ret) @@ -1780,6 +1764,10 @@ static int __init amd_pstate_init(void) } } + /* Enable ITMT support once all CPUs have initialized their asym priorities. */ + if (amd_pstate_prefcore) + sched_set_itmt_support(); + return ret; global_attr_free: