From patchwork Thu Apr 10 06:49:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jai Luthra X-Patchwork-Id: 880748 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E14D11D5143; Thu, 10 Apr 2025 06:49:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744267790; cv=none; b=fjAeiPlHnjFJWJ/Gff0rJZWnc7ewCEMJz2wdi9RfAHPMbFTGCKzuaOMNCIOz/2MEfbj4p3O9ydWFFrX8Hg41gAcF0U7Q1l9kGIkgDW9/vZkZiuKNOTjPpTnxm+7wpCVzHPfNhfeuKbfC9JYXFryYkcAKYG2z74E8UDn+mzlNrDk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744267790; c=relaxed/simple; bh=Qmh6mblMPaKUFpH+6loOYkLwSxCVt2hNWZhCNqv1ojs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k2n3kMr7G/SoTR6zcEClWTWvHyNkZz298xudjuKltP2uz3cJIKVaZ4iCWB2IbX7LqYpILSz6EUE8PvYc62gnIbwK/GlhH7U1wyTdbrrtFsRKF14VIhGcRCoCvBTjbjJKvi9tpp2osWBlrfdnaVcYPFakeP+2VjrtRW9pAWeyBH4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=LoXQ87V2; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="LoXQ87V2" Received: from mail.ideasonboard.com (unknown [IPv6:2401:4900:1c68:389d:1fcb:c0f8:ff7c:208d]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id C7BAAEE4; Thu, 10 Apr 2025 08:47:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1744267669; bh=Qmh6mblMPaKUFpH+6loOYkLwSxCVt2hNWZhCNqv1ojs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LoXQ87V26TjCoAP0Zyg77KBuyawJ8fJwnF5+wK8U+Vl1gW4soNZ8nlhEiP+WTtFO3 ZvPJMQbbdztAo/LqyshtKSK6c+zKqMKbmdGKaQOLSyKtiUJEU44maC5BLjjMdYrqPN WuyMpQ85PMcR2Xa+9H4X/iERBUG7DS6rC/S0jKCU= From: Jai Luthra Date: Thu, 10 Apr 2025 12:19:00 +0530 Subject: [PATCH v2 2/6] media: ti: j721e-csi2rx: Use fwnode_get_named_child_node Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-probe_fixes-v2-2-801bc6eebdea@ideasonboard.com> References: <20250410-probe_fixes-v2-0-801bc6eebdea@ideasonboard.com> In-Reply-To: <20250410-probe_fixes-v2-0-801bc6eebdea@ideasonboard.com> To: Mauro Carvalho Chehab , Hans Verkuil , Tomi Valkeinen , Sakari Ailus , Maxime Ripard Cc: Devarsh Thakkar , Rishikesh Donadkar , Vaishnav Achath , Changhuang Liang , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Jai Luthra X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1925; i=jai.luthra@ideasonboard.com; h=from:subject:message-id; bh=Qmh6mblMPaKUFpH+6loOYkLwSxCVt2hNWZhCNqv1ojs=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBn92n3JSzLrDTKSmTlsu6K4vn3vcSvKyj09Eu0J t4u78alPSCJAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZ/dp9wAKCRBD3pH5JJpx Ra1oEACNhrTaNHHA+VsNdppXcFqScfJbsz42AWsmSrzbRjWd5O+YdtFgPaAh7jx6M6yeGCr1RUT W9WS16fDXPIGDU9RFu1dunif9A48hSBHozMCVjmeJXbROdTDvQLHneohNTmy7QQQxM7gTBkfeah 9Jy3DfaTFruKX1Fvn/hR0zg9MdUUv+F0i+0r8Z69FS3BbI4R5aHFJ8ZcOPUQIcI7DdmqGv5XO4f V3msA22ZN2AWkPPpTBAmt56udLJMOi2J0OFQm9cZTZFbnjmsY7x9fe1xm82z9lTWYeq/9iuXnJu gzrqsra2bhRU405mwxjaK9N+fL8PEs4sPOfugHx4nuIawlCgIIxt9HnzT73YBPc7XEXAsXJXlT6 N4YuEyfyLoYaz2SZXE5QUZBIJwQh5oiYQQtQV/BK3b5hjVeU7orpbcVb5Dkkoq+Qx6sJbCFT2fi r6kqnuTD2A1mBNBShDWHWs9II4Vy/aLqvA5EJZ4aU61PAcNQGRJ6ZWXI5hB+hu8/ORcYzv31e2U oBVWlqhNxvyCG6Yd6jS3lW59pprqqM/BVyfO/WWJA2G9ztHKmNOGJv/Ltx4e6wJj7H4rwt80iVQ 5/5CrpDAlqpNVKk6KlJNtTIUEZ5aO+5PNfQbgT0OXbIRYQpvOJtKFcgxxor9y+a314VEou4zjG/ pY6G0apCLfAe1Hg== X-Developer-Key: i=jai.luthra@ideasonboard.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 Simplify notifier registration logic. Instead of first getting the device node, get the fwnode of the child directly. Reviewed-by: Devarsh Thakkar Signed-off-by: Jai Luthra --- drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index a066024bf745450e2ba01d06c0fec4e6bdbfa97e..6d406925e092660cb67c04cc2a7e1e10c14e295e 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -450,25 +451,23 @@ static int ti_csi2rx_notifier_register(struct ti_csi2rx_dev *csi) { struct fwnode_handle *fwnode; struct v4l2_async_connection *asc; - struct device_node *node; int ret; - node = of_get_child_by_name(csi->dev->of_node, "csi-bridge"); - if (!node) + fwnode = fwnode_get_named_child_node(csi->dev->fwnode, "csi-bridge"); + if (!fwnode) return -EINVAL; - fwnode = of_fwnode_handle(node); - if (!fwnode) { - of_node_put(node); - return -EINVAL; - } - v4l2_async_nf_init(&csi->notifier, &csi->v4l2_dev); csi->notifier.ops = &csi_async_notifier_ops; asc = v4l2_async_nf_add_fwnode(&csi->notifier, fwnode, struct v4l2_async_connection); - of_node_put(node); + /* + * Calling v4l2_async_nf_add_fwnode grabs a refcount, + * so drop the one we got in fwnode_get_named_child_node + */ + fwnode_handle_put(fwnode); + if (IS_ERR(asc)) { v4l2_async_nf_cleanup(&csi->notifier); return PTR_ERR(asc); From patchwork Thu Apr 10 06:49:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jai Luthra X-Patchwork-Id: 880747 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05A45204C17; Thu, 10 Apr 2025 06:49:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="MLjz7XME" Received: from mail.ideasonboard.com (unknown [IPv6:2401:4900:1c68:389d:1fcb:c0f8:ff7c:208d]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id DCE24EE4; Thu, 10 Apr 2025 08:47:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1744267674; bh=4MJSk39sy9UrQBNk5KWmQcjTHvyHa4DM84YIW+K0a9w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MLjz7XMEEMsQ43axbfJu8EMOKH8a82VRBNtsvieoLwx5oyvUuli3mZSNOgd/MDWdo IE9kCLfOdsPFauS93FzE58KEQIxtPZtt2h1zY/w5cuGA9uklxhERuo3lB6aiMnJgag qK2BlzBiVV/ojrV/uNKZJR+Feug8KN5nrP2f/Dn8= From: Jai Luthra Date: Thu, 10 Apr 2025 12:19:01 +0530 Subject: [PATCH v2 3/6] media: ti: j721e-csi2rx: Fix source subdev link creation Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-probe_fixes-v2-3-801bc6eebdea@ideasonboard.com> References: <20250410-probe_fixes-v2-0-801bc6eebdea@ideasonboard.com> In-Reply-To: <20250410-probe_fixes-v2-0-801bc6eebdea@ideasonboard.com> To: Mauro Carvalho Chehab , Hans Verkuil , Tomi Valkeinen , Sakari Ailus , Maxime Ripard Cc: Devarsh Thakkar , Rishikesh Donadkar , Vaishnav Achath , Changhuang Liang , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Jai Luthra , stable@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 We don't use OF ports and remote-endpoints to connect the CSI2RX bridge and this device in the device tree, thus it is wrong to use v4l2_create_fwnode_links_to_pad() to create the media graph link between the two. It works out on accident, as neither the source nor the sink implement the .get_fwnode_pad() callback, and the framework helper falls back on using the first source and sink pads to create the link between them. Instead, manually create the media link from the first source pad of the bridge to the first sink pad of the J721E CSI2RX. Fixes: b4a3d877dc92 ("media: ti: Add CSI2RX support for J721E") Cc: stable@vger.kernel.org Reviewed-by: Devarsh Thakkar Signed-off-by: Jai Luthra --- drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index 6d406925e092660cb67c04cc2a7e1e10c14e295e..ad51d033b6725426550578bdac1bae8443458f13 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -53,6 +53,8 @@ #define DRAIN_TIMEOUT_MS 50 #define DRAIN_BUFFER_SIZE SZ_32K +#define CSI2RX_BRIDGE_SOURCE_PAD 1 + struct ti_csi2rx_fmt { u32 fourcc; /* Four character code. */ u32 code; /* Mbus code. */ @@ -427,8 +429,9 @@ static int csi_async_notifier_complete(struct v4l2_async_notifier *notifier) if (ret) return ret; - ret = v4l2_create_fwnode_links_to_pad(csi->source, &csi->pad, - MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED); 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Thu, 10 Apr 2025 08:48:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1744267684; bh=nCnnDofJha84+eIcewsfKIHBiGBGP2QkbQJkJ/ggr40=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=FHx1PcZ8RbQPBY0GRpLaWEWv3Fb4kOn706WM7rrO8oDI57yGIkQXOoAT7HDQ54tLs P2uATbIKOA0f0ccLrxApsefaKFvZa5RoS+4/mC4i3zVVDx84kwbsQ0so8h24e1tocH RNLBKlYY2dHgUh5gtC9Y2TZBCVwV3rCSpzcr4HYA= From: Jai Luthra Date: Thu, 10 Apr 2025 12:19:03 +0530 Subject: [PATCH v2 5/6] media: cadence: cdns-csi2rx: Support multiple pixels per clock cycle Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-probe_fixes-v2-5-801bc6eebdea@ideasonboard.com> References: <20250410-probe_fixes-v2-0-801bc6eebdea@ideasonboard.com> In-Reply-To: <20250410-probe_fixes-v2-0-801bc6eebdea@ideasonboard.com> To: Mauro Carvalho Chehab , Hans Verkuil , Tomi Valkeinen , Sakari Ailus , Maxime Ripard Cc: Devarsh Thakkar , Rishikesh Donadkar , Vaishnav Achath , Changhuang Liang , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Jai Luthra X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 The output pixel interface is a parallel bus (32 bits), which supports sending multiple pixels (1, 2 or 4) per clock cycle for smaller pixel widths like RAW8-RAW16. Dual-pixel and Quad-pixel modes can be a requirement if the export rate of the Cadence IP in Single-pixel mode maxes out before the maximum supported DPHY-RX frequency, which is the case with TI's integration of this IP [1]. So, we export a function that lets the downstream hardware block request a higher pixel-per-clock on a particular output pad. We check if we can support the requested pixels per clock given the known maximum for the currently configured format. If not, we set it to the highest feasible value and return this value to the caller. [1] Section 12.6.1.4.8.14 CSI_RX_IF Programming Restrictions of AM62 TRM Link: https://www.ti.com/lit/pdf/spruj16 Signed-off-by: Jai Luthra --- drivers/media/platform/cadence/cdns-csi2rx.c | 75 +++++++++++++++++++++------- drivers/media/platform/cadence/cdns-csi2rx.h | 19 +++++++ 2 files changed, 76 insertions(+), 18 deletions(-) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index 608298c72462031515d9ad01c6b267bf7375a5bf..154eaacc39ad294db0524e88be888bd0929af071 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -5,6 +5,7 @@ * Copyright (C) 2017 Cadence Design Systems Inc. */ +#include #include #include #include @@ -22,6 +23,8 @@ #include #include +#include "cdns-csi2rx.h" + #define CSI2RX_DEVICE_CFG_REG 0x000 #define CSI2RX_SOFT_RESET_REG 0x004 @@ -53,6 +56,8 @@ #define CSI2RX_STREAM_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x00c) #define CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF (1 << 8) +#define CSI2RX_STREAM_CFG_NUM_PIXELS_MASK GENMASK(5, 4) +#define CSI2RX_STREAM_CFG_NUM_PIXELS(n) ((n) >> 1) #define CSI2RX_LANES_MAX 4 #define CSI2RX_STREAMS_MAX 4 @@ -68,7 +73,10 @@ enum csi2rx_pads { struct csi2rx_fmt { u32 code; + /* width of a single pixel on CSI-2 bus */ u8 bpp; + /* max pixels per clock supported on output bus */ + u8 max_pixels; }; struct csi2rx_priv { @@ -90,6 +98,7 @@ struct csi2rx_priv { struct reset_control *pixel_rst[CSI2RX_STREAMS_MAX]; struct phy *dphy; + u8 num_pixels[CSI2RX_STREAMS_MAX]; u8 lanes[CSI2RX_LANES_MAX]; u8 num_lanes; u8 max_lanes; @@ -106,22 +115,22 @@ struct csi2rx_priv { }; static const struct csi2rx_fmt formats[] = { - { .code = MEDIA_BUS_FMT_YUYV8_1X16, .bpp = 16, }, - { .code = MEDIA_BUS_FMT_UYVY8_1X16, .bpp = 16, }, - { .code = MEDIA_BUS_FMT_YVYU8_1X16, .bpp = 16, }, - { .code = MEDIA_BUS_FMT_VYUY8_1X16, .bpp = 16, }, - { .code = MEDIA_BUS_FMT_SBGGR8_1X8, .bpp = 8, }, - { .code = MEDIA_BUS_FMT_SGBRG8_1X8, .bpp = 8, }, - { .code = MEDIA_BUS_FMT_SGRBG8_1X8, .bpp = 8, }, - { .code = MEDIA_BUS_FMT_SRGGB8_1X8, .bpp = 8, }, - { .code = MEDIA_BUS_FMT_Y8_1X8, .bpp = 8, }, - { .code = MEDIA_BUS_FMT_SBGGR10_1X10, .bpp = 10, }, - { .code = MEDIA_BUS_FMT_SGBRG10_1X10, .bpp = 10, }, - { .code = MEDIA_BUS_FMT_SGRBG10_1X10, .bpp = 10, }, - { .code = MEDIA_BUS_FMT_SRGGB10_1X10, .bpp = 10, }, - { .code = MEDIA_BUS_FMT_RGB565_1X16, .bpp = 16, }, - { .code = MEDIA_BUS_FMT_RGB888_1X24, .bpp = 24, }, - { .code = MEDIA_BUS_FMT_BGR888_1X24, .bpp = 24, }, + { .code = MEDIA_BUS_FMT_YUYV8_1X16, .bpp = 16, .max_pixels = 2, }, + { .code = MEDIA_BUS_FMT_UYVY8_1X16, .bpp = 16, .max_pixels = 2, }, + { .code = MEDIA_BUS_FMT_YVYU8_1X16, .bpp = 16, .max_pixels = 2, }, + { .code = MEDIA_BUS_FMT_VYUY8_1X16, .bpp = 16, .max_pixels = 2, }, + { .code = MEDIA_BUS_FMT_SBGGR8_1X8, .bpp = 8, .max_pixels = 4, }, + { .code = MEDIA_BUS_FMT_SGBRG8_1X8, .bpp = 8, .max_pixels = 4, }, + { .code = MEDIA_BUS_FMT_SGRBG8_1X8, .bpp = 8, .max_pixels = 4, }, + { .code = MEDIA_BUS_FMT_SRGGB8_1X8, .bpp = 8, .max_pixels = 4, }, + { .code = MEDIA_BUS_FMT_Y8_1X8, .bpp = 8, .max_pixels = 4, }, + { .code = MEDIA_BUS_FMT_SBGGR10_1X10, .bpp = 10, .max_pixels = 2, }, + { .code = MEDIA_BUS_FMT_SGBRG10_1X10, .bpp = 10, .max_pixels = 2, }, + { .code = MEDIA_BUS_FMT_SGRBG10_1X10, .bpp = 10, .max_pixels = 2, }, + { .code = MEDIA_BUS_FMT_SRGGB10_1X10, .bpp = 10, .max_pixels = 2, }, + { .code = MEDIA_BUS_FMT_RGB565_1X16, .bpp = 16, .max_pixels = 1, }, + { .code = MEDIA_BUS_FMT_RGB888_1X24, .bpp = 24, .max_pixels = 1, }, + { .code = MEDIA_BUS_FMT_BGR888_1X24, .bpp = 24, .max_pixels = 1, }, }; static const struct csi2rx_fmt *csi2rx_get_fmt_by_code(u32 code) @@ -276,8 +285,10 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) reset_control_deassert(csi2rx->pixel_rst[i]); - writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF, - csi2rx->base + CSI2RX_STREAM_CFG_REG(i)); + reg = CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF; + reg |= FIELD_PREP(CSI2RX_STREAM_CFG_NUM_PIXELS_MASK, + csi2rx->num_pixels[i]); + writel(reg, csi2rx->base + CSI2RX_STREAM_CFG_REG(i)); /* * Enable one virtual channel. When multiple virtual channels @@ -458,6 +469,34 @@ static int csi2rx_init_state(struct v4l2_subdev *subdev, return csi2rx_set_fmt(subdev, state, &format); } +int cdns_csi2rx_negotiate_ppc(struct v4l2_subdev *subdev, unsigned int pad, + u8 *ppc) +{ + struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(subdev); + const struct csi2rx_fmt *csi_fmt; + struct v4l2_subdev_state *state; + struct v4l2_mbus_framefmt *fmt; + int ret = 0; + + if (!ppc || pad < CSI2RX_PAD_SOURCE_STREAM0 || pad >= CSI2RX_PAD_MAX) + return -EINVAL; + + state = v4l2_subdev_lock_and_get_active_state(subdev); + fmt = v4l2_subdev_state_get_format(state, pad); + csi_fmt = csi2rx_get_fmt_by_code(fmt->code); + + /* Reduce requested PPC if it is too high */ + *ppc = min(*ppc, csi_fmt->max_pixels); + + v4l2_subdev_unlock_state(state); + + csi2rx->num_pixels[pad - CSI2RX_PAD_SOURCE_STREAM0] = + CSI2RX_STREAM_CFG_NUM_PIXELS(*ppc); + + return ret; +} +EXPORT_SYMBOL(cdns_csi2rx_negotiate_ppc); + static const struct v4l2_subdev_pad_ops csi2rx_pad_ops = { .enum_mbus_code = csi2rx_enum_mbus_code, .get_fmt = v4l2_subdev_get_fmt, diff --git a/drivers/media/platform/cadence/cdns-csi2rx.h b/drivers/media/platform/cadence/cdns-csi2rx.h new file mode 100644 index 0000000000000000000000000000000000000000..128d47e8513c99c083f49e249e876be6d19389f6 --- /dev/null +++ b/drivers/media/platform/cadence/cdns-csi2rx.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef CDNS_CSI2RX_H +#define CDNS_CSI2RX_H + +#include + +/** + * cdns_csi2rx_negotiate_ppc - Negotiate pixel-per-clock on output interface + * + * @subdev: point to &struct v4l2_subdev + * @pad: pad number of the source pad + * @ppc: pointer to requested pixel-per-clock value + * + * Returns 0 on success, negative error code otherwise. + */ +int cdns_csi2rx_negotiate_ppc(struct v4l2_subdev *subdev, unsigned int pad, + u8 *ppc); + +#endif