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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Piotr Oniszczuk Subject: [PATCH 1/6] thermal/drivers/sun8i: add gpadc clock Date: Fri, 11 Apr 2025 08:38:21 +0800 Message-ID: <20250411003827.782544-2-iuncuim@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250411003827.782544-1-iuncuim@gmail.com> References: <20250411003827.782544-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mikhail Kalashnikov Some processors (e.g. Allwinner A523) require GPADC clocking activation for temperature sensors to work. So let's add support for enabling it. Signed-off-by: Mikhail Kalashnikov --- drivers/thermal/sun8i_thermal.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c index 226747906..1f3908a60 100644 --- a/drivers/thermal/sun8i_thermal.c +++ b/drivers/thermal/sun8i_thermal.c @@ -66,8 +66,9 @@ struct tsensor { }; struct ths_thermal_chip { - bool has_mod_clk; - bool has_bus_clk_reset; + bool has_gpadc_clk; + bool has_mod_clk; + bool has_bus_clk_reset; bool needs_sram; int sensor_num; int offset; @@ -89,7 +90,8 @@ struct ths_device { struct regmap_field *sram_regmap_field; struct reset_control *reset; struct clk *bus_clk; - struct clk *mod_clk; + struct clk *mod_clk; + struct clk *gpadc_clk; struct tsensor sensor[MAX_SENSOR_NUM]; }; @@ -417,6 +419,16 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev) if (ret) return ret; + if (tmdev->chip->has_gpadc_clk) { + tmdev->gpadc_clk = devm_clk_get_enabled(&pdev->dev, "gpadc"); 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Thu, 10 Apr 2025 17:39:44 -0700 (PDT) Received: from localhost.localdomain ([176.106.241.81]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464ea5c6sm6344251fa.62.2025.04.10.17.39.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Apr 2025 17:39:44 -0700 (PDT) From: iuncuim To: Vasily Khoruzhick , Yangtao Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Piotr Oniszczuk Subject: [PATCH 2/6] thermal/drivers/sun8i: replace devm_reset_control_get to shared Date: Fri, 11 Apr 2025 08:38:22 +0800 Message-ID: <20250411003827.782544-3-iuncuim@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250411003827.782544-1-iuncuim@gmail.com> References: <20250411003827.782544-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mikhail Kalashnikov The A523 processor has two temperature controllers, but they share a common reset line. We need to use devm_reset_control_get_shared() instead of devm_reset_control_get() Signed-off-by: Mikhail Kalashnikov --- drivers/thermal/sun8i_thermal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c index 1f3908a60..dc4055c9c 100644 --- a/drivers/thermal/sun8i_thermal.c +++ b/drivers/thermal/sun8i_thermal.c @@ -391,7 +391,7 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev) return PTR_ERR(tmdev->regmap); if (tmdev->chip->has_bus_clk_reset) { - tmdev->reset = devm_reset_control_get(dev, NULL); + tmdev->reset = devm_reset_control_get_shared(dev, NULL); if (IS_ERR(tmdev->reset)) return PTR_ERR(tmdev->reset); From patchwork Fri Apr 11 00:38:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikhail Kalashnikov X-Patchwork-Id: 880814 Received: from mail-lj1-f172.google.com (mail-lj1-f172.google.com [209.85.208.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B84C17C68; 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Thu, 10 Apr 2025 17:40:03 -0700 (PDT) Received: from localhost.localdomain ([176.106.241.81]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464ea5c6sm6344251fa.62.2025.04.10.17.39.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Apr 2025 17:40:03 -0700 (PDT) From: iuncuim To: Vasily Khoruzhick , Yangtao Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Piotr Oniszczuk Subject: [PATCH 3/6] thermal/drivers/sun8i: Add support for A523 THS0/1 controllers Date: Fri, 11 Apr 2025 08:38:23 +0800 Message-ID: <20250411003827.782544-4-iuncuim@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250411003827.782544-1-iuncuim@gmail.com> References: <20250411003827.782544-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mikhail Kalashnikov The A523 processor has two temperature controllers, THS0 and THS1. THS0 has only one temperature sensor, which is located in the DRAM. THS1 does have 3 sensors: ths1_0 - "big" cores ths1_1 - "little" cores ths1_2 - gpu The datasheet mentions a fourth sensor in the NPU, but lacks any registers for operation other than calibration registers. The vendor code reads the value from ths1_2, but uses separate calibration data, so we get two different values from real one. Signed-off-by: Mikhail Kalashnikov --- drivers/thermal/sun8i_thermal.c | 134 ++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c index dc4055c9c..919b05a96 100644 --- a/drivers/thermal/sun8i_thermal.c +++ b/drivers/thermal/sun8i_thermal.c @@ -116,6 +116,15 @@ static int sun50i_h5_calc_temp(struct ths_device *tmdev, return -1590 * reg / 10 + 276000; } +static int sun55i_a523_calc_temp(struct ths_device *tmdev, + int id, int reg) +{ + if (reg >= 0x7c8) + return tmdev->chip->scale * (tmdev->chip->offset - reg); + else + return 65 * (2825 - reg); +} + static int sun8i_ths_get_temp(struct thermal_zone_device *tz, int *temp) { struct tsensor *s = thermal_zone_device_priv(tz); @@ -208,6 +217,100 @@ static irqreturn_t sun8i_irq_thread(int irq, void *data) return IRQ_HANDLED; } + +/* + * The A523 nvmem calibration values. The ths1_3 is not used as it + * doesn't have its own sensor and doesn't have any internal switch. + * Instead, the value from the ths1_2 sensor is used, which gives the + * illusion of an independent sensor for NPU and GPU when using + * different calibration values. + * + * efuse layout 0x38-0x3F (caldata[0..3]): + * caldata[0] caldata[1] caldata[2] caldata[3] + * 0 16 24 32 36 48 60 64 + * +---------------+---------------+---------------+---------------+ + * | | | temp | ths1_0 | ths1_1 | + + * +---------------+---------------+---------------+---------------+ + * + * efuse layout 0x40-0x43 (caldata[4..5]) - not in use + * + * efuse layout 0x44-0x4B (caldata[6..9]): + * caldata[6] caldata[7] caldata[8] caldata[9] + * 0 12 16 24 32 36 48 64 + * +---------------+---------------+---------------+---------------+ + * | ths1_2 | ths1_3 | ths0_0 | | + + * +---------------+---------------+---------------+---------------+ + */ +static int sun55i_a523_ths_calibrate(struct ths_device *tmdev, + u16 *caldata, int callen) +{ + struct device *dev = tmdev->dev; + int i, ft_temp; + + if (!caldata[0]) + return -EINVAL; + + ft_temp = (((caldata[2] << 8) | (caldata[1] >> 8)) & FT_TEMP_MASK) * 100; + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + int sensor_reg, sensor_temp, cdata, offset; + /* + * Chips ths0 and ths1 have common parameters for value + * calibration. To separate them we can use the number of + * temperature sensors on each chip. + * For ths0 this value is 1. + */ + if (tmdev->chip->sensor_num == 1) { + sensor_reg = ((caldata[7] >> 8) | (caldata[8] << 8)) & TEMP_CALIB_MASK; + } else { + switch (i) { + case 0: + sensor_reg = (caldata[2] >> 4) & TEMP_CALIB_MASK; + break; + case 1: + sensor_reg = caldata[3] & TEMP_CALIB_MASK; + break; + case 2: + sensor_reg = caldata[6] & TEMP_CALIB_MASK; + break; + default: + sensor_reg = 0; + break; + } + } + + sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg); + + /* + * Calibration data is CALIBRATE_DEFAULT - (calculated + * temperature from sensor reading at factory temperature + * minus actual factory temperature) * X (scale from + * temperature to register values) + */ + cdata = CALIBRATE_DEFAULT - + ((sensor_temp - ft_temp) / tmdev->chip->scale); + + if (cdata & ~TEMP_CALIB_MASK) { + /* + * Calibration value more than 12-bit, but calibration + * register is 12-bit. In this case, ths hardware can + * still work without calibration, although the data + * won't be so accurate. + */ + dev_warn(dev, "sensor%d is not calibrated.\n", i); + continue; + } + + offset = (i % 2) * 16; + regmap_update_bits(tmdev->regmap, + SUN50I_H6_THS_TEMP_CALIB + (i / 2 * 4), + TEMP_CALIB_MASK << offset, + cdata << offset); + } + + return 0; +} + static int sun8i_h3_ths_calibrate(struct ths_device *tmdev, u16 *caldata, int callen) { @@ -721,6 +824,35 @@ static const struct ths_thermal_chip sun50i_h616_ths = { .calc_temp = sun8i_ths_calc_temp, }; +/* The A523 has a shared reset line for both chips */ +static const struct ths_thermal_chip sun55i_a523_ths0 = { + .sensor_num = 1, + .has_bus_clk_reset = true, + .has_gpadc_clk = true, + .ft_deviation = 5000, + .offset = 2736, + .scale = 74, + .temp_data_base = SUN50I_H6_THS_TEMP_DATA, + .calibrate = sun55i_a523_ths_calibrate, + .init = sun50i_h6_thermal_init, + .irq_ack = sun50i_h6_irq_ack, + .calc_temp = sun55i_a523_calc_temp, +}; + +static const struct ths_thermal_chip sun55i_a523_ths1 = { + .sensor_num = 3, + .has_bus_clk_reset = true, + .has_gpadc_clk = true, + .ft_deviation = 5000, + .offset = 2736, + .scale = 74, + .temp_data_base = SUN50I_H6_THS_TEMP_DATA, + .calibrate = sun55i_a523_ths_calibrate, + .init = sun50i_h6_thermal_init, + .irq_ack = sun50i_h6_irq_ack, + .calc_temp = sun55i_a523_calc_temp, +}; + static const struct of_device_id of_ths_match[] = { { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths }, { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths }, @@ -731,6 +863,8 @@ static const struct of_device_id of_ths_match[] = { { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths }, { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths }, { .compatible = "allwinner,sun50i-h616-ths", .data = &sun50i_h616_ths }, + { .compatible = "allwinner,sun55i-a523-ths0", .data = &sun55i_a523_ths0 }, + { .compatible = "allwinner,sun55i-a523-ths1", .data = &sun55i_a523_ths1 }, { /* sentinel */ }, }; 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Thu, 10 Apr 2025 17:40:23 -0700 (PDT) Received: from localhost.localdomain ([176.106.241.81]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464ea5c6sm6344251fa.62.2025.04.10.17.40.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Apr 2025 17:40:22 -0700 (PDT) From: iuncuim To: Vasily Khoruzhick , Yangtao Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Piotr Oniszczuk Subject: [PATCH 4/6] arm64: dts: allwinner: A523: Add SID controller node Date: Fri, 11 Apr 2025 08:38:24 +0800 Message-ID: <20250411003827.782544-5-iuncuim@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250411003827.782544-1-iuncuim@gmail.com> References: <20250411003827.782544-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mikhail Kalashnikov The SID controller should be compatible with A64 and others SoC with 0x200 offset. Signed-off-by: Mikhail Kalashnikov --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index ee485899b..d626612bb 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -171,6 +171,13 @@ ccu: clock-controller@2001000 { #reset-cells = <1>; }; + sid: efuse@3006000 { + compatible = "allwinner,sun50i-a523-sid", "allwinner,sun50i-a64-sid"; + reg = <0x03006000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + mmc0: mmc@4020000 { compatible = "allwinner,sun55i-a523-mmc", "allwinner,sun20i-d1-mmc"; From patchwork Fri Apr 11 00:38:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikhail Kalashnikov X-Patchwork-Id: 880813 Received: from mail-lj1-f173.google.com (mail-lj1-f173.google.com [209.85.208.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8E9817BA1; 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Thu, 10 Apr 2025 17:40:42 -0700 (PDT) Received: from localhost.localdomain ([176.106.241.81]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464ea5c6sm6344251fa.62.2025.04.10.17.40.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Apr 2025 17:40:42 -0700 (PDT) From: iuncuim To: Vasily Khoruzhick , Yangtao Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Piotr Oniszczuk Subject: [PATCH 5/6] arm64: dts: allwinner: A523: Add thermal sensors and zones Date: Fri, 11 Apr 2025 08:38:25 +0800 Message-ID: <20250411003827.782544-6-iuncuim@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250411003827.782544-1-iuncuim@gmail.com> References: <20250411003827.782544-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mikhail Kalashnikov The A523 processor has two temperature controllers, THS0 and THS1. THS0 has only one temperature sensor, which is located in the DRAM. THS1 does have 3 sensors: ths1_0 - "big" cores ths1_1 - "little" cores ths1_2 - gpu Add the thermal sensor configuration and the thermal zones Signed-off-by: Mikhail Kalashnikov --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 138 ++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index d626612bb..4f36032b2 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -22,6 +23,7 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0x000>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu1: cpu@100 { @@ -29,6 +31,7 @@ cpu1: cpu@100 { device_type = "cpu"; reg = <0x100>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu2: cpu@200 { @@ -36,6 +39,7 @@ cpu2: cpu@200 { device_type = "cpu"; reg = <0x200>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu3: cpu@300 { @@ -43,6 +47,7 @@ cpu3: cpu@300 { device_type = "cpu"; reg = <0x300>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu4: cpu@400 { @@ -50,6 +55,7 @@ cpu4: cpu@400 { device_type = "cpu"; reg = <0x400>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu5: cpu@500 { @@ -57,6 +63,7 @@ cpu5: cpu@500 { device_type = "cpu"; reg = <0x500>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu6: cpu@600 { @@ -64,6 +71,7 @@ cpu6: cpu@600 { device_type = "cpu"; reg = <0x600>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu7: cpu@700 { @@ -71,6 +79,7 @@ cpu7: cpu@700 { device_type = "cpu"; reg = <0x700>; enable-method = "psci"; + #cooling-cells = <2>; }; }; @@ -171,11 +180,39 @@ ccu: clock-controller@2001000 { #reset-cells = <1>; }; + ths1: thermal-sensor@2009400 { + compatible = "allwinner,sun55i-a523-ths1"; + reg = <0x02009400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC1>; + clock-names = "bus", "gpadc"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + + ths0: thermal-sensor@200a000 { + compatible = "allwinner,sun55i-a523-ths0"; + reg = <0x0200a000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC0>; + clock-names = "bus", "gpadc"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <0>; + }; + sid: efuse@3006000 { compatible = "allwinner,sun50i-a523-sid", "allwinner,sun50i-a64-sid"; reg = <0x03006000 0x1000>; #address-cells = <1>; #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@38 { + reg = <0x38 0x14>; + }; }; mmc0: mmc@4020000 { @@ -602,4 +639,105 @@ rtc: rtc@7090000 { #clock-cells = <1>; }; }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + polling-delay-passive = <500>; + polling-delay = <1000>; + thermal-sensors = <&ths1 1>; + sustainable-power = <1200>; + + trips { + cpu0_threshold: cpu-trip-0 { + temperature = <70000>; + type = "passive"; + hysteresis = <0>; + }; + cpu0_target: cpu-trip-1 { + temperature = <90000>; + type = "passive"; + hysteresis = <0>; + }; + cpu0_critical: cpu-trip-2 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4_thermal: cpu4-thermal { + polling-delay-passive = <500>; + polling-delay = <1000>; + thermal-sensors = <&ths1 0>; + sustainable-power = <1600>; + + trips { + cpu4_threshold: cpu-trip-0 { + temperature = <70000>; + type = "passive"; + hysteresis = <0>; + }; + cpu4_target: cpu-trip-1 { + temperature = <90000>; + type = "passive"; + hysteresis = <0>; + }; + cpu4_critical: cpu-trip-2 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu4_target>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <500>; + polling-delay = <1000>; + thermal-sensors = <&ths1 2>; + sustainable-power = <2400>; + + trips { + gpu_temp_critical: gpu-trip-0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths0>; + + trips { + ddr_temp_critical: ddr-trip-0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + }; }; From patchwork Fri Apr 11 00:38:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikhail Kalashnikov X-Patchwork-Id: 880479 Received: from mail-lj1-f182.google.com (mail-lj1-f182.google.com [209.85.208.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22BB4FC08; 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Thu, 10 Apr 2025 17:41:02 -0700 (PDT) Received: from localhost.localdomain ([176.106.241.81]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30f464ea5c6sm6344251fa.62.2025.04.10.17.40.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Apr 2025 17:41:01 -0700 (PDT) From: iuncuim To: Vasily Khoruzhick , Yangtao Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Piotr Oniszczuk Subject: [PATCH 6/6] dt-bindings: thermal: sun8i: Add A523 THS0/1 controllers Date: Fri, 11 Apr 2025 08:38:26 +0800 Message-ID: <20250411003827.782544-7-iuncuim@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250411003827.782544-1-iuncuim@gmail.com> References: <20250411003827.782544-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mikhail Kalashnikov Add dt-bindings description of the thermal sensors in the A523 processor. Signed-off-by: Mikhail Kalashnikov --- .../bindings/thermal/allwinner,sun8i-a83t-ths.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml index 3e61689f6..70ac395ef 100644 --- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml +++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml @@ -24,17 +24,21 @@ properties: - allwinner,sun50i-h5-ths - allwinner,sun50i-h6-ths - allwinner,sun50i-h616-ths + - allwinner,sun55i-a523-ths0 + - allwinner,sun55i-a523-ths1 clocks: minItems: 1 items: - description: Bus Clock + - description: GPADC Clock - description: Module Clock clock-names: minItems: 1 items: - const: bus + - const: gpadc - const: mod reg: @@ -107,6 +111,7 @@ allOf: enum: - allwinner,sun8i-h3-ths - allwinner,sun20i-d1-ths + - allwinner,sun55i-a523-ths0 then: properties: