From patchwork Thu Apr 10 15:47:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880009 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0C751EF381; Thu, 10 Apr 2025 15:47:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300069; cv=none; b=flGQo7kkf4um+GWbMiZ+DbzAAYjQUYofIxen5E9VEBnWSsiXMJVvizIrIespGWG6EdbRYASMhztG36C4wMLZpHTZ6ksL918XPsPG8V1IiFKl5xDkGJJGJ4TdFezsiN9KUM44EEC1LlbUFiQWy0ES8/VUFytRV2f3j2wyP1iMgZE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300069; c=relaxed/simple; bh=17E6AqFYyreXuXiCUMrel7kiiXcdT5b24ICEL4rFA+A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bp1E7gERqX1br4Y+l1zLCAb46x+Mb0Z8Vi690tn9j6QH9TWTSYl8er8MrDEShIYtZvDU9IcqhZ1cADHLIWWP/oc1VQF+ytBCA3AZMOU0p93xKKq3rsgAjpt3wPV07eHMXdD5LKGwWrXA2MACutbZBoYlXD0x1LN4A4I4Vjl6p0M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EO3eS51E; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EO3eS51E" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 33747C4CEE9; Thu, 10 Apr 2025 15:47:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300067; bh=17E6AqFYyreXuXiCUMrel7kiiXcdT5b24ICEL4rFA+A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=EO3eS51Ey9S8GJDcQAD6Rr1t3w6p6SAFWhoWkQ3W2bG6/AQW4FOhZwWpfKl+Wa2CX rjHhnrPIfNDzvsNPhaHlwKdZoeWSmw4nX1LiK+OVHzZwvwGzoEcL5T6BrmVVYaChhw P89evcQIT5K7fAHjnq9wbIjJ7jWx+ciBKRTcDqM2aZmRBv/n3LnYH+n9JuvVJQap9w 3F9BCpDxC9gZjNGhRtDyqme2YIWauF1tC7B4P4JU0v2WqsTaDPyhu83pmJz++H32z/ 4GL746Vd9s/tc+V5Y4TK6nVcNQK/xh15HP+fsn0Oks0zVeOoxrV/b/vl3RxLG+kHyZ 8GAJNzuFYqX6A== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:22 -0500 Subject: [PATCH v2 01/17] arm64: dts: allwinner: h5/h6: Drop spurious 'clock-latency-ns' properties Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-1-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, Andre Przywara X-Mailer: b4 0.15-dev 'clock-latency-ns' is not a valid property for CPU nodes. It belongs in OPP table (which has it). Drop them from the CPU nodes. Signed-off-by: Rob Herring (Arm) Reviewed-by: Andre Przywara Acked-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 ---- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index d3caf27b6a55..48802bf02f3b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -16,7 +16,6 @@ cpu0: cpu@0 { reg = <0>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; @@ -26,7 +25,6 @@ cpu1: cpu@1 { reg = <1>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; @@ -36,7 +34,6 @@ cpu2: cpu@2 { reg = <2>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; @@ -46,7 +43,6 @@ cpu3: cpu@3 { reg = <3>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 2301c59b41b1..73e8604315c5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -27,7 +27,6 @@ cpu0: cpu@0 { reg = <0>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -44,7 +43,6 @@ cpu1: cpu@1 { reg = <1>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -61,7 +59,6 @@ cpu2: cpu@2 { reg = <2>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -78,7 +75,6 @@ cpu3: cpu@3 { reg = <3>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; i-cache-size = <0x8000>; i-cache-line-size = <64>; From patchwork Thu Apr 10 15:47:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880829 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52C651EF365; Thu, 10 Apr 2025 15:47:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300069; cv=none; b=LdthCRVNdHFQhAcCnBavLc8jWFk4IbeqDB+4UayT5PlQhXNGfkO/pzbTcCVWvhlT2s1Z8v6WlCubDBGG+qj9BwnuhIQpdl2w1fueW4eWdJTsRWVraXOz8yYUtlVOlR4/aOQ4ndNSnep5QqLEmTf/LiaxRZTgJIv3uQ0APoslY9Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300069; c=relaxed/simple; bh=MJ4WoqvhgC/aZjAy/ZTQhYcG1cI4RNuRYa6MzsWqQtk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VxZTjEWCjLkHz5cJ5oSIEaPopeZcsJ5E7IYLsjizPAhHccg4SOZwdnPmZc2nhuQuAqDXsNqfJN5Dv6CUgqQ1yOCEdQO6MiFOful+3pogDrfqgZwaSqDz9sK/Z/SKuw9bFLKQ99qPybiMpusPSYPgBAQQnLmUOczUlaPeRSsu8+M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hKfnqZne; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hKfnqZne" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 95E14C4CEEA; Thu, 10 Apr 2025 15:47:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300068; bh=MJ4WoqvhgC/aZjAy/ZTQhYcG1cI4RNuRYa6MzsWqQtk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=hKfnqZneC+abzLvYTV6plSnmp6les52XSC3Xz9C7Rcp6J4l9nCVNuTwwlTUqDwC2q +72ANtmUuZvc/VC9/xocD3jWreOuzykzBrMs4XMQ+5mfaCArgkpCjWOGupDZjoz5Ow 8UosB8hJqyiNrk+9DA7VvUzhvQIATUk+C0zQVQFDi+LPw+XTwEqa/nzR/JLtX1szDN PBgCNHvQouW1ck4kouSglDLfZtlrrW/w97heJkhLLQgWU5bkcf8/K4TkAhklO7XJAd vNyAf87yOvTzcn67GZHe95oSdT4xtwNHwsePQSTvc2Glij/FQIgwfTDE2C7PXQwh/o +h/3lbYv+BgBQ== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:23 -0500 Subject: [PATCH v2 02/17] arm64: dts: broadcom: bcm2712: Use "l2-cache" for L2 cache node names Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-2-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.15-dev There's no need include the CPU number in the L2 cache node names as the names are local to the CPU nodes. The documented node name is also just "l2-cache". Signed-off-by: Rob Herring (Arm) Reviewed-by: Philippe Mathieu-Daudé --- arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index 9e610a89a337..ad0cac8e4444 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -64,7 +64,7 @@ cpu0: cpu@0 { i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l0>; - l2_cache_l0: l2-cache-l0 { + l2_cache_l0: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; @@ -88,7 +88,7 @@ cpu1: cpu@1 { i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l1>; - l2_cache_l1: l2-cache-l1 { + l2_cache_l1: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; @@ -112,7 +112,7 @@ cpu2: cpu@2 { i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l2>; - l2_cache_l2: l2-cache-l2 { + l2_cache_l2: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; @@ -136,7 +136,7 @@ cpu3: cpu@3 { i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l3>; - l2_cache_l3: l2-cache-l3 { + l2_cache_l3: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; From patchwork Thu Apr 10 15:47:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880008 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0A9A256C8A; Thu, 10 Apr 2025 15:47:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300071; cv=none; b=KtIqkK5yqCYZ37jioNkk8WFwS4N5aJ87HYD0459z954lGRvMKHBef3rOAN7fZqB1QtRaKTvDCWjDqU/Dqkhuadpe9evUB6tHts+s+FgHs09SoQRQ8DwwiTcHBQejpfVbI7oYZzJi/Ydv2kNHSyMRtFt4S34YnVvj1pv3ZbgJZYU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300071; c=relaxed/simple; bh=iDeiMpH2/KxFQOc/7AuYydAb8NCVCSm+fEB6mcijRro=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eTP1CEZDlKFq72Gm9khm5ZQbb4el5DA0FmZyZ7X+h5GZp9xKNlF8n0q6krB98b5cYHEmBEw1P2q0vDhHsddXSm3h/iLB1XRQgoa7Kzqmjg2/5nRU47/BbftTavthav+68IZD5VkZfk1ay8n4n1zmQhb5sQsRoO7nofNR3wWAXYg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=N3WR9nvb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="N3WR9nvb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 16781C4CEDD; Thu, 10 Apr 2025 15:47:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300070; bh=iDeiMpH2/KxFQOc/7AuYydAb8NCVCSm+fEB6mcijRro=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=N3WR9nvbHwdU8OqfFIc/mAfEz0Nmc09RDoFYeBK7Cd1q4dU8AiGidDCnyDh2Yd6Ff khtIEZeAm5b3jsSSJCwlepHT5Cjj7NPKSZRHCw+YnxgdCh+KREBBp8Lv14VEFi4Dwi RlYARWcnQS1qsk7DPNfsjiBO0DHdhlse12UYxFM9X2jY8w8vYAu8NxrNxkiG4smfD2 K+u7CqTDULdw+eay4gEuHbdO4mN6JROOW/+cMc8jwjY3mdH4cOIFRIqM2LD4ggstNg XT+EhJsutbL2iP7y0ydVIsOgAupR55qA+AUnocPW19n1khPPot918ofQg6cvjhRrCs aMHf0ORhxZLHg== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:24 -0500 Subject: [PATCH v2 03/17] arm64: dts: microchip: sparx5: Fix CPU node "enable-method" property dependencies Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-3-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org X-Mailer: b4 0.15-dev The "spin-table" enable-method requires "cpu-release-addr" property, so add a dummy entry. It is assumed the bootloader will fill in the correct values. Signed-off-by: Rob Herring (Arm) Reviewed-by: Daniel Machon Tested-by: Daniel Machon --- arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi index 32bb76b3202a..83bf5c81b5f7 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi @@ -12,10 +12,12 @@ &psci { &cpu0 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu1 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &uart0 { From patchwork Thu Apr 10 15:47:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880828 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCB1328C5A1; Thu, 10 Apr 2025 15:47:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300072; cv=none; b=QySQ8T+8NmGc0l560uMqcholIr9JJJYVhNhMluh81aN6hEOpC5NONuNJ4v2ljutxzlyhP6oyzjxMn+6+Qm7CPGx6FgQBH9bdnJHQpT9Pu5re0VViY3keG95MXibu7IFcElF2zb1l1ha9idSfnG6TjxVpq0yrUbj6iT4mM0SIkPs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300072; c=relaxed/simple; bh=zdpdwCUxt4/JGxD9zT4n5tnKqmSCQRjKtGwRibbyTKY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=a6sgO7u6q9lVb3cFwaoquVXV7E5KWaOZua7+SW0IgzPX4mPfhFQQgRM6uhZsxHUNg0cntYrC2I6EwyCh0O3QuzjirpkC4q+vwfKkVEHkvE/2qerIIOJp/HzyhfIGM3EejKhIBBwymrxxJhsGKw5UScnbttWAmMwI6EauBNhr7Oc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Tp2pgYbw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Tp2pgYbw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 80D35C4CEEB; Thu, 10 Apr 2025 15:47:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300071; bh=zdpdwCUxt4/JGxD9zT4n5tnKqmSCQRjKtGwRibbyTKY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Tp2pgYbwXQf4eNwmKaH2Y9ewJRXbwjukqmEfd7gasC1BhxcwjreBEF/j1FACoOJ3n fKdwiHbTde/95llhHDX8LEPLU4Q4kNtch6X4Gtag9EjN2DFSU8oWDvoTpT/y2sS1Pn YmTtSWsXG0o9T5Sg1Jk0GmoLLj5liyC4MKb2I4in0MtWDSMgjb7jQH7P54PdHi0Fge /tyeSwBW8Wh77LfjdWWAOh6WEV2iDOQG5FKK3zDdiLTqnwsmbzSybdW8BOIUXAcbdX 0UJ7W6RDn1M45MgKlVI+3jHU6otRqGgsNJieEZO0dRqPBzL4/hTBj9ujca+//zyDCU vOQslelhGs3xw== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:25 -0500 Subject: [PATCH v2 04/17] arm64: dts: qcom: qdu1000: Fix qcom,freq-domain Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-4-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, Konrad Dybcio X-Mailer: b4 0.15-dev The correct property name is 'qcom,freq-domain', not 'qcom,freq-domains'. Signed-off-by: Rob Herring (Arm) Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index f973aa8f7477..7c8d78fd7ebf 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -47,7 +47,7 @@ cpu0: cpu@0 { enable-method = "psci"; power-domains = <&cpu_pd0>; power-domain-names = "psci"; - qcom,freq-domains = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_0>; l2_0: l2-cache { compatible = "cache"; @@ -70,7 +70,7 @@ cpu1: cpu@100 { enable-method = "psci"; power-domains = <&cpu_pd1>; power-domain-names = "psci"; - qcom,freq-domains = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_100>; l2_100: l2-cache { compatible = "cache"; @@ -88,7 +88,7 @@ cpu2: cpu@200 { enable-method = "psci"; power-domains = <&cpu_pd2>; power-domain-names = "psci"; - qcom,freq-domains = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_200>; l2_200: l2-cache { compatible = "cache"; @@ -106,7 +106,7 @@ cpu3: cpu@300 { enable-method = "psci"; power-domains = <&cpu_pd3>; power-domain-names = "psci"; - qcom,freq-domains = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_300>; l2_300: l2-cache { compatible = "cache"; From patchwork Thu Apr 10 15:47:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880007 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B416128D827; Thu, 10 Apr 2025 15:47:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300073; cv=none; b=MkHrV47KuA0kzeHr8w8elr10yFWEICvPIidtfLHAcvqkvlGkKXclVBdaOlH3KmTNHd4pmx/3uD8hrrxOwt/33S+xuMjSuVIDJ95KOvTkoJnRZ1fg4gIpwF+V2/roh202ncbWD2R5agzxnf7bKb1cghXJZM3dc3pmpckJSIH9XMk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300073; c=relaxed/simple; bh=ra1+/x5tvvdws+NLgU93cbl0GnrL59uh7spZ77Nu2f0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Hq6lsWl+u7XIgrB4Ix5F37CmjWoQAbvOVNj3zO4r4bTb21DTU/dBZP8A33EKktEcevTBwPZLff8R2YoLFS23mKBga5/JaySEfPTheOobLytV1kKBJqkWerLM/Pkutn4NE48eNHnnaVmruWmryjP/LNgXPrxtYFojQ/lK486i1YA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=osXSzsJi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="osXSzsJi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E5B12C4CEDD; Thu, 10 Apr 2025 15:47:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300073; bh=ra1+/x5tvvdws+NLgU93cbl0GnrL59uh7spZ77Nu2f0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=osXSzsJizztnuyucaAb6gJ3UnBpmWkaUistvD0lZeqHTGwkjWKi3KEbYTQc9vnNd8 sYwJPDNuPwtCN3FbYhNJzKOH8iR0FyZoK9WBBgXFt3JR+GViSj93+J7IKND0x4Nqx3 mteKEAyhxOqLlMAH+Bld4AJLE7kyo0qJreNViUmg0SphBF/SUah93W5gpNiwKwgnJZ h8VkECzVm/u3cjOq1pgdbjQHY2CAAKM63iZNYoXv2C4afiK7sga5pqTFTt4hVSadce Hn9ZuGY+KfW+EEWq/+17zPu4G+BWN7J8jRcwOdp4injNxLwJPJaVG76MQRoToHmJKa BhezofOyJOZaQ== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:26 -0500 Subject: [PATCH v2 05/17] arm64: dts: qcom: msm8939: Fix CPU node "enable-method" property dependencies Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-5-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org X-Mailer: b4 0.15-dev The "spin-table" enable-method requires "cpu-release-addr" property, so add a dummy entry. It is assumed the bootloader will fill in the correct values. Signed-off-by: Rob Herring (Arm) Acked-by: Konrad Dybcio --- v2: - Keep qcom,saw and qcom,acc properties --- arch/arm64/boot/dts/qcom/msm8939.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 7cd5660de1b3..72f01953e65c 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -46,6 +46,7 @@ cpu0: cpu@100 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x100>; next-level-cache = <&l2_1>; qcom,acc = <&acc0>; @@ -64,6 +65,7 @@ cpu1: cpu@101 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x101>; next-level-cache = <&l2_1>; qcom,acc = <&acc1>; @@ -77,6 +79,7 @@ cpu2: cpu@102 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x102>; next-level-cache = <&l2_1>; qcom,acc = <&acc2>; @@ -90,6 +93,7 @@ cpu3: cpu@103 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x103>; next-level-cache = <&l2_1>; qcom,acc = <&acc3>; @@ -103,6 +107,7 @@ cpu4: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x0>; qcom,acc = <&acc4>; qcom,saw = <&saw4>; @@ -121,6 +126,7 @@ cpu5: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x1>; next-level-cache = <&l2_0>; qcom,acc = <&acc5>; @@ -134,6 +140,7 @@ cpu6: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x2>; next-level-cache = <&l2_0>; qcom,acc = <&acc6>; @@ -147,6 +154,7 @@ cpu7: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x3>; next-level-cache = <&l2_0>; qcom,acc = <&acc7>; From patchwork Thu Apr 10 15:47:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880827 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9E4528D85A; Thu, 10 Apr 2025 15:47:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300074; cv=none; b=qd+hZNWgwC5nSrFyny8gPHcfNREBw94cD3ARWKAIK18rp+Xr5+jjqacX1sp4HxjTWwBXBiG/q+itf5zoeNmtydQKNyZwMwNZI4orzt4ptJtZtMzqRjAFmZVE7MQ2pwa9t8tk2/TXB5Dg7d9wnefwKVNQQvy6wbJOlmPBdUVB3mo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300074; c=relaxed/simple; bh=nVo5X/MosXjoMIZOdVn7ETl8AN7NiwovxfdEw8OmSOs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UQWDIQsSXytOrAQwBVhvW83+RQ8vt8MHB/t60fXqG7OeqwrOmio0BgKh0Yn9cbDFV8I9dU3sBjWQEo+9jIY3zY0K3UYmD1J/mDLipG1gWPql3d1Ku+g1u8F/TOKbI/z1e/1IpP1cw60uCac3lnuuNoRaFxHtxwxc+rt0H6nDY4M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uGYzjYYn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uGYzjYYn" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 55A8CC4CEE9; Thu, 10 Apr 2025 15:47:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300074; bh=nVo5X/MosXjoMIZOdVn7ETl8AN7NiwovxfdEw8OmSOs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=uGYzjYYnTyApltpYtEA9/9oZnG7/797Cn8q6jqLk/EiRZu5XNF9EqiZug9/5/DkhX FRosU37qIN5bQ1dUS0YVTjxFaqmabQ38JtCNt1L0lFwpmaWS5mnlYPBXQY6s0rIHQc Nsu2qcZnsHflTkFFwv8LjQyI1/3LA0m8kUxUChx9BT0j/UhiUPJCikDLhEclCZHBIC si6a0LUoUuapa5Y9l8wAc5gqlVpgGczwcdrrgDhN4YbSPiV+50DSgLPVlpyH2bpcbC 2MRLG1p4C84SGSxRS3OFcHEyOHInbBplC/dIIFurvHHjPYY9PShPHMVmWUO9mmFbmq 8QArAGCBXYMSQ== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:27 -0500 Subject: [PATCH v2 06/17] arm64: dts: qcom: msm8992-lg-h815: Fix CPU node "enable-method" property dependencies Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-6-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org X-Mailer: b4 0.15-dev The "spin-table" enable-method requires "cpu-release-addr" property, so add a dummy entry. It is assumed the bootloader will fill in the correct values. Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts b/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts index 4520d5d51a29..6a231afad85d 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts @@ -93,26 +93,32 @@ key-vol-up { &cpu0 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu1 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu2 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu3 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu4 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu5 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &pm8994_resin { From patchwork Thu Apr 10 15:47:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880826 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 943A128EA7F; Thu, 10 Apr 2025 15:47:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300077; cv=none; b=qhcORsP1VxRoi4wRtrPJFnrBGJpI72oGh8TUklHILb5mN+dYjn4cIRfvtJgRucIjGOgCD4+8v/7iFwcE2SOjSdo6GMPHqNWBRVRDhZ1+Lr2AzZTIy2J5mUpS8Q9UZHEQ5ac1vVDBUcZU3Nl1eappS/NZJmgNJs8qhXhlo/HPqIw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300077; c=relaxed/simple; bh=w8D/oQlbjYFMA654Kfwwvab2rVq8372zGCPcqKW1Iu0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lVSxWQul8mRTcH4cdvjnyylSeqD4HXdcq20LU//2dW5GCX2NePYYFhlmVqI0QupN3Uaa4LcqgWXmzqDCMBLEfYyVuJJnYSM8vDzdXRntb0VjFRjTP9cDiERQMz3IjQGp1VMjU36WkkY9sWyJqjPY+5aXfXoMq8gJgUOrRh80/NI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fG2TpuqM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fG2TpuqM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AE3ADC4CEE8; Thu, 10 Apr 2025 15:47:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300076; bh=w8D/oQlbjYFMA654Kfwwvab2rVq8372zGCPcqKW1Iu0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=fG2TpuqMMHHyYZtykHxBYOOreDpwV+ldhF4Z5Qy+/+1VXWQ49leBhORYlyDtMvG/U s0WqonhwLJRWz0RL+p1Pn0QquD9o35gsf+po8VW6kll00ijBpV0kRkUFtAN8tW/UPD qYfRXrcQ1KCnPHN8qNAPaYn7F+b8tWIiL4aR0n5C3a6Fq7S12sz5nXEnBcuZFyvaGn cSuVuT01eLQbeYBv51ckvqUHv3N9rjCw/uF9DlZTS4EKdamYhxQ4/Zh/EJtAFERtPU FFNHgAu3/FaAT+jqRU1sI5ZiGte/aL2KnKPX5eJUdd2+unfwIwf6LeZPkclUmONFY7 wOKwYMsAvfkSA== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:28 -0500 Subject: [PATCH v2 07/17] arm: dts: qcom: sdx55/sdx65: Fix CPU power-domain-names Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-7-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org X-Mailer: b4 0.15-dev "rpmhpd" is not documented nor used anywhere. The power-domain is used for performance scaling (cpufreq), so "perf" is the correct name to use. Signed-off-by: Rob Herring (Arm) --- v2: - Use "perf" instead of "psci" --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 39530eb580ea..20fdae9825e0 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -57,7 +57,7 @@ cpu0: cpu@0 { enable-method = "psci"; clocks = <&apcs>; power-domains = <&rpmhpd SDX55_CX>; - power-domain-names = "rpmhpd"; + power-domain-names = "perf"; operating-points-v2 = <&cpu_opp_table>; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 6b23ee676c9e..c8e312dcd26b 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -58,7 +58,7 @@ cpu0: cpu@0 { enable-method = "psci"; clocks = <&apcs>; power-domains = <&rpmhpd SDX65_CX_AO>; - power-domain-names = "rpmhpd"; + power-domain-names = "perf"; operating-points-v2 = <&cpu_opp_table>; }; }; From patchwork Thu Apr 10 15:47:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880006 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89B8928EA7E; Thu, 10 Apr 2025 15:47:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300077; cv=none; b=D0gmKwZqviduPXhfXz/pfKwXtMTUaJUHEqdm7CUCGlw6bl28e6lVXit4Y1PbdGz6+P9hH1t6QCPISxZwFuVebhPRLngFk6z3l6JM6ihW1zAufUdt5cGe6qoo8reRkVrK+aOJJEE/ZC9zEB9OZLulr/nUQKZmPwQTvlsqilr8VU0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300077; c=relaxed/simple; bh=xMgbsjBv9Kef+UFcQ6l0JsE73pnNHHIi5V3EKTVvKZU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kwJ/iBPAG7pAHWuNFTGlzPMFm/ILDhsxH6h5biFn6iJ1WQp6TeYVO0zuWGOdBXsb6GlP2ofiN9uT6hbwqddTaIiMY30Wdi/hgStEBdFi7WJumQl6lWInIiaN5VmOrDjOvuMvP+E1bJmPlEIN7r9VtzsN1Cp/ybwIT3MVQKRzCL4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aQOmjXnq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aQOmjXnq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 26405C4CEDD; Thu, 10 Apr 2025 15:47:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300077; bh=xMgbsjBv9Kef+UFcQ6l0JsE73pnNHHIi5V3EKTVvKZU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=aQOmjXnqnWK8Nld/ZGzxs4xNkx46h21EaRICn25BYXuFTFYoPBcPH3fp3tvu0Nz5s DLQmHkmLKQSHWzVXzLYg1566gLijWI2uFV+/OxcMmmm5GGFBbPXAOn7CBBfAYiz3Dm ttkmY5t4PXSe+qDyQmwyn6h7ywO+0uVpG+0D9wT+B9VJVpTF3CbsTHHp8472LTaLe5 WiIXKlohnsSpd2Jf62u1AJY/4jfhKtNb/DwQp2ZMlbYzdoBx+uyJgl1ed9s9yw8tKC uCvtb5UGywK4j8VEQe2SHf/jJ6zxxP5rn3JjytQgQkC1EyugBS6VwnFHhl7++QWwkE rVo3Wdgs4jZtw== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:29 -0500 Subject: [PATCH v2 08/17] arm/arm64: dts: imx: Drop redundant CPU "clock-latency" Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-8-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org X-Mailer: b4 0.15-dev The "clock-latency" property is part of the deprecated opp-v1 binding and is redundant if the opp-v2 table has equal or larger values in any "clock-latency-ns". The OPP tables have values of 150000, so it can be removed. Signed-off-by: Rob Herring (Arm) --- arch/arm/boot/dts/nxp/imx/imx7s.dtsi | 1 - arch/arm64/boot/dts/freescale/imx8mm.dtsi | 4 ---- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 4 ---- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 4 ---- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 4 ---- 5 files changed, 17 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi index 2629968001a7..9235dd7e93bb 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi @@ -73,7 +73,6 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0>; clock-frequency = <792000000>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX7D_CLK_ARM>; cpu-idle-states = <&cpu_sleep_wait>; operating-points-v2 = <&cpu0_opp_table>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 4de3bf22902b..cfebaa01217e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -62,7 +62,6 @@ A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -83,7 +82,6 @@ A53_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -102,7 +100,6 @@ A53_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -121,7 +118,6 @@ A53_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index a5f9cfb46e5d..848ba5e46ee6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -62,7 +62,6 @@ A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; - clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -83,7 +82,6 @@ A53_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; - clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -102,7 +100,6 @@ A53_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; - clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -121,7 +118,6 @@ A53_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; - clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index ce6793b2d57e..f8afdba71c36 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -65,7 +65,6 @@ A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; - clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -86,7 +85,6 @@ A53_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; - clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -105,7 +103,6 @@ A53_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; - clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -124,7 +121,6 @@ A53_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; - clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index d51de8d899b2..d27b824995eb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -106,7 +106,6 @@ A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -126,7 +125,6 @@ A53_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -144,7 +142,6 @@ A53_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -162,7 +159,6 @@ A53_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; From patchwork Thu Apr 10 15:47:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880005 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F23E28F95A; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iIQUvuA3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8F97AC4CEDD; Thu, 10 Apr 2025 15:47:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300078; bh=rxpmdQ00QIobReD/bCkMksNDeC2yXxfKVAGTAYhvgkc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=iIQUvuA3gCshAauWH6zqRI+XnRTwwMXV9I3TGGqvy/FEER7QJ7uNg9cI44qlxasr5 R+ZaP9NiVZ34J1QGpo5SeLFChNsPeTgAxjM27nsqqT4e3WUqtyKOsQLY/aVPEunLoj m/wI1Hh9QqYtsFJ6rwrqHfViwqaTpORKlJy6QsjVkjPiSww29Trsj7jmsrdWY+hlSg MiLq+RXW8Pv/nuX92JbMAqgRxs026LTnIx1WqmLlezoEukSV6ShwHIzhAlypfoJq23 zgY8buBGUkvYk1b+aZru6NhR15CWbwZqMBVTjo/NhBVD9EaxYG/+4t0ydMjHFfl1S1 js7HvMT+iaIqQ== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:30 -0500 Subject: [PATCH v2 09/17] arm: dts: qcom: ipq4019: Drop redundant CPU "clock-latency" Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-9-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, Konrad Dybcio X-Mailer: b4 0.15-dev The "clock-latency" property is part of the deprecated opp-v1 binding and is redundant if the opp-v2 table has equal or larger values in any "clock-latency-ns". The OPP table has values of 256000, so it can be removed. Signed-off-by: Rob Herring (Arm) Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 06b20c196faf..fceb2f5f5482 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -53,7 +53,6 @@ cpu@0 { reg = <0x0>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -67,7 +66,6 @@ cpu@1 { reg = <0x1>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -81,7 +79,6 @@ cpu@2 { reg = <0x2>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -95,7 +92,6 @@ cpu@3 { reg = <0x3>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; From patchwork Thu Apr 10 15:47:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880825 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EB5F28FFE1; Thu, 10 Apr 2025 15:48:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300080; cv=none; b=cBjpqt4OWdOWipnTJFCjRx5hcohZulKGaYEuOH2BC22mDLIJRFEPvTLaSqngbF0GCXmRyz+XQxdbnSJJMGqgpS0Foaju7CCRnUUXaph3tSTWFDzbq3YhWai/9/7AnNtiaIl6VdoBVmWTuX8h9CRLILVxZP7240SdBy4jLiaJrFU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300080; c=relaxed/simple; bh=xnnf/JMo7g8hotGpKUR0IYT07WFDf4YWzcm+WUwyUKc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WYNGcuJh9mnlMdFyk2ukjZCHZ+jUM314G34wuCHYEdHOlIUmZYfnvLMnHBCl3UmOkU5xFpQG+kqGR7YG+eFOcgwmmRhxonuh8x3g0fEKj2JwV56nmHi7TgH1hkLGEZyZtX+NE8aO0/UWpo/AiKNji0efL08XXquCriwwXQdTWTk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=auwxjw2t; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="auwxjw2t" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F236DC4CEE8; Thu, 10 Apr 2025 15:47:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300080; bh=xnnf/JMo7g8hotGpKUR0IYT07WFDf4YWzcm+WUwyUKc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=auwxjw2tabmR3j6czYfHJ2Ftx0bKAKDvpJxupRWC3c3TooP0NGWSQTloRzerUXGyv cfV6ImAGjJSXKtGcuw3EH5yL2wgpZXbxCANR0W1x+AEowm2XbBlWkt897w8kxAYQUj pjywt414Q8DCrFX7/Lh37dovG8HQP0Fwr3j4q7+cRXh0vc1Tw1bWEE3F4kJD6pVDsP lTBOxqtO0hvjHrjEDjGZJrl9Fk7jOp/w+J+3uygbgezRqH+/qhJi1nbkNms7BtaNxe P7Vo36xuI0vQZ+X2eI37RniaVxDAaQ6RbJHm7EIIH1KLd0nAIQ4OxiA5WlXx7bHGLT XueIeaIeEtOxg== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:31 -0500 Subject: [PATCH v2 10/17] arm: dts: rockchip: Drop redundant CPU "clock-latency" Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-10-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org X-Mailer: b4 0.15-dev The "clock-latency" property is part of the deprecated opp-v1 binding and is redundant if the opp-v2 table has equal or larger values in any "clock-latency-ns". Add any missing "clock-latency-ns" properties and remove "clock-latency". Signed-off-by: Rob Herring (Arm) --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 8 +++++++- arch/arm/boot/dts/rockchip/rk3188.dtsi | 1 - arch/arm/boot/dts/rockchip/rk322x.dtsi | 1 - arch/arm/boot/dts/rockchip/rk3288.dtsi | 5 +---- arch/arm/boot/dts/rockchip/rv1108.dtsi | 1 - 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index d4572146d135..c49099954c28 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -48,7 +48,6 @@ cpu0: cpu@f00 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf00>; - clock-latency = <40000>; clocks = <&cru ARMCLK>; resets = <&cru SRST_CORE0>; operating-points-v2 = <&cpu_opp_table>; @@ -87,31 +86,38 @@ cpu_opp_table: opp-table-0 { opp-216000000 { opp-hz = /bits/ 64 <216000000>; opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; }; opp-408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; }; opp-696000000 { opp-hz = /bits/ 64 <696000000>; opp-microvolt = <975000 975000 1325000>; + clock-latency-ns = <40000>; }; opp-816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1075000 1075000 1325000>; opp-suspend; + clock-latency-ns = <40000>; }; opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1200000 1200000 1325000>; + clock-latency-ns = <40000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1325000 1325000 1325000>; + clock-latency-ns = <40000>; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3188.dtsi b/arch/arm/boot/dts/rockchip/rk3188.dtsi index 44b54af0bbf9..850bd6e67895 100644 --- a/arch/arm/boot/dts/rockchip/rk3188.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3188.dtsi @@ -23,7 +23,6 @@ cpu0: cpu@0 { compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; - clock-latency = <40000>; clocks = <&cru ARMCLK>; operating-points-v2 = <&cpu0_opp_table>; resets = <&cru SRST_CORE0>; diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi index 96421355c274..cd11a018105b 100644 --- a/arch/arm/boot/dts/rockchip/rk322x.dtsi +++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi @@ -36,7 +36,6 @@ cpu0: cpu@f00 { resets = <&cru SRST_CORE0>; operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; enable-method = "psci"; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi index 3f1d640afafa..42d705b544ec 100644 --- a/arch/arm/boot/dts/rockchip/rk3288.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi @@ -70,7 +70,6 @@ cpu0: cpu@500 { resets = <&cru SRST_CORE0>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -81,7 +80,6 @@ cpu1: cpu@501 { resets = <&cru SRST_CORE1>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -92,7 +90,6 @@ cpu2: cpu@502 { resets = <&cru SRST_CORE2>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -103,7 +100,6 @@ cpu3: cpu@503 { resets = <&cru SRST_CORE3>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -116,6 +112,7 @@ cpu_opp_table: opp-table-0 { opp-126000000 { opp-hz = /bits/ 64 <126000000>; opp-microvolt = <900000>; + clock-latency-ns = <40000>; }; opp-216000000 { opp-hz = /bits/ 64 <216000000>; diff --git a/arch/arm/boot/dts/rockchip/rv1108.dtsi b/arch/arm/boot/dts/rockchip/rv1108.dtsi index f3291f3bbc6f..42a4d72597a5 100644 --- a/arch/arm/boot/dts/rockchip/rv1108.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1108.dtsi @@ -32,7 +32,6 @@ cpu0: cpu@f00 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf00>; - clock-latency = <40000>; clocks = <&cru ARMCLK>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <75>; From patchwork Thu Apr 10 15:47:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880004 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD239290097; Thu, 10 Apr 2025 15:48:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300082; cv=none; b=aLV9yr0lY5YENj50WBR05c9ZqU056uBUUVc5sdD9CswXr4udDkC+AcfHiAi3PxNIhXnzDVAamcMB2Rfs8Cv3hInMATfu3e4sy15+YheEcV0NrqN7VVM25KRd7wnoF2ANUKu8kyDR6TYrb25UdejgHL5UYg07wOvnAD2y/hdo+RQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300082; c=relaxed/simple; bh=8YulZS5rVvSFRAgkgvbNbhZdIxjWTn1rNADsTiMIqPo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Dyi9pNURSRst5BeExhgdFJrQ0dbU0jsYZWF7VGEuXQFnLSzIOpwbY3gCGPxm5kYnPpPTdSru5hlitnobHk9zGZGYUkrXtn4SJwXEmQCTmtrmVhlfhJWxYSHSyA/xdJCtcC0dKF+3RKZeuz5rMK0/MUgkOpMAS29uZ1oC6pn9JgA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gUvlEuWx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gUvlEuWx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6395EC4CEDD; Thu, 10 Apr 2025 15:48:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300081; bh=8YulZS5rVvSFRAgkgvbNbhZdIxjWTn1rNADsTiMIqPo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=gUvlEuWx7kv4iuO/mJmzQu4q6ksnEITBeKHGfi+2NmS1Z1xOLAPF3734ouRBv3/b9 o4JioKZrSWgO5kgfFtIz61qfM4kgsZdoR+Tzo+gxEC0C6ipCFl0yFwUpzHNCEVx1CA IOZ0twEQYPFNlgojXiBVweBxXBWF7RZmTrve84Pp7IXijSZRGYVMHqErWVI6Bgj5J8 pEd1dU/HjDpEQnYuvCx8H4N2jh+xJbrGExt/dvKWopXgnEQ7dRoDGaFE6TVvwQ2+CG A7Ub40ZTax5520CtX1yDYlAIt/asqgPgQf0l0bBBUATZx4lJh6EQj/UhpXRFMAMny0 4Jdn7o/Z0+4vg== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:32 -0500 Subject: [PATCH v2 11/17] arm64: dts: amlogic: Drop redundant CPU "clock-latency" Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-11-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org X-Mailer: b4 0.15-dev The "clock-latency" property is part of the deprecated opp-v1 binding and is redundant if the opp-v2 table has equal or larger values in any "clock-latency-ns". Add any missing "clock-latency-ns" properties and remove "clock-latency". Signed-off-by: Rob Herring (Arm) Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts | 4 ---- arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts | 4 ---- arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts | 4 ---- arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 4 ---- arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts | 4 ---- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts | 6 ------ arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi | 2 ++ arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi | 6 ------ arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi | 6 ------ arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi | 6 ------ arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts | 6 ------ arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi | 6 ------ arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts | 6 ------ arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi | 2 ++ arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi | 6 ------ arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi | 4 ---- arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi | 4 ---- arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts | 4 ---- arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi | 4 ---- arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts | 4 ---- arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts | 4 ---- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 1 + 23 files changed, 6 insertions(+), 92 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts index 9aa36f17ffa2..d0a3b4b9229c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts @@ -267,28 +267,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; ðmac { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts index 952b8d02e5c2..4353485c6f26 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts @@ -220,28 +220,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts index 52fbc5103e45..f39fcabc763f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts @@ -314,28 +314,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts index 5407049d2647..b5bf8ecc91e6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts @@ -407,28 +407,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &clkc_audio { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts index 01da83658ae3..5ab460a3e637 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -263,28 +263,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 543e70669df5..deee61dbe074 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -62,6 +62,7 @@ cpu_opp_table: opp-table { opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <731000>; + clock-latency-ns = <50000>; }; opp-1200000000 { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts index adedc1340c78..415248931ab1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts @@ -76,42 +76,36 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu100 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu101 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu102 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu103 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &pwm_ab { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi index 8e9ad1e51d66..8ecb5bd125c1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi @@ -14,6 +14,7 @@ cpu_opp_table_0: opp-table-0 { opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <761000>; + clock-latency-ns = <50000>; }; opp-1200000000 { @@ -54,6 +55,7 @@ cpub_opp_table_1: opp-table-1 { opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <731000>; + clock-latency-ns = <50000>; }; opp-1200000000 { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi index 92e8b26ecccc..39011b645128 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi @@ -155,42 +155,36 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu100 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu101 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu102 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu103 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &ext_mdio { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi index 54663c55a20e..1b08303c4282 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi @@ -263,42 +263,36 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu100 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu101 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu102 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu103 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; ðmac { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi index 48650bad230d..fc737499f207 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi @@ -51,42 +51,36 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu100 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu101 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu102 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu103 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &pwm_ab { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts index e21831dfceee..d5938a4a6da3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts @@ -281,42 +281,36 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu100 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu101 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu102 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu103 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; /* RK817 only supports 12.5mV steps, round up the values */ diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi index 7e8964bacfce..3298d59833b6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi @@ -227,42 +227,36 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu100 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu101 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu102 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu103 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu_thermal { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts index fc05ecf90714..1e5c6f984945 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts @@ -259,42 +259,36 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu100 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu101 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu102 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu103 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu_thermal { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi index 44c23c984034..19cad93a6889 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi @@ -14,6 +14,7 @@ cpu_opp_table_0: opp-table-0 { opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <731000>; + clock-latency-ns = <50000>; }; opp-1200000000 { @@ -59,6 +60,7 @@ cpub_opp_table_1: opp-table-1 { opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <771000>; + clock-latency-ns = <50000>; }; opp-1200000000 { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi index a7a0fc264cdc..9b6d780eada7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi @@ -213,42 +213,36 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu100 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu101 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu102 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cpu103 { cpu-supply = <&vddcpu_a>; operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi index a3463149db3d..9be3084b090d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi @@ -147,28 +147,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi index 40db95f64636..538b35036954 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi @@ -185,28 +185,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; }; &ext_mdio { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts index 5d75ad3f3e46..a3d9b66b6878 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts @@ -51,28 +51,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; }; &pwm_AO_cd { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi index ad8d07883760..c4524eb4f099 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi @@ -250,28 +250,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; }; &ext_mdio { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts index 537370db360f..5daadfb170b4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts @@ -64,26 +64,22 @@ &cpu0 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu_b>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts index 37d7f64b6d5d..024d2eb8e6ee 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts @@ -359,28 +359,24 @@ &cpu0 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; }; &cpu1 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; }; &cpu2 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; }; &cpu3 { cpu-supply = <&vddcpu>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; }; ðmac { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 97e4b52066dc..966ebb19cc55 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -100,6 +100,7 @@ cpu_opp_table: opp-table { opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <770000>; + clock-latency-ns = <50000>; }; opp-1200000000 { From patchwork Thu Apr 10 15:47:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880824 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72C972900BE; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hvr+MRXW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 007AAC4CEDD; Thu, 10 Apr 2025 15:48:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300083; bh=08ZHSMoqcp6muzXlw3I6sj8QXRZ+fQyHgNMZj1SSrdY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=hvr+MRXWz6zZDqbGyKtarK07qSeX1tVPFXSoarGPEnD0U89TtphwqxdOSRLJUGR8s ijse85CijxUfmz4anXLpHxCZKbQPb/AX1QQ1dN4FedmWWau4+rvqXhgNFDAbFrPvhw YJWwW+1vted2FUTHOwDNhA8UGfbMx+nKhAZ19SWkUTR1SsMURjrv54YmGB6PV9SS9Z 1khj6/sx3iSVKSHhelpuYN7tfbIQtVcdGpfcBIKLpQ/MjxraUlaGtpNhleFxFwq1Ku QimonuVOeh0Zwbj5EUUOk5DYIoJ/qmzM2cUcj12IC6hrggz5lNM2kXaBE3kWR3MwXo cL4uCcB7HchBA== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:33 -0500 Subject: [PATCH v2 12/17] dt-bindings: arm/cpus: Add schemas for "enable-method" dependencies Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-12-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, Sudeep Holla X-Mailer: b4 0.15-dev Replace the prose for properties dependent on specific "enable-method" values with schemas defining the same requirements. Both "qcom,acc" and "qcom,saw" properties appear to be required for any of the Qualcomm enable-method values, so the schema is a bit simpler than what the text said. The properties are also needed on some Qualcomm platforms with other enable-method values. It's limited to Cortex A53 based platforms so use that to disable the properties. The references to arm/msm/qcom,saw2.txt and arm/msm/qcom,kpss-acc.txt are out of date, so just drop them. Signed-off-by: Rob Herring (Arm) Reviewed-by: Sudeep Holla --- v2: - Only disallow qcom,acc and qcom,saw on !cortex-a53 - Fix example in qcom,saw2.yaml --- Documentation/devicetree/bindings/arm/cpus.yaml | 91 ++++++++++++++-------- .../devicetree/bindings/soc/qcom/qcom,saw2.yaml | 3 +- 2 files changed, 60 insertions(+), 34 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 2e666b2a4dcd..351be2f77581 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -273,8 +273,6 @@ properties: description: The DT specification defines this as 64-bit always, but some 32-bit Arm systems have used a 32-bit value which must be supported. - Required for systems that have an "enable-method" - property value of "spin-table". cpu-idle-states: $ref: /schemas/types.yaml#/definitions/phandle-array @@ -333,24 +331,13 @@ properties: qcom,saw: $ref: /schemas/types.yaml#/definitions/phandle - description: | - Specifies the SAW* node associated with this CPU. - - Required for systems that have an "enable-method" property - value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" - - * arm/msm/qcom,saw2.txt + description: + Specifies the SAW node associated with this CPU. qcom,acc: $ref: /schemas/types.yaml#/definitions/phandle - description: | - Specifies the ACC* node associated with this CPU. - - Required for systems that have an "enable-method" property - value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or - "qcom,msm8916-smp". - - * arm/msm/qcom,kpss-acc.txt + description: + Specifies the ACC node associated with this CPU. rockchip,pmu: $ref: /schemas/types.yaml#/definitions/phandle @@ -378,22 +365,60 @@ properties: formed by encoding the target CPU id into the low bits of the physical start address it should jump to. -if: - # If the enable-method property contains one of those values - properties: - enable-method: - contains: - enum: - - brcm,bcm11351-cpu-method - - brcm,bcm23550 - - brcm,bcm-nsp-smp - # and if enable-method is present - required: - - enable-method - -then: - required: - - secondary-boot-reg +allOf: + - if: + # If the enable-method property contains one of those values + properties: + enable-method: + contains: + enum: + - brcm,bcm11351-cpu-method + - brcm,bcm23550 + - brcm,bcm-nsp-smp + # and if enable-method is present + required: + - enable-method + then: + required: + - secondary-boot-reg + - if: + properties: + enable-method: + enum: + - spin-table + - renesas,r9a06g032-smp + required: + - enable-method + then: + required: + - cpu-release-addr + - if: + properties: + enable-method: + enum: + - qcom,kpss-acc-v1 + - qcom,kpss-acc-v2 + - qcom,msm8226-smp + - qcom,msm8916-smp + required: + - enable-method + then: + required: + - qcom,acc + - qcom,saw + - if: + # 2 Qualcomm platforms bootloaders need qcom,acc and qcom,saw yet use + # "spin-table" or "psci" enable-methods. Disallowing the properties for + # all other CPUs is the best we can do as there's not any way to + # distinguish these Qualcomm platforms. + not: + properties: + compatible: + const: arm,cortex-a53 + then: + properties: + qcom,acc: false + qcom,saw: false required: - device_type diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index ca4bce817273..c2f1f5946cfa 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -73,9 +73,10 @@ examples: #size-cells = <0>; cpu@0 { - compatible = "qcom,kryo"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "qcom,kpss-acc-v2"; + qcom,acc = <&acc0>; qcom,saw = <&saw0>; reg = <0x0>; operating-points-v2 = <&cpu_opp_table>; From patchwork Thu Apr 10 15:47:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880003 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E3BF290BC3; Thu, 10 Apr 2025 15:48:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300085; cv=none; b=O0Ag1ugGxcFfpPTw98fxUz3gmnnevCIkWw8SbuaXchrKPrFqpbumWBbzXx/kbCKNULFxBcCim2/qvaF1IDKV2+YV1Mf6w/JN873lUSdSi/vLcz5QySyoR3vTHi+HusxHJIWDB59UwZdO4GURsHG1lpxXghvtJ+XBD/G39hkPtGM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300085; c=relaxed/simple; bh=dKAOoXa8SCYRYEZ5DexCu2UhSLqHH8rlgSZklM08q94=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oZt4nKbxjgTc3ZOTwZGbisxkQ+NVoFNAerHgwcmZAbIlBbHk3xsDPMbuMGnVAWnpgTDXrhtY0v0EyvD1toVvjdesCH6v8G6R6Fl/i5zSWgjvVuySaWoU9xL9j+4aa7mHunZdpovmsZi1F4wDccfypU4/i6KkPuki/L0i2H6Vm28= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l2gIODf+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l2gIODf+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 74791C4CEDD; Thu, 10 Apr 2025 15:48:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300084; bh=dKAOoXa8SCYRYEZ5DexCu2UhSLqHH8rlgSZklM08q94=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=l2gIODf+ANFVlqZ9CulzWNQFCDEoQRk9OTYtBUUUmUr+0KRxQ+QpqorLHa6YLWbl8 v3Oi2r0xr7ARSLLOMqYg5AZWNrArNFy1udHWR+bJVRxAxFquzbOBL3NmlJ561hNlLA fgqJ3BYhZfnGst0as+dG+23NMcPorSF+hKBPcg2XZk1HNLWkLkkH51tNlODcQCvckQ 4LSBDn59C62j13sYFO/xz4YPyXOa0LmbDztipsCo3yE50CeVEm/RfpOSRPmrotfBrH QjFjYrdKte/IjRM21kzYTJi9VvedUeiF+JT+R2BNFy99OSpj3GB9FUVaTetGmcoZq2 18/BEZEbZraOA== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:34 -0500 Subject: [PATCH v2 13/17] dt-bindings: arm/cpus: Re-wrap 'description' entries Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-13-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, Sudeep Holla X-Mailer: b4 0.15-dev Some of the 'description' entries have odd line wrapping and incorrect YAML block modifiers. The 'description' entries should typically wrap at 80 chars. Reformat the entries to follow that along with using '>' modifiers as appropriate. Signed-off-by: Rob Herring (Arm) Reviewed-by: Sudeep Holla --- Documentation/devicetree/bindings/arm/cpus.yaml | 85 +++++++++++-------------- 1 file changed, 36 insertions(+), 49 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 351be2f77581..acf38b3518dd 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -10,9 +10,9 @@ maintainers: - Lorenzo Pieralisi description: |+ - The device tree allows to describe the layout of CPUs in a system through - the "cpus" node, which in turn contains a number of subnodes (ie "cpu") - defining properties for every cpu. + The device tree allows to describe the layout of CPUs in a system through the + "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining + properties for every cpu. Bindings for CPU nodes follow the Devicetree Specification, available from: @@ -41,45 +41,40 @@ description: |+ properties: reg: maxItems: 1 - description: | - Usage and definition depend on ARM architecture version and - configuration: + description: > + Usage and definition depend on ARM architecture version and configuration: - On uniprocessor ARM architectures previous to v7 - this property is required and must be set to 0. + On uniprocessor ARM architectures previous to v7 this property is required + and must be set to 0. - On ARM 11 MPcore based systems this property is - required and matches the CPUID[11:0] register bits. + On ARM 11 MPcore based systems this property is required and matches the + CPUID[11:0] register bits. - Bits [11:0] in the reg cell must be set to - bits [11:0] in CPU ID register. + Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register. All other bits in the reg cell must be set to 0. - On 32-bit ARM v7 or later systems this property is - required and matches the CPU MPIDR[23:0] register - bits. + On 32-bit ARM v7 or later systems this property is required and matches + the CPU MPIDR[23:0] register bits. - Bits [23:0] in the reg cell must be set to - bits [23:0] in MPIDR. + Bits [23:0] in the reg cell must be set to bits [23:0] in MPIDR. All other bits in the reg cell must be set to 0. - On ARM v8 64-bit systems this property is required - and matches the MPIDR_EL1 register affinity bits. + On ARM v8 64-bit systems this property is required and matches the + MPIDR_EL1 register affinity bits. * If cpus node's #address-cells property is set to 2 - The first reg cell bits [7:0] must be set to - bits [39:32] of MPIDR_EL1. + The first reg cell bits [7:0] must be set to bits [39:32] of + MPIDR_EL1. - The second reg cell bits [23:0] must be set to - bits [23:0] of MPIDR_EL1. + The second reg cell bits [23:0] must be set to bits [23:0] of + MPIDR_EL1. * If cpus node's #address-cells property is set to 1 - The reg cell bits [23:0] must be set to bits [23:0] - of MPIDR_EL1. + The reg cell bits [23:0] must be set to bits [23:0] of MPIDR_EL1. All other bits in the reg cells must be set to 0. @@ -278,29 +273,26 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle-array items: maxItems: 1 - description: | - List of phandles to idle state nodes supported - by this cpu (see ./idle-states.yaml). + description: + List of phandles to idle state nodes supported by this cpu (see + ./idle-states.yaml). capacity-dmips-mhz: description: u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in - DMIPS/MHz, relative to highest capacity-dmips-mhz - in the system. + DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. cci-control-port: true dynamic-power-coefficient: $ref: /schemas/types.yaml#/definitions/uint32 - description: - A u32 value that represents the running time dynamic - power coefficient in units of uW/MHz/V^2. The - coefficient can either be calculated from power + description: > + A u32 value that represents the running time dynamic power coefficient in + units of uW/MHz/V^2. The coefficient can either be calculated from power measurements or derived by analysis. - The dynamic power consumption of the CPU is - proportional to the square of the Voltage (V) and - the clock frequency (f). The coefficient is used to + The dynamic power consumption of the CPU is proportional to the square of + the Voltage (V) and the clock frequency (f). The coefficient is used to calculate the dynamic power as below - Pdyn = dynamic-power-coefficient * V^2 * f @@ -309,10 +301,6 @@ properties: performance-domains: maxItems: 1 - description: - List of phandles and performance domain specifiers, as defined by - bindings of the performance domain provider. See also - dvfs/performance-domain.yaml. power-domains: description: @@ -341,22 +329,21 @@ properties: rockchip,pmu: $ref: /schemas/types.yaml#/definitions/phandle - description: | + description: > Specifies the syscon node controlling the cpu core power domains. - Optional for systems that have an "enable-method" - property value of "rockchip,rk3066-smp" - While optional, it is the preferred way to get access to - the cpu-core power-domains. + Optional for systems that have an "enable-method" property value of + "rockchip,rk3066-smp". While optional, it is the preferred way to get + access to the cpu-core power-domains. secondary-boot-reg: $ref: /schemas/types.yaml#/definitions/uint32 - description: | + description: > Required for systems that have an "enable-method" property value of "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". - This includes the following SoCs: | - BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 + This includes the following SoCs: + BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550, BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 The secondary-boot-reg property is a u32 value that specifies the From patchwork Thu Apr 10 15:47:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880823 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 510AF29344A; Thu, 10 Apr 2025 15:48:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300086; cv=none; b=HV5gHtifVp/Y2hQWea+OWOnOJnqPMXeCgIQ3Nyf3XCwgxzMUeeJSwKcnNOXjbI3wXHlPXu3Q430uNPWjeoNZIWC1cSBx+8xGnn07p3hh2DFO2YVfmn248GzHF9qhAZl2oo6aebpc3MgIiOR359ottY/XRbZAjC2GkJLvff1/0no= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300086; c=relaxed/simple; bh=d2xEle5JR0P+8ywA0siIkzQPF9OlhK/me+6AtXOc0AY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Osx311PQ79Mk5Phqr/2hx4+zu8QY5Fu5KOjVyuB3hCfv/ptXgakIsw2OAkM2187wHB3i7FZOIjd0DwR5MCAyFwyQgR79p7gpcsYaEugzvLPl2NFbzx0vI2uqlyRA7uqflbkFd41xrFC79k+6f0rg2KqRiIp4kIN3rARwexJ53yM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qg97LQXx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qg97LQXx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E4C31C4CEDD; Thu, 10 Apr 2025 15:48:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300086; bh=d2xEle5JR0P+8ywA0siIkzQPF9OlhK/me+6AtXOc0AY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qg97LQXxGV9ue31R3MdJVO2YsWgEzGw16N4u8DA8cSMGiQre4zl71TcotrYsR03/s qxPvL6r0xo8sAMHg/GmU2Ydh7pqHl4uCL4KwtnVRK4bZcRVsku0EjD5jyo920SnEgM 3YPNYEJKauEYI/YTN2EPPH9Sgs2M98xRB4VCeDSvhZ0XTwsK3MYnJyr5+oehnPZQPR x7DBrqvDUukbGMNLfanV1kuogiP7OWadByi5f7drA7qqyQOQ/TrgE8YzeedwdpTED9 TzmFsWHaGHmHPqL4Wkm1pjhIUHDaaOUuQh+21Lzzb9zRW9meTqoHS7x7RiG56MLbUg XAsxucDqzahhA== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:35 -0500 Subject: [PATCH v2 14/17] dt-bindings: Reference opp-v1 schema in CPU schemas Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-14-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, Viresh Kumar , Sudeep Holla X-Mailer: b4 0.15-dev The opp-v1 binding is only used in MIPS and arm32 CPU nodes, so add a $ref to it in the CPU schemas and drop the "select". As opp-v1 has long been deprecated, mark it as such. Signed-off-by: Rob Herring (Arm) Acked-by: Viresh Kumar Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sudeep Holla --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + Documentation/devicetree/bindings/mips/cpus.yaml | 3 ++- Documentation/devicetree/bindings/opp/opp-v1.yaml | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index acf38b3518dd..5af1396d631f 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -353,6 +353,7 @@ properties: physical start address it should jump to. allOf: + - $ref: /schemas/opp/opp-v1.yaml# - if: # If the enable-method property contains one of those values properties: diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml index a85137add668..471373ad0cfb 100644 --- a/Documentation/devicetree/bindings/mips/cpus.yaml +++ b/Documentation/devicetree/bindings/mips/cpus.yaml @@ -50,6 +50,7 @@ properties: device_type: true allOf: + - $ref: /schemas/opp/opp-v1.yaml# - if: properties: compatible: @@ -68,7 +69,7 @@ required: - compatible - reg -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/opp/opp-v1.yaml b/Documentation/devicetree/bindings/opp/opp-v1.yaml index 07e26c267815..1b59b103dab6 100644 --- a/Documentation/devicetree/bindings/opp/opp-v1.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v1.yaml @@ -18,7 +18,7 @@ description: |+ This binding only supports voltage-frequency pairs. -select: true +deprecated: true properties: operating-points: From patchwork Thu Apr 10 15:47:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880002 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEFB8293B54; Thu, 10 Apr 2025 15:48:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300088; cv=none; b=WEVQkRnx5gZeS92XVC8eIDZo3XOzNub38wTBQkYPLXMA0HK/f/xNHeYCuKg53C8ugVPqTK/naZFIht6zyNbTBgoFkF/gO+I0PfPEBnjW7iTgY6pwqperz6VATyLop+79E3QH36g8ksglwU/dAyS+CgNMvsBmNjGYVyz703o2t2k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300088; c=relaxed/simple; bh=TllkH9uFMCMy3fpbEojTrBhyQXHNcCjD8yUla2JfvUo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fXDs+Q+oYdyPGLShd199VCrXfB5iHB+NezjsKUg4hWCmLGK/btpfNDVxCB3crb6cp7UH31qFuy07BUC3nuh/zI+eUSwIaAhxe+fVFGfbK58/aSjmvSEudiunXSZFGlyGj9m/PN2npqu1fVrEoIH8lPKa6A97/1y73tpXkKTcIys= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sNAb1E5V; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sNAb1E5V" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7AA7BC4CEDD; Thu, 10 Apr 2025 15:48:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300087; bh=TllkH9uFMCMy3fpbEojTrBhyQXHNcCjD8yUla2JfvUo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=sNAb1E5VbKgvxSB5W3oXYM6325xj/OjVnNTVVDPRi2u7yWVdb5WhwxzWS3GnEI8IU QXfRiPgLCaC4MN87EoSVzc7bDHTOs4ov/CKCH9VUY2KNPFXJKR18ahp2xr8D2IVZgv cl7KHWg33at5mbc2qs8CfQaFuBtnK2XJ9D10oset4tdFmRUWcPuQL3NfdSk8wSegaA BegkCLM6ILpgSAtCD/PoTDG7BfGxhZ7m4gdEFhuVmedd9Dp3VnapsdudQww5uL9pBy +0RrwJFf84k44bfu2YJhTdWyGl7y/yqV2ZkgnYsMCv5AGyoSDscCPSW2Ow5DRLshbo i29dHN5eZOggw== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:36 -0500 Subject: [PATCH v2 15/17] dt-bindings: arm/cpus: Add missing properties Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-15-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, Sudeep Holla , Viresh Kumar X-Mailer: b4 0.15-dev The Arm CPU schema is missing a number of properties already in use. This has gone unnoticed as extra properties have not been restricted. Add a missing reference to cpu.yaml, and add all the missing properties. As "clock-latency" and "voltage-tolerance" are related to opp-v1, add those properties to the opp-v1.yaml schema. With this, other properties can be prevented from creeping in with 'unevaluatedProperties: false'. Signed-off-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sudeep Holla Acked-by: Viresh Kumar --- Documentation/devicetree/bindings/arm/cpus.yaml | 46 ++++++++++++++++++++++- Documentation/devicetree/bindings/opp/opp-v1.yaml | 16 ++++++++ 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 5af1396d631f..3846f13ded5b 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -299,6 +299,16 @@ properties: where voltage is in V, frequency is in MHz. + interconnects: + minItems: 1 + maxItems: 2 + + nvmem-cells: + maxItems: 1 + + nvmem-cell-names: + const: speed_grade + performance-domains: maxItems: 1 @@ -317,6 +327,31 @@ properties: corresponding to the index of an SCMI performance domain provider, must be "perf". + resets: + maxItems: 1 + + arm-supply: + deprecated: true + description: Use 'cpu-supply' instead + + cpu0-supply: + deprecated: true + description: Use 'cpu-supply' instead + + mem-supply: true + + proc-supply: + deprecated: true + description: Use 'cpu-supply' instead + + sram-supply: + deprecated: true + description: Use 'mem-supply' instead + + mediatek,cci: + $ref: /schemas/types.yaml#/definitions/phandle + description: Link to Mediatek Cache Coherent Interconnect + qcom,saw: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -327,6 +362,11 @@ properties: description: Specifies the ACC node associated with this CPU. + qcom,freq-domain: + description: Specifies the QCom CPUFREQ HW associated with the CPU. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + rockchip,pmu: $ref: /schemas/types.yaml#/definitions/phandle description: > @@ -352,7 +392,11 @@ properties: formed by encoding the target CPU id into the low bits of the physical start address it should jump to. + thermal-idle: + type: object + allOf: + - $ref: /schemas/cpu.yaml# - $ref: /schemas/opp/opp-v1.yaml# - if: # If the enable-method property contains one of those values @@ -416,7 +460,7 @@ required: dependencies: rockchip,pmu: [enable-method] -additionalProperties: true +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/opp/opp-v1.yaml b/Documentation/devicetree/bindings/opp/opp-v1.yaml index 1b59b103dab6..61c080e50859 100644 --- a/Documentation/devicetree/bindings/opp/opp-v1.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v1.yaml @@ -21,6 +21,18 @@ description: |+ deprecated: true properties: + clock-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The latency in nanoseconds for clock changes. Use OPP tables for new + designs instead. + + voltage-tolerance: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 10 + description: + The voltage tolerance in percent. Use OPP tables for new designs instead. + operating-points: $ref: /schemas/types.yaml#/definitions/uint32-matrix items: @@ -28,8 +40,12 @@ properties: - description: Frequency in kHz - description: Voltage for OPP in uV +dependencies: + clock-latency: [ operating-points ] + voltage-tolerance: [ operating-points ] additionalProperties: true + examples: - | cpus { From patchwork Thu Apr 10 15:47:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880822 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A83B29614C; Thu, 10 Apr 2025 15:48:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300089; cv=none; b=MlP9EMALdBVkOguGLvu8KsG6SeQjCSB+/Co0vjYfYhZsCO+53z6d7x6zZmzhhPOZMRFnJRa9ROTffZuAkFt1D0eBCd8+zpTA7oL+NBYJzk20G2vlKt7ab8gciZyXIq5wKsc+Qa9nFm+7Aw5uNEL8pqACOVuZ3HuTjkT+kz/4+fo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300089; c=relaxed/simple; bh=HIIKA21HRG0UMoa6Z5akxw0Rd/PBeaBOvNKebLyM4Fo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UWUXFqcSKmvRlRfGJzY90iCbczcmTin6UAPgr64u4BiPesLTdiPcTi4RbDOfu0NrJZOAwMz18+yV4dy4ehNQmK+y0xpmK7AUyOPIDrIACPYogBCf5ZdLF0/GmASS76VxzjB2Tt6MSON/0HULmFrEFdimsVtMOHn1KttuoT8dDnI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NDuyjHuA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NDuyjHuA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DDA26C4CEDD; Thu, 10 Apr 2025 15:48:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300089; bh=HIIKA21HRG0UMoa6Z5akxw0Rd/PBeaBOvNKebLyM4Fo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=NDuyjHuAfA6KjGorxG2uu7aOlrv9cSAfO+afdA6IkAmxInucrHnIseovaP9t5II0m WEz7WVg0CpzfebCU948awd0ZQYWGd26CUcmNyGgwMekzzuOjtl2t3erSWy0NrwsK01 O9aVDq1O5lzEvp118vPWAaGTJL2aZ0GRDYuY+0y+5BefpFipNwJU8SA3QbSmrtm16D jtoVcxXu62TgBYgsFNxHw6DCt2wJ6lNKnJOiwoFw3rN4TOTSjFsxWqp/b7Lbb5pJ1q vAHEgDd4YWmKnC9K7XAW3kppXIg3wtlTHcJIz56fq4wS/0dDVRJPw0M1gvO+6y6LdY lPwe8Fo4bUENA== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:37 -0500 Subject: [PATCH v2 16/17] dt-bindings: arm/cpus: Add power-domains constraints Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-16-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, Ulf Hansson , Sudeep Holla X-Mailer: b4 0.15-dev The "power-domains" and "power-domains-names" properties are missing any constraints. Add the constraints and drop the generic descriptions. Signed-off-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Ulf Hansson Reviewed-by: Sudeep Holla --- Documentation/devicetree/bindings/arm/cpus.yaml | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 3846f13ded5b..3d61313ca00e 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -313,19 +313,15 @@ properties: maxItems: 1 power-domains: - description: - List of phandles and PM domain specifiers, as defined by bindings of the - PM domain provider (see also ../power_domain.txt). + maxItems: 1 power-domain-names: description: - A list of power domain name strings sorted in the same order as the - power-domains property. - For PSCI based platforms, the name corresponding to the index of the PSCI PM domain provider, must be "psci". For SCMI based platforms, the name corresponding to the index of an SCMI performance domain provider, must be "perf". + enum: [ psci, perf, cpr ] resets: maxItems: 1 From patchwork Thu Apr 10 15:47:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 880001 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5C53296179; Thu, 10 Apr 2025 15:48:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300090; cv=none; b=jTxvYSDPtODN46dHTyHO1m3p5dNJN4mUlgKT7L6yM3Kv814KuX3VIxqxoTRIAxN9mcQbgjQ3G6JiYuaR/Mc5v8ORRka4C/8A1A7qfqyO7l4GlFuynXb+ITp1D9i7blrZP5qEPhKWEfOzYq3PYMfHl3Q9QEipvmHqecX4nFC+aUM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744300090; c=relaxed/simple; bh=8tfaaNZ4HrH7opoaFMg4/Qd0jHKomOYwuo5NwUKhvx0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=o6OC9b5c/+N5GMTQ5LbJtf7PzJ3I6fzGefSZ8txVUURU1i3yCfOZqYXc2CQFIf4aX4mTVJebpWaVGvzoakCL3pQ3qnBxxlTk1qYVb+C/sz9FS+7xBLFfKdFfJags/qIxcrw1ORGQa/9cfh3H0jKhyYAz8v4lc6ds0F6f/m6pzAw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=F07Lc4bp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F07Lc4bp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 50FF4C4CEDD; Thu, 10 Apr 2025 15:48:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744300090; bh=8tfaaNZ4HrH7opoaFMg4/Qd0jHKomOYwuo5NwUKhvx0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=F07Lc4bpt+yN+th4lZJNLUif9Vsbs8jnsVA6h1SEMAAxVrX+FL4/Au5KWenw+1DH9 BH6yiYIZmka6TMCrTmOJ6M1rp46sGn4toqpLPa+fzTNNn8OBVUk5tm+MrmGeLGtp4v 0t08uUIYAhHkGvs4IpQOEZEHXIojnzNcl2f+3yHjgP0JTy6xYRjxiWwtaTjbg95rz7 /uEl+E10tBzh5CvL3m6w6qy/ck4AJQjiwbobS6qZG66/NYkbJ1QRHlGCA8SAlCgNUE Ud/S2sHTPErUfalr4V9fg1m5v0/lTQklRsHgcL77c5S3/NmmfVOtoujb6pTEDjlGaj WsGZ5T9YPKZbQ== From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:38 -0500 Subject: [PATCH v2 17/17] dt-bindings: cpufreq: Drop redundant Mediatek binding Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250410-dt-cpu-schema-v2-17-63d7dc9ddd0a@kernel.org> References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Bjorn Andersson , Konrad Dybcio , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Andy Gross , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Dmitry Baryshkov , Stephan Gerhold Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-mips@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, Sudeep Holla , Viresh Kumar X-Mailer: b4 0.15-dev The Mediatek CPUFreq binding document just describes properties from the CPU node which the driver uses. This is redundant as all the properties are described in the arm/cpus.yaml schema. Signed-off-by: "Rob Herring (Arm)" Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sudeep Holla Acked-by: Viresh Kumar --- .../bindings/cpufreq/cpufreq-mediatek.txt | 250 --------------------- 1 file changed, 250 deletions(-) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt deleted file mode 100644 index e0a4ba599abc..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt +++ /dev/null @@ -1,250 +0,0 @@ -Binding for MediaTek's CPUFreq driver -===================================== - -Required properties: -- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names. -- clock-names: Should contain the following: - "cpu" - The multiplexer for clock input of CPU cluster. - "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock - source (usually MAINPLL) when the original CPU PLL is under - transition and not stable yet. - Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for - generic clock consumer properties. -- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml - for detail. -- proc-supply: Regulator for Vproc of CPU cluster. - -Optional properties: -- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver - needs to do "voltage tracking" to step by step scale up/down Vproc and - Vsram to fit SoC specific needs. When absent, the voltage scaling - flow is handled by hardware, hence no software "voltage tracking" is - needed. -- mediatek,cci: - Used to confirm the link status between cpufreq and mediatek cci. Because - cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs. - To prevent the issue of high frequency and low voltage, we need to use this - property to make sure mediatek cci is ready. - For details of mediatek cci, please refer to - Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml -- #cooling-cells: - For details, please refer to - Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml - -Example 1 (MT7623 SoC): - - cpu_opp_table: opp_table { - compatible = "operating-points-v2"; - opp-shared; - - opp-598000000 { - opp-hz = /bits/ 64 <598000000>; - opp-microvolt = <1050000>; - }; - - opp-747500000 { - opp-hz = /bits/ 64 <747500000>; - opp-microvolt = <1050000>; - }; - - opp-1040000000 { - opp-hz = /bits/ 64 <1040000000>; - opp-microvolt = <1150000>; - }; - - opp-1196000000 { - opp-hz = /bits/ 64 <1196000000>; - opp-microvolt = <1200000>; - }; - - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1300000>; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - clocks = <&infracfg CLK_INFRA_CPUSEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - operating-points-v2 = <&cpu_opp_table>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - operating-points-v2 = <&cpu_opp_table>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - operating-points-v2 = <&cpu_opp_table>; - }; - -Example 2 (MT8173 SoC): - cpu_opp_table_a: opp_table_a { - compatible = "operating-points-v2"; - opp-shared; - - opp-507000000 { - opp-hz = /bits/ 64 <507000000>; - opp-microvolt = <859000>; - }; - - opp-702000000 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <908000>; - }; - - opp-1001000000 { - opp-hz = /bits/ 64 <1001000000>; - opp-microvolt = <983000>; - }; - - opp-1105000000 { - opp-hz = /bits/ 64 <1105000000>; - opp-microvolt = <1009000>; - }; - - opp-1183000000 { - opp-hz = /bits/ 64 <1183000000>; - opp-microvolt = <1028000>; - }; - - opp-1404000000 { - opp-hz = /bits/ 64 <1404000000>; - opp-microvolt = <1083000>; - }; - - opp-1508000000 { - opp-hz = /bits/ 64 <1508000000>; - opp-microvolt = <1109000>; - }; - - opp-1573000000 { - opp-hz = /bits/ 64 <1573000000>; - opp-microvolt = <1125000>; - }; - }; - - cpu_opp_table_b: opp_table_b { - compatible = "operating-points-v2"; - opp-shared; - - opp-507000000 { - opp-hz = /bits/ 64 <507000000>; - opp-microvolt = <828000>; - }; - - opp-702000000 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <867000>; - }; - - opp-1001000000 { - opp-hz = /bits/ 64 <1001000000>; - opp-microvolt = <927000>; - }; - - opp-1209000000 { - opp-hz = /bits/ 64 <1209000000>; - opp-microvolt = <968000>; - }; - - opp-1404000000 { - opp-hz = /bits/ 64 <1007000000>; - opp-microvolt = <1028000>; - }; - - opp-1612000000 { - opp-hz = /bits/ 64 <1612000000>; - opp-microvolt = <1049000>; - }; - - opp-1807000000 { - opp-hz = /bits/ 64 <1807000000>; - opp-microvolt = <1089000>; - }; - - opp-1989000000 { - opp-hz = /bits/ 64 <1989000000>; - opp-microvolt = <1125000>; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x000>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA53SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_a>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x001>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA53SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_a>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA72SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_b>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA72SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_b>; - }; - - &cpu0 { - proc-supply = <&mt6397_vpca15_reg>; - }; - - &cpu1 { - proc-supply = <&mt6397_vpca15_reg>; - }; - - &cpu2 { - proc-supply = <&da9211_vcpu_reg>; - sram-supply = <&mt6397_vsramca7_reg>; - }; - - &cpu3 { - proc-supply = <&da9211_vcpu_reg>; - sram-supply = <&mt6397_vsramca7_reg>; - };