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Wysocki" , Praveen Talari , , , , , CC: , , , , , , , Nikunj Kela Subject: [PATCH v1 1/9] opp: add new helper API dev_pm_opp_set_level() Date: Thu, 10 Apr 2025 23:10:02 +0530 Message-ID: <20250410174010.31588-2-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250410174010.31588-1-quic_ptalari@quicinc.com> References: <20250410174010.31588-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: J97y74t0Yo913xGJERyN2HHWKUm__JQP X-Authority-Analysis: v=2.4 cv=T7OMT+KQ c=1 sm=1 tr=0 ts=67f8029d cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=m4zHK0A4y4sg-DzA2o0A:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: J97y74t0Yo913xGJERyN2HHWKUm__JQP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-10_05,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 phishscore=0 bulkscore=0 mlxscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 spamscore=0 clxscore=1011 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100127 From: Nikunj Kela To configure a device to a specific performance level, consumer drivers currently need to determine the OPP based on the exact level and then set it, resulting in code duplication across drivers. The new helper API, dev_pm_opp_set_level(), addresses this issue by providing a streamlined method for consumer drivers to find and set the OPP based on the desired performance level, thereby eliminating redundancy. Co-developed-by: Praveen Talari Signed-off-by: Praveen Talari Signed-off-by: Nikunj Kela --- drivers/opp/core.c | 22 ++++++++++++++++++++++ include/linux/pm_opp.h | 6 ++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 73e9a3b2f29b..a9bca9502f71 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -3151,3 +3151,25 @@ void dev_pm_opp_remove_table(struct device *dev) dev_pm_opp_put_opp_table(opp_table); } EXPORT_SYMBOL_GPL(dev_pm_opp_remove_table); + +/* + * dev_pm_opp_set_level() - Configure device for a level + * @dev: device for which we do this operation + * @level: level to set to + * + * Return: 0 on success, a negative error number otherwise. + */ +int dev_pm_opp_set_level(struct device *dev, unsigned int level) +{ + struct dev_pm_opp *opp = dev_pm_opp_find_level_exact(dev, level); + int ret; + + if (IS_ERR(opp)) + return -EINVAL; + + ret = dev_pm_opp_set_opp(dev, opp); + dev_pm_opp_put(opp); + + return ret; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_set_level); diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index c247317aae38..c17271947f83 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -196,6 +196,7 @@ int dev_pm_opp_get_sharing_cpus(struct device *cpu_dev, struct cpumask *cpumask) void dev_pm_opp_remove_table(struct device *dev); void dev_pm_opp_cpumask_remove_table(const struct cpumask *cpumask); int dev_pm_opp_sync_regulators(struct device *dev); +int dev_pm_opp_set_level(struct device *dev, unsigned int level); #else static inline struct opp_table *dev_pm_opp_get_opp_table(struct device *dev) { @@ -454,6 +455,11 @@ static inline int dev_pm_opp_sync_regulators(struct device *dev) return -EOPNOTSUPP; } +static inline int dev_pm_opp_set_level(struct device *dev, unsigned int level) +{ + return -EOPNOTSUPP; +} + #endif /* CONFIG_PM_OPP */ #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_PM_OPP) From patchwork Thu Apr 10 17:40:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Talari X-Patchwork-Id: 879999 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A1D028A40E; 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Wysocki" , Praveen Talari , , , , , CC: , , , , , , , Nikunj Kela Subject: [PATCH v1 2/9] dt-bindings: serial: describe SA8255p Date: Thu, 10 Apr 2025 23:10:03 +0530 Message-ID: <20250410174010.31588-3-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250410174010.31588-1-quic_ptalari@quicinc.com> References: <20250410174010.31588-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: VA5DFFa_9IKVQs_lBtzx_u1ol7zKrsaF X-Proofpoint-ORIG-GUID: VA5DFFa_9IKVQs_lBtzx_u1ol7zKrsaF X-Authority-Analysis: v=2.4 cv=dbeA3WXe c=1 sm=1 tr=0 ts=67f802a5 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=XR8D0OoHHMoA:10 a=gEfo2CItAAAA:8 a=COk6AnOGAAAA:8 a=rjx3OjMNV77wTL7fGyAA:9 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-10_05,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 mlxlogscore=999 phishscore=0 mlxscore=0 spamscore=0 malwarescore=0 clxscore=1011 adultscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100127 From: Nikunj Kela SA8255p platform abstracts resources such as clocks, interconnect and GPIO pins configuration in Firmware. SCMI power and perf protocols are used to send request for resource configurations. Add DT bindings for the QUP GENI UART controller on sa8255p platform. Co-developed-by: Praveen Talari Signed-off-by: Praveen Talari Signed-off-by: Nikunj Kela Signed-off-by: Nikunj Kela Signed-off-by: Praveen Talari --- .../serial/qcom,sa8255p-geni-uart.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml diff --git a/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml b/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml new file mode 100644 index 000000000000..0dbfbfa1d504 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/qcom,sa8255p-geni-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Geni based QUP UART interface + +maintainers: + - Praveen Talari + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + enum: + - qcom,sa8255p-geni-uart + - qcom,sa8255p-geni-debug-uart + + interrupts: + minItems: 1 + items: + - description: UART core irq + - description: Wakeup irq (RX GPIO) + + power-domains: + minItems: 2 + maxItems: 2 + + power-domain-names: + items: + - const: power + - const: perf + + reg: + maxItems: 1 + +required: + - compatible + - interrupts + - reg + - power-domains + - power-domain-names + +unevaluatedProperties: false + +examples: + - | + #include + + serial@990000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x990000 0x4000>; + interrupts = ; + power-domains = <&scmi0_pd 0>, <&scmi0_dvfs 0>; + power-domain-names = "power", "perf"; + }; +... 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Wysocki" , Praveen Talari , , , , , CC: , , , , , , , Nikunj Kela Subject: [PATCH v1 3/9] dt-bindings: qcom: geni-se: describe SA8255p Date: Thu, 10 Apr 2025 23:10:04 +0530 Message-ID: <20250410174010.31588-4-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250410174010.31588-1-quic_ptalari@quicinc.com> References: <20250410174010.31588-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: tqIpBGFNwoavirgIP5IjS_AINHPb3hR6 X-Proofpoint-GUID: tqIpBGFNwoavirgIP5IjS_AINHPb3hR6 X-Authority-Analysis: v=2.4 cv=NaLm13D4 c=1 sm=1 tr=0 ts=67f802ad cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=XR8D0OoHHMoA:10 a=gEfo2CItAAAA:8 a=COk6AnOGAAAA:8 a=s2ejLvL1BUKWkZXtkIwA:9 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-10_05,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 priorityscore=1501 adultscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 clxscore=1011 phishscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100127 From: Nikunj Kela SA8255p platform abstracts resources such as clocks, interconnect configuration in Firmware. Add DT bindings for the QUP Wrapper on sa8255p platform. Co-developed-by: Praveen Talari Signed-off-by: Praveen Talari Signed-off-by: Nikunj Kela --- .../soc/qcom/qcom,sa8255p-geni-se-qup.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml new file mode 100644 index 000000000000..cdc2e032f570 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,sa8255p-geni-se-qup.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GENI Serial Engine QUP Wrapper Controller + +maintainers: + - Praveen Talari + +description: + Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper + is a programmable module for supporting a wide range of serial interfaces + like UART, SPI, I2C, I3C, etc. A single QUP module can provide up to 8 Serial + Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP + Wrapper controller is modeled as a node with zero or more child nodes each + representing a serial engine. + +properties: + compatible: + const: qcom,sa8255p-geni-se-qup + + reg: + description: QUP wrapper common register address and length. + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + iommus: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +patternProperties: + "spi@[0-9a-f]+$": + type: object + description: GENI serial engine based SPI controller. SPI in master mode + supports up to 50MHz, up to four chip selects, programmable + data path from 4 bits to 32 bits and numerous protocol + variants. + additionalProperties: true + + properties: + compatible: + const: qcom,sa8255p-geni-spi + + "i2c@[0-9a-f]+$": + type: object + description: GENI serial engine based I2C controller. + additionalProperties: true + + properties: + compatible: + const: qcom,sa8255p-geni-i2c + + "serial@[0-9a-f]+$": + type: object + description: GENI Serial Engine based UART Controller. + additionalProperties: true + + properties: + compatible: + const: qcom,sa8255p-geni-uart + +additionalProperties: false + +examples: + - | + #include + + geniqup@9c0000 { + compatible = "qcom,sa8255p-geni-se-qup"; + reg = <0 0x9c0000 0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + serial@990000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0 0x990000 0 0x4000>; + interrupts = ; + power-domains = <&scmi0_pd 0>, <&scmi0_dvfs 0>; + power-domain-names = "power", "perf"; + }; + }; +... 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Wysocki" , Praveen Talari , , , , , CC: , , , , , , Subject: [PATCH v1 4/9] soc: qcom: geni-se: Enable QUPs on SA8255p Qualcomm platforms Date: Thu, 10 Apr 2025 23:10:05 +0530 Message-ID: <20250410174010.31588-5-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250410174010.31588-1-quic_ptalari@quicinc.com> References: <20250410174010.31588-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: PgkW7RIMOdxFQMLho6VLk1ewC8U0ptug X-Proofpoint-GUID: PgkW7RIMOdxFQMLho6VLk1ewC8U0ptug X-Authority-Analysis: v=2.4 cv=NaLm13D4 c=1 sm=1 tr=0 ts=67f802b4 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=-8ewQQW4l5uToJikuzQA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-10_05,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 priorityscore=1501 adultscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 phishscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100127 On the sa8255p platform, resources such as clocks,interconnects and TLMM (GPIO) configurations are managed by firmware. Introduce a platform data function callback to distinguish whether resource control is performed by firmware or directly by the driver in linux. The refactor ensures clear differentiation of resource management mechanisms, improving maintainability and flexibility in handling platform-specific configurations. Signed-off-by: Praveen Talari --- drivers/soc/qcom/qcom-geni-se.c | 78 +++++++++++++++++++++------------ 1 file changed, 50 insertions(+), 28 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 4cb959106efa..5e2add1e04d3 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -105,6 +105,8 @@ struct geni_wrapper { struct geni_se_desc { unsigned int num_clks; const char * const *clks; + int (*geni_se_rsc_init)(struct geni_wrapper *wrapper, + const struct geni_se_desc *desc); }; static const char * const icc_path_names[] = {"qup-core", "qup-config", @@ -891,10 +893,44 @@ int geni_icc_disable(struct geni_se *se) } EXPORT_SYMBOL_GPL(geni_icc_disable); +static int geni_se_resource_init(struct geni_wrapper *wrapper, + const struct geni_se_desc *desc) +{ + struct device *dev = wrapper->dev; + int ret; + int i; + + wrapper->num_clks = min_t(unsigned int, desc->num_clks, MAX_CLKS); + + for (i = 0; i < wrapper->num_clks; ++i) + wrapper->clks[i].id = desc->clks[i]; + + ret = of_count_phandle_with_args(dev->of_node, "clocks", "#clock-cells"); + if (ret < 0) { + dev_err(dev, "invalid clocks property at %pOF\n", dev->of_node); + return ret; + } + + if (ret < wrapper->num_clks) { + dev_err(dev, "invalid clocks count at %pOF, expected %d entries\n", + dev->of_node, wrapper->num_clks); + return -EINVAL; + } + + ret = devm_clk_bulk_get(dev, wrapper->num_clks, wrapper->clks); + if (ret) { + dev_err(dev, "Err getting clks %d\n", ret); + return ret; + } + + return ret; +} + static int geni_se_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct geni_wrapper *wrapper; + const struct geni_se_desc *desc; int ret; wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL); @@ -906,38 +942,15 @@ static int geni_se_probe(struct platform_device *pdev) if (IS_ERR(wrapper->base)) return PTR_ERR(wrapper->base); - if (!has_acpi_companion(&pdev->dev)) { - const struct geni_se_desc *desc; - int i; - - desc = device_get_match_data(&pdev->dev); - if (!desc) - return -EINVAL; - - wrapper->num_clks = min_t(unsigned int, desc->num_clks, MAX_CLKS); - - for (i = 0; i < wrapper->num_clks; ++i) - wrapper->clks[i].id = desc->clks[i]; - - ret = of_count_phandle_with_args(dev->of_node, "clocks", "#clock-cells"); - if (ret < 0) { - dev_err(dev, "invalid clocks property at %pOF\n", dev->of_node); - return ret; - } + desc = device_get_match_data(&pdev->dev); - if (ret < wrapper->num_clks) { - dev_err(dev, "invalid clocks count at %pOF, expected %d entries\n", - dev->of_node, wrapper->num_clks); + if (!has_acpi_companion(&pdev->dev) && desc->geni_se_rsc_init) { + ret = desc->geni_se_rsc_init(wrapper, desc); + if (ret) return -EINVAL; - } - - ret = devm_clk_bulk_get(dev, wrapper->num_clks, wrapper->clks); - if (ret) { - dev_err(dev, "Err getting clks %d\n", ret); - return ret; - } } +out: dev_set_drvdata(dev, wrapper); dev_dbg(dev, "GENI SE Driver probed\n"); return devm_of_platform_populate(dev); @@ -951,6 +964,13 @@ static const char * const qup_clks[] = { static const struct geni_se_desc qup_desc = { .clks = qup_clks, .num_clks = ARRAY_SIZE(qup_clks), + .geni_se_rsc_init = geni_se_resource_init, +}; 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Wysocki" , Praveen Talari , , , , , CC: , , , , , , Subject: [PATCH v1 5/9] serial: qcom-geni: move resource initialization to separate functions Date: Thu, 10 Apr 2025 23:10:06 +0530 Message-ID: <20250410174010.31588-6-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250410174010.31588-1-quic_ptalari@quicinc.com> References: <20250410174010.31588-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: llUCm-ZZeIokyzqlQinJvkYfGYJAZDIX X-Authority-Analysis: v=2.4 cv=LLlmQIW9 c=1 sm=1 tr=0 ts=67f802bb cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=0DDkC8yEFXPSaA7UoRYA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: llUCm-ZZeIokyzqlQinJvkYfGYJAZDIX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-10_05,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 malwarescore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 adultscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100127 Enhances code readability and future modifications within the new API. Move the code that handles the actual initialization of resources like clock and ICC paths to a separate function, making the probe function cleaner. Signed-off-by: Praveen Talari --- drivers/tty/serial/qcom_geni_serial.c | 65 ++++++++++++++++----------- 1 file changed, 39 insertions(+), 26 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index a80ce7aaf309..889ce8961e0a 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1572,6 +1572,42 @@ static struct uart_driver qcom_geni_uart_driver = { .nr = GENI_UART_PORTS, }; +static int geni_serial_resource_init(struct qcom_geni_serial_port *port) +{ + int ret; + + port->se.clk = devm_clk_get(port->se.dev, "se"); + if (IS_ERR(port->se.clk)) { + ret = PTR_ERR(port->se.clk); + dev_err(port->se.dev, "Err getting SE Core clk %d\n", ret); + return ret; + } + + ret = geni_icc_get(&port->se, NULL); + if (ret) + return ret; + + port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; + port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; + + /* Set BW for register access */ + ret = geni_icc_set_bw(&port->se); + if (ret) + return ret; + + ret = devm_pm_opp_set_clkname(port->se.dev, "se"); + if (ret) + return ret; + + /* OPP table is optional */ + ret = devm_pm_opp_of_add_table(port->se.dev); + if (ret && ret != -ENODEV) { + dev_err(port->se.dev, "invalid OPP table in device tree\n"); + return ret; + } + + return 0; +} static void qcom_geni_serial_pm(struct uart_port *uport, unsigned int new_state, unsigned int old_state) { @@ -1674,12 +1710,10 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) port->dev_data = data; port->se.dev = &pdev->dev; port->se.wrapper = dev_get_drvdata(pdev->dev.parent); - port->se.clk = devm_clk_get(&pdev->dev, "se"); - if (IS_ERR(port->se.clk)) { - ret = PTR_ERR(port->se.clk); - dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); + + ret = geni_serial_resource_init(port); + if (ret) return ret; - } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) @@ -1697,17 +1731,6 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) return -ENOMEM; } - ret = geni_icc_get(&port->se, NULL); - if (ret) - return ret; - port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; - port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; - - /* Set BW for register access */ - ret = geni_icc_set_bw(&port->se); - if (ret) - return ret; - port->name = devm_kasprintf(uport->dev, GFP_KERNEL, "qcom_geni_serial_%s%d", uart_console(uport) ? "console" : "uart", uport->line); @@ -1729,16 +1752,6 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) port->cts_rts_swap = true; - ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); - if (ret) - return ret; - /* OPP table is optional */ - ret = devm_pm_opp_of_add_table(&pdev->dev); - if (ret && ret != -ENODEV) { - dev_err(&pdev->dev, "invalid OPP table in device tree\n"); - return ret; - } - port->private_data.drv = drv; uport->private_data = &port->private_data; platform_set_drvdata(pdev, port); From patchwork Thu Apr 10 17:40:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Talari X-Patchwork-Id: 879997 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13F5B1EDA08; Thu, 10 Apr 2025 17:41:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744306889; cv=none; b=NS6xzYt9nqcUNDd7KKFx3HCtg5aYcg9pEyQS3sGUVz/eJ2liCoohYdNqoLH9Sq33YXSpCZ66CNfaPX0b2UuwfCPKy1efZL8rom+krN3SgbTuRqStKros3/KlEtWMJWor5XX2FU1yhucgWqEq46hgOYJ6R/LBSFqiiPkrWGXmCDI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744306889; c=relaxed/simple; bh=TqAlJB4xv+wYZZWP3oLDnvztznoItIfeLo7p1nnPVQQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bG0vsJpuqNT7k/YqiOaV52sROPAWcafp1b1k9a7T/bXnxCtzJyIK/b1YegV53M4wIh6q6Jt72NBRxRc/uHZjzee8LIbnZr+CU/2oe6/U06O7b/SVk++EBtUy1tvJ3sWuU+p2rytL4iF5/TCxGHcexDegKRRn8Zr8rZ8MwppU6w4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=lEu/0Iz9; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="lEu/0Iz9" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53AG14qR000661; Thu, 10 Apr 2025 17:41:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to; s=qcppdkim1; bh=qHaLMf2xSqzmUJ8P5zqxTmml 8zMmJl9pNciHZcM3sBo=; b=lEu/0Iz9OX3ehpDrfKO1R+REZv2Iuv/tCT8BZP9g BIH3PfOIPEWS51Zpr9MSOCCO52LHsizawtk1WcCqnmNBO5bigKiJLy+V1F8kc2bR hGvJyw7eUkvNtUEOt754JugoXd5CNwsiRVR7mz7olpqBi8ynI9W9cIqApteYgIId KrAqeYaBG5mrKleZT7TdrpKQicTJwvRfJWgO/pTJINGt0L7DK8iMdW+tFdsB7izV vwNm8Y2tHYOgsf/i9PwkGnUcxVaDsnRBwzCuLI4oYYRunc/JRUNtUqGwZ/sHGnzT B6kZoNZyCkxO8nQ467XGktkNo/92kgNk4u9KoNh90yBYJQ== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45twd2yu60-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Apr 2025 17:41:23 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53AHfMR1008427 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Apr 2025 17:41:23 GMT Received: from hu-ptalari-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 10 Apr 2025 10:41:16 -0700 From: Praveen Talari To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Viresh Kumar , Nishanth Menon , Stephen Boyd , "Rafael J. Wysocki" , Praveen Talari , , , , , CC: , , , , , , Subject: [PATCH v1 6/9] serial: qcom-geni: move resource control logic to separate functions Date: Thu, 10 Apr 2025 23:10:07 +0530 Message-ID: <20250410174010.31588-7-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250410174010.31588-1-quic_ptalari@quicinc.com> References: <20250410174010.31588-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Z9YyMHW8Em7HYVs6D1eZhFWmf1On43Wd X-Proofpoint-GUID: Z9YyMHW8Em7HYVs6D1eZhFWmf1On43Wd X-Authority-Analysis: v=2.4 cv=NaLm13D4 c=1 sm=1 tr=0 ts=67f802c3 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=HYIVWE9JnHk2aDURxZAA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-10_05,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 priorityscore=1501 adultscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 phishscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100127 Supports use in PM system/runtime frameworks, helping to distinguish new resource control mechanisms and facilitate future modifications within the new API. The code that handles the actual enable or disable of resources like clock and ICC paths to a separate function (geni_serial_resources_on() and geni_serial_resources_off()) which enhances code readability. Signed-off-by: Praveen Talari --- drivers/tty/serial/qcom_geni_serial.c | 53 +++++++++++++++++++++------ 1 file changed, 42 insertions(+), 11 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 889ce8961e0a..e341f5090ecc 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1572,6 +1572,42 @@ static struct uart_driver qcom_geni_uart_driver = { .nr = GENI_UART_PORTS, }; +static int geni_serial_resources_off(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + int ret; + + dev_pm_opp_set_rate(uport->dev, 0); + ret = geni_se_resources_off(&port->se); + if (ret) + return ret; + + geni_icc_disable(&port->se); + + return ret; +} + +static int geni_serial_resources_on(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + int ret; + + ret = geni_icc_enable(&port->se); + if (ret) + return ret; + + ret = geni_se_resources_on(&port->se); + if (ret) { + geni_icc_disable(&port->se); + return ret; + } + + if (port->clk_rate) + dev_pm_opp_set_rate(uport->dev, port->clk_rate); + + return ret; +} + static int geni_serial_resource_init(struct qcom_geni_serial_port *port) { int ret; @@ -1617,17 +1653,12 @@ static void qcom_geni_serial_pm(struct uart_port *uport, if (old_state == UART_PM_STATE_UNDEFINED) old_state = UART_PM_STATE_OFF; - if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { - geni_icc_enable(&port->se); - if (port->clk_rate) - dev_pm_opp_set_rate(uport->dev, port->clk_rate); - geni_se_resources_on(&port->se); - } else if (new_state == UART_PM_STATE_OFF && - old_state == UART_PM_STATE_ON) { - geni_se_resources_off(&port->se); - dev_pm_opp_set_rate(uport->dev, 0); - geni_icc_disable(&port->se); - } + if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) + geni_serial_resources_on(uport); + else if (new_state == UART_PM_STATE_OFF && + old_state == UART_PM_STATE_ON) + geni_serial_resources_off(uport); + } static const struct uart_ops qcom_geni_console_pops = { From patchwork Thu Apr 10 17:40:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Talari X-Patchwork-Id: 880817 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 718A7284B22; Thu, 10 Apr 2025 17:41:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744306899; cv=none; b=RAV7GEVuclLQXdd37F8gt5/BLBmK6fkSX2UvITvMo6HwmF6wZ8kgjU26xIbfM2XzfZ+gvXCeOOFMlkoqavk62DcMER2auRqlVJf3GTptKWdSDfRmvP8HRV+2Z2dHIp6uoF7Qb+dOMql/jKNiHrA9mJNtHZ3s+SiRdhz/LB+xzRg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744306899; 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Wysocki" , Praveen Talari , , , , , CC: , , , , , , Subject: [PATCH v1 7/9] serial: qcom-geni: move clock-rate logic to separate function Date: Thu, 10 Apr 2025 23:10:08 +0530 Message-ID: <20250410174010.31588-8-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250410174010.31588-1-quic_ptalari@quicinc.com> References: <20250410174010.31588-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=PJgP+eqC c=1 sm=1 tr=0 ts=67f802cb cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=X08zvMDfRsL5Z2rP0xYA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: TjeekzzRTy2YOCH0p9IUFFUOhu7zGnZA X-Proofpoint-GUID: TjeekzzRTy2YOCH0p9IUFFUOhu7zGnZA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-10_05,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 clxscore=1011 adultscore=0 malwarescore=0 spamscore=0 impostorscore=0 suspectscore=0 mlxlogscore=999 bulkscore=0 mlxscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100127 Facilitates future modifications within the new function, leading to better readability and maintainability of the code. Move the code that handles the actual logic of clock-rate calculations to a separate function geni_serial_set_rate() which enhances code readability. Signed-off-by: Praveen Talari --- drivers/tty/serial/qcom_geni_serial.c | 56 +++++++++++++++++---------- 1 file changed, 36 insertions(+), 20 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index e341f5090ecc..25d16ac3f406 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1267,27 +1267,14 @@ static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud, return ser_clk; } -static void qcom_geni_serial_set_termios(struct uart_port *uport, - struct ktermios *termios, - const struct ktermios *old) +static int geni_serial_set_rate(struct uart_port *uport, unsigned long baud) { - unsigned int baud; - u32 bits_per_char; - u32 tx_trans_cfg; - u32 tx_parity_cfg; - u32 rx_trans_cfg; - u32 rx_parity_cfg; - u32 stop_bit_len; - unsigned int clk_div; - u32 ser_clk_cfg; struct qcom_geni_serial_port *port = to_dev_port(uport); unsigned long clk_rate; - u32 ver, sampling_rate; unsigned int avg_bw_core; - unsigned long timeout; - - /* baud rate */ - baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); + unsigned int clk_div; + u32 ver, sampling_rate; + u32 ser_clk_cfg; sampling_rate = UART_OVERSAMPLING; /* Sampling rate is halved for IP versions >= 2.5 */ @@ -1301,7 +1288,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, dev_err(port->se.dev, "Couldn't find suitable clock rate for %u\n", baud * sampling_rate); - return; + return -EINVAL; } dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n", @@ -1323,6 +1310,37 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); geni_icc_set_bw(&port->se); + writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); + writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); + return 0; +} + +static void qcom_geni_serial_set_termios(struct uart_port *uport, + struct ktermios *termios, + const struct ktermios *old) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + unsigned int baud; + unsigned long timeout; + u32 bits_per_char; + u32 tx_trans_cfg; + u32 tx_parity_cfg; + u32 rx_trans_cfg; + u32 rx_parity_cfg; + u32 stop_bit_len; + int ret = 0; + + /* baud rate */ + baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); + + ret = geni_serial_set_rate(uport, baud); + if (ret) { + dev_err(port->se.dev, + "%s: Failed to set baud: %u ret: %d\n", + __func__, baud, ret); + return; + } + /* parity */ tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); @@ -1390,8 +1408,6 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); - writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); - writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); } #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE From patchwork Thu Apr 10 17:40:09 2025 Content-Type: text/plain; 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Wysocki" , Praveen Talari , , , , , CC: , , , , , , Subject: [PATCH v1 8/9] serial: qcom-geni: Enable PM runtime for serial driver Date: Thu, 10 Apr 2025 23:10:09 +0530 Message-ID: <20250410174010.31588-9-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250410174010.31588-1-quic_ptalari@quicinc.com> References: <20250410174010.31588-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: SgJX610SjsQI99skK9Do0JskZVxvT7iS X-Authority-Analysis: v=2.4 cv=QuVe3Uyd c=1 sm=1 tr=0 ts=67f802d3 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=NvXbtCnAfBVqmBDmsI8A:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: SgJX610SjsQI99skK9Do0JskZVxvT7iS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-10_05,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501 clxscore=1015 phishscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100127 Add Power Management (PM) runtime support to Qualcomm GENI serial driver. Introduce necessary callbacks and updates to ensure seamless transitions between power states, enhancing overall power efficiency. Signed-off-by: Praveen Talari --- drivers/tty/serial/qcom_geni_serial.c | 35 ++++++++++++++++++++++----- 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 25d16ac3f406..9649297d4a9e 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1663,17 +1663,15 @@ static int geni_serial_resource_init(struct qcom_geni_serial_port *port) static void qcom_geni_serial_pm(struct uart_port *uport, unsigned int new_state, unsigned int old_state) { - struct qcom_geni_serial_port *port = to_dev_port(uport); - /* If we've never been called, treat it as off */ if (old_state == UART_PM_STATE_UNDEFINED) old_state = UART_PM_STATE_OFF; if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) - geni_serial_resources_on(uport); + pm_runtime_resume_and_get(uport->dev); else if (new_state == UART_PM_STATE_OFF && old_state == UART_PM_STATE_ON) - geni_serial_resources_off(uport); + pm_runtime_put_sync(uport->dev); } @@ -1811,9 +1809,11 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) return ret; } + pm_runtime_enable(port->se.dev); + ret = uart_add_one_port(drv, uport); if (ret) - return ret; + goto error; if (port->wakeup_irq > 0) { device_init_wakeup(&pdev->dev, true); @@ -1822,11 +1822,15 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) if (ret) { device_init_wakeup(&pdev->dev, false); uart_remove_one_port(drv, uport); - return ret; + goto error; } } return 0; + +error: + pm_runtime_disable(port->se.dev); + return ret; } static void qcom_geni_serial_remove(struct platform_device *pdev) @@ -1836,9 +1840,26 @@ static void qcom_geni_serial_remove(struct platform_device *pdev) dev_pm_clear_wake_irq(&pdev->dev); device_init_wakeup(&pdev->dev, false); + pm_runtime_disable(port->se.dev); uart_remove_one_port(drv, &port->uport); } +static int qcom_geni_serial_runtime_suspend(struct device *dev) +{ + struct qcom_geni_serial_port *port = dev_get_drvdata(dev); + struct uart_port *uport = &port->uport; + + return geni_serial_resources_off(uport); +}; + +static int qcom_geni_serial_runtime_resume(struct device *dev) +{ + struct qcom_geni_serial_port *port = dev_get_drvdata(dev); + struct uart_port *uport = &port->uport; + + return geni_serial_resources_on(uport); +}; + static int qcom_geni_serial_suspend(struct device *dev) { struct qcom_geni_serial_port *port = dev_get_drvdata(dev); @@ -1882,6 +1903,8 @@ static const struct qcom_geni_device_data qcom_geni_uart_data = { }; static const struct dev_pm_ops qcom_geni_serial_pm_ops = { + SET_RUNTIME_PM_OPS(qcom_geni_serial_runtime_suspend, + qcom_geni_serial_runtime_resume, NULL) SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_suspend, qcom_geni_serial_resume) }; From patchwork Thu Apr 10 17:40:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Talari X-Patchwork-Id: 880816 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07C2A293B53; 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Wysocki" , Praveen Talari , , , , , CC: , , , , , , Subject: [PATCH v1 9/9] serial: qcom-geni: Enable Serial on SA8255p Qualcomm platforms Date: Thu, 10 Apr 2025 23:10:10 +0530 Message-ID: <20250410174010.31588-10-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250410174010.31588-1-quic_ptalari@quicinc.com> References: <20250410174010.31588-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=B5+50PtM c=1 sm=1 tr=0 ts=67f802da cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=_gOkJu00RtHYCxNnkZMA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: APJrblqz01FAAvKM_FtgAZFTZ0AC0Jk5 X-Proofpoint-ORIG-GUID: APJrblqz01FAAvKM_FtgAZFTZ0AC0Jk5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-10_05,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 suspectscore=0 malwarescore=0 bulkscore=0 phishscore=0 spamscore=0 priorityscore=1501 adultscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100127 The Qualcomm automotive SA8255p SoC relies on firmware to configure platform resources, including clocks, interconnects and TLMM. The driver requests resources operations over SCMI using power and performance protocols. The SCMI power protocol enables or disables resources like clocks, interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs, such as resume/suspend, to control power states(on/off). The SCMI performance protocol manages UART baud rates, with each baud rate represented by a performance level. The driver uses the dev_pm_opp_set_level() API to request the desired baud rate by specifying the performance level. Signed-off-by: Praveen Talari --- drivers/tty/serial/qcom_geni_serial.c | 150 +++++++++++++++++++++++--- 1 file changed, 136 insertions(+), 14 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 9649297d4a9e..40b71d4b7590 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -98,9 +99,16 @@ #define DMA_RX_BUF_SIZE 2048 +#define DOMAIN_IDX_POWER 0 +#define DOMAIN_IDX_PERF 1 + struct qcom_geni_device_data { bool console; enum geni_se_xfer_mode mode; + struct dev_pm_domain_attach_data pd_data; + int (*geni_serial_pwr_rsc_init)(struct uart_port *uport); + int (*geni_serial_set_rate)(struct uart_port *uport, unsigned long clk_freq); + int (*geni_serial_switch_power_state)(struct uart_port *uport, bool state); }; struct qcom_geni_private_data { @@ -138,6 +146,7 @@ struct qcom_geni_serial_port { struct qcom_geni_private_data private_data; const struct qcom_geni_device_data *dev_data; + struct dev_pm_domain_list *pd_list; }; static const struct uart_ops qcom_geni_console_pops; @@ -1315,6 +1324,42 @@ static int geni_serial_set_rate(struct uart_port *uport, unsigned long baud) return 0; } +static int geni_serial_set_level(struct uart_port *uport, unsigned long baud) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + struct device *perf_dev = port->pd_list->pd_devs[DOMAIN_IDX_PERF]; + + /* + * The performance protocol sets UART communication + * speeds by selecting different performance levels + * through the OPP framework. + * + * Supported perf levels for baudrates in firmware are below + * +---------------------+--------------------+ + * | Perf level value | Baudrate values | + * +---------------------+--------------------+ + * | 300 | 300 | + * | 1200 | 1200 | + * | 2400 | 2400 | + * | 4800 | 4800 | + * | 9600 | 9600 | + * | 19200 | 19200 | + * | 38400 | 38400 | + * | 57600 | 57600 | + * | 115200 | 115200 | + * | 230400 | 230400 | + * | 460800 | 460800 | + * | 921600 | 921600 | + * | 2000000 | 2000000 | + * | 3000000 | 3000000 | + * | 3200000 | 3200000 | + * | 4000000 | 4000000 | + * +---------------------+--------------------+ + */ + + return dev_pm_opp_set_level(perf_dev, baud); +} + static void qcom_geni_serial_set_termios(struct uart_port *uport, struct ktermios *termios, const struct ktermios *old) @@ -1333,7 +1378,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, /* baud rate */ baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); - ret = geni_serial_set_rate(uport, baud); + ret = port->dev_data->geni_serial_set_rate(uport, baud); if (ret) { dev_err(port->se.dev, "%s: Failed to set baud: %u ret: %d\n", @@ -1624,8 +1669,27 @@ static int geni_serial_resources_on(struct uart_port *uport) return ret; } -static int geni_serial_resource_init(struct qcom_geni_serial_port *port) +static int geni_serial_resource_state(struct uart_port *uport, bool power_on) +{ + return power_on ? geni_serial_resources_on(uport) : geni_serial_resources_off(uport); +} + +static int geni_serial_pwr_init(struct uart_port *uport) { + struct qcom_geni_serial_port *port = to_dev_port(uport); + int ret; + + ret = dev_pm_domain_attach_list(port->se.dev, + &port->dev_data->pd_data, &port->pd_list); + if (ret <= 0) + return -EINVAL; + + return 0; +} + +static int geni_serial_resource_init(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); int ret; port->se.clk = devm_clk_get(port->se.dev, "se"); @@ -1756,13 +1820,16 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) port->se.dev = &pdev->dev; port->se.wrapper = dev_get_drvdata(pdev->dev.parent); - ret = geni_serial_resource_init(port); + ret = port->dev_data->geni_serial_pwr_rsc_init(uport); if (ret) return ret; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -EINVAL; + if (!res) { + ret = -EINVAL; + goto error; + } + uport->mapbase = res->start; port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; @@ -1772,19 +1839,26 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) if (!data->console) { port->rx_buf = devm_kzalloc(uport->dev, DMA_RX_BUF_SIZE, GFP_KERNEL); - if (!port->rx_buf) - return -ENOMEM; + if (!port->rx_buf) { + ret = -ENOMEM; + goto error; + } } port->name = devm_kasprintf(uport->dev, GFP_KERNEL, "qcom_geni_serial_%s%d", uart_console(uport) ? "console" : "uart", uport->line); - if (!port->name) - return -ENOMEM; + if (!port->name) { + ret = -ENOMEM; + goto error; + } irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; + if (irq < 0) { + ret = irq; + goto error; + } + uport->irq = irq; uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); @@ -1806,7 +1880,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) IRQF_TRIGGER_HIGH, port->name, uport); if (ret) { dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); - return ret; + goto error; } pm_runtime_enable(port->se.dev); @@ -1830,6 +1904,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) error: pm_runtime_disable(port->se.dev); + dev_pm_domain_detach_list(port->pd_list); return ret; } @@ -1842,22 +1917,31 @@ static void qcom_geni_serial_remove(struct platform_device *pdev) device_init_wakeup(&pdev->dev, false); pm_runtime_disable(port->se.dev); uart_remove_one_port(drv, &port->uport); + dev_pm_domain_detach_list(port->pd_list); } static int qcom_geni_serial_runtime_suspend(struct device *dev) { struct qcom_geni_serial_port *port = dev_get_drvdata(dev); struct uart_port *uport = &port->uport; + int ret = 0; - return geni_serial_resources_off(uport); + if (port->dev_data->geni_serial_switch_power_state) + ret = port->dev_data->geni_serial_switch_power_state(uport, false); + + return ret; }; static int qcom_geni_serial_runtime_resume(struct device *dev) { struct qcom_geni_serial_port *port = dev_get_drvdata(dev); struct uart_port *uport = &port->uport; + int ret = 0; + + if (port->dev_data->geni_serial_switch_power_state) + ret = port->dev_data->geni_serial_switch_power_state(uport, true); - return geni_serial_resources_on(uport); + return ret; }; static int qcom_geni_serial_suspend(struct device *dev) @@ -1895,11 +1979,41 @@ static int qcom_geni_serial_resume(struct device *dev) static const struct qcom_geni_device_data qcom_geni_console_data = { .console = true, .mode = GENI_SE_FIFO, + .geni_serial_pwr_rsc_init = geni_serial_resource_init, + .geni_serial_set_rate = geni_serial_set_rate, + .geni_serial_switch_power_state = geni_serial_resource_state, }; static const struct qcom_geni_device_data qcom_geni_uart_data = { .console = false, .mode = GENI_SE_DMA, + .geni_serial_pwr_rsc_init = geni_serial_resource_init, + .geni_serial_set_rate = geni_serial_set_rate, + .geni_serial_switch_power_state = geni_serial_resource_state, +}; + +static const struct qcom_geni_device_data sa8255p_qcom_geni_console_data = { + .console = true, + .mode = GENI_SE_FIFO, + .pd_data = { + .pd_flags = PD_FLAG_DEV_LINK_ON, + .pd_names = (const char*[]) { "power", "perf" }, + .num_pd_names = 2, + }, + .geni_serial_pwr_rsc_init = geni_serial_pwr_init, + .geni_serial_set_rate = geni_serial_set_level, +}; + +static const struct qcom_geni_device_data sa8255p_qcom_geni_uart_data = { + .console = false, + .mode = GENI_SE_DMA, + .pd_data = { + .pd_flags = PD_FLAG_DEV_LINK_ON, + .pd_names = (const char*[]) { "power", "perf" }, + .num_pd_names = 2, + }, + .geni_serial_pwr_rsc_init = geni_serial_pwr_init, + .geni_serial_set_rate = geni_serial_set_level, }; static const struct dev_pm_ops qcom_geni_serial_pm_ops = { @@ -1913,10 +2027,18 @@ static const struct of_device_id qcom_geni_serial_match_table[] = { .compatible = "qcom,geni-debug-uart", .data = &qcom_geni_console_data, }, + { + .compatible = "qcom,sa8255p-geni-debug-uart", + .data = &sa8255p_qcom_geni_console_data, + }, { .compatible = "qcom,geni-uart", .data = &qcom_geni_uart_data, }, + { + .compatible = "qcom,sa8255p-geni-uart", + .data = &sa8255p_qcom_geni_uart_data, + }, {} }; MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);