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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec34be2f4sm27264105e9.19.2025.04.03.13.40.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 13:40:36 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrew Jones , =?utf-8?q?Alex_Benn=C3=A9e?= , "Michael S. Tsirkin" , qemu-arm@nongnu.org, Udo Steinberg , Shannon Zhao , Gustavo Romero , Igor Mammedov , Peter Maydell , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v3 1/9] hw/arm/virt: Remove pointless VirtMachineState::tcg_its field Date: Thu, 3 Apr 2025 22:40:21 +0200 Message-ID: <20250403204029.47958-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403204029.47958-1-philmd@linaro.org> References: <20250403204029.47958-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org VirtMachineState::tcg_its has the negated logic value of VirtMachineClass::no_tcg_its. Directly use the latter, removing the former. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/virt.h | 1 - hw/arm/virt.c | 13 +++++-------- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index c8e94e6aedc..17c160429ea 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -150,7 +150,6 @@ struct VirtMachineState { bool highmem_mmio; bool highmem_redists; bool its; - bool tcg_its; bool virt; bool ras; bool mte; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a96452f17a4..177e9e0eadb 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -710,11 +710,12 @@ static inline DeviceState *create_acpi_ged(VirtMachineState *vms) static void create_its(VirtMachineState *vms) { + VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); const char *itsclass = its_class_name(); DeviceState *dev; if (!strcmp(itsclass, "arm-gicv3-its")) { - if (!vms->tcg_its) { + if (vmc->no_tcg_its) { itsclass = NULL; } } @@ -831,7 +832,9 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) redist_region_count); if (!kvm_irqchip_in_kernel()) { - if (vms->tcg_its) { + VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); + + if (!vmc->no_tcg_its) { object_property_set_link(OBJECT(vms->gic), "sysmem", OBJECT(mem), &error_fatal); qdev_prop_set_bit(vms->gic, "has-lpi", true); @@ -3357,12 +3360,6 @@ static void virt_instance_init(Object *obj) } else { /* Default allows ITS instantiation */ vms->its = true; - - if (vmc->no_tcg_its) { - vms->tcg_its = false; - } else { - vms->tcg_its = true; - } } /* Default disallows iommu instantiation */ From patchwork Thu Apr 3 20:40:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877947 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp3468078wrs; Thu, 3 Apr 2025 13:41:15 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXXP0hRSXqAoh/uIFo0ZBUNqjxWQWr61nHRRtegC5FPPB94liKrLNt8EvmhieN+AXPUVWAW5g==@linaro.org X-Google-Smtp-Source: AGHT+IGdTNIDr5/ovOMnrAOgLZbqS7ehlwLv3B8359w8lrPFwC8Z8G9uoHvkkaAIQF1zUEnPXq2F X-Received: by 2002:a05:6214:1903:b0:6e4:4adb:8c29 with SMTP id 6a1803df08f44-6ef0bec78d4mr59647186d6.12.1743712874688; Thu, 03 Apr 2025 13:41:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743712874; cv=none; d=google.com; s=arc-20240605; b=CxiOqcaF3Yk3rigvu62NL4mf0SJGdhPmvp+gS8kMqN545A6Q2tFfin/NyeK+BGfhPo c1r5z7qD4bF0P8dxuY8auaPOA/cFI2z9yzfRPYgX8lUDnnY31287z1mTo2ArBQdbB6aM pgSjsoCksUXiRC1wYqq0mwNhNqMdjlvAJ+IU+mr0nW2HDOLFUHgTnwjoQ+Dnk4hGnt6+ lCB665Z9HEGJqExzVUDIPosS/2S1GJ0aJVXk7oC2Nsi/R8MQpjqZtDmu6ekDgu3TSDT7 iMQas4r813VMsHPPltK+Vy4D4fv2lb2dxoDrH26rs7WLMDFK/KxUi3b9LiKa1Ykfwes2 hXuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=91qw8dB7Eg7Eq+MHz4XIrej88B1FVRM9ctS9zjgiZGk=; fh=MyqIMCjZFHy0NzBnvXc8KFcCapThoPogDzLe5J0FgH4=; b=XHtGev6/3nHBTNeWffsFAkEdSceqYOmDp/TWTAoJFdPZWCmJBUTxoUd+gz75UwwPM5 aQYJhddSY0fgkyzzS8PBEYo0V0VEsNSqvE79WZaVa0Z2MTMWqn+kzKnFBYvhlT9JGOPy LsrByrwSftEB+ab1YHsmBuIKqObWIf0Hx7TITagIALrV22FfJGHY6kB38GWptL7J/MbJ P28hAmryOH8My5FeiWBDOasl53a0iMJBqePiZjt79L/ZRDcCebDjdYykKqLMb7wgYnmf /iYuPG1ZvOX1IgSxsYDKhBzcWAWIuLiloFKPVimkG2+8bUYzf45PxiADJBCdsfnRvmN+ T8rw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wiNHb4TX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec1663053sm30876275e9.15.2025.04.03.13.40.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 13:40:41 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrew Jones , =?utf-8?q?Alex_Benn=C3=A9e?= , "Michael S. Tsirkin" , qemu-arm@nongnu.org, Udo Steinberg , Shannon Zhao , Gustavo Romero , Igor Mammedov , Peter Maydell , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH-for-10.1 v3 2/9] hw/intc/gicv3_its: Do not check its_class_name() for NULL Date: Thu, 3 Apr 2025 22:40:22 +0200 Message-ID: <20250403204029.47958-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403204029.47958-1-philmd@linaro.org> References: <20250403204029.47958-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since commit cc5e719e2c8 ("kvm: require KVM_CAP_SIGNAL_MSI"), its_class_name() single implementation doesn't return NULL anymore. Update the prototype docstring, and remove the pointless checks. Reported-by: Gustavo Romero Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/intc/arm_gicv3_its_common.h | 2 +- hw/arm/virt-acpi-build.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h index 7dc712b38d2..3c7b543b018 100644 --- a/include/hw/intc/arm_gicv3_its_common.h +++ b/include/hw/intc/arm_gicv3_its_common.h @@ -128,7 +128,7 @@ struct GICv3ITSCommonClass { * Return the ITS class name to use depending on whether KVM acceleration * and KVM CAP_SIGNAL_MSI are supported * - * Returns: class name to use or NULL + * Returns: class name to use */ const char *its_class_name(void); diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 3ac8f8e1786..9b7fc99f170 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -741,7 +741,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) memmap[VIRT_HIGH_GIC_REDIST2].size); } - if (its_class_name() && !vmc->no_its) { + if (!vmc->no_its) { /* * ACPI spec, Revision 6.0 Errata A * (original 6.0 definition has invalid Length) @@ -973,7 +973,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) vms->oem_table_id); } - if (its_class_name() && !vmc->no_its) { + if (!vmc->no_its) { acpi_add_table(table_offsets, tables_blob); build_iort(tables_blob, tables->linker, vms); } From patchwork Thu Apr 3 20:40:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877955 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp3469064wrs; Thu, 3 Apr 2025 13:44:19 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV8V/gl4oos90g9ib/Wer1gaH+7irIvxCOKdXsP16RePqNA+Fy77EobdFG9gSEzhPS11fw19g==@linaro.org X-Google-Smtp-Source: AGHT+IGV3ohL3UY0f/nZIWsHJtDQ5Fid/cp/QibptqDbopY+zBxXb4Enh0nJSGmLDMSvMdd4BKgW X-Received: by 2002:a05:620a:254e:b0:7c5:538f:ae4a with SMTP id af79cd13be357-7c774d6f830mr88506385a.26.1743713059010; Thu, 03 Apr 2025 13:44:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743713058; cv=none; d=google.com; s=arc-20240605; b=YRWPeWjV9SJLKMcrGniBdtI+gpCDdBv7ds8y+6OP7/8Mt5u0ROE0DfDj/+O0OYdcpS rZkwziY5/EPtkiYdVHrlxcVIdiWhZ1FIBnibT5VcK6utFSEsgCAMuGECA5l6BNaig3xr mhzEP2khROp455qQdP8eIJ2MkUje5u4cb31lqemHLuui8VnzTNfnDxtZ6vdtZqyYIzPo D6zEgbdvewUdN6lePdJ2iIRP2oLZ8thEKk7g9qxPg3hDdb7YLaoH3C2HbVPHxRJwy8vf ybfh4GM4QjR83dUvJqiA2Ja1fLaR5D7x36DlhJRwSl0JrkXem5hnxEBWARSfZJPgptzw dbZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SuT3rRChRQlFqOt9wOfD9dqVNsRbmscUvrlQveNmeCQ=; fh=MyqIMCjZFHy0NzBnvXc8KFcCapThoPogDzLe5J0FgH4=; b=atAzgKf9PLt3rm976+bth1ffztjRvDMo10t3J2j+lujHNNN2X2oK0y20sSHR6jCTic 9tcuX4PVPpiUPp1hSqz+xMBrOzjRLj9n0kLavUEZxJ7K6CYPQ/poglXifmC9jk86qfDC 26w3BQ8CoQF/Cc64D6Cbxffa6Cqx+RWrRuIDG9h6LjW/YfgnrbcHf9Lwy0Lnvnsffh7d 8yZiYi9OucKv5tO6OZZKwbGwTnO4RdgOLsRRMmOE2r0Fm5jC+1yQuYnmW0QH1RV2ZX4D YJ9VzWE4CeS7Qn9WMf3AF8lnX3sjpFBKwzxGkS1s5EK/b33MqSMFjgGb40V4f40Zi6us Ba9A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uOUHGa3n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec34a8d67sm27667955e9.12.2025.04.03.13.40.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 13:40:47 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrew Jones , =?utf-8?q?Alex_Benn=C3=A9e?= , "Michael S. Tsirkin" , qemu-arm@nongnu.org, Udo Steinberg , Shannon Zhao , Gustavo Romero , Igor Mammedov , Peter Maydell , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH-for-10.1 v3 3/9] hw/arm/virt: Simplify create_its() Date: Thu, 3 Apr 2025 22:40:23 +0200 Message-ID: <20250403204029.47958-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403204029.47958-1-philmd@linaro.org> References: <20250403204029.47958-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org No need to strstr() check the class name when we can use kvm_irqchip_in_kernel(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gustavo Romero --- hw/arm/virt.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 177e9e0eadb..326986deb16 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -711,21 +711,15 @@ static inline DeviceState *create_acpi_ged(VirtMachineState *vms) static void create_its(VirtMachineState *vms) { VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); - const char *itsclass = its_class_name(); DeviceState *dev; - if (!strcmp(itsclass, "arm-gicv3-its")) { - if (vmc->no_tcg_its) { - itsclass = NULL; - } - } - - if (!itsclass) { + assert(!vmc->no_its); + if (!kvm_irqchip_in_kernel() && vmc->no_tcg_its) { /* Do nothing if not supported */ return; } - dev = qdev_new(itsclass); + dev = qdev_new(its_class_name()); object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), &error_abort); From patchwork Thu Apr 3 20:40:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877956 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp3469107wrs; Thu, 3 Apr 2025 13:44:26 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXrNQ1OmY6VibZ75dzKySW0NR8oNsCixUMaXXV+JDVL1m9yUGVPHaGak+FHkU6mvaqydMxruQ==@linaro.org X-Google-Smtp-Source: AGHT+IEK1r2y5IhDQx1cO61O7kHVCND9NKnun47vvMgHeA1TtuG91MfWTnp/7LIPoCI84TwOOupi X-Received: by 2002:a05:620a:2596:b0:7c5:94ec:5114 with SMTP id af79cd13be357-7c774a3bf73mr116887585a.18.1743713066099; Thu, 03 Apr 2025 13:44:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743713066; cv=none; d=google.com; s=arc-20240605; b=AgNFq/L1KElA2cWIktLZ1nD1Hzc2PXVVXbpAw7I52hGybnq1cI+Uqqr2XMDksrCsl9 UnyjCTdVpWY4bS9MTxdeS2irXnf/KBphODvOE5t4NjLLv2Ea87dBNjan0gbI2gbCxk44 mWALZNF3ksctXIq60+gRxsWdMtnldFd+AHgaH276v8YTgOiiUj1jeC7glu3zZdjoYeLb N+JAo15K/5pJIhr+wOUunetMhivyoCJQrw+8EIdOAMLQnA3BU7Ksqlgv8n7pvR6iMKwP RwHNY4GbKgO7f+H2hJXkXhFXWbjTY5Jakq37py5ZkdfvAV0a0TuAERetbMdG+PKLX2DY 4AJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wgBNy0vxL5goVE1RO7+eU01X51ted55h8TOUfbLYmNA=; fh=MyqIMCjZFHy0NzBnvXc8KFcCapThoPogDzLe5J0FgH4=; b=J7YkXFpMROSUSNi/0pdOxQQrWgxuMi141dXLwyqMo6Aa5M+dVTR2qHIjo2F5fiOCkx c70ba6LFGUXFRPSZTo9jjeZfIj/9W72puxqUL0uQvlzGLFK9FM1x/Xm9T17a6tAbh5Us l2SSZYajFNDiVlqNAkGdCeTaEugZF2FTFGwjk2ZEc6ii5isuwSo1MZLT2ckGO7IqnHhL wFTPzQMS268/Fdzm80Dh0+Cb7GJVEo83R6C3sTj8s/7/bIi4Mvb0ke+T43GCCKn7H1Vl /ZqkclqRSZRXN4zA9kKFyaQH4x278voniZMZ38H8bXVROh8job1ynWmXmLgcypdT644s hWtA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H30ZVGJK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c3020d92dsm2701086f8f.71.2025.04.03.13.40.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 13:40:52 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrew Jones , =?utf-8?q?Alex_Benn=C3=A9e?= , "Michael S. Tsirkin" , qemu-arm@nongnu.org, Udo Steinberg , Shannon Zhao , Gustavo Romero , Igor Mammedov , Peter Maydell , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH-for-10.1 v3 4/9] hw/arm/virt-acpi: Factor its_enabled() helper out Date: Thu, 3 Apr 2025 22:40:24 +0200 Message-ID: <20250403204029.47958-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403204029.47958-1-philmd@linaro.org> References: <20250403204029.47958-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org GIC ITS is checked for the MADT and IORT tables. Factor the checks out to the its_enabled() helper. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Gustavo Romero Reviewed-by: Richard Henderson --- hw/arm/virt-acpi-build.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 9b7fc99f170..1c389ef5cdb 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -208,6 +208,13 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) #define ROOT_COMPLEX_ENTRY_SIZE 36 #define IORT_NODE_OFFSET 48 +static bool its_enabled(VirtMachineState *vms) +{ + VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); + + return !vmc->no_its; +} + /* * Append an ID mapping entry as described by "Table 4 ID mapping format" in * "IO Remapping Table System Software on ARM Platforms", Chapter 3. @@ -670,7 +677,6 @@ static void build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { int i; - VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); const MemMapEntry *memmap = vms->memmap; AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id, .oem_table_id = vms->oem_table_id }; @@ -741,7 +747,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) memmap[VIRT_HIGH_GIC_REDIST2].size); } - if (!vmc->no_its) { + if (its_enabled(vms)) { /* * ACPI spec, Revision 6.0 Errata A * (original 6.0 definition has invalid Length) @@ -973,7 +979,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) vms->oem_table_id); } - if (!vmc->no_its) { + if (its_enabled(vms)) { acpi_add_table(table_offsets, tables_blob); build_iort(tables_blob, tables->linker, vms); } From patchwork Thu Apr 3 20:40:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877953 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp3468746wrs; Thu, 3 Apr 2025 13:43:21 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXU8wA9EPbM+gZyjf03MTzEPtwWl8YNi4BukWnuslxMy6z7H2jCi0WtSQiaGbaIureDBcSPcQ==@linaro.org X-Google-Smtp-Source: AGHT+IHmvP8e6C7RCVqZLEzmyWfcRw5pdbzSrZZVpWPlYn2Dr1w0V84DOq9B+qNMiiYCpD0sDmT4 X-Received: by 2002:a05:622a:f:b0:476:881e:eeda with SMTP id d75a77b69052e-4792598ee31mr4519201cf.24.1743713000884; Thu, 03 Apr 2025 13:43:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743713000; cv=none; d=google.com; s=arc-20240605; b=CkS07rOm5ib2YY1vcQoRWiXZMPDT1SfJyKRkkWyWVB+g2XwNOfOpV6S2YO392igEjZ +B+3kEUxpVYr9/OU3sVIBr1rCCZ1CLiKk+amtlltCepRdWLhiu0X8T6r/StJY3Cg8xIb ybPc4+br+DtDjeN91Sj00xvEF424ivh2/vvxLztDbWZMOYEDVEipj+mxudLai3ke78/Y MwaU5dprhZYyMZIVwYldZNPFPg7MEz4nsLhUOzsaafqshSwhVeX469bDBVPNTZ4DsnaN LFuYE4vXFY9y+p49a+dku+deIGnBlgGuHNJR8X4o9RgeL2pPXW3rS+FWcVvWPOolHYej b4BQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=877Ft8S2r+Y3e5owHO3tHYlDGhoIjLwtX0511Fk5+so=; fh=cT8sTm3MaRRFY9PfjuzDPMPIjI/oXWRSXbH4Hrbck2w=; b=UrMoy7Rb1B9yPBFHAe0qKJxga/sEsavUulxEpcTeDNuT1ihqwvpZry7ECbnPpCJu2/ uYr3BytlFtp5DdxKc9LNhovBAYD68R+XG9eZ9L42wFxvHfttWA4Pl1huQG7S6UHgGWTu lPjryS9VDkMkceHmnTPPU1bkrshAF23PG/wONtJn1Jz3JECkQ0604Lp5HtH9mDBIV6K6 xbK6GKCPMkJjG24KKV6X8rp9GZXWhcQAYXjIjT24PZD05ysVdb9bfzO1h22u1ZbJEgto 66FVrT2LnUQwKGhFD8ibmOhbLfFF+5pucuSn0lKl9q/sl+ILmDCJu3e7r1/yA06vGmIH cJ5Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="fU/VdtIO"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=fail header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c30096ecasm2751545f8f.18.2025.04.03.13.40.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 13:40:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrew Jones , =?utf-8?q?Alex_Benn=C3=A9e?= , "Michael S. Tsirkin" , qemu-arm@nongnu.org, Udo Steinberg , Shannon Zhao , Gustavo Romero , Igor Mammedov , Peter Maydell , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v3 5/9] qtest/bios-tables-test: Add test for -M virt, its=off Date: Thu, 3 Apr 2025 22:40:25 +0200 Message-ID: <20250403204029.47958-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403204029.47958-1-philmd@linaro.org> References: <20250403204029.47958-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add the use case reported as issue #2886 [*]. The test passes while it shouldn't. We are going to fix that in the following commits. [*] https://gitlab.com/qemu-project/qemu/-/issues/2886 Signed-off-by: Philippe Mathieu-Daudé --- tests/qtest/bios-tables-test.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 0a333ec4353..baaf199e01c 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -2146,6 +2146,25 @@ static void test_acpi_aarch64_virt_tcg_topology(void) free_test_data(&data); } +static void test_acpi_aarch64_virt_tcg_its_off(void) +{ + test_data data = { + .machine = "virt", + .arch = "aarch64", + .tcg_only = true, + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", + .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2", + .ram_start = 0x40000000ULL, + .scan_len = 128ULL * 1024 * 1024, + }; + + test_acpi_one("-cpu cortex-a57 " + "-M virtualization=on,secure=off " + "-M gic-version=max,its=off,iommu=smmuv3", &data); + free_test_data(&data); +} + static void test_acpi_q35_viot(void) { test_data data = { @@ -2577,6 +2596,8 @@ int main(int argc, char *argv[]) test_acpi_aarch64_virt_tcg_acpi_hmat); qtest_add_func("acpi/virt/topology", test_acpi_aarch64_virt_tcg_topology); + qtest_add_func("acpi/virt/its_off", + test_acpi_aarch64_virt_tcg_its_off); qtest_add_func("acpi/virt/numamem", test_acpi_aarch64_virt_tcg_numamem); qtest_add_func("acpi/virt/memhp", test_acpi_aarch64_virt_tcg_memhp); From patchwork Thu Apr 3 20:40:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877949 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp3468216wrs; Thu, 3 Apr 2025 13:41:39 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWYr1pmxYWY1NDEKW4W9xjC1jy27oBW14HKAQnM+dC/L/OdSypEixGMH9zmpFOBdBZ2v2RJfA==@linaro.org X-Google-Smtp-Source: AGHT+IGjeEOywKHAguGkw/CsDb5ioWQn4FS72PIL1OKcxpSeSziwcJnktbQRt8CQuhE7z/V5i5mO X-Received: by 2002:a05:620a:460e:b0:7c5:4b6a:d862 with SMTP id af79cd13be357-7c774d71ca7mr110446785a.33.1743712899495; Thu, 03 Apr 2025 13:41:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743712899; cv=none; d=google.com; s=arc-20240605; b=UFOxtmqDiqRDdwd7h1HPj4/YyPdqwnxWaeyxpfQNJBhQFQeUi4mLsS1Xbh7GZ1nhhD zG0dPe8jVPTOV3HJSAFANB4n/WwveCf7gK43own3uEomwKZNqS6X8/HsfNR/q/gV2z3x sGQZH5Pjpe8K74YPVgavQJPoXMkRGnoVqzETnjvuCJm94A3z8c2x3U/c9+1OogOShLxW 8qRQF986C3x7gOINgiYaV7GVUdzwQgZdKtxAhz0MWIQVkUxBINWma0sMqsrWOAhPEDnJ g67AIRndCNsTYGKvDLBhLZEI7DQ+BhenRoBtNhcVAPCHkMn4ea2Q8d4l0awP8KikShly Adsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MLYRdVVgThynsCkkZUPojC5QmxuF1gOqeLFrpCloSHE=; fh=cT8sTm3MaRRFY9PfjuzDPMPIjI/oXWRSXbH4Hrbck2w=; b=C005E1gG6tXeg4iuF/D0cLIMzBlwVGtJNnxS2GHz1mYSwtpRpnGf+UNBO5IYfgnYVB 3Fvu7+UuiBPfXI/94KA/ClRG4hWNUoy+kFgy7CBafISAjY4dL69WdMbs5hN6Q5pY/PWm ACIdsa3gV0vDoMC56I33FQI8h8YsLY8/syejeWPbasKviJrUGdSxM8PQGV5y7MbnJujw 7niZ5mNcHYxWzzNM8Z4xDPo0EeAC9o36nlkqqEA+jIuuAqi6wokrD4BNfsuHqofIbVbS 3i9CBN9pKDjB/HjbscUHnWXspZ7Db6Z7MH3HehfOhyO1ks64+V8MLZwPOub8EhAQTzdh xE3Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="xq/grt//"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec1662feesm30696335e9.12.2025.04.03.13.41.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 13:41:03 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrew Jones , =?utf-8?q?Alex_Benn=C3=A9e?= , "Michael S. Tsirkin" , qemu-arm@nongnu.org, Udo Steinberg , Shannon Zhao , Gustavo Romero , Igor Mammedov , Peter Maydell , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v3 6/9] qtest/bios-tables-test: Whitelist aarch64/virt 'its_off' variant blobs Date: Thu, 3 Apr 2025 22:40:26 +0200 Message-ID: <20250403204029.47958-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403204029.47958-1-philmd@linaro.org> References: <20250403204029.47958-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We are going to fix the test_acpi_aarch64_virt_tcg_its_off() test. In preparation, copy the ACPI tables which will be altered as 'its_off' variants, and whitelist them. Reviewed-by: Gustavo Romero Signed-off-by: Philippe Mathieu-Daudé --- tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ tests/qtest/bios-tables-test.c | 1 + tests/data/acpi/aarch64/virt/APIC.its_off | Bin 0 -> 184 bytes tests/data/acpi/aarch64/virt/FACP.its_off | Bin 0 -> 276 bytes tests/data/acpi/aarch64/virt/IORT.its_off | Bin 0 -> 236 bytes 5 files changed, 4 insertions(+) create mode 100644 tests/data/acpi/aarch64/virt/APIC.its_off create mode 100644 tests/data/acpi/aarch64/virt/FACP.its_off create mode 100644 tests/data/acpi/aarch64/virt/IORT.its_off GIT binary patch literal 236 zcmebD4+?q1z`(#9?&R<65v<@85#X!<1dKp25F11@1F-=RgMkDCNC*yK9F_TjFfcO#g+N#Zh@s|zoCF3AP#UU@ R!2`+%Dg6Hr$N|zYvjDIZ5CH%H literal 0 HcmV?d00001 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8bf..3421dd5adf3 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,4 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/APIC.its_off", +"tests/data/acpi/aarch64/virt/FACP.its_off", +"tests/data/acpi/aarch64/virt/IORT.its_off", diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index baaf199e01c..55366bf4956 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -2151,6 +2151,7 @@ static void test_acpi_aarch64_virt_tcg_its_off(void) test_data data = { .machine = "virt", .arch = "aarch64", + .variant = ".its_off", .tcg_only = true, .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", diff --git a/tests/data/acpi/aarch64/virt/APIC.its_off b/tests/data/acpi/aarch64/virt/APIC.its_off new file mode 100644 index 0000000000000000000000000000000000000000..c37d05d6e05805304f10afe73eb7cb9100fcccfa GIT binary patch literal 184 zcmZ<^@O0k6z`($=+{xeBBUr&HBEVSz2pEB4AU24G0Uik$i-7~iVgWL^17JJ`2AFzr bgb+@aBn}xq0gwb2)Q)cq{30-g9B_L93G4|0 literal 0 HcmV?d00001 diff --git a/tests/data/acpi/aarch64/virt/FACP.its_off b/tests/data/acpi/aarch64/virt/FACP.its_off new file mode 100644 index 0000000000000000000000000000000000000000..606dac3fe4b55c31fd68b25d3a4127eeef227434 GIT binary patch literal 276 zcmZ>BbPf< X-Patchwork-Id: 877954 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp3469047wrs; Thu, 3 Apr 2025 13:44:13 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXhu5xvEZyiG1fxnc1Jpl6Gf87DK9j9tGnbPmuNXlYeVNCa33QsFh+ivXZypPmjZe9VhGalEA==@linaro.org X-Google-Smtp-Source: AGHT+IEcF/aOZhGGth5T81wm9TxCB9LzoE3G3F8GG7NhSENG9LYXOZDMpreyujSmE/xwXKU6yGPx X-Received: by 2002:a05:622a:110e:b0:477:6c0e:d5b4 with SMTP id d75a77b69052e-479248fc1ebmr14546721cf.2.1743713053053; Thu, 03 Apr 2025 13:44:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743713053; cv=none; d=google.com; s=arc-20240605; b=lo9VHPla5zlRfNQhRvL2kGrXvjZIYXkdA6+Oh4gGMGHrmODHfi/CBTsD4UnMup+g9N lgbcJasPzm3rYO6XQ44Ds8DBikPx2yCQQiMyqSRdM14LsRdcez5I272isok/wJmTMLUi 11XQGTtWfP03MKzp8S1/r2HxZ7miLapBeWEThLalPzpEEBdTUx6jLIZKwRchjiTAOqfN XWG1f2L/K5l91V8AwcZ5KSQKq0I8zCquI8e3XgqaTrCo1DS01r1gZXdRj8U9L2oHIRnR R77AdB9WVAl5aFqWXOYBkV2uoceIbvWin6SDIUCnYPnOkdUySTyySi/h0UF7olnAeRYS iDmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=AzIe1y6exrD0xJczT8npcuq1OBfi7eudR1jNiJ2MiPM=; fh=cT8sTm3MaRRFY9PfjuzDPMPIjI/oXWRSXbH4Hrbck2w=; b=YsiM5zWkxY4sz2b1iZfP490+oKx1Pm0cEr1qSvLZkN2Jjhn0k8ejVUtzaJCj9eTmhw y94dxw4hT+ZdGsV7m/OaKPRWNuV4pWAIUqcEPW96PijapRN9mkUODPEhHDSucJi4wVI9 z5ukFSLN6r2Ul0rNk5mf4BlKsJBLKZnf4SDJjiKHpqgf93joKHazAdkYdO9wSso7AXTo Z+U4nwUXGXV+9o5H5BwakpJMzBI1pxI19+NVDAPxmjFxjcPhLxpZsL96Fwm4sTZ0RwtW PGT27rqxvHHNC10W1mql44bwLw+AicpdrY7RdM247mAnpyr1Vh08VmYFGI2/VTJO3Ei+ HOPA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s+rknz10; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec1630ddesm30923505e9.5.2025.04.03.13.41.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 13:41:08 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrew Jones , =?utf-8?q?Alex_Benn=C3=A9e?= , "Michael S. Tsirkin" , qemu-arm@nongnu.org, Udo Steinberg , Shannon Zhao , Gustavo Romero , Igor Mammedov , Peter Maydell , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v3 7/9] hw/arm/virt-acpi: Always build IORT table (even with GIC ITS disabled) Date: Thu, 3 Apr 2025 22:40:27 +0200 Message-ID: <20250403204029.47958-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403204029.47958-1-philmd@linaro.org> References: <20250403204029.47958-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Citing Gustavo [*]: Gating IORT table generation entirely based on the presence of ITS looks wrong because IORT table has data beyond GIC ITS, like for SMMUv3 etc.. [*] https://lore.kernel.org/qemu-devel/bae6e29a-7290-47d2-8caf-14702ee091f0@linaro.org/ Reported-by: Gustavo Romero Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt-acpi-build.c | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 1c389ef5cdb..e7e27951cb9 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -287,6 +287,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) uint32_t id = 0; GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); + bool has_its = its_enabled(vms); AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id, .oem_table_id = vms->oem_table_id }; @@ -325,9 +326,12 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) nb_nodes = 3; /* RC, ITS, SMMUv3 */ rc_mapping_count = smmu_idmaps->len + its_idmaps->len; - } else { + } else if (has_its) { nb_nodes = 2; /* RC, ITS */ rc_mapping_count = 1; + } else { + nb_nodes = 1; /* RC */ + rc_mapping_count = 1; } /* Number of IORT Nodes */ build_append_int_noprefix(table_data, nb_nodes, 4); @@ -336,17 +340,19 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ - /* Table 12 ITS Group Format */ - build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */ - node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */; - build_append_int_noprefix(table_data, node_size, 2); /* Length */ - build_append_int_noprefix(table_data, 1, 1); /* Revision */ - build_append_int_noprefix(table_data, id++, 4); /* Identifier */ - build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */ - build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */ - build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */ - /* GIC ITS Identifier Array */ - build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); + if (has_its) { + /* Table 12 ITS Group Format */ + build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */ // + node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */; + build_append_int_noprefix(table_data, node_size, 2); /* Length */ + build_append_int_noprefix(table_data, 1, 1); /* Revision */ + build_append_int_noprefix(table_data, id++, 4); /* Identifier */ + build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */ + build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */ + build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */ + /* GIC ITS Identifier Array */ + build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); + } if (vms->iommu == VIRT_IOMMU_SMMUV3) { int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; @@ -429,7 +435,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) build_iort_id_mapping(table_data, range->input_base, range->id_count, IORT_NODE_OFFSET); } - } else { + } else if (has_its) { /* output IORT node is the ITS group node (the first node) */ build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET); } @@ -979,10 +985,8 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) vms->oem_table_id); } - if (its_enabled(vms)) { - acpi_add_table(table_offsets, tables_blob); - build_iort(tables_blob, tables->linker, vms); - } + acpi_add_table(table_offsets, tables_blob); + build_iort(tables_blob, tables->linker, vms); #ifdef CONFIG_TPM if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { From patchwork Thu Apr 3 20:40:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877950 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp3468228wrs; Thu, 3 Apr 2025 13:41:41 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXp72iZEMOy1vwaUmvIMcAfLb5eaWjclACrsh+qjdmFhsvBn6qCJ1FuioHISkYhGsbx2U/nHQ==@linaro.org X-Google-Smtp-Source: AGHT+IG5I/1sp1s+hmgTx6kN9yfu/k96oylX+AfSP6aHfD4hM1O8C4NYK+ztdbo0TM5Wp690A0R5 X-Received: by 2002:a05:622a:50d:b0:476:8825:99ba with SMTP id d75a77b69052e-4792594fbe3mr4677291cf.12.1743712901773; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec34a7615sm27325625e9.9.2025.04.03.13.41.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 13:41:13 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrew Jones , =?utf-8?q?Alex_Benn=C3=A9e?= , "Michael S. Tsirkin" , qemu-arm@nongnu.org, Udo Steinberg , Shannon Zhao , Gustavo Romero , Igor Mammedov , Peter Maydell , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v3 8/9] hw/arm/virt-acpi: Do not advertise disabled GIC ITS Date: Thu, 3 Apr 2025 22:40:28 +0200 Message-ID: <20250403204029.47958-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403204029.47958-1-philmd@linaro.org> References: <20250403204029.47958-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org GIC ITS can be disabled at runtime using '-M its=off', which sets VirtMachineState::its = false. Check this field to avoid advertising the ITS in the MADT table. Reported-by: Udo Steinberg Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2886 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Gustavo Romero --- hw/arm/virt-acpi-build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index e7e27951cb9..38a9e6fe0c5 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -212,7 +212,7 @@ static bool its_enabled(VirtMachineState *vms) { VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); - return !vmc->no_its; + return !vmc->no_its && vms->its; } /* From patchwork Thu Apr 3 20:40:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877951 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp3468337wrs; Thu, 3 Apr 2025 13:42:05 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUKuVbSttWHD4seVE7faE9sHp0HSJurzgPb66vwEZv8P4N5UPiAIPMQNHnTh4WWtGjwta4c+Q==@linaro.org X-Google-Smtp-Source: AGHT+IGVgfgZ0rKBUm9e//wK/6u2hbDXsvcP5xY0OP6F4Vq5rBXtgXYyDc4AKh/sg3ghq9HHr9iL X-Received: by 2002:ac8:5a48:0:b0:479:1a10:8958 with SMTP id d75a77b69052e-47924900406mr14454231cf.1.1743712925222; Thu, 03 Apr 2025 13:42:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743712925; cv=none; d=google.com; s=arc-20240605; b=T7QIrUdWQXceuAykynqd23KGz3pDYIiNYHUss4CSci8SVJvaQgDmsJ50QHQ0EzafK2 PP+TbCj/NZqhqYgxZuAAEOKApPoBr1MJgjV3nkCX82GgeDU7DghshRByLuHcytQTS4nU 5WaxNKkKbw0eynwHeBDvGaUW33yUBtJRVvroDKPlqBtEGjWkoi9vCHikJ/aYTQuFt9YK PihEGhpScJA9OA2Eh6zrPBc2ledYNAVaB/RjBxFCADwqbRvcVwaY8YqBshLBmSPyJDYt qegMLtHcfxV7JTNUfrxGGkCUTFZ/hdX8rzs2TxLkkJp5R+8yAjyzXpNQ40/1hO/4E/dz 0SUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5zTfaj2srAh7NFFgFGPtQA78JVUrBzadEZv8Wvdm4mc=; fh=cT8sTm3MaRRFY9PfjuzDPMPIjI/oXWRSXbH4Hrbck2w=; b=gdjGHZMc07N9LCtUCTjYvJ/hafPiEy08ZBlqJ7y2Qp53HM2RTrC/mVa2DmxES7QjAB hkSdw3klFaUCINRIuAIvYjD9aMhFdztpSdNg2wxBlJ3YORLoFEGBvBZ85oP6MelUyla+ w/mr/SsKDsi5SUG19Oneo02YsCzvrveR+DBcV2bGZJVH+55c/ihzAU5BD4tLyAlzQiaG iyvoO/CIOmEx5nhkpVOLLsTG8v6mGcXhrlxEaNwZ6WzPrLg0ki2IkqYkaGuorS4w9xc4 XZvgzkmYynxT3BS7TQNDVJH+3yTVLAI6DSjw+TD/JK4ipaHK775ijXmZyFP/QPv1h93L TF1Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TXt9LFRG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c3020da49sm2607411f8f.80.2025.04.03.13.41.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 13:41:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrew Jones , =?utf-8?q?Alex_Benn=C3=A9e?= , "Michael S. Tsirkin" , qemu-arm@nongnu.org, Udo Steinberg , Shannon Zhao , Gustavo Romero , Igor Mammedov , Peter Maydell , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v3 9/9] qtest/bios-tables-test: Update aarch64/virt 'its_off' variant blobs Date: Thu, 3 Apr 2025 22:40:29 +0200 Message-ID: <20250403204029.47958-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403204029.47958-1-philmd@linaro.org> References: <20250403204029.47958-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Commit the blobs generated by tests/data/acpi/rebuild-expected-aml.sh. Changes in the tables: @@ -1,32 +1,32 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20240927 (64-bit version) * Copyright (c) 2000 - 2023 Intel Corporation * * Disassembly of tests/data/acpi/aarch64/virt/APIC.its_off * * ACPI Data Table [APIC] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in hex) */ [000h 0000 004h] Signature : "APIC" [Multiple APIC Description Table (MADT)] -[004h 0004 004h] Table Length : 000000B8 +[004h 0004 004h] Table Length : 000000A4 [008h 0008 001h] Revision : 04 -[009h 0009 001h] Checksum : A7 +[009h 0009 001h] Checksum : EE [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 [024h 0036 004h] Local Apic Address : 00000000 [028h 0040 004h] Flags (decoded below) : 00000000 PC-AT Compatibility : 0 [02Ch 0044 001h] Subtable Type : 0C [Generic Interrupt Distributor] [02Dh 0045 001h] Length : 18 [02Eh 0046 002h] Reserved : 0000 [030h 0048 004h] Local GIC Hardware ID : 00000000 [034h 0052 008h] Base Address : 0000000008000000 [03Ch 0060 004h] Interrupt Base : 00000000 @@ -49,37 +49,29 @@ [06Ch 0108 008h] Virtual GIC Base Address : 0000000000000000 [074h 0116 008h] Hypervisor GIC Base Address : 0000000000000000 [07Ch 0124 004h] Virtual GIC Interrupt : 00000019 [080h 0128 008h] Redistributor Base Address : 0000000000000000 [088h 0136 008h] ARM MPIDR : 0000000000000000 [090h 0144 001h] Efficiency Class : 00 [091h 0145 001h] Reserved : 00 [092h 0146 002h] SPE Overflow Interrupt : 0000 [094h 0148 002h] TRBE Interrupt : 100E [094h 0148 001h] Subtable Type : 0E [Generic Interrupt Redistributor] [095h 0149 001h] Length : 10 [097h 0151 002h] Reserved : 0000 [098h 0152 008h] Base Address : 00000000080A0000 [0A0h 0160 004h] Length : 00F60000 -[0A4h 0164 001h] Subtable Type : 0F [Generic Interrupt Translator] -[0A5h 0165 001h] Length : 14 -[0A7h 0167 002h] Reserved : 0000 -[0A8h 0168 004h] Translation ID : 00000000 -[0ACh 0172 008h] Base Address : 0000000008080000 -[0B4h 0180 004h] Reserved : 00000000 +Raw Table Data: Length 164 (0xA4) -Raw Table Data: Length 184 (0xB8) - - 0000: 41 50 49 43 B8 00 00 00 04 A7 42 4F 43 48 53 20 // APIC......BOCHS + 0000: 41 50 49 43 A4 00 00 00 04 EE 42 4F 43 48 53 20 // APIC......BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC 0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // ................ 0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // ................ 0040: 04 00 00 00 0B 50 00 00 00 00 00 00 00 00 00 00 // .....P.......... 0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ................ 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0070: 00 00 00 00 00 00 00 00 00 00 00 00 19 00 00 00 // ................ 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0090: 00 00 00 00 0E 10 00 00 00 00 0A 08 00 00 00 00 // ................ - 00A0: 00 00 F6 00 0F 14 00 00 00 00 00 00 00 00 08 08 // ................ - 00B0: 00 00 00 00 00 00 00 00 // ........ + 00A0: 00 00 F6 00 // .... /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20240927 (64-bit version) * Copyright (c) 2000 - 2023 Intel Corporation * * Disassembly of tests/data/acpi/aarch64/virt/FACP * * ACPI Data Table [FACP] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in hex) */ [000h 0000 004h] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 004h] Table Length : 00000114 [008h 0008 001h] Revision : 06 -[009h 0009 001h] Checksum : 12 +[009h 0009 001h] Checksum : 14 [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 [024h 0036 004h] FACS Address : 00000000 [028h 0040 004h] DSDT Address : 00000000 [02Ch 0044 001h] Model : 00 [02Dh 0045 001h] PM Profile : 00 [Unspecified] [02Eh 0046 002h] SCI Interrupt : 0000 [030h 0048 004h] SMI Command Port : 00000000 [034h 0052 001h] ACPI Enable Value : 00 [035h 0053 001h] ACPI Disable Value : 00 [036h 0054 001h] S4BIOS Command : 00 [037h 0055 001h] P-State Control : 00 @@ -82,35 +82,35 @@ Use Platform Timer (V4) : 0 RTC_STS valid on S4 wake (V4) : 0 Remote Power-on capable (V4) : 0 Use APIC Cluster Model (V4) : 0 Use APIC Physical Destination Mode (V4) : 0 Hardware Reduced (V5) : 1 Low Power S0 Idle (V5) : 0 [074h 0116 00Ch] Reset Register : [Generic Address Structure] [074h 0116 001h] Space ID : 00 [SystemMemory] [075h 0117 001h] Bit Width : 00 [076h 0118 001h] Bit Offset : 00 [077h 0119 001h] Encoded Access Width : 00 [Undefined/Legacy] [078h 0120 008h] Address : 0000000000000000 [080h 0128 001h] Value to cause reset : 00 -[081h 0129 002h] ARM Flags (decoded below) : 0003 +[081h 0129 002h] ARM Flags (decoded below) : 0001 PSCI Compliant : 1 - Must use HVC for PSCI : 1 + Must use HVC for PSCI : 0 [083h 0131 001h] FADT Minor Revision : 03 [084h 0132 008h] FACS Address : 0000000000000000 [08Ch 0140 008h] DSDT Address : 0000000000000000 [094h 0148 00Ch] PM1A Event Block : [Generic Address Structure] [094h 0148 001h] Space ID : 00 [SystemMemory] [095h 0149 001h] Bit Width : 00 [096h 0150 001h] Bit Offset : 00 [097h 0151 001h] Encoded Access Width : 00 [Undefined/Legacy] [098h 0152 008h] Address : 0000000000000000 [0A0h 0160 00Ch] PM1B Event Block : [Generic Address Structure] [0A0h 0160 001h] Space ID : 00 [SystemMemory] [0A1h 0161 001h] Bit Width : 00 [0A2h 0162 001h] Bit Offset : 00 [0A3h 0163 001h] Encoded Access Width : 00 [Undefined/Legacy] @@ -164,34 +164,34 @@ [0F5h 0245 001h] Bit Width : 00 [0F6h 0246 001h] Bit Offset : 00 [0F7h 0247 001h] Encoded Access Width : 00 [Undefined/Legacy] [0F8h 0248 008h] Address : 0000000000000000 [100h 0256 00Ch] Sleep Status Register : [Generic Address Structure] [100h 0256 001h] Space ID : 00 [SystemMemory] [101h 0257 001h] Bit Width : 00 [102h 0258 001h] Bit Offset : 00 [103h 0259 001h] Encoded Access Width : 00 [Undefined/Legacy] [104h 0260 008h] Address : 0000000000000000 [10Ch 0268 008h] Hypervisor ID : 00000000554D4551 Raw Table Data: Length 276 (0x114) - 0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20 // FACP......BOCHS + 0000: 46 41 43 50 14 01 00 00 06 14 42 4F 43 48 53 20 // FACP......BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 01 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............QEMU 0110: 00 00 00 00 // .... @@ -1,122 +1,111 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20240927 (64-bit version) * Copyright (c) 2000 - 2023 Intel Corporation * * Disassembly of tests/data/acpi/aarch64/virt/IORT.its_off * * ACPI Data Table [IORT] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in hex) */ [000h 0000 004h] Signature : "IORT" [IO Remapping Table] -[004h 0004 004h] Table Length : 000000EC +[004h 0004 004h] Table Length : 000000D4 [008h 0008 001h] Revision : 03 -[009h 0009 001h] Checksum : 57 +[009h 0009 001h] Checksum : A3 [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 [024h 0036 004h] Node Count : 00000003 [028h 0040 004h] Node Offset : 00000030 [02Ch 0044 004h] Reserved : 00000000 -[030h 0048 001h] Type : 00 -[031h 0049 002h] Length : 0018 -[033h 0051 001h] Revision : 01 +[030h 0048 001h] Type : 04 +[031h 0049 002h] Length : 0058 +[033h 0051 001h] Revision : 04 [034h 0052 004h] Identifier : 00000000 -[038h 0056 004h] Mapping Count : 00000000 -[03Ch 0060 004h] Mapping Offset : 00000000 +[038h 0056 004h] Mapping Count : 00000001 +[03Ch 0060 004h] Mapping Offset : 00000044 -[040h 0064 004h] ItsCount : 00000001 -[044h 0068 004h] Identifiers : 00000000 - -[048h 0072 001h] Type : 04 -[049h 0073 002h] Length : 0058 -[04Bh 0075 001h] Revision : 04 -[04Ch 0076 004h] Identifier : 00000001 -[050h 0080 004h] Mapping Count : 00000001 -[054h 0084 004h] Mapping Offset : 00000044 - -[058h 0088 008h] Base Address : 0000000009050000 -[060h 0096 004h] Flags (decoded below) : 00000001 +[040h 0064 008h] Base Address : 0000000009050000 +[048h 0072 004h] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 DeviceID Valid : 0 -[064h 0100 004h] Reserved : 00000000 -[068h 0104 008h] VATOS Address : 0000000000000000 -[070h 0112 004h] Model : 00000000 -[074h 0116 004h] Event GSIV : 0000006A -[078h 0120 004h] PRI GSIV : 0000006B -[07Ch 0124 004h] GERR GSIV : 0000006D -[080h 0128 004h] Sync GSIV : 0000006C -[084h 0132 004h] Proximity Domain : 00000000 -[088h 0136 004h] Device ID Mapping Index : 00000000 +[04Ch 0076 004h] Reserved : 00000000 +[050h 0080 008h] VATOS Address : 0000000000000000 +[058h 0088 004h] Model : 00000000 +[05Ch 0092 004h] Event GSIV : 0000006A +[060h 0096 004h] PRI GSIV : 0000006B +[064h 0100 004h] GERR GSIV : 0000006D +[068h 0104 004h] Sync GSIV : 0000006C +[06Ch 0108 004h] Proximity Domain : 00000000 +[070h 0112 004h] Device ID Mapping Index : 00000000 -[08Ch 0140 004h] Input base : 00000000 -[090h 0144 004h] ID Count : 0000FFFF -[094h 0148 004h] Output Base : 00000000 -[098h 0152 004h] Output Reference : 00000030 -[09Ch 0156 004h] Flags (decoded below) : 00000000 +[074h 0116 004h] Input base : 00000000 +[078h 0120 004h] ID Count : 0000FFFF +[07Ch 0124 004h] Output Base : 00000000 +[080h 0128 004h] Output Reference : 00000030 +[084h 0132 004h] Flags (decoded below) : 00000000 Single Mapping : 0 -[0A0h 0160 001h] Type : 02 -[0A1h 0161 002h] Length : 004C -[0A3h 0163 001h] Revision : 03 -[0A4h 0164 004h] Identifier : 00000002 -[0A8h 0168 004h] Mapping Count : 00000002 -[0ACh 0172 004h] Mapping Offset : 00000024 +[088h 0136 001h] Type : 02 +[089h 0137 002h] Length : 004C +[08Bh 0139 001h] Revision : 03 +[08Ch 0140 004h] Identifier : 00000001 +[090h 0144 004h] Mapping Count : 00000002 +[094h 0148 004h] Mapping Offset : 00000024 -[0B0h 0176 008h] Memory Properties : [IORT Memory Access Properties] -[0B0h 0176 004h] Cache Coherency : 00000001 -[0B4h 0180 001h] Hints (decoded below) : 00 +[098h 0152 008h] Memory Properties : [IORT Memory Access Properties] +[098h 0152 004h] Cache Coherency : 00000001 +[09Ch 0156 001h] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 -[0B5h 0181 002h] Reserved : 0000 -[0B7h 0183 001h] Memory Flags (decoded below) : 03 +[09Dh 0157 002h] Reserved : 0000 +[09Fh 0159 001h] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 Ensured Coherency of Accesses : 0 -[0B8h 0184 004h] ATS Attribute : 00000000 -[0BCh 0188 004h] PCI Segment Number : 00000000 -[0C0h 0192 001h] Memory Size Limit : 40 -[0C1h 0193 002h] PASID Capabilities : 0000 -[0C3h 0195 001h] Reserved : 00 +[0A0h 0160 004h] ATS Attribute : 00000000 +[0A4h 0164 004h] PCI Segment Number : 00000000 +[0A8h 0168 001h] Memory Size Limit : 40 +[0A9h 0169 002h] PASID Capabilities : 0000 +[0ABh 0171 001h] Reserved : 00 -[0C4h 0196 004h] Input base : 00000000 -[0C8h 0200 004h] ID Count : 000000FF -[0CCh 0204 004h] Output Base : 00000000 -[0D0h 0208 004h] Output Reference : 00000048 -[0D4h 0212 004h] Flags (decoded below) : 00000000 +[0ACh 0172 004h] Input base : 00000000 +[0B0h 0176 004h] ID Count : 000000FF +[0B4h 0180 004h] Output Base : 00000000 +[0B8h 0184 004h] Output Reference : 00000030 +[0BCh 0188 004h] Flags (decoded below) : 00000000 Single Mapping : 0 -[0D8h 0216 004h] Input base : 00000100 -[0DCh 0220 004h] ID Count : 0000FEFF -[0E0h 0224 004h] Output Base : 00000100 -[0E4h 0228 004h] Output Reference : 00000030 -[0E8h 0232 004h] Flags (decoded below) : 00000000 +[0C0h 0192 004h] Input base : 00000100 +[0C4h 0196 004h] ID Count : 0000FEFF +[0C8h 0200 004h] Output Base : 00000100 +[0CCh 0204 004h] Output Reference : 00000030 +[0D0h 0208 004h] Flags (decoded below) : 00000000 Single Mapping : 0 -Raw Table Data: Length 236 (0xEC) +Raw Table Data: Length 212 (0xD4) - 0000: 49 4F 52 54 EC 00 00 00 03 57 42 4F 43 48 53 20 // IORT.....WBOCHS + 0000: 49 4F 52 54 D4 00 00 00 03 A3 42 4F 43 48 53 20 // IORT......BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC 0020: 01 00 00 00 03 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 0030: 00 18 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0040: 01 00 00 00 00 00 00 00 04 58 00 04 01 00 00 00 // .........X...... - 0050: 01 00 00 00 44 00 00 00 00 00 05 09 00 00 00 00 // ....D........... - 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0070: 00 00 00 00 6A 00 00 00 6B 00 00 00 6D 00 00 00 // ....j...k...m... - 0080: 6C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // l............... - 0090: FF FF 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0....... - 00A0: 02 4C 00 03 02 00 00 00 02 00 00 00 24 00 00 00 // .L..........$... - 00B0: 01 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 // ................ - 00C0: 40 00 00 00 00 00 00 00 FF 00 00 00 00 00 00 00 // @............... - 00D0: 48 00 00 00 00 00 00 00 00 01 00 00 FF FE 00 00 // H............... - 00E0: 00 01 00 00 30 00 00 00 00 00 00 00 // ....0....... + 0030: 04 58 00 04 00 00 00 00 01 00 00 00 44 00 00 00 // .X..........D... + 0040: 00 00 05 09 00 00 00 00 01 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 6A 00 00 00 // ............j... + 0060: 6B 00 00 00 6D 00 00 00 6C 00 00 00 00 00 00 00 // k...m...l....... + 0070: 00 00 00 00 00 00 00 00 FF FF 00 00 00 00 00 00 // ................ + 0080: 30 00 00 00 00 00 00 00 02 4C 00 03 01 00 00 00 // 0........L...... + 0090: 02 00 00 00 24 00 00 00 01 00 00 00 00 00 00 03 // ....$........... + 00A0: 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 // ........@....... + 00B0: FF 00 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0....... + 00C0: 00 01 00 00 FF FE 00 00 00 01 00 00 30 00 00 00 // ............0... + 00D0: 00 00 00 00 // .... Signed-off-by: Philippe Mathieu-Daudé --- tests/qtest/bios-tables-test-allowed-diff.h | 3 --- tests/data/acpi/aarch64/virt/APIC.its_off | Bin 184 -> 164 bytes tests/data/acpi/aarch64/virt/IORT.its_off | Bin 236 -> 212 bytes 3 files changed, 3 deletions(-) diff --git a/tests/data/acpi/aarch64/virt/APIC.its_off b/tests/data/acpi/aarch64/virt/APIC.its_off index c37d05d6e05805304f10afe73eb7cb9100fcccfa..f24ac8fbff5261a52434abcfcff96dbdc7709de4 100644 GIT binary patch delta 18 ZcmdnNxP+0*F~HM#2?GNI%e#qOvj8xy1yKM1 delta 39 jcmZ3&xPy_)F~HM#2Ll5G%kqg_vqbnsfJ`vp;DE6Jpmzmj diff --git a/tests/data/acpi/aarch64/virt/IORT.its_off b/tests/data/acpi/aarch64/virt/IORT.its_off index 0fceb820d509e852ca0849baf568a8e93e426738..25f64407c4aac11bda2d1ac24cd8999a1d84c80d 100644 GIT binary patch delta 37 tcmaFEc!iP6(?2NW3IhWJ^WuqIYOE{~3@i*2eZv_UCoa`yG?;i%8UVn-3Gn~` delta 61 zcmcb@_=b_o(?2NW4FdxMbNECqHCYA;21XzU4qzOX2nH6$iKgL