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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c30226cf6sm38142f8f.87.2025.04.02.15.23.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 15:23:40 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.1 01/13] target/arm/cpu-features: Include missing 'cpu.h' header Date: Thu, 3 Apr 2025 00:23:21 +0200 Message-ID: <20250402222334.66511-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402222334.66511-1-philmd@linaro.org> References: <20250402222334.66511-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/arm/cpu-features.h" dereferences the ARMISARegisters structure, which is defined in "cpu.h". Include the latter to avoid when refactoring unrelated headers: In file included from target/arm/internals.h:33: target/arm/cpu-features.h:45:54: error: unknown type name 'ARMISARegisters' 45 | static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) | ^ target/arm/cpu-features.h:47:12: error: use of undeclared identifier 'R_ID_ISAR0_DIVIDE_SHIFT' 47 | return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; | ^ Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu-features.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 525e4cee12f..4452e7c21e3 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -22,6 +22,7 @@ #include "hw/registerfields.h" #include "qemu/host-utils.h" +#include "cpu.h" /* * Naming convention for isar_feature functions: From patchwork Wed Apr 2 22:23:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877754 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2986722wrs; Wed, 2 Apr 2025 15:28:10 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWV7mha3G/Xg5D+6umRRSjFHMuTd0CvYcbmsnLAAdKikXrUQ2L7HbWNaXxP0Ysft8kuMFCQwg==@linaro.org X-Google-Smtp-Source: AGHT+IEtHLqPdhndqhsWApg60gqn5S9IZMRdZA1d3f0BOyShOUQG4EdtzbAT9wAk26cPGKMkTklO X-Received: by 2002:a05:6000:40d9:b0:399:6d53:68d9 with SMTP id ffacd0b85a97d-39c297e42a2mr3927447f8f.38.1743632890265; Wed, 02 Apr 2025 15:28:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743632890; cv=none; d=google.com; s=arc-20240605; b=B/2COFDJADdO45EzSkJhQrXb/jpBWyE1HsPvzZRNb9lPi+T0l0z0RifVm0PyIXETGE SU/tAo0XzDIYyEtA5jWXeTbl8/nAuuOOZCClYSiHONDJMGGQjjxFwCe/woevxjzFX5io N9lHLmTxeN1xP7fYscddMKqeZ27BgcM0WW+1UmkJWpjWQrZMbZeEZOVr2DyTFLKvhdsI HrhDrSWOIXnlkmREvqMONLLJ2q52gFSXLBCZuLrHB+U5eLbFnXFSDX+Kj48LTJhpgR4/ C3off97abRO1PZodBZckH1OEfE2UMARIcFs31HloZHVEI2ARfwC2R9C9UiAOUDcnSbag VqEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nUYX2kXnCOGEv2tsFjiwF/vNelOghwEQOe8hhegma5c=; fh=ILu9n9UJYyGKJ+F9rVBU1LrxK5aJ3ihMVgUEh7OR7WA=; b=OYM25GGGqNmwZNUKaxX3k5q7YkEgazZNjF2VBoWRLVdYg11LQ3en0txKMudM6MMxiw 7qOFJETc8XwCyDsQhgw+gvQPPDAEB3Kj1977QLbu3oEOBjCVjZecE9RWujHV19GCXPDl tZGpo7X3NBVIRSQFDpqHfacXAtw6/4aTf7lyb3IdWy1SfiBfEpJ5VRwclEyAgRfZu9HW cSG2qM+hiLRi1dMws/D1NIUdKVdgmbG5410C8jWiiXlUeHxwG5s/OKq0gYevPQqO3VAK +GCV9ASJjvcZ5z8+m1HDGqanDOIxik1uDfptUqKLYERiP2gEUKrnbAKzSRr9OJQ9FAR9 jV5g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e17PYVKB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec364ec90sm178875e9.27.2025.04.02.15.23.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 15:23:46 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.1 02/13] target/arm/qmp: Include missing 'cpu.h' header Date: Thu, 3 Apr 2025 00:23:22 +0200 Message-ID: <20250402222334.66511-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402222334.66511-1-philmd@linaro.org> References: <20250402222334.66511-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org arm-qmp-cmds.c uses ARM_MAX_VQ, which is defined in "cpu.h". Include the latter to avoid when refactoring unrelated headers: target/arm/arm-qmp-cmds.c:83:19: error: use of undeclared identifier 'ARM_MAX_VQ' 83 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); | ^ Signed-off-by: Philippe Mathieu-Daudé --- target/arm/arm-qmp-cmds.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c index 883c0a0e8cc..d654be2a619 100644 --- a/target/arm/arm-qmp-cmds.c +++ b/target/arm/arm-qmp-cmds.c @@ -30,6 +30,7 @@ #include "qapi/qapi-commands-misc-target.h" #include "qobject/qdict.h" #include "qom/qom-qobject.h" +#include "cpu.h" static GICCapability *gic_cap_new(int version) { From patchwork Wed Apr 2 22:23:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877751 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2986352wrs; Wed, 2 Apr 2025 15:26:40 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCURdyb+mlUdY/VmayFYHvOzEQ3G/EWmIL4O1KosavKzFtPYeT+54uQrK4BFVX1NsISwdZzYIw==@linaro.org X-Google-Smtp-Source: AGHT+IE5sGVMwCbHxx7eeGZoeAFg94G5vdHuK1h8aXqQ0Gzkl+L3X5ZbfpdtbBZnb4EvC5jnnLE2 X-Received: by 2002:a05:600c:5251:b0:43c:ef55:f1e8 with SMTP id 5b1f17b1804b1-43db6248b91mr149526145e9.13.1743632800691; Wed, 02 Apr 2025 15:26:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743632800; cv=none; d=google.com; s=arc-20240605; b=lQNWfAKADZGjzNbCdIw30MnfqhPSnfKcGPMXzcmEaHKLTz9EbtE1j04ykK2+JMX6Av d0to2O285L/7GqfzZYf/NBu2SKONgCms8xzqjGeXawSsqi3SOdqWtPa7kyGc84QQDgq2 Uv2iOV84fFi0joZNyOILNDXLxZnnkrhC9MDFVqMNDb9pNredHvt5Tb6lKNwmRJcq5Da5 6WeZ3MlEH8m+1HvXNxH22myAnZy9tP3k+fC7VepKePGK8Z1q0k7o3txt4CZuXSmiSqwi XrOfmxVQNhcv8NfO2VSlhxFItY3UwKhlP6jnsPOL+G1vOudndDscL8s0+tN5iCfaMVUn UGkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=IF+jDmIMfBmIbllVlD3DN4Sv3rGc5cOgP9Etawn2VWg=; fh=ILu9n9UJYyGKJ+F9rVBU1LrxK5aJ3ihMVgUEh7OR7WA=; b=FEk/MGLIUIsdALhmIcoTLHn6P7Xdsu8KEpEp95qkNN5apURN9ZVEHPihzGG8Wb6zau /nLWAtJf8nfAWKPx90PnsH5Ej2ZTsLR6LjkApQupf9WFTyUh4fz9/ixEZ9XtxvP6jIzo q8woPNNSSwXhYY0MYNbzZ/HL/0pAUn+5Wkz2l33fhnopQgQplC5eJP0MAk2PCNU5CRi3 a+FmpzrsLJd8gdlUFNqinrKf5aAVxpV3DNP6mqRAeGAIsSCvCKKFp56EPwPgueaD+u/L be+DCPFwwmWxMr1ehrR2GDbT/Ei8GrMc7gG+UIv0dMhepyatLDRamsmWON14ZZIkQ4/e qxQQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=loar4jw5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec34a895fsm407675e9.13.2025.04.02.15.23.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 15:23:50 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.1 03/13] target/arm/kvm: Include missing 'cpu-qom.h' header Date: Thu, 3 Apr 2025 00:23:23 +0200 Message-ID: <20250402222334.66511-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402222334.66511-1-philmd@linaro.org> References: <20250402222334.66511-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org ARMCPU typedef is declared in "cpu-qom.h". Include it in order to avoid when refactoring unrelated headers: target/arm/kvm_arm.h:54:29: error: unknown type name 'ARMCPU' 54 | bool write_list_to_kvmstate(ARMCPU *cpu, int level); | ^ Signed-off-by: Philippe Mathieu-Daudé --- target/arm/kvm_arm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 05c3de8cd46..2db2f060e6a 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -12,6 +12,7 @@ #define QEMU_KVM_ARM_H #include "system/kvm.h" +#include "target/arm/cpu-qom.h" #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) From patchwork Wed Apr 2 22:23:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877749 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2986257wrs; Wed, 2 Apr 2025 15:26:18 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXysRaZwtB+8Kwb7Ssh36JPPfE2Sf/4a6Of+FwEWfnaro3C9+us69prsb1Upc2HyWIlm0apYw==@linaro.org X-Google-Smtp-Source: AGHT+IER34feQb67IAMDQrKcOgs1vEbG5m55RDVHGr/tyFP1bK8aPRWm3eTJrazt6gH0S40D7Mts X-Received: by 2002:a05:6000:4203:b0:39c:1f0b:8f6f with SMTP id ffacd0b85a97d-39c297538f4mr3379604f8f.24.1743632778677; Wed, 02 Apr 2025 15:26:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743632778; cv=none; d=google.com; s=arc-20240605; b=gqmMXK5V9sLDG0/HwHEDaj0h+6LIVqS0RB/p0DJtzIAaUrPix+GQn3iwyBr6AOp0a7 K/HXGevRII+NpA98WaLSYFpHbCSPAspoTE/Rgz1/eiCN58N8ghUOAdM+UL949PKXUTfB LK/sV63klxyaQw28rCVstcBvRHYSY+OlXbCcrN6Qxk7W3cPLrOkXfzEY6HeBpJuxpwqY Ivvoa2uTbABqur8WQhLcU2EZcWxZI3GWnkAk+Q+ualdzjUC+zyRYNsBUu2xKRB3sEIag ogqKbvEZC8CKAV/Pfa8MNbCobTRHgz9c07Y4X1pCi4rZNua6mEfyR5bUwZOk6TjrgQu7 0DgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bumN4/Pb+TslNnZNvPYQc/X9CuHJhfIAJHquLppK698=; fh=ILu9n9UJYyGKJ+F9rVBU1LrxK5aJ3ihMVgUEh7OR7WA=; b=YtGdB7nLZ1fkesqSzd7RXhWjoEH/CMOM00OoNJGxoBqSagwkH48GUWXCkhbycJJ1L5 pevb4Vq5j6i1obCGYcWoExIBgWvxxDrQHzoXmKJ/VLl0+JZbwu9vkGKXrdfIAzWvW9lk +NjBNbmwzJK6G//lAOoOSlynNBo9zkNEjJpWx7ewGNjuQVbNncT7PRqWJJ12RwPdGB7s +M/WTeWoMU+vOB3Gx+sX1/donsEOW46aeBIgfG0zH5vfBjeqxnktviwajSG/tUqquiRD FTx6f2pwsdfZoGpPjjCgQZ51nm3vyE0b+t1M5sfo8lG9gPZk6nY7Kn1HNmCtRiOXfkew 1hQw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="n+Fna2/+"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec3669d0fsm158475e9.36.2025.04.02.15.23.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 15:23:55 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.1 04/13] target/arm/hvf: Include missing 'cpu-qom.h' header Date: Thu, 3 Apr 2025 00:23:24 +0200 Message-ID: <20250402222334.66511-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402222334.66511-1-philmd@linaro.org> References: <20250402222334.66511-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org ARMCPU typedef is declared in "cpu-qom.h". Include it in order to avoid when refactoring unrelated headers: target/arm/hvf_arm.h:23:41: error: unknown type name 'ARMCPU' 23 | void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); | ^ Signed-off-by: Philippe Mathieu-Daudé --- target/arm/hvf_arm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h index 26c717b3826..ee5545f2d10 100644 --- a/target/arm/hvf_arm.h +++ b/target/arm/hvf_arm.h @@ -11,7 +11,7 @@ #ifndef QEMU_HVF_ARM_H #define QEMU_HVF_ARM_H -#include "cpu.h" +#include "target/arm/cpu-qom.h" /** * hvf_arm_init_debug() - initialize guest debug capabilities From patchwork Wed Apr 2 22:23:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877743 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2985853wrs; Wed, 2 Apr 2025 15:24:41 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXl6Rq7U+OCXjV7uSg3lKzxsJZf1JZbmlqB9MPCCJLQJ9F12zg6OKAwCnfjOMJN3kObKSSU0g==@linaro.org X-Google-Smtp-Source: AGHT+IG6CFk6FPmYrqCT1qkH/xuDWGKWatLrc9Ib9dK8PTUtcy4AHxcw0BhaxZLGsUbgBFHWnsN7 X-Received: by 2002:ad4:5c8e:0:b0:6e2:383f:4acd with SMTP id 6a1803df08f44-6ef0bebd14dmr21161746d6.7.1743632681181; Wed, 02 Apr 2025 15:24:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743632681; cv=none; d=google.com; s=arc-20240605; b=FmnTruKG3LL7o2aLSejI8C7GN0wNVW2j1+VL+ekQjvhFiUcUVdupbZ+iCf58wTFoAT +yWUGA3YjO4MiAJLTb2unJgsK4qw0cK7nVgfsdNLJUuOhd35AoHGucI8nEp/aVyNxJ4/ 1NEaBRop2XtXQ+MgTcNwwGhBcGOtNX5o6quQNQQGksDwtX4EJ0gNScAPqBCr0FOUovvq 7l3sMMpHfBoPQtzUTB3zf74BAz4rIyMFlQAIjCiHCmembgkdgBbyp+cbjm2/CWL63G3u GSxtMoMae4yez9/0IaaR1RA6cKCmt0LQIwfn6HbME15lW1Ic37B+ushk/ZTBTWa+pfuz KPiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=NVShLiex+VpxD1+UXUcJFbn1pbrK3CPKZRrEhd996ZI=; fh=ILu9n9UJYyGKJ+F9rVBU1LrxK5aJ3ihMVgUEh7OR7WA=; b=SSz/hm8B1ZlBxoAXdhTQHVKcxzfTvS46uXhdSgpMsIKnnQRooZHrZ+P0i0M7tslpHs dIxIEpfUYIrn4Fldr4TKJNbfIrw7NrlL0mfmuC5U9emBigJdHOSMhiNe4KH1yiUjGuXP ldB26GnOfe9cig0/WIuTtaNjvlA0IQHL3CFE0Rtreog80eQezNnW9Z/7nqwGZlDwCLMH p9l2gfJDCmuJ3vYtY+uoQxrcHXxs1x4GpE9XEm+Z9P7pT5BAH3FhYehK0mJS9GWvWj4C d+gl78uiXJcmjIdt9g6VN47WlBnj5eTsLYaApLDtt0g95T3/CNrNjxOI+w5rsv3nNwa1 sm/g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DRRqEPTg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec169b8a3sm3815005e9.19.2025.04.02.15.23.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 15:23:59 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.1 05/13] hw/arm: Remove unnecessary 'cpu.h' header Date: Thu, 3 Apr 2025 00:23:25 +0200 Message-ID: <20250402222334.66511-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402222334.66511-1-philmd@linaro.org> References: <20250402222334.66511-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/exynos4210.c | 1 - hw/arm/highbank.c | 1 - hw/arm/mps3r.c | 1 - hw/arm/smmuv3.c | 1 - 4 files changed, 4 deletions(-) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index b452470598b..04439364370 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -24,7 +24,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "exec/tswap.h" -#include "cpu.h" #include "hw/cpu/a9mpcore.h" #include "hw/irq.h" #include "system/blockdev.h" diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index ea3621e4f87..0caa08631ad 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -35,7 +35,6 @@ #include "hw/cpu/a15mpcore.h" #include "qemu/log.h" #include "qom/object.h" -#include "cpu.h" #include "target/arm/cpu-qom.h" #define SMP_BOOT_ADDR 0x100 diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c index e9abbf00b43..604f6845fde 100644 --- a/hw/arm/mps3r.c +++ b/hw/arm/mps3r.c @@ -29,7 +29,6 @@ #include "qapi/error.h" #include "qobject/qlist.h" #include "system/address-spaces.h" -#include "cpu.h" #include "system/system.h" #include "hw/boards.h" #include "hw/or-irq.h" diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 4362ae6aa1c..df3f5a707a9 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -24,7 +24,6 @@ #include "hw/qdev-properties.h" #include "hw/qdev-core.h" #include "hw/pci/pci.h" -#include "cpu.h" #include "exec/target_page.h" #include "trace.h" #include "qemu/log.h" From patchwork Wed Apr 2 22:23:26 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec34a895fsm412665e9.13.2025.04.02.15.24.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 15:24:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.1 06/13] target/arm: Restrict inclusion of 'multiprocessing.h' Date: Thu, 3 Apr 2025 00:23:26 +0200 Message-ID: <20250402222334.66511-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402222334.66511-1-philmd@linaro.org> References: <20250402222334.66511-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Only cpu.c requires "multiprocessing.h" definitions so far. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 1 - target/arm/cpu.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 88ed06987f3..768e784c3e9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -30,7 +30,6 @@ #include "exec/gdbstub.h" #include "exec/page-protection.h" #include "qapi/qapi-types-common.h" -#include "target/arm/multiprocessing.h" #include "target/arm/gtimer.h" #define EXCP_UDEF 1 /* undefined instruction */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b1aa482c726..6f62745d7f6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -53,6 +53,7 @@ #include "qemu/target_info-qom.h" #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" +#include "target/arm/multiprocessing.h" static void arm_cpu_set_pc(CPUState *cs, vaddr value) { From patchwork Wed Apr 2 22:23:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877755 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2986731wrs; Wed, 2 Apr 2025 15:28:13 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX1rlPBsl58kggNK+tq+x8MckC49OaOwyb4W2Jxjr6hVfmozZuf63l/k0xbM/YfPaLpud+07w==@linaro.org X-Google-Smtp-Source: AGHT+IESpDLUVKInNBNQJFm+YBrzgEjjx+ML08YK7FbOOXLnycdP0pVfCDfhq31NUJsldnG0MSbQ X-Received: by 2002:a05:600c:45cd:b0:43d:54a:221c with SMTP id 5b1f17b1804b1-43e94a3bccdmr170207085e9.18.1743632893218; Wed, 02 Apr 2025 15:28:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743632893; cv=none; d=google.com; s=arc-20240605; b=C/gfRZXr0n7djGL29D5HMPhEusD/Jmiml5bx0+UBUqo/AXdOb9+RHRXWEzqiwipU4O g6Xu+8TA1wD4jAnXhxjiZ/8OCTXqiwdPA8TmIN0zQ45n+Jr0P70EsujaOKg9loVo6mqs +jFn+zFXiVgj8RqzjWqCs/Rk8e+6KGIDiEGGbffhxQpA/3fcSo64WrerQypPADMAZTGP 4am5gdDIo1rf1iNzI4ibeXvgTy1sqF8ALng54Jb1DRY+PWaMAvG7r24hOvc4kheni4d2 UPkviqq4LIM7RuLF5Rxg3vkzESggHh0rnu2Su5Cd5R+oycrVL9TcmyA9qDLcDwVVcXAe QJ7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gVdlHjO6zMdyeJFXmWmW2B+qZ532MIXjoEVZuCPnDX0=; fh=ILu9n9UJYyGKJ+F9rVBU1LrxK5aJ3ihMVgUEh7OR7WA=; b=UsThga/h6AIXFd6PM+q0woL+Eps2GdByXKQGWdswghzYscMeL5zoQSrDkwOujpAk2A aGMPfQ7TGXPoKsao0uZOG8pmm/0E6c3Oe5TKN0cyuXxoSMWboBCuA9Shao3RPwGoeSbS 5bfqip3/t8zhjalORQ3n3lUJFoCTzMOfDsb/gtpg79gELO3I4EOMeN7dfRFyGmzYG6LS eZS6nCfIu7qNZ6KaMbfNFiEXGqm+EtdLv97MH3mD43Nt2K2cumzU/TyYLiFi627T619l KKydGPBJB/Ho/ziZqNS20vgFB1h1lkAV4tMdkrbX/TCa/JAcfw3o84Goajj7rKusTVsd RLLw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IOV3ssRD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c300968cfsm64135f8f.16.2025.04.02.15.24.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 15:24:09 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.1 07/13] target/arm: Move some definitions from 'cpu.h' to 'multiprocessing.h' Date: Thu, 3 Apr 2025 00:23:27 +0200 Message-ID: <20250402222334.66511-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402222334.66511-1-philmd@linaro.org> References: <20250402222334.66511-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org arm_build_mp_affinity() and affinity mask definitionss are related to multiprocessing. Move them to "multiprocessing.h", including this header when necessary. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 17 ----------------- target/arm/multiprocessing.h | 18 ++++++++++++++++++ hw/arm/aspeed_ast2600.c | 1 + hw/arm/aspeed_ast27x0.c | 1 + hw/arm/exynos4210.c | 1 + hw/arm/npcm8xx.c | 1 + hw/arm/sbsa-ref.c | 1 + hw/vmapple/vmapple.c | 1 + target/arm/kvm.c | 1 + 9 files changed, 25 insertions(+), 17 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 768e784c3e9..45a9551535e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1158,23 +1158,6 @@ void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); void arm_cpu_post_init(Object *obj); -#define ARM_AFF0_SHIFT 0 -#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) -#define ARM_AFF1_SHIFT 8 -#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) -#define ARM_AFF2_SHIFT 16 -#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) -#define ARM_AFF3_SHIFT 32 -#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) -#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 - -#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) -#define ARM64_AFFINITY_MASK \ - (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) -#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) - -uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); - #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_arm_cpu; diff --git a/target/arm/multiprocessing.h b/target/arm/multiprocessing.h index 81715d345c2..8eec79b11d8 100644 --- a/target/arm/multiprocessing.h +++ b/target/arm/multiprocessing.h @@ -11,6 +11,24 @@ #include "target/arm/cpu-qom.h" +#define ARM_AFF0_SHIFT 0 +#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) +#define ARM_AFF1_SHIFT 8 +#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) +#define ARM_AFF2_SHIFT 16 +#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) +#define ARM_AFF3_SHIFT 32 +#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) +#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 + +#define ARM32_AFFINITY_MASK \ + (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) +#define ARM64_AFFINITY_MASK \ + (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) +#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) + +uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); + uint64_t arm_cpu_mp_affinity(ARMCPU *cpu); #endif diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 1f994ba26c6..4438402340b 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -17,6 +17,7 @@ #include "net/net.h" #include "system/system.h" #include "target/arm/cpu-qom.h" +#include "target/arm/multiprocessing.h" #define ASPEED_SOC_IOMEM_SIZE 0x00200000 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index dce7255a2c0..37bfeef304d 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -22,6 +22,7 @@ #include "hw/intc/arm_gicv3.h" #include "qobject/qlist.h" #include "qemu/log.h" +#include "target/arm/multiprocessing.h" static const hwaddr aspeed_soc_ast2700_memmap[] = { [ASPEED_DEV_SRAM] = 0x10000000, diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 04439364370..01e6e2fb052 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -36,6 +36,7 @@ #include "hw/sd/sdhci.h" #include "hw/usb/hcd-ehci.h" #include "target/arm/cpu-qom.h" +#include "target/arm/multiprocessing.h" #define EXYNOS4210_CHIPID_ADDR 0x10000000 diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c index f182accc47c..3987e55355b 100644 --- a/hw/arm/npcm8xx.c +++ b/hw/arm/npcm8xx.c @@ -29,6 +29,7 @@ #include "qapi/error.h" #include "qemu/units.h" #include "system/system.h" +#include "target/arm/multiprocessing.h" /* * This covers the whole MMIO space. We'll use this to catch any MMIO accesses diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 112cbbf29e6..90fbb56ba7a 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -52,6 +52,7 @@ #include "qom/object.h" #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" +#include "target/arm/multiprocessing.h" #define RAMLIMIT_GB 8192 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) diff --git a/hw/vmapple/vmapple.c b/hw/vmapple/vmapple.c index fa117bf1511..9bb5b0553a2 100644 --- a/hw/vmapple/vmapple.c +++ b/hw/vmapple/vmapple.c @@ -51,6 +51,7 @@ #include "system/reset.h" #include "system/runstate.h" #include "system/system.h" +#include "target/arm/multiprocessing.h" struct VMAppleMachineState { MachineState parent; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 97de8c7e939..a28acdecf3e 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -39,6 +39,7 @@ #include "hw/acpi/acpi.h" #include "hw/acpi/ghes.h" #include "target/arm/gtimer.h" +#include "target/arm/multiprocessing.h" #include "migration/blocker.h" const KVMCapabilityInfo kvm_arch_required_capabilities[] = { From patchwork Wed Apr 2 22:23:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877747 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2986097wrs; Wed, 2 Apr 2025 15:25:37 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWiPkUVOKtzl1zxKlIP2NO2zo2cDwv2kCxyqbrauroijXKTCsE3d0bwVrYiR1um6HwFFnD5+A==@linaro.org X-Google-Smtp-Source: AGHT+IHgzVZ84NQo7KukKaIA0KmWRadicJFQtd69lr9s+drn8uABDZXOtGLkp12+P4hitMQoDKN1 X-Received: by 2002:a05:600c:34c9:b0:43c:eea9:f438 with SMTP id 5b1f17b1804b1-43eb5c21213mr44815835e9.15.1743632736820; Wed, 02 Apr 2025 15:25:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743632736; cv=none; d=google.com; s=arc-20240605; b=VJo9ho99KRsq9F7zWCikRSVKXy05smJPEeK/uh7VBiiz/xryiliXQf+nZiW2wqFbMT h133CLtOUsr/R5PfURctBXLlhlkB93RzFkCvNILIvAbCJk6xrupqDpWeC9JMMPTbxN0z shWf0bkrlqKIuNqH8D/h08y86Dl9lgg9mOTBbephl9V+6xFAIodXcH/1Q8LoqaMWk+Hf HbxZfqxs+/3YIMUKHv/t+0hjRaLvWHw9XO+3gevHrQR7O3RXRjUqx56u7kCeG5L/swJH 9Vltasr8j6oUv6PGZ5oPo/xZoPL4CEtYd5c0zeLzRCmUeV3jaoXxV4q/hCNjnqCZi+xF maKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=eDr84eNBH4L+uB6tLy9qxz5WkTQN5f+BnjFqIVkh0pg=; fh=ILu9n9UJYyGKJ+F9rVBU1LrxK5aJ3ihMVgUEh7OR7WA=; b=U9Iag6bYfoC4Tt2GQwhdmVs3wIKcisdtZTZrKWHgA7JQYsD0iSOMIlzATlEWoOjRsV 6vcDcr1hbH5p02xjyFbi6Iw+1qH11CCXdgYZvIVmsOyJxCDlTwwC6U8F1OGeGK25iuHW 6F4aqBCkF191UCuDmw5x6ktK096Y6m3Qj5NC1Oy3iP8LMDoiF4QTixJcx7P2HbFG0eRT x8B/F9HTxdTZzA25jQJnLxbsHZNxrlXzCVYUeIjYk1wrDYwM4rpXfs8u63n2MBJIBcNv 7k9gvEftXKZeMN0VeVxn1ZC0lxuUTLhLFyHui9/Kwsm95bjloNbU0Xh66pbKOrE9lKzS 5rag==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dfrR6a1w; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec34ae0c5sm416475e9.15.2025.04.02.15.24.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 15:24:13 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.1 08/13] hw/arm: Include missing 'target/arm/gtimer.h' header Date: Thu, 3 Apr 2025 00:23:28 +0200 Message-ID: <20250402222334.66511-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402222334.66511-1-philmd@linaro.org> References: <20250402222334.66511-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/aspeed_ast27x0.c | 1 + hw/arm/bcm2838.c | 1 + hw/arm/exynos4210.c | 1 + hw/arm/fsl-imx8mp.c | 1 + hw/arm/mps3r.c | 1 + hw/arm/npcm8xx.c | 1 + hw/vmapple/vmapple.c | 1 + target/arm/tcg/op_helper.c | 1 + 8 files changed, 8 insertions(+) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 37bfeef304d..5c2481225dd 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -22,6 +22,7 @@ #include "hw/intc/arm_gicv3.h" #include "qobject/qlist.h" #include "qemu/log.h" +#include "target/arm/gtimer.h" #include "target/arm/multiprocessing.h" static const hwaddr aspeed_soc_ast2700_memmap[] = { diff --git a/hw/arm/bcm2838.c b/hw/arm/bcm2838.c index ddb7c5f757a..38d9b785a75 100644 --- a/hw/arm/bcm2838.c +++ b/hw/arm/bcm2838.c @@ -12,6 +12,7 @@ #include "hw/arm/raspi_platform.h" #include "hw/sysbus.h" #include "hw/arm/bcm2838.h" +#include "target/arm/gtimer.h" #include "trace.h" #define GIC400_MAINTENANCE_IRQ 9 diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 01e6e2fb052..ca40df3db75 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -36,6 +36,7 @@ #include "hw/sd/sdhci.h" #include "hw/usb/hcd-ehci.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" #include "target/arm/multiprocessing.h" #define EXYNOS4210_CHIPID_ADDR 0x10000000 diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 2cf5eeaf313..180feca9d80 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -17,6 +17,7 @@ #include "hw/boards.h" #include "system/system.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" #include "qapi/error.h" #include "qobject/qlist.h" diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c index 604f6845fde..37c0de28a92 100644 --- a/hw/arm/mps3r.c +++ b/hw/arm/mps3r.c @@ -47,6 +47,7 @@ #include "hw/ssi/pl022.h" #include "hw/timer/cmsdk-apb-dualtimer.h" #include "hw/watchdog/cmsdk-apb-watchdog.h" +#include "target/arm/gtimer.h" /* Define the layout of RAM and ROM in a board */ typedef struct RAMInfo { diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c index 3987e55355b..2f11bc53a86 100644 --- a/hw/arm/npcm8xx.c +++ b/hw/arm/npcm8xx.c @@ -29,6 +29,7 @@ #include "qapi/error.h" #include "qemu/units.h" #include "system/system.h" +#include "target/arm/gtimer.h" #include "target/arm/multiprocessing.h" /* diff --git a/hw/vmapple/vmapple.c b/hw/vmapple/vmapple.c index 9bb5b0553a2..25652b16f0c 100644 --- a/hw/vmapple/vmapple.c +++ b/hw/vmapple/vmapple.c @@ -51,6 +51,7 @@ #include "system/reset.h" #include "system/runstate.h" #include "system/system.h" +#include "target/arm/gtimer.h" #include "target/arm/multiprocessing.h" struct VMAppleMachineState { diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 38d49cbb9d8..005f84082af 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -25,6 +25,7 @@ #include "cpu-features.h" #include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" +#include "target/arm/gtimer.h" #include "cpregs.h" #define SIGNBIT (uint32_t)0x80000000 From patchwork Wed Apr 2 22:23:29 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c3020d9cfsm42716f8f.78.2025.04.02.15.24.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 15:24:18 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.1 09/13] target/arm: Extract PSCI definitions to 'psci.h' Date: Thu, 3 Apr 2025 00:23:29 +0200 Message-ID: <20250402222334.66511-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402222334.66511-1-philmd@linaro.org> References: <20250402222334.66511-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Extract PSCI definitions (which are not target specific) to the new "target/arm/psci.h", so code from hw/arm/ can use them without having to include the target specific "cpu.h" header. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/boot.h | 3 ++- target/arm/cpu.h | 6 ------ target/arm/psci.h | 18 ++++++++++++++++++ hw/arm/bananapi_m2u.c | 1 + hw/arm/boot.c | 1 + hw/arm/highbank.c | 1 + hw/arm/imx8mp-evk.c | 1 + hw/arm/mcimx6ul-evk.c | 1 + hw/arm/mcimx7d-sabre.c | 1 + hw/arm/orangepi.c | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt-acpi-build.c | 1 + hw/arm/virt.c | 1 + hw/arm/xlnx-versal-virt.c | 1 + hw/arm/xlnx-zcu102.c | 1 + hw/vmapple/vmapple.c | 1 + target/arm/helper.c | 1 + target/arm/hvf/hvf.c | 1 + target/arm/tcg/op_helper.c | 1 + target/arm/tcg/psci.c | 1 + 20 files changed, 37 insertions(+), 7 deletions(-) create mode 100644 target/arm/psci.h diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h index b12bf61ca81..648fdb88862 100644 --- a/include/hw/arm/boot.h +++ b/include/hw/arm/boot.h @@ -12,6 +12,7 @@ #define HW_ARM_BOOT_H #include "target/arm/cpu-qom.h" +//#include "target/arm/psci.h" #include "qemu/notify.h" typedef enum { @@ -100,7 +101,7 @@ struct arm_boot_info { * as the conduit specifies calls should go to (eg guest firmware booted * to EL3) then PSCI will not be enabled. */ - int psci_conduit; + int psci_conduit;// /* Used internally by arm_boot.c */ int is_linux; hwaddr initrd_start; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 45a9551535e..e78a1668bba 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3104,12 +3104,6 @@ static inline bool bswap_code(bool sctlr_b) void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags); -enum { - QEMU_PSCI_CONDUIT_DISABLED = 0, - QEMU_PSCI_CONDUIT_SMC = 1, - QEMU_PSCI_CONDUIT_HVC = 2, -}; - #ifndef CONFIG_USER_ONLY /* Return the address space index to use for a memory access */ static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) diff --git a/target/arm/psci.h b/target/arm/psci.h new file mode 100644 index 00000000000..8b868dfbb91 --- /dev/null +++ b/target/arm/psci.h @@ -0,0 +1,18 @@ +/* + * ARM Power State Coordination Interface (PSCI) definitions + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef TARGET_ARM_PSCI_H +#define TARGET_ARM_PSCI_H + +enum { + QEMU_PSCI_CONDUIT_DISABLED = 0, + QEMU_PSCI_CONDUIT_SMC = 1, + QEMU_PSCI_CONDUIT_HVC = 2, +}; + +#endif diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c index b750a575f72..61e01a38099 100644 --- a/hw/arm/bananapi_m2u.c +++ b/hw/arm/bananapi_m2u.c @@ -27,6 +27,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-r40.h" #include "hw/arm/boot.h" +#include "target/arm/psci.h" static struct arm_boot_info bpim2u_binfo; diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 79afb51b8a5..b81a850819b 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -29,6 +29,7 @@ #include "qemu/config-file.h" #include "qemu/option.h" #include "qemu/units.h" +#include "target/arm/psci.h" /* Kernel boot protocol is specified in the kernel docs * Documentation/arm/Booting and Documentation/arm64/booting.txt diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 0caa08631ad..16fb2508d30 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -36,6 +36,7 @@ #include "qemu/log.h" #include "qom/object.h" #include "target/arm/cpu-qom.h" +#include "target/arm/psci.h" #define SMP_BOOT_ADDR 0x100 #define SMP_BOOT_REG 0x40 diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c index 6e64ec4ea54..c8a99b2c49e 100644 --- a/hw/arm/imx8mp-evk.c +++ b/hw/arm/imx8mp-evk.c @@ -15,6 +15,7 @@ #include "system/qtest.h" #include "qemu/error-report.h" #include "qapi/error.h" +#include "target/arm/psci.h" static void imx8mp_evk_init(MachineState *machine) { diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index 86982cb0772..be5e50abf17 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -18,6 +18,7 @@ #include "hw/qdev-properties.h" #include "qemu/error-report.h" #include "system/qtest.h" +#include "target/arm/psci.h" static void mcimx6ul_evk_init(MachineState *machine) { diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index 33119610113..e0f25b92594 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -20,6 +20,7 @@ #include "hw/qdev-properties.h" #include "qemu/error-report.h" #include "system/qtest.h" +#include "target/arm/psci.h" static void mcimx7d_sabre_init(MachineState *machine) { diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index e0956880d11..99037a09a36 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -26,6 +26,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-h3.h" #include "hw/arm/boot.h" +#include "target/arm/psci.h" static struct arm_boot_info orangepi_binfo; diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 90fbb56ba7a..1f592627c99 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -53,6 +53,7 @@ #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" #include "target/arm/multiprocessing.h" +#include "target/arm/psci.h" #define RAMLIMIT_GB 8192 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 3ac8f8e1786..da61af1d359 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -59,6 +59,7 @@ #include "hw/acpi/viot.h" #include "hw/virtio/virtio-acpi.h" #include "target/arm/multiprocessing.h" +#include "target/arm/psci.h" #define ARM_SPI_BASE 32 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a96452f17a4..fe2dec9500f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -79,6 +79,7 @@ #include "target/arm/internals.h" #include "target/arm/multiprocessing.h" #include "target/arm/gtimer.h" +#include "target/arm/psci.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" #include "hw/acpi/generic_event_device.h" diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index e19c4d9ef58..94fad8e60f2 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -21,6 +21,7 @@ #include "hw/arm/xlnx-versal.h" #include "hw/arm/boot.h" #include "target/arm/multiprocessing.h" +#include "target/arm/psci.h" #include "qom/object.h" #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 88b1eafab4d..902ee65ca5f 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -26,6 +26,7 @@ #include "qom/object.h" #include "net/can_emu.h" #include "audio/audio.h" +#include "target/arm/psci.h" struct XlnxZCU102 { MachineState parent_obj; diff --git a/hw/vmapple/vmapple.c b/hw/vmapple/vmapple.c index 25652b16f0c..b73b6fb8115 100644 --- a/hw/vmapple/vmapple.c +++ b/hw/vmapple/vmapple.c @@ -53,6 +53,7 @@ #include "system/system.h" #include "target/arm/gtimer.h" #include "target/arm/multiprocessing.h" +#include "target/arm/psci.h" struct VMAppleMachineState { MachineState parent; diff --git a/target/arm/helper.c b/target/arm/helper.c index 7fb6e886306..48238ae0b20 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -34,6 +34,7 @@ #endif #include "cpregs.h" #include "target/arm/gtimer.h" +#include "target/arm/psci.h" #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 34ca36fab55..f617e73feae 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -33,6 +33,7 @@ #include "target/arm/internals.h" #include "target/arm/multiprocessing.h" #include "target/arm/gtimer.h" +#include "target/arm/psci.h" #include "trace.h" #include "migration/vmstate.h" diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 005f84082af..6e9db2e77e2 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -26,6 +26,7 @@ #include "exec/exec-all.h" #include "accel/tcg/cpu-ldst.h" #include "target/arm/gtimer.h" +#include "target/arm/psci.h" #include "cpregs.h" #define SIGNBIT (uint32_t)0x80000000 diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index cabed43e8a8..0313cdd6ba2 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -25,6 +25,7 @@ #include "internals.h" #include "arm-powerctl.h" #include "target/arm/multiprocessing.h" +#include "target/arm/psci.h" bool arm_is_psci_call(ARMCPU *cpu, int excp_type) { From patchwork Wed Apr 2 22:23:30 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec36699e0sm162755e9.35.2025.04.02.15.24.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 15:24:23 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.1 10/13] target/arm: Extract feature definitions to 'cpu_has_feature.h' header Date: Thu, 3 Apr 2025 00:23:30 +0200 Message-ID: <20250402222334.66511-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402222334.66511-1-philmd@linaro.org> References: <20250402222334.66511-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 54 +----------------------------- target/arm/cpu_has_feature.h | 65 ++++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+), 53 deletions(-) create mode 100644 target/arm/cpu_has_feature.h diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e78a1668bba..a76874badc3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -30,6 +30,7 @@ #include "exec/gdbstub.h" #include "exec/page-protection.h" #include "qapi/qapi-types-common.h" +#include "target/arm/cpu_has_feature.h" #include "target/arm/gtimer.h" #define EXCP_UDEF 1 /* undefined instruction */ @@ -2379,59 +2380,6 @@ FIELD(MFAR, NS, 63, 1) QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); -/* If adding a feature bit which corresponds to a Linux ELF - * HWCAP bit, remember to update the feature-bit-to-hwcap - * mapping in linux-user/elfload.c:get_elf_hwcap(). - */ -enum arm_features { - ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ - ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ - ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ - ARM_FEATURE_V6, - ARM_FEATURE_V6K, - ARM_FEATURE_V7, - ARM_FEATURE_THUMB2, - ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ - ARM_FEATURE_NEON, - ARM_FEATURE_M, /* Microcontroller profile. */ - ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ - ARM_FEATURE_THUMB2EE, - ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ - ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ - ARM_FEATURE_V4T, - ARM_FEATURE_V5, - ARM_FEATURE_STRONGARM, - ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ - ARM_FEATURE_GENERIC_TIMER, - ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ - ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ - ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ - ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ - ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ - ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ - ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ - ARM_FEATURE_V8, - ARM_FEATURE_AARCH64, /* supports 64 bit mode */ - ARM_FEATURE_CBAR, /* has cp15 CBAR */ - ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ - ARM_FEATURE_EL2, /* has EL2 Virtualization support */ - ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ - ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ - ARM_FEATURE_PMU, /* has PMU support */ - ARM_FEATURE_VBAR, /* has cp15 VBAR */ - ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ - ARM_FEATURE_M_MAIN, /* M profile Main Extension */ - ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ - /* - * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz - * if the board doesn't set a value, instead of 1GHz. It is for backwards - * compatibility and used only with CPU definitions that were already - * in QEMU before we changed the default. It should not be set on any - * CPU types added in future. - */ - ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ -}; - static inline int arm_feature(CPUARMState *env, int feature) { return (env->features & (1ULL << feature)) != 0; diff --git a/target/arm/cpu_has_feature.h b/target/arm/cpu_has_feature.h new file mode 100644 index 00000000000..2adfccd9208 --- /dev/null +++ b/target/arm/cpu_has_feature.h @@ -0,0 +1,65 @@ +/* + * Helper to check ARM CPU has features + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#ifndef TARGET_ARM_CPU_HAS_FEATURE_H +#define TARGET_ARM_CPU_HAS_FEATURE_H + +/* + * If adding a feature bit which corresponds to a Linux ELF + * HWCAP bit, remember to update the feature-bit-to-hwcap + * mapping in linux-user/elfload.c:get_elf_hwcap(). + */ +typedef enum arm_features { + ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ + ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ + ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ + ARM_FEATURE_V6, + ARM_FEATURE_V6K, + ARM_FEATURE_V7, + ARM_FEATURE_THUMB2, + ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ + ARM_FEATURE_NEON, + ARM_FEATURE_M, /* Microcontroller profile. */ + ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ + ARM_FEATURE_THUMB2EE, + ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ + ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ + ARM_FEATURE_V4T, + ARM_FEATURE_V5, + ARM_FEATURE_STRONGARM, + ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ + ARM_FEATURE_GENERIC_TIMER, + ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ + ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ + ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ + ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ + ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ + ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ + ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ + ARM_FEATURE_V8, + ARM_FEATURE_AARCH64, /* supports 64 bit mode */ + ARM_FEATURE_CBAR, /* has cp15 CBAR */ + ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ + ARM_FEATURE_EL2, /* has EL2 Virtualization support */ + ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ + ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ + ARM_FEATURE_PMU, /* has PMU support */ + ARM_FEATURE_VBAR, /* has cp15 VBAR */ + ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ + ARM_FEATURE_M_MAIN, /* M profile Main Extension */ + ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ + /* + * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz + * if the board doesn't set a value, instead of 1GHz. It is for backwards + * compatibility and used only with CPU definitions that were already + * in QEMU before we changed the default. It should not be set on any + * CPU types added in future. + */ + ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ +} ArmCpuFeature; + +#endif From patchwork Wed Apr 2 22:23:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877750 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2986342wrs; Wed, 2 Apr 2025 15:26:38 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVh2sM3rRKYd6jhSQW9Ekci5njLJhqDa4CT62IpgmAcf+k9F3y5A8xAgv3MIoUDIJW3jpd7fA==@linaro.org X-Google-Smtp-Source: AGHT+IHe+buXLLmHRw+QA0UM3tvTzMQKNPT4ur+ix7CsU+OgnbprxzkScLjqFWe0oXrb9fZjgyW4 X-Received: by 2002:a05:6000:430d:b0:399:71d4:b8 with SMTP id ffacd0b85a97d-39c2975399emr3530140f8f.23.1743632798584; Wed, 02 Apr 2025 15:26:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743632798; cv=none; d=google.com; s=arc-20240605; b=cj/ayR+mLQDRPef1S5Z9EIOngHKmONXQ3YyE8g9z8Fgrb2rVzwZPQdzpi61IMoY4t6 ZqsAqHumcUIMA+lswK9znrMN8imJFDV2SnRqCrhxbpeu0ewK2ifzNiToxzRmtc5DmRrI LKCOI3mM8Zbg2aBzRMskykm8Ix5AHPkZd3IhSFpVziR6GWdRf6bGABU552UVW32P1TEV Xfi/AhTg0gU1zhESzdXMOGt/rUOo3rqNlE6WOE/MMBC/SUILdaueIhgceizA7tTh0dxi BhMVgR80JExuyYMgpT4W4SNzKt/Wyy60+Xok6n/wvENzkIn+ErjhVvEoPGDJ3Km/Ld3a 3OKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=S80Ep4y75m4Bi1aemZem1kJn5yNrKjC8vfumsxl24F4=; fh=ILu9n9UJYyGKJ+F9rVBU1LrxK5aJ3ihMVgUEh7OR7WA=; b=SLvzX5SmPPBUNCUPXJV+bamYnmAgwy8oxdAB4PJ+YBHatfSmvfOOfo6m/EbZv2nLUl UA1o7yLMT3m1EF3rDUP0mxAwS5M2uVIufzYMYaWiCt5lMdJ0PjfVcv4L9VdIyf1ZdIjp uktXsQI+OQgspF8UITYRK8oL4BUdufH/ApwZgzversBRrwlS2Qf9ZrWQYPuVZ6NEil3M Q9lYGAVeFdlfVNJ8tG/WYHukzCwzfs+vfWR/m/GYt8DB+/9Rwv9Kb1k3R51U5xEhqjSq dHAsKND9Den6D8uJZRM2aVE6+sU/ZyfqoDO7vOT74LtBpxx6MbkL3fzqFKkm6uLg9QAW 7owA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jHC+Y4ch; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec366aa29sm161795e9.39.2025.04.02.15.24.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 15:24:27 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.1 11/13] target/arm: Add arm_cpu_has_feature() helper Date: Thu, 3 Apr 2025 00:23:31 +0200 Message-ID: <20250402222334.66511-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402222334.66511-1-philmd@linaro.org> References: <20250402222334.66511-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org arm_cpu_has_feature() is equivalent of arm_feature(), however while the latter uses CPUARMState so is target-specific, the former doesn't and can be called by target-agnostic code in hw/. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu_has_feature.h | 2 ++ target/arm/cpu.c | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/target/arm/cpu_has_feature.h b/target/arm/cpu_has_feature.h index 2adfccd9208..352f9d75bed 100644 --- a/target/arm/cpu_has_feature.h +++ b/target/arm/cpu_has_feature.h @@ -62,4 +62,6 @@ typedef enum arm_features { ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ } ArmCpuFeature; +bool arm_cpu_has_feature(ARMCPU *cpu, ArmCpuFeature feature); + #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6f62745d7f6..66a58916fcc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -55,6 +55,13 @@ #include "target/arm/gtimer.h" #include "target/arm/multiprocessing.h" +bool arm_cpu_has_feature(ARMCPU *cpu, ArmCpuFeature feature) +{ + CPUARMState *env = &cpu->env; + + return arm_feature(env, feature); +} + static void arm_cpu_set_pc(CPUState *cs, vaddr value) { ARMCPU *cpu = ARM_CPU(cs); From patchwork Wed Apr 2 22:23:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877748 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2986167wrs; Wed, 2 Apr 2025 15:25:56 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVPG8PjpNSsstnierviG3f1JGyBGGlB1xZ7a6uryLU3jSYzwmoqBDIXXlGWrDglLh2f1jxYnw==@linaro.org X-Google-Smtp-Source: AGHT+IHC27cbabdZcUx3gtVL0HkHsHA4C8iTkvSabyWicSgxIMU1AAmH2yBfsKwiPpdMXRMu+8fo X-Received: by 2002:a05:600c:510d:b0:43c:fee3:2bce with SMTP id 5b1f17b1804b1-43e258cc945mr141142575e9.26.1743632756281; Wed, 02 Apr 2025 15:25:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743632756; cv=none; d=google.com; s=arc-20240605; b=XUGY+XrxmY5QiMbBklcqkfq5PjeT0Z1EOeLcRbhdKWR47fA0jXOH7NQPXWf4GvCMNE nH6qRk69UG6J+DpZr1cWpZEbVjxLGyYFf0iwGfAKnuXbzLSk3pXNUWnIgA8FMGmoFVrP d2p46G7c9dU3H1wI+r+rQuvz6vPyKXx4LmDreilanJLm2viu/5ECPAMpwJjSzcGniMGD VgbwGCoZVyNTvRtFlIOKoe4crKtuLeaKpS5PzEPdNtu6CXpiEZNlP6Rlwu7aR/wURL7n /3Q9u781LSNCz0+EI9F46DO9CxoWKEV1S8IUNNXLd7JXkzhk2gYFDGYaO9I8n09ulGrS 33wA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jF70aNm+iGgL2ioq9Xiaj6FEbb6pAabZS82CmNkwLqw=; fh=ILu9n9UJYyGKJ+F9rVBU1LrxK5aJ3ihMVgUEh7OR7WA=; b=VRUxvpNlOWVeB1THjm93xExt/xckgH9BU0STMwfFPy0XW55Q9zjbeHz7Jjp5CUJJP9 LNWhMiRLqK3IKotAJ0hYRAeocVbpyA+K/e4iiJleicJSKWMBlgk4MswrLWZNxJEdG4uu fp913EwxgxQyeqpeqh+sDCZpA98q8tpW0Tevx2n4yiyVGijRzDcWAnEt08tUHeY+M2b9 /xeN0ksVZYJeJaZLx6I2Tk1PvRfFZ7zdTrbNGy19IZYwk3QrgQxv7vr9odViAmWt7TJ4 CRyev8b/WsAlsDcFTXIvWfbFYDyggNV+e28RfTG48sSTUlk3rb4/4W7qkiD4eUiE4BLr VlKQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NTBPdEmh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c30226f1fsm40966f8f.95.2025.04.02.15.24.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 15:24:32 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.1 12/13] hw/arm/realview: Replace arm_feature() -> arm_cpu_has_feature() Date: Thu, 3 Apr 2025 00:23:32 +0200 Message-ID: <20250402222334.66511-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402222334.66511-1-philmd@linaro.org> References: <20250402222334.66511-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org By using arm_cpu_has_feature() instead of arm_feature() we don't need to include "cpu.h" anymore. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/realview.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index f81d084eb80..48cfe05add0 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -9,7 +9,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" @@ -31,6 +30,7 @@ #include "hw/sd/sd.h" #include "audio/audio.h" #include "target/arm/cpu-qom.h" +#include "target/arm/cpu_has_feature.h" #define SMP_BOOT_ADDR 0xe0000000 #define SMP_BOOTREG_ADDR 0x10000030 @@ -77,7 +77,6 @@ static void realview_init(MachineState *machine, enum realview_board_type board_type) { ARMCPU *cpu = NULL; - CPUARMState *env; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram_lo; MemoryRegion *ram_hi = g_new(MemoryRegion, 1); @@ -138,16 +137,15 @@ static void realview_init(MachineState *machine, cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ); } cpu = ARM_CPU(first_cpu); - env = &cpu->env; - if (arm_feature(env, ARM_FEATURE_V7)) { + if (arm_cpu_has_feature(cpu, ARM_FEATURE_V7)) { if (is_mpcore) { proc_id = 0x0c000000; } else { proc_id = 0x0e000000; } - } else if (arm_feature(env, ARM_FEATURE_V6K)) { + } else if (arm_cpu_has_feature(cpu, ARM_FEATURE_V6K)) { proc_id = 0x06000000; - } else if (arm_feature(env, ARM_FEATURE_V6)) { + } else if (arm_cpu_has_feature(cpu, ARM_FEATURE_V6)) { proc_id = 0x04000000; } else { proc_id = 0x02000000; From patchwork Wed Apr 2 22:23:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877753 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2986700wrs; Wed, 2 Apr 2025 15:28:07 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUuxn7NjyTD7odypgbx8hOHbiqZUbNduLC8oL5oYfVZTQSY7SKy3jdZ3QWsUyw1C4Zn/a9g9w==@linaro.org X-Google-Smtp-Source: AGHT+IF6OtRbzG59TKc53kOY6ZbuzXvk8qInrbDyJ20tMNFlSl1eyAw+ww4J8nvurXhPZfv8FJpo X-Received: by 2002:a05:600c:3c9a:b0:43c:ec0a:ddfd with SMTP id 5b1f17b1804b1-43eb5c18448mr31687775e9.6.1743632886978; Wed, 02 Apr 2025 15:28:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743632886; cv=none; d=google.com; s=arc-20240605; b=QmiASRxee+JlVpOBZ07S7UhW+mQIWQ1lb+BZAWnRnDioBEM+A1AjgoJWFgjMTi73s7 xnJsdzaO0pM/QMC/xA8443bxgzXs3pTxVMwLZ0cVaWuFv0jKhUSohTwi2dKXnz4nFqnK WFzzK360hjCH90ucoCjpbvOqKynK12mGnEo30V64nLWwQ4g2/orAhj02PbgWIudr69Lr iw6j7RazmkB9I+OQU4lvaHJeBVMLLE0CGDylGZFz7ByMrYzsXvM1OqS78/ylNrX7PbMK 8S3eRX3PUVlSGd0cKr6II5EdJ3dmOnfXv6D0zo23szObvAZTNQ4+yoDersjKjZiCT+6O 8DwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Bvg0sskfp1zs/zAw+tx6oTWh/pDWcI3/X7VI/A1vFkg=; fh=ILu9n9UJYyGKJ+F9rVBU1LrxK5aJ3ihMVgUEh7OR7WA=; b=QNzR8OtkCKYAKlRVAdj3pejEE/CgZa0tvWGiI2PQOwRe274VqNDH8eJSc6o7IcPajO oXxTersHgNotWNh2/d3LEMN0ddM87A9FOEFvcCt1+2Xchbw1PyHselK/6Jiis24c+bXH dHx6jv1nOgeIUaS1zvvq0ckrWOkuWfmISs4j2lWMJ21/cMdNc9IM7xdX8Hebqzjz2W0Q j87RWvrO0T5ivnTnotzmIlo5K2ihecZ/YWwUuL4/cfCP79cRB1r4MMFE2JvxzmqTBRUH 19JETI4SI6TtrVjldiy0RgEDdkmYE99py3NHzgKvullCegRVzPVdB6o3CA1JI8ZCYKU0 0ouw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AfD3Ebn1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c3020da22sm43807f8f.68.2025.04.02.15.24.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 15:24:37 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.1 13/13] hw/arm/virt-acpi: Replace arm_feature() -> arm_cpu_has_feature() Date: Thu, 3 Apr 2025 00:23:33 +0200 Message-ID: <20250402222334.66511-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402222334.66511-1-philmd@linaro.org> References: <20250402222334.66511-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Using arm_cpu_has_feature() instead of arm_feature() remove a dependency on (the indirectly included) "cpu.h" header. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt-acpi-build.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index da61af1d359..ae28d958895 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -58,6 +58,7 @@ #include "hw/acpi/ghes.h" #include "hw/acpi/viot.h" #include "hw/virtio/virtio-acpi.h" +#include "target/arm/cpu_has_feature.h" #include "target/arm/multiprocessing.h" #include "target/arm/psci.h" @@ -697,7 +698,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); uint64_t physical_base_address = 0, gich = 0, gicv = 0; uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0; - uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? + uint32_t pmu_interrupt = arm_cpu_has_feature(armcpu, ARM_FEATURE_PMU) ? VIRTUAL_PMU_IRQ : 0; if (vms->gic_version == VIRT_GIC_VERSION_2) {