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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec24ff85asm451385e9.22.2025.04.02.14.23.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 14:23:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Richard Henderson Subject: [PATCH-for-10.1 v2 38/43] tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h' Date: Wed, 2 Apr 2025 23:23:14 +0200 Message-ID: <20250402212319.58349-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402212319.58349-1-philmd@linaro.org> References: <20250402212319.58349-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/backend-ldst.h | 41 +++++++++++++++++++++++++++++++++++++ accel/tcg/internal-common.h | 27 ++++++++++++++++++++++++ accel/tcg/internal-target.h | 28 ------------------------- accel/tcg/cputlb.c | 1 + accel/tcg/user-exec.c | 1 + 5 files changed, 70 insertions(+), 28 deletions(-) create mode 100644 accel/tcg/backend-ldst.h diff --git a/accel/tcg/backend-ldst.h b/accel/tcg/backend-ldst.h new file mode 100644 index 00000000000..9c3a407a5af --- /dev/null +++ b/accel/tcg/backend-ldst.h @@ -0,0 +1,41 @@ +/* + * Internal memory barrier helpers for QEMU (target agnostic) + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ACCEL_TCG_BACKEND_LDST_H +#define ACCEL_TCG_BACKEND_LDST_H + +#include "tcg-target-mo.h" + +/** + * tcg_req_mo: + * @guest_mo: Guest default memory order + * @type: TCGBar + * + * Filter @type to the barrier that is required for the guest + * memory ordering vs the host memory ordering. A non-zero + * result indicates that some barrier is required. + */ +#define tcg_req_mo(guest_mo, type) \ + ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) + +/** + * cpu_req_mo: + * @cpu: CPUState + * @type: TCGBar + * + * If tcg_req_mo indicates a barrier for @type is required + * for the guest memory model, issue a host memory barrier. + */ +#define cpu_req_mo(cpu, type) \ + do { \ + if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \ + smp_mb(); \ + } \ + } while (0) + +#endif diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 2f00560d102..829ae9389d2 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -108,4 +108,31 @@ static inline tb_page_addr_t get_page_addr_code(CPUArchState *env, return get_page_addr_code_hostp(env, addr, NULL); } +/** + * tcg_req_mo: + * @guest_mo: Guest default memory order + * @type: TCGBar + * + * Filter @type to the barrier that is required for the guest + * memory ordering vs the host memory ordering. A non-zero + * result indicates that some barrier is required. + */ +#define tcg_req_mo(guest_mo, type) \ + ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) + +/** + * cpu_req_mo: + * @cpu: CPUState + * @type: TCGBar + * + * If tcg_req_mo indicates a barrier for @type is required + * for the guest memory model, issue a host memory barrier. + */ +#define cpu_req_mo(cpu, type) \ + do { \ + if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \ + smp_mb(); \ + } \ + } while (0) + #endif diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index f5a3fd7e402..9a9cef31406 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -13,7 +13,6 @@ #include "exec/exec-all.h" #include "exec/translation-block.h" #include "tb-internal.h" -#include "tcg-target-mo.h" #include "exec/mmap-lock.h" /* @@ -44,31 +43,4 @@ void page_table_config_init(void); G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); #endif /* CONFIG_USER_ONLY */ -/** - * tcg_req_mo: - * @guest_mo: Guest default memory order - * @type: TCGBar - * - * Filter @type to the barrier that is required for the guest - * memory ordering vs the host memory ordering. A non-zero - * result indicates that some barrier is required. - */ -#define tcg_req_mo(guest_mo, type) \ - ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) - -/** - * cpu_req_mo: - * @cpu: CPUState - * @type: TCGBar - * - * If tcg_req_mo indicates a barrier for @type is required - * for the guest memory model, issue a host memory barrier. - */ -#define cpu_req_mo(cpu, type) \ - do { \ - if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \ - smp_mb(); \ - } \ - } while (0) - #endif /* ACCEL_TCG_INTERNAL_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 35b1ff03a51..d9fb68d7198 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -48,6 +48,7 @@ #include "qemu/plugin-memory.h" #endif #include "tcg/tcg-ldst.h" +#include "backend-ldst.h" /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 3f4d6824460..5eef8e7f186 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -37,6 +37,7 @@ #include "qemu/int128.h" #include "trace.h" #include "tcg/tcg-ldst.h" +#include "backend-ldst.h" #include "internal-common.h" #include "internal-target.h" #include "tb-internal.h" From patchwork Wed Apr 2 21:23:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877738 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2967110wrs; Wed, 2 Apr 2025 14:24:24 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWW6dATKy9I4dNARarsxGkrzhMGkeyxB39OoROcesTDSmKiQOFUv1iWdp84Mtg81Q1wVmx58Q==@linaro.org X-Google-Smtp-Source: AGHT+IFrRMIR52H7fHpyBRtB+lFjkhc+xCv9KKUEQtRd2iSPxQLIQ1SBBB0/qivBbQxg7CGxxi7p X-Received: by 2002:a05:622a:134e:b0:476:afd2:5b5d with SMTP id d75a77b69052e-477e4ae462cmr326900701cf.4.1743629064317; Wed, 02 Apr 2025 14:24:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743629064; cv=none; d=google.com; s=arc-20240605; b=gVI5IozrhNM92CToY+Hvdd8Df/G7qjB3oxcEx18uwAmtZEAdFqOVelfjvqBYiZylaG XLFqkfnWTNcCACV3ZJ+Bv8vsEi73hNO17r1e9F9m7h2HyluGoBrQZ53Go09N51QebfnX hhPCvlS5lmCwtEpO+0lJwYxwoG7/EyrR38HCV+t+PgBNd0JjTvSpkPdafWVxMQUvk6mt aKFShbAAWwY3QXA+iIx35p1WHhAvVm2gyJ2yre87F8gluoNlUu4h82USJwP2vVT+YYi1 dkZ30P7alnuXtJFFBpFSrbrZjsLTZ5298q630jIcKhyk75rS12aUSb8XNpuzPhwDN8ui 4xlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kv473foA2Lz/6LlrfWieB+cyNxqB+oMm/dNGpDxxZmg=; fh=2WsjhQWI4lQgYgc4VV8bbFA9ixJvTm6B39az9SeRSzU=; b=Ww+wDCytl5h9O5pgLKNfShENBZFiLDcm+LY/lXh5/hODGnkN+MdC6kTn3bBsl2GeYU mvQSPU53ebalBZEIeAJ2sElYAbT86iVofOzw3EZ9rtJ/0gviaviNE6HtkM+81bnznEbq X3Je/K5Q4uoxopR5pYSFnTlYtua4XQKBVateW6bjNw2LQGgaGgX6UUlTcG7JqDkhD+gh xxdwqq9LEP+ARU8YfzCqMAFnjJHMxXQYWrBeYasYSDUfQfGLV4h4vx99ZTFvsxVWqt/l R+7/6bImB4payY+L8eYWOHm6MNeNbB5jDYsEOfXjMmYcY0g/uZilEEamoB5TrGrCp4WW QrxA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="cDkx/Kdg"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec169abd7sm2470665e9.18.2025.04.02.14.23.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 14:23:30 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Richard Henderson Subject: [PATCH-for-10.1 v2 39/43] tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h' Date: Wed, 2 Apr 2025 23:23:15 +0200 Message-ID: <20250402212319.58349-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402212319.58349-1-philmd@linaro.org> References: <20250402212319.58349-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org qemu_tcg_mttcg_enabled() is specific to 1/ TCG and 2/ system emulation. Move the prototype declaration to "system/tcg.h", reducing 'mttcg_enabled' variable scope. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 9 --------- include/system/tcg.h | 8 ++++++++ accel/tcg/tcg-all.c | 16 ++++++++++++++-- target/riscv/tcg/tcg-cpu.c | 1 + tcg/region.c | 4 +++- 5 files changed, 26 insertions(+), 12 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 10b6b25b344..c8d6abff19a 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -594,15 +594,6 @@ extern CPUTailQ cpus_queue; extern __thread CPUState *current_cpu; -/** - * qemu_tcg_mttcg_enabled: - * Check whether we are running MultiThread TCG or not. - * - * Returns: %true if we are in MTTCG mode %false otherwise. - */ -extern bool mttcg_enabled; -#define qemu_tcg_mttcg_enabled() (mttcg_enabled) - /** * cpu_paging_enabled: * @cpu: The CPU whose state is to be inspected. diff --git a/include/system/tcg.h b/include/system/tcg.h index 73229648c63..7622dcea302 100644 --- a/include/system/tcg.h +++ b/include/system/tcg.h @@ -17,4 +17,12 @@ extern bool tcg_allowed; #define tcg_enabled() 0 #endif +/** + * qemu_tcg_mttcg_enabled: + * Check whether we are running MultiThread TCG or not. + * + * Returns: %true if we are in MTTCG mode %false otherwise. + */ +bool qemu_tcg_mttcg_enabled(void); + #endif diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index a5a1fd6a11e..b8874430d30 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -38,6 +38,7 @@ #include "hw/qdev-core.h" #else #include "hw/boards.h" +#include "system/tcg.h" #endif #include "internal-common.h" #include "cpu-param.h" @@ -58,6 +59,17 @@ typedef struct TCGState TCGState; DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE, TYPE_TCG_ACCEL) +#ifndef CONFIG_USER_ONLY + +static bool mttcg_enabled; + +bool qemu_tcg_mttcg_enabled(void) +{ + return mttcg_enabled; +} + +#endif /* !CONFIG_USER_ONLY */ + /* * We default to false if we know other options have been enabled * which are currently incompatible with MTTCG. Otherwise when each @@ -97,7 +109,6 @@ static void tcg_accel_instance_init(Object *obj) #endif } -bool mttcg_enabled; bool one_insn_per_tb; static int tcg_init_machine(MachineState *ms) @@ -107,10 +118,11 @@ static int tcg_init_machine(MachineState *ms) unsigned max_cpus = 1; #else unsigned max_cpus = ms->smp.max_cpus; + + mttcg_enabled = s->mttcg_enabled; #endif tcg_allowed = true; - mttcg_enabled = s->mttcg_enabled; page_init(); tb_htable_init(); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 50e81b2e521..88f7cdb887c 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -36,6 +36,7 @@ #include "tcg/tcg.h" #ifndef CONFIG_USER_ONLY #include "hw/boards.h" +#include "system/tcg.h" #endif /* Hash that stores user set extensions */ diff --git a/tcg/region.c b/tcg/region.c index 478ec051c4b..56d2e988719 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -34,7 +34,9 @@ #include "exec/translation-block.h" #include "tcg-internal.h" #include "host/cpuinfo.h" - +#ifndef CONFIG_USER_ONLY +#include "system/tcg.h" +#endif /* * Local source-level compatibility with Unix. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec16313edsm2515875e9.6.2025.04.02.14.23.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 14:23:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Richard Henderson Subject: [PATCH-for-10.1 v2 40/43] tcg: Convert TCGState::mttcg_enabled to TriState Date: Wed, 2 Apr 2025 23:23:16 +0200 Message-ID: <20250402212319.58349-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402212319.58349-1-philmd@linaro.org> References: <20250402212319.58349-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use the OnOffAuto type as 3-state. Since the TCGState instance is zero-initialized, the mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO). In tcg_init_machine(), if mttcg_enabled is still AUTO, set a default value (effectively inlining the default_mttcg_enabled() method content). In the tcg_get_thread() getter, consider AUTO / OFF states as "single", otherwise ON is "multi". Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/tcg-all.c | 60 ++++++++++++++++++++++----------------------- 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index b8874430d30..15d4e9232ae 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -32,6 +32,7 @@ #include "qemu/error-report.h" #include "qemu/accel.h" #include "qemu/atomic.h" +#include "qapi/qapi-types-common.h" #include "qapi/qapi-builtin-visit.h" #include "qemu/units.h" #if defined(CONFIG_USER_ONLY) @@ -47,7 +48,7 @@ struct TCGState { AccelState parent_obj; - bool mttcg_enabled; + OnOffAuto mttcg_enabled; bool one_insn_per_tb; int splitwx_enabled; unsigned long tb_size; @@ -70,37 +71,10 @@ bool qemu_tcg_mttcg_enabled(void) #endif /* !CONFIG_USER_ONLY */ -/* - * We default to false if we know other options have been enabled - * which are currently incompatible with MTTCG. Otherwise when each - * guest (target) has been updated to support: - * - atomic instructions - * - memory ordering primitives (barriers) - * they can set the appropriate CONFIG flags in ${target}-softmmu.mak - * - * Once a guest architecture has been converted to the new primitives - * there is one remaining limitation to check: - * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host) - */ - -static bool default_mttcg_enabled(void) -{ - if (icount_enabled()) { - return false; - } -#ifdef TARGET_SUPPORTS_MTTCG - return true; -#else - return false; -#endif -} - static void tcg_accel_instance_init(Object *obj) { TCGState *s = TCG_STATE(obj); - s->mttcg_enabled = default_mttcg_enabled(); - /* If debugging enabled, default "auto on", otherwise off. */ #if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY) s->splitwx_enabled = -1; @@ -118,7 +92,31 @@ static int tcg_init_machine(MachineState *ms) unsigned max_cpus = 1; #else unsigned max_cpus = ms->smp.max_cpus; +#ifdef TARGET_SUPPORTS_MTTCG + bool mttcg_supported = true; +#else + bool mttcg_supported = false; +#endif + if (s->mttcg_enabled == ON_OFF_AUTO_AUTO) { + /* + * We default to false if we know other options have been enabled + * which are currently incompatible with MTTCG. Otherwise when each + * guest (target) has been updated to support: + * - atomic instructions + * - memory ordering primitives (barriers) + * they can set the appropriate CONFIG flags in ${target}-softmmu.mak + * + * Once a guest architecture has been converted to the new primitives + * there is one remaining limitation to check: + * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host) + */ + if (icount_enabled()) { + s->mttcg_enabled = ON_OFF_AUTO_OFF; + } else { + s->mttcg_enabled = mttcg_supported; + } + } mttcg_enabled = s->mttcg_enabled; #endif @@ -147,7 +145,7 @@ static char *tcg_get_thread(Object *obj, Error **errp) { TCGState *s = TCG_STATE(obj); - return g_strdup(s->mttcg_enabled ? "multi" : "single"); + return g_strdup(s->mttcg_enabled == ON_OFF_AUTO_ON ? "multi" : "single"); } static void tcg_set_thread(Object *obj, const char *value, Error **errp) @@ -162,10 +160,10 @@ static void tcg_set_thread(Object *obj, const char *value, Error **errp) warn_report("Guest not yet converted to MTTCG - " "you may get unexpected results"); #endif - s->mttcg_enabled = true; + s->mttcg_enabled = ON_OFF_AUTO_ON; } } else if (strcmp(value, "single") == 0) { - s->mttcg_enabled = false; + s->mttcg_enabled = ON_OFF_AUTO_OFF; } else { error_setg(errp, "Invalid 'thread' setting %s", value); } From patchwork Wed Apr 2 21:23:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877736 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2966968wrs; Wed, 2 Apr 2025 14:24:00 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUdhLaNBu3BQp7ZQq5jfG2ug6YzLF3kQSv0t7/yUYFmhCdpar8Z4/PJNpvV5TDltubljq2cUQ==@linaro.org X-Google-Smtp-Source: AGHT+IHE0aZnCvRuaHxK8m+lB6iwwoNAjIRHkOK5/O9+NN/HV0j//j/3854btOuvrW/DKeCTKrFv X-Received: by 2002:a05:622a:594:b0:476:980c:10a9 with SMTP id d75a77b69052e-47909f79ed2mr67711331cf.21.1743629040687; Wed, 02 Apr 2025 14:24:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743629040; cv=none; d=google.com; s=arc-20240605; b=UZrZN5YwaR/mUu8OrCKZVrYDDyL5rJBA3yJ03mKtWTg5RaMoDR/YK57/pI7taNErVA e2bdY+0H0UNx5vZNJFPeiYDWvIlHArQDu1okf9Ot94aj9I09JHxHZ3H9sfMzIe75GkVq wC5+3QVaNTj3pZbPpqWNnHCbUu3zA978A07TTq8y/yFvYxSoKWwYUsCpELHyrTzSVivk L+Iqrd/N2x1eI0v+DLQ+YC5Q4A/dfer1dJJRKWd4YUlvw4LFtFW9j/2PirkQbUjfsBnL Y4PzwSzEhLD3bdXmCROyU0g/+YKT8MzHwN6LhuKkqSi+JwyT19lgxSp8MrsuLbFt5pTc maXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bkCr362ZjamcjiYyXQYAVlRzEd6wzep8CllaznGqzgQ=; fh=2WsjhQWI4lQgYgc4VV8bbFA9ixJvTm6B39az9SeRSzU=; b=gcL/3MZir9KBXiswr1HOpMZzxiGsXdfSdYlpQxWoQxJelDbLrxo56xu7TZC7M9epd3 LN/zFZl1EYczEQZFWm0KABuJ7dUJ5P2l52IJ5fAO+PKkaBPMd71os6T8Y1okjdznkljS v/VhuUPBBAEGiDMvND+5h2PYrQmOKOg0vC8ZOfW5Fvttt+0MGrQ4YWMp11Un3BFKPIm0 HwXN9XuxbcUfaMX097YKp2yLF+lB4xORq8yQoXU8kpx3SzV/vQZ0QB/561FtxoretafD NrrM7hAi29kDB+IJ0n0vVDI5r+ZBm85BC0BCtxQzRKtlsRSBgV7u0ZcOkAt6NZZlLQb/ MkPA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SFOHWnhh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec256e727sm280355e9.29.2025.04.02.14.23.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 14:23:40 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Richard Henderson Subject: [PATCH-for-10.1 v2 41/43] tcg: Factor mttcg_init() out Date: Wed, 2 Apr 2025 23:23:17 +0200 Message-ID: <20250402212319.58349-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402212319.58349-1-philmd@linaro.org> References: <20250402212319.58349-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Keep MTTCG initialization code out of tcg_init_machine(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/tcg-all.c | 50 +++++++++++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 22 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 15d4e9232ae..267830658ca 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -69,29 +69,8 @@ bool qemu_tcg_mttcg_enabled(void) return mttcg_enabled; } -#endif /* !CONFIG_USER_ONLY */ - -static void tcg_accel_instance_init(Object *obj) +static void mttcg_init(TCGState *s) { - TCGState *s = TCG_STATE(obj); - - /* If debugging enabled, default "auto on", otherwise off. */ -#if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY) - s->splitwx_enabled = -1; -#else - s->splitwx_enabled = 0; -#endif -} - -bool one_insn_per_tb; - -static int tcg_init_machine(MachineState *ms) -{ - TCGState *s = TCG_STATE(current_accel()); -#ifdef CONFIG_USER_ONLY - unsigned max_cpus = 1; -#else - unsigned max_cpus = ms->smp.max_cpus; #ifdef TARGET_SUPPORTS_MTTCG bool mttcg_supported = true; #else @@ -118,6 +97,33 @@ static int tcg_init_machine(MachineState *ms) } } mttcg_enabled = s->mttcg_enabled; +} + +#endif /* !CONFIG_USER_ONLY */ + +static void tcg_accel_instance_init(Object *obj) +{ + TCGState *s = TCG_STATE(obj); + + /* If debugging enabled, default "auto on", otherwise off. */ +#if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY) + s->splitwx_enabled = -1; +#else + s->splitwx_enabled = 0; +#endif +} + +bool one_insn_per_tb; + +static int tcg_init_machine(MachineState *ms) +{ + TCGState *s = TCG_STATE(current_accel()); +#ifdef CONFIG_USER_ONLY + unsigned max_cpus = 1; +#else + unsigned max_cpus = ms->smp.max_cpus; + + mttcg_init(s); #endif tcg_allowed = true; From patchwork Wed Apr 2 21:23:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877740 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2967201wrs; Wed, 2 Apr 2025 14:24:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXzVKz1dngS9MrL9G1cezvjNrM0PcSdh5utcKUZxljnaSvtqkAuZZtqqnEUmCp0+TMpstbb8w==@linaro.org X-Google-Smtp-Source: AGHT+IHSJDBs4IXqYnuCPolfwhrCYT8ywy1WHQCiZio/+0TtmjxgLrOy5Dh83P95wQks1dNltm4Y X-Received: by 2002:a05:6214:19ca:b0:6ee:ba58:e099 with SMTP id 6a1803df08f44-6eed61dcb24mr218132976d6.15.1743629085297; Wed, 02 Apr 2025 14:24:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743629085; cv=none; d=google.com; s=arc-20240605; b=hdA1dMfThR/0zhHxa+gg7BS4kW2r7+TijFesdwPgpa0l6IDcdbbvrD/LMSnl52y/yt LJxPnczOYEqii73s09eohXNlqfXl9LzkOPx1tJemvFNwvHb625mq7LaV7yRN8oP38CYh 0nps5ouKFLfn+h5tg3wvuaZhWMPHDKbZ0CVaLvZRJxhTp2ugPIueHW1YUgcHCY549f/d kLg9QsvVQ5o3Qxt/onIOMSCAtvvEiYSsKtFnzRmq4uaUu+Dkuwza2QKpiaKpaXg3XIxH 8UPtccSZpHNoWKnjl4satWhWOWFfvjI1ZjRJL3tEH7xE/G3G28hh+twjtfJZeL00I4vJ 0IOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=f7vzxSOMlZ7lM1+pTz+/Da4DQOGjOvlVy5ydXulvhME=; fh=2WsjhQWI4lQgYgc4VV8bbFA9ixJvTm6B39az9SeRSzU=; b=S8GnmyBJ3iIvepMkgDTrYC/C5tSGVSYwO73tGTxRysb/U1ntFeOvtpdLT2lOyieRQj i3xNrBg4Nk1P9Y9qns0uRG2HSOYA8E8WXpQZbwmdJkrk/0YHzeigaTYDDVy0haJCGmWK ZOnuwCKRAZ7fVCKr27gU9vlB8ZcP9HmLR8GJaie0M3YxSGOD5Wd6HF69mqoF0UzM7aDV Obn3m/lBxr0QZKwx6FcXpU6bTmpzLIzuyzzYGlDdnE5FPdeuHKgw8kfX025WEJ9YhDrl V40T9RPfrXQWycOVd0BL1nro2nXahaMHPG8kGtQTxqmvts8erxPua17wnQ3oCnNZBogT /cNw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TvPljux3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec24b223csm558505e9.4.2025.04.02.14.23.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 14:23:44 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Richard Henderson Subject: [PATCH-for-10.1 v2 42/43] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field Date: Wed, 2 Apr 2025 23:23:18 +0200 Message-ID: <20250402212319.58349-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402212319.58349-1-philmd@linaro.org> References: <20250402212319.58349-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition, have each target set the 'mttcg_supported' field in the TCGCPUOps structure. Since so far we only emulate one target architecture at a time, tcg_init_machine() gets whether MTTCG is supported via the current CPU class (CPU_RESOLVING_TYPE). Since TARGET_SUPPORTS_MTTCG isn't available anymore, instead of emiting a warning when the 'thread' property is set in tcg_set_thread(), emit it in tcg_init_machine() where it is consumed. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- docs/devel/multi-thread-tcg.rst | 2 +- configs/targets/aarch64-softmmu.mak | 1 - configs/targets/alpha-softmmu.mak | 1 - configs/targets/arm-softmmu.mak | 1 - configs/targets/hppa-softmmu.mak | 1 - configs/targets/i386-softmmu.mak | 1 - configs/targets/loongarch64-softmmu.mak | 1 - configs/targets/microblaze-softmmu.mak | 1 - configs/targets/microblazeel-softmmu.mak | 1 - configs/targets/mips-softmmu.mak | 1 - configs/targets/mipsel-softmmu.mak | 1 - configs/targets/or1k-softmmu.mak | 1 - configs/targets/ppc64-softmmu.mak | 1 - configs/targets/riscv32-softmmu.mak | 1 - configs/targets/riscv64-softmmu.mak | 1 - configs/targets/s390x-softmmu.mak | 1 - configs/targets/sparc-softmmu.mak | 1 - configs/targets/sparc64-softmmu.mak | 1 - configs/targets/x86_64-softmmu.mak | 1 - configs/targets/xtensa-softmmu.mak | 1 - configs/targets/xtensaeb-softmmu.mak | 1 - include/accel/tcg/cpu-ops.h | 8 ++++++++ include/exec/poison.h | 1 - accel/tcg/tcg-all.c | 17 ++++++++--------- target/alpha/cpu.c | 1 + target/arm/cpu.c | 1 + target/arm/tcg/cpu-v7m.c | 1 + target/avr/cpu.c | 1 + target/hexagon/cpu.c | 1 + target/hppa/cpu.c | 1 + target/i386/tcg/tcg-cpu.c | 1 + target/loongarch/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 1 + target/rx/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + 44 files changed, 37 insertions(+), 31 deletions(-) diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.rst index 14a2a9dc7b5..da9a1530c9f 100644 --- a/docs/devel/multi-thread-tcg.rst +++ b/docs/devel/multi-thread-tcg.rst @@ -30,7 +30,7 @@ user-space thread. This is enabled by default for all FE/BE combinations where the host memory model is able to accommodate the guest (TCGCPUOps::guest_default_memory_order & ~TCG_TARGET_DEFAULT_MO is zero) and the guest has had the required work done to support this safely -(TARGET_SUPPORTS_MTTCG). +(TCGCPUOps::mttcg_supported). System emulation will fall back to the original round robin approach if: diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak index 82cb72cb83d..5dfeb35af90 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml # needed by boot.c diff --git a/configs/targets/alpha-softmmu.mak b/configs/targets/alpha-softmmu.mak index 89f3517aca0..5275076e50d 100644 --- a/configs/targets/alpha-softmmu.mak +++ b/configs/targets/alpha-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=alpha -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=64 diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.mak index afc64f5927b..6a5a8eda949 100644 --- a/configs/targets/arm-softmmu.mak +++ b/configs/targets/arm-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=arm -TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml # needed by boot.c TARGET_NEED_FDT=y diff --git a/configs/targets/hppa-softmmu.mak b/configs/targets/hppa-softmmu.mak index 63ca74ed5e6..ea331107a08 100644 --- a/configs/targets/hppa-softmmu.mak +++ b/configs/targets/hppa-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=hppa TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=64 diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmmu.mak index 5dd89217560..e9d89e8ab41 100644 --- a/configs/targets/i386-softmmu.mak +++ b/configs/targets/i386-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=i386 -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_KVM_HAVE_RESET_PARKED_VCPU=y TARGET_XML_FILES= gdb-xml/i386-32bit.xml diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak index 351341132f6..fc44c54233d 100644 --- a/configs/targets/loongarch64-softmmu.mak +++ b/configs/targets/loongarch64-softmmu.mak @@ -1,7 +1,6 @@ TARGET_ARCH=loongarch64 TARGET_BASE_ARCH=loongarch TARGET_KVM_HAVE_GUEST_DEBUG=y -TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-lasx.xml # all boards require libfdt TARGET_NEED_FDT=y diff --git a/configs/targets/microblaze-softmmu.mak b/configs/targets/microblaze-softmmu.mak index 99a33ed44a8..23457d0ae65 100644 --- a/configs/targets/microblaze-softmmu.mak +++ b/configs/targets/microblaze-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=microblaze TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y # needed by boot.c TARGET_NEED_FDT=y TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml diff --git a/configs/targets/microblazeel-softmmu.mak b/configs/targets/microblazeel-softmmu.mak index 52cdeae1a28..c82c509623d 100644 --- a/configs/targets/microblazeel-softmmu.mak +++ b/configs/targets/microblazeel-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=microblaze -TARGET_SUPPORTS_MTTCG=y # needed by boot.c TARGET_NEED_FDT=y TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml diff --git a/configs/targets/mips-softmmu.mak b/configs/targets/mips-softmmu.mak index b62a0882499..c9588066b8d 100644 --- a/configs/targets/mips-softmmu.mak +++ b/configs/targets/mips-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=mips TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=32 diff --git a/configs/targets/mipsel-softmmu.mak b/configs/targets/mipsel-softmmu.mak index 620ec681785..90e09bdc3e5 100644 --- a/configs/targets/mipsel-softmmu.mak +++ b/configs/targets/mipsel-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=mips -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=32 diff --git a/configs/targets/or1k-softmmu.mak b/configs/targets/or1k-softmmu.mak index adfddb1a8ac..0e47d9878b0 100644 --- a/configs/targets/or1k-softmmu.mak +++ b/configs/targets/or1k-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=openrisc -TARGET_SUPPORTS_MTTCG=y TARGET_BIG_ENDIAN=y # needed by boot.c and all boards TARGET_NEED_FDT=y diff --git a/configs/targets/ppc64-softmmu.mak b/configs/targets/ppc64-softmmu.mak index 7cee0e97f43..74572864b36 100644 --- a/configs/targets/ppc64-softmmu.mak +++ b/configs/targets/ppc64-softmmu.mak @@ -1,7 +1,6 @@ TARGET_ARCH=ppc64 TARGET_BASE_ARCH=ppc TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/power64-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml gdb-xml/power-vsx.xml # all boards require libfdt diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-softmmu.mak index c828066ce6b..db55275b868 100644 --- a/configs/targets/riscv32-softmmu.mak +++ b/configs/targets/riscv32-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=riscv32 TARGET_BASE_ARCH=riscv -TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c TARGET_NEED_FDT=y diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak index 09f613d24a0..2bdd4a62cd2 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c diff --git a/configs/targets/s390x-softmmu.mak b/configs/targets/s390x-softmmu.mak index 5242ebe7c2e..76dd5de6584 100644 --- a/configs/targets/s390x-softmmu.mak +++ b/configs/targets/s390x-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=s390x TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml TARGET_LONG_BITS=64 diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak index 78c2e25bd13..57801faf1fc 100644 --- a/configs/targets/sparc-softmmu.mak +++ b/configs/targets/sparc-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=sparc TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=32 diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak index f7bab97a002..2504e31ae33 100644 --- a/configs/targets/sparc64-softmmu.mak +++ b/configs/targets/sparc64-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=sparc64 TARGET_BASE_ARCH=sparc TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=64 diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-softmmu.mak index 1ceefde1313..5619b2bc686 100644 --- a/configs/targets/x86_64-softmmu.mak +++ b/configs/targets/x86_64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=x86_64 TARGET_BASE_ARCH=i386 -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_KVM_HAVE_RESET_PARKED_VCPU=y TARGET_XML_FILES= gdb-xml/i386-64bit.xml diff --git a/configs/targets/xtensa-softmmu.mak b/configs/targets/xtensa-softmmu.mak index 65845df4ffa..2a9797338a6 100644 --- a/configs/targets/xtensa-softmmu.mak +++ b/configs/targets/xtensa-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=xtensa -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=32 diff --git a/configs/targets/xtensaeb-softmmu.mak b/configs/targets/xtensaeb-softmmu.mak index f1f789d6971..5204729af8b 100644 --- a/configs/targets/xtensaeb-softmmu.mak +++ b/configs/targets/xtensaeb-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=xtensa TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=32 diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index a4932fc5d7c..0e4352513d1 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -19,6 +19,14 @@ #include "tcg/tcg-mo.h" struct TCGCPUOps { + /** + * mttcg_supported: multi-threaded TCG is supported + * + * Target (TCG frontend) supports: + * - atomic instructions + * - memory ordering primitives (barriers) + */ + bool mttcg_supported; /** * @guest_default_memory_order: default barrier that is required diff --git a/include/exec/poison.h b/include/exec/poison.h index a09e0c12631..bc422719d80 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -35,7 +35,6 @@ #pragma GCC poison TARGET_HAS_BFLT #pragma GCC poison TARGET_NAME -#pragma GCC poison TARGET_SUPPORTS_MTTCG #pragma GCC poison TARGET_BIG_ENDIAN #pragma GCC poison TCG_GUEST_DEFAULT_MO #pragma GCC poison TARGET_HAS_PRECISE_SMC diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 267830658ca..bf27c5c0fb3 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -41,8 +41,10 @@ #include "hw/boards.h" #include "system/tcg.h" #endif +#include "accel/tcg/cpu-ops.h" #include "internal-common.h" #include "cpu-param.h" +#include "cpu.h" struct TCGState { @@ -71,11 +73,8 @@ bool qemu_tcg_mttcg_enabled(void) static void mttcg_init(TCGState *s) { -#ifdef TARGET_SUPPORTS_MTTCG - bool mttcg_supported = true; -#else - bool mttcg_supported = false; -#endif + CPUClass *cc = CPU_CLASS(object_class_by_name(CPU_RESOLVING_TYPE)); + bool mttcg_supported = cc->tcg_ops->mttcg_supported; if (s->mttcg_enabled == ON_OFF_AUTO_AUTO) { /* @@ -96,6 +95,10 @@ static void mttcg_init(TCGState *s) s->mttcg_enabled = mttcg_supported; } } + if (s->mttcg_enabled == ON_OFF_AUTO_ON && !mttcg_supported) { + warn_report("Guest not yet converted to MTTCG - " + "you may get unexpected results"); + } mttcg_enabled = s->mttcg_enabled; } @@ -162,10 +165,6 @@ static void tcg_set_thread(Object *obj, const char *value, Error **errp) if (icount_enabled()) { error_setg(errp, "No MTTCG when icount is enabled"); } else { -#ifndef TARGET_SUPPORTS_MTTCG - warn_report("Guest not yet converted to MTTCG - " - "you may get unexpected results"); -#endif s->mttcg_enabled = ON_OFF_AUTO_ON; } } else if (strcmp(value, "single") == 0) { diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index eeaf3a81c1a..851a3d10d59 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -235,6 +235,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps alpha_tcg_ops = { + .mttcg_supported = true, /* Alpha processors have a weak memory model */ .guest_default_memory_order = 0, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3e9760b5518..377791c84dd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2671,6 +2671,7 @@ static const struct SysemuCPUOps arm_sysemu_ops = { #ifdef CONFIG_TCG static const TCGCPUOps arm_tcg_ops = { + .mttcg_supported = true, /* ARM processors have a weak memory model */ .guest_default_memory_order = 0, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 89d4e4b4a2f..85d8db87f9b 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -232,6 +232,7 @@ static void cortex_m55_initfn(Object *obj) } static const TCGCPUOps arm_v7m_tcg_ops = { + .mttcg_supported = true, /* ARM processors have a weak memory model */ .guest_default_memory_order = 0, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 8f79cf4c08b..064ee3ec3f1 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -224,6 +224,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps avr_tcg_ops = { + .mttcg_supported = false, .guest_default_memory_order = 0, .initialize = avr_cpu_tcg_init, .translate_code = avr_cpu_translate_code, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index ed56a16921f..7c3a1a6a7d8 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -320,6 +320,7 @@ static void hexagon_cpu_init(Object *obj) #include "accel/tcg/cpu-ops.h" static const TCGCPUOps hexagon_tcg_ops = { + .mttcg_supported = false, /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, .initialize = hexagon_translate_init, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index dfbd9330565..1bfd2a402a9 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -253,6 +253,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps hppa_tcg_ops = { + .mttcg_supported = true, /* PA-RISC 1.x processors have a strong memory model. */ /* * ??? While we do not yet implement PA-RISC 2.0, those processors have diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index d941df09560..a0258f4739e 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -125,6 +125,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "accel/tcg/cpu-ops.h" static const TCGCPUOps x86_tcg_ops = { + .mttcg_supported = true, /* * The x86 has a strong memory model with some store-after-load re-ordering */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index f5b8ef29ab0..19151651ae0 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -864,6 +864,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) #include "accel/tcg/cpu-ops.h" static const TCGCPUOps loongarch_tcg_ops = { + .mttcg_supported = true, .guest_default_memory_order = 0, .initialize = loongarch_translate_init, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index b2d8c8f1dea..2fda167b73e 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -589,6 +589,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps m68k_tcg_ops = { + .mttcg_supported = false, /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 4efba0dddb2..65c461265fb 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -427,6 +427,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps mb_tcg_ops = { + .mttcg_supported = true, /* MicroBlaze is always in-order. */ .guest_default_memory_order = TCG_MO_ALL, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 010773405a8..77bdb6db887 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -550,6 +550,7 @@ static const Property mips_cpu_properties[] = { #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" static const TCGCPUOps mips_tcg_ops = { + .mttcg_supported = TARGET_LONG_BITS == 32, .guest_default_memory_order = 0, .initialize = mips_tcg_init, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 87fe779042c..51df212bd6b 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -243,6 +243,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps openrisc_tcg_ops = { + .mttcg_supported = true, .guest_default_memory_order = 0, .initialize = openrisc_translate_init, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 722e3125a72..4c5919074ac 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7483,6 +7483,7 @@ static const TCGCPUOps ppc_tcg_ops = { .restore_state_to_opc = ppc_restore_state_to_opc, .mmu_index = ppc_cpu_mmu_index, + .mttcg_supported = TARGET_LONG_BITS == 64, .guest_default_memory_order = 0, #ifdef CONFIG_USER_ONLY diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 88f7cdb887c..3afbae9733b 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -141,6 +141,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, } static const TCGCPUOps riscv_tcg_ops = { + .mttcg_supported = true, .guest_default_memory_order = 0, .initialize = riscv_translate_init, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index f073fe8fc98..654bf7ae5b2 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -204,6 +204,7 @@ static const struct SysemuCPUOps rx_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps rx_tcg_ops = { + .mttcg_supported = false, /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 85e6336cba1..f85371a0def 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -345,6 +345,7 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, } static const TCGCPUOps s390_tcg_ops = { + .mttcg_supported = true, /* * The z/Architecture has a strong memory model with some * store-after-load re-ordering. diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 7a05301c6ff..e20e49fca8a 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -262,6 +262,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps superh_tcg_ops = { + .mttcg_supported = false, /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 56d9417ae3f..f6b3c0f129a 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1001,6 +1001,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps sparc_tcg_ops = { + .mttcg_supported = true, /* * From Oracle SPARC Architecture 2015: * diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index c68954b4096..258f55a566f 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -172,6 +172,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps tricore_tcg_ops = { + .mttcg_supported = false, /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, .initialize = tricore_tcg_init, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 2cbf4e30108..3f00e8e4239 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -232,6 +232,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps xtensa_tcg_ops = { + .mttcg_supported = true, /* Xtensa processors have a weak memory model */ .guest_default_memory_order = 0, From patchwork Wed Apr 2 21:23:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877739 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec17b1352sm2267875e9.37.2025.04.02.14.23.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 14:23:49 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Richard Henderson Subject: [PATCH-for-10.1 v2 43/43] target/arm: Update comment around cpu_untagged_addr() Date: Wed, 2 Apr 2025 23:23:19 +0200 Message-ID: <20250402212319.58349-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402212319.58349-1-philmd@linaro.org> References: <20250402212319.58349-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since commit f9ba56a03c2 ("user: Introduce 'user/guest-host.h' header") cpu_untagged_addr() is only needed in "user/guest-host.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3705b34285b..88ed06987f3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3233,7 +3233,7 @@ extern const uint64_t pred_esz_masks[5]; * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. * * There should be a better place to put this, but we need this in - * include/exec/cpu_ldst.h, and not some place linux-user specific. + * include/user/guest-host.h, and not some place linux-user specific. */ static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) {