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Tue, 01 Apr 2025 00:45:22 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8ff02f9csm148715295e9.26.2025.04.01.00.45.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Apr 2025 00:45:22 -0700 (PDT) From: Neil Armstrong Date: Tue, 01 Apr 2025 09:45:19 +0200 Subject: [PATCH 1/2] gpio: msm: fix get_function return for special pins MIME-Version: 1.0 Message-Id: <20250401-topic-sm8x50-msm-gpio-special-fixes-v1-1-a1148a02bb16@linaro.org> References: <20250401-topic-sm8x50-msm-gpio-special-fixes-v1-0-a1148a02bb16@linaro.org> In-Reply-To: <20250401-topic-sm8x50-msm-gpio-special-fixes-v1-0-a1148a02bb16@linaro.org> To: Caleb Connolly , Sumit Garg , Tom Rini Cc: u-boot-qcom@groups.io, u-boot@lists.denx.de, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2093; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=ufkIG+Z9d/QK2KTEf9XPSmq9r7U9SUbvTMFbO30otkk=; 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Fixes: f9bb539460d ("gpio: msm: add support for special pins") Signed-off-by: Neil Armstrong --- drivers/gpio/msm_gpio.c | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index cea073b329777d4e03fbfa86415041a825f65aad..f208eec7e56170a9a79f8f021ceec85b7da0ed81 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -192,13 +192,41 @@ static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio) return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN); } +static int msm_gpio_get_function_special(struct msm_gpio_bank *priv, + unsigned int gpio) +{ + unsigned int offset = gpio - priv->pin_data->special_pins_start; + const struct msm_special_pin_data *data; + + if (!priv->pin_data->special_pins_data) + return GPIOF_UNKNOWN; + + data = &priv->pin_data->special_pins_data[offset]; + + /* No I/O fields, cannot control/read the I/O value */ + if (!data->io_reg || (data->out_bit >= 31 && data->in_bit >= 31)) + return GPIOF_FUNC; + + /* No Output-Enable register, cannot control I/O direction */ + if (!data->ctl_reg || data->oe_bit >= 31) { + if (data->out_bit >= 31) + return GPIOF_INPUT; + else + return GPIOF_OUTPUT; + } + + if (readl(priv->base + data->ctl_reg) & BIT(data->oe_bit)) + return GPIOF_OUTPUT; + + return GPIOF_INPUT; +} + static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); - /* Always NOP for special pins, assume they're in the correct state */ if (qcom_is_special_pin(priv->pin_data, gpio)) - return 0; + return msm_gpio_get_function_special(priv, gpio); if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE) return GPIOF_OUTPUT; From patchwork Tue Apr 1 07:45:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 877446 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp2123686wrs; Tue, 1 Apr 2025 00:45:46 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXsOG8GFX7R/Ooz1p2vawlrZXBvQNQuXqHKeXcnepEQ7Y6kJWH5YajyzS1sorNYgc6ChNlghw==@linaro.org X-Google-Smtp-Source: AGHT+IG15elXIwBgan8YfvGuRT8TlQJYbUaqJs74Mfkxjd+Zc9Gl+/8UlbuUO3So2nHiAZ2oqfwX X-Received: by 2002:a05:6102:d91:b0:4ba:95f1:cc83 with SMTP id ada2fe7eead31-4c6d3952343mr6738821137.16.1743493545905; Tue, 01 Apr 2025 00:45:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743493545; cv=none; d=google.com; s=arc-20240605; b=EamUyBtjppVrkZIHYR3ivdxmgOam4Q7c5jtrruzTBz3e7wAlJIQQxUrBWnqEu6kPVd NxoKucWcSfKGnMszNkkNk+jlKfA6Lbl335nbClyQYTZ32TB0yVtik78BKCQ0h2i6/iFA 3gA9IeTsGBc/xLYDElIqSxfuH8LEbKhqlFZBFqmpwHR1Q1ZdP3Mr2j/sfh0Mri9mj87h JyQ8YBILzKuTr26o/yUBoAnO0MfUhzvAlCOUiCbfdICqf6fhr55u4BbtlVIQVMWhKrno Fprbs8if2SmL4rIQQckyfDXi9a6OyJafdALMJn3IppbLIJvjRykCqYyimipOAnpGGbZx WaWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=ec1XQppwNIBrqjNQ3+jcBRMvjcVkSGM39Fb6VVuz3hI=; fh=BMSEHcLZHstN8p+6qYA2W5Yy5uecYIvFwqtRYxQs6HY=; b=j/L2bxjLx/Q9TivT4/OJVlKrCvzF37DYg1j1xMmOv06/A70GMmV8R8yQ2U/0nqB2Ub 2TDiOXGH0fT7PF9jr6AcIxdPpVgXIcQXWfgSTYxGCFWEiFkzGzlJcAqCZzrdsfcFN7zK mBFfrtbzBpA1QnMuaf7Y00CKIf+lvLMkbXMU4gOJ5tGfEnZCoSu5kzJI/KEobs0GY/Or 5j7CgwME2ZR5zRuew9tXS6fPL+XXd5YAuEY/zjuyG7q5gijPZo60G86mF5oOn8itCXNx 6S9KK3hCMAv6xjcIm1YkpBXK9+nBoBYooT4tgKLWaovuHQw8qaKjLBiAzLitM/6D9Elf 8ACw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Oa+4GuCM; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Tue, 01 Apr 2025 00:45:23 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8ff02f9csm148715295e9.26.2025.04.01.00.45.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Apr 2025 00:45:23 -0700 (PDT) From: Neil Armstrong Date: Tue, 01 Apr 2025 09:45:20 +0200 Subject: [PATCH 2/2] gpio: msm: return correct value return for special output pins MIME-Version: 1.0 Message-Id: <20250401-topic-sm8x50-msm-gpio-special-fixes-v1-2-a1148a02bb16@linaro.org> References: <20250401-topic-sm8x50-msm-gpio-special-fixes-v1-0-a1148a02bb16@linaro.org> In-Reply-To: <20250401-topic-sm8x50-msm-gpio-special-fixes-v1-0-a1148a02bb16@linaro.org> To: Caleb Connolly , Sumit Garg , Tom Rini Cc: u-boot-qcom@groups.io, u-boot@lists.denx.de, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1302; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=hoLA7ZKCAOAW0iiHzQaX1JDz3A8RRPfy/MSRs50n4dc=; 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Try to return the output value and in all the other cases return an error instead of 0. Fixes: f9bb539460d ("gpio: msm: add support for special pins") Signed-off-by: Neil Armstrong --- drivers/gpio/msm_gpio.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index f208eec7e56170a9a79f8f021ceec85b7da0ed81..54afd44fbd3c53ccbe2c6c46ac1c9cf7bb0f7107 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -172,12 +172,19 @@ static int msm_gpio_get_value_special(struct msm_gpio_bank *priv, unsigned int g const struct msm_special_pin_data *data; if (!priv->pin_data->special_pins_data) - return 0; + return -EINVAL; data = &priv->pin_data->special_pins_data[offset]; - if (!data->io_reg || data->in_bit >= 31) - return 0; + if (!data->io_reg) + return -EINVAL; + + if (data->in_bit >= 31) { + if (data->out_bit >= 31) + return -EINVAL; + + return !!(readl(priv->base + data->io_reg) >> data->out_bit); + } return !!(readl(priv->base + data->io_reg) >> data->in_bit); }