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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d82dede2csm178484285e9.5.2025.03.31.16.04.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 16:04:51 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Steven Lee , Peter Maydell , Jamin Lin , Troy Lee , Joel Stanley , =?utf-8?q?C=C3=A9dric_Le_Goater?= , qemu-arm@nongnu.org, Andrew Jeffery , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= Subject: [PATCH-for-10.0 1/2] hw/misc/aspeed_scu: Set MemoryRegionOps::impl::access_size to 32-bit Date: Tue, 1 Apr 2025 01:04:43 +0200 Message-ID: <20250331230444.88295-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331230444.88295-1-philmd@linaro.org> References: <20250331230444.88295-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All MemoryRegionOps::read/write() handlers switch over a 32-bit aligned value, because converted using TO_REG(), which is defined as: #define TO_REG(offset) ((offset) >> 2) So all implementations are 32-bit. Set min/max access_size accordingly. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Andrew Jeffery --- hw/misc/aspeed_scu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 76cfd916716..6703f3f9691 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -427,6 +427,10 @@ static const MemoryRegionOps aspeed_ast2400_scu_ops = { .read = aspeed_scu_read, .write = aspeed_ast2400_scu_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, .valid = { .min_access_size = 1, .max_access_size = 4, @@ -437,6 +441,8 @@ static const MemoryRegionOps aspeed_ast2500_scu_ops = { .read = aspeed_scu_read, .write = aspeed_ast2500_scu_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, .valid.min_access_size = 4, .valid.max_access_size = 4, .valid.unaligned = false, @@ -779,6 +785,8 @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = { .read = aspeed_ast2600_scu_read, .write = aspeed_ast2600_scu_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, .valid.min_access_size = 4, .valid.max_access_size = 4, .valid.unaligned = false, @@ -906,6 +914,8 @@ static const MemoryRegionOps aspeed_ast2700_scu_ops = { .read = aspeed_ast2700_scu_read, .write = aspeed_ast2700_scu_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, .valid.min_access_size = 1, .valid.max_access_size = 8, .valid.unaligned = false, @@ -1028,6 +1038,8 @@ static const MemoryRegionOps aspeed_ast2700_scuio_ops = { .read = aspeed_ast2700_scuio_read, .write = aspeed_ast2700_scuio_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, .valid.min_access_size = 1, .valid.max_access_size = 8, .valid.unaligned = false, From patchwork Mon Mar 31 23:04:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 877336 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp1987737wrs; Mon, 31 Mar 2025 16:05:46 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWIDkDhfRuwm3z5Jj6IgPsziEE2kOmQ2Y/580e1ovUeVIkT9gQrOKglkg+tja6HgdePb1WT4g==@linaro.org X-Google-Smtp-Source: AGHT+IGikhoAl2kTBYGX8cedMrB4xlRnBr9KoRsFnBZLv1v97LuQCF9CX7ILMoRb8UYms19JvIDT X-Received: by 2002:a05:620a:4152:b0:7c5:53ab:a74c with SMTP id af79cd13be357-7c6862ebd01mr1448543585a.10.1743462346098; Mon, 31 Mar 2025 16:05:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743462346; cv=none; d=google.com; s=arc-20240605; b=HsHa+SmJZa6UbpXclJk/v27CZU8//ZmakO4cP5aNobiYQeCFHB9/OFEai1MxmAqgc5 uScIhTtDVxvEQ+xS+lOrzWu/AY8HWawinfk2Lx14rTo+GKmXJdf5x+ZOuaf121c+EH4T QLsmABfyNlBEdIM5GaWGMrFIwcRi2gCtF3rmbprtfc6W6pTTTqCgG/fpGavqbxbNJT8j 7H3WBoEFHfQOkc9xXkIxQ2jyo1DmO4AZiiNcyxbWUhfGamctQaccrGo5NVPBEves+xHB ged0vGk+B/e4UsU+nCaUKoNZKbDpAk5DRGiqelMW6lFiFf9gep3euxtExrYDuTorBJ9Z o2pQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YlaEyhXAp6ocXg8HeW9O6/zASqUSt0dLhdV4fK8vO5o=; fh=V8dBZo/pKotciLd1l91bWiyDHbNrUdpmdA2WAWExemk=; b=FfayKyErYFU9WKQKSxwDZ5QJheyrZ1V3kxfP1ushT3fO2VS8byrvBEqEz3RWK1DvE+ Du2NqSksHg9/7M+WUpigsb1fzSfDAKjRtV/PWJbRiqhntjQO7s8u5yT3RhE8P9mUZLyP Rsa3Gm6SJYWOOZstno6g18Hm0aYusESaWhh019bxmQv3RiGuZrH6DcLRNcqA9BGxr4Rs PVeiNvwiKrrVEqcZrac92BCSomJO2kChusD+BWiyQ2VHN3PxfkajvbTu7dB/RnIeC8QI qiyjXm4Cq3A/dn6oLcsgDptvB+x02C+PivG6T48b0yyMf6ooQtwjkbpQQy3aH4p8npfw ZMeA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=C8pT92wb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b79e0afsm12611613f8f.65.2025.03.31.16.04.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 16:04:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Steven Lee , Peter Maydell , Jamin Lin , Troy Lee , Joel Stanley , =?utf-8?q?C=C3=A9dric_Le_Goater?= , qemu-arm@nongnu.org, Andrew Jeffery , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= Subject: [PATCH-for-10.0 2/2] hw/misc/aspeed_scu: Correct minimum access size for AST2500 / AST2600 Date: Tue, 1 Apr 2025 01:04:44 +0200 Message-ID: <20250331230444.88295-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331230444.88295-1-philmd@linaro.org> References: <20250331230444.88295-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Joel Stanley Guest code was performing a byte load to the SCU MMIO region, leading to the guest code crashing (it should be using proper accessors, but that is not Qemu's bug). Hardware and the documentation[1] both agree that byte loads are okay, so change all of the aspeed SCU devices to accept a minimum access size of 1. [1] See the 'ARM Address Space Mapping' table in the ASPEED docs. This is section 6.1 in the ast2400 and ast2700, and 7.1 in the ast2500 and ast2600 datasheets. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2636 Signed-off-by: Joel Stanley Reviewed-by: Troy Lee Message-ID: <20241118021820.4928-1-joel@jms.id.au> [PMD: Rebased, only including SCU changes] Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Andrew Jeffery --- hw/misc/aspeed_scu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 6703f3f9691..1af1a35a081 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -443,7 +443,7 @@ static const MemoryRegionOps aspeed_ast2500_scu_ops = { .endianness = DEVICE_LITTLE_ENDIAN, .impl.min_access_size = 4, .impl.max_access_size = 4, - .valid.min_access_size = 4, + .valid.min_access_size = 1, .valid.max_access_size = 4, .valid.unaligned = false, }; @@ -787,7 +787,7 @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = { .endianness = DEVICE_LITTLE_ENDIAN, .impl.min_access_size = 4, .impl.max_access_size = 4, - .valid.min_access_size = 4, + .valid.min_access_size = 1, .valid.max_access_size = 4, .valid.unaligned = false, };