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[71.42.197.3]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3ff052799b6sm465104b6e.37.2025.03.28.13.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 13:05:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH 1/9] include/exec: Move tb_{, set_}page_addr[01] to translation-block.h Date: Fri, 28 Mar 2025 15:04:51 -0500 Message-ID: <20250328200459.483089-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250328200459.483089-1-richard.henderson@linaro.org> References: <20250328200459.483089-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move the accessor functions for TranslationBlock into the header related to the structure. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/exec/exec-all.h | 49 ------------------------------- include/exec/translation-block.h | 50 ++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 49 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 19b0eda44a..fcad3446fe 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -123,55 +123,6 @@ int probe_access_full_mmu(CPUArchState *env, vaddr addr, int size, #endif /* !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ -static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb) -{ -#ifdef CONFIG_USER_ONLY - return tb->itree.start; -#else - return tb->page_addr[0]; -#endif -} - -static inline tb_page_addr_t tb_page_addr1(const TranslationBlock *tb) -{ -#ifdef CONFIG_USER_ONLY - tb_page_addr_t next = tb->itree.last & TARGET_PAGE_MASK; - return next == (tb->itree.start & TARGET_PAGE_MASK) ? -1 : next; -#else - return tb->page_addr[1]; -#endif -} - -static inline void tb_set_page_addr0(TranslationBlock *tb, - tb_page_addr_t addr) -{ -#ifdef CONFIG_USER_ONLY - tb->itree.start = addr; - /* - * To begin, we record an interval of one byte. When the translation - * loop encounters a second page, the interval will be extended to - * include the first byte of the second page, which is sufficient to - * allow tb_page_addr1() above to work properly. The final corrected - * interval will be set by tb_page_add() from tb->size before the - * node is added to the interval tree. - */ - tb->itree.last = addr; -#else - tb->page_addr[0] = addr; -#endif -} - -static inline void tb_set_page_addr1(TranslationBlock *tb, - tb_page_addr_t addr) -{ -#ifdef CONFIG_USER_ONLY - /* Extend the interval to the first byte of the second page. See above. */ - tb->itree.last = addr; -#else - tb->page_addr[1] = addr; -#endif -} - /* TranslationBlock invalidate API */ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last); diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h index 3c69bc71a9..8b8e730561 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -13,6 +13,7 @@ #include "exec/vaddr.h" #ifdef CONFIG_USER_ONLY #include "qemu/interval-tree.h" +#include "exec/target_page.h" #endif /* @@ -157,4 +158,53 @@ static inline uint32_t tb_cflags(const TranslationBlock *tb) bool tcg_cflags_has(CPUState *cpu, uint32_t flags); void tcg_cflags_set(CPUState *cpu, uint32_t flags); +static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb) +{ +#ifdef CONFIG_USER_ONLY + return tb->itree.start; +#else + return tb->page_addr[0]; +#endif +} + +static inline tb_page_addr_t tb_page_addr1(const TranslationBlock *tb) +{ +#ifdef CONFIG_USER_ONLY + tb_page_addr_t next = tb->itree.last & TARGET_PAGE_MASK; + return next == (tb->itree.start & TARGET_PAGE_MASK) ? -1 : next; +#else + return tb->page_addr[1]; +#endif +} + +static inline void tb_set_page_addr0(TranslationBlock *tb, + tb_page_addr_t addr) +{ +#ifdef CONFIG_USER_ONLY + tb->itree.start = addr; + /* + * To begin, we record an interval of one byte. When the translation + * loop encounters a second page, the interval will be extended to + * include the first byte of the second page, which is sufficient to + * allow tb_page_addr1() above to work properly. The final corrected + * interval will be set by tb_page_add() from tb->size before the + * node is added to the interval tree. + */ + tb->itree.last = addr; +#else + tb->page_addr[0] = addr; +#endif +} + +static inline void tb_set_page_addr1(TranslationBlock *tb, + tb_page_addr_t addr) +{ +#ifdef CONFIG_USER_ONLY + /* Extend the interval to the first byte of the second page. See above. */ + tb->itree.last = addr; +#else + tb->page_addr[1] = addr; +#endif +} + #endif /* EXEC_TRANSLATION_BLOCK_H */ From patchwork Fri Mar 28 20:04:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 876732 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp737166wrs; Fri, 28 Mar 2025 13:05:58 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXECLdg3kG58Czw3Drh00GCy+M5O7a9fqVj7OHOmMtW1s5Oxm7ZsOCstr7nBFAaen24AzPg8A==@linaro.org X-Google-Smtp-Source: AGHT+IGMHhOvbI2zyu2eAZubVJhgYrr1qVeocU9AnQZ485j7zPkq+W1gda01EdqZ3M4nLvrYKA/2 X-Received: by 2002:a05:6214:268e:b0:6e8:fa38:46aa with SMTP id 6a1803df08f44-6eed6271805mr5664696d6.33.1743192358613; Fri, 28 Mar 2025 13:05:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743192358; cv=none; d=google.com; s=arc-20240605; b=F9i8nXL8l+PIvtdUTrHjQHqkZRVFZjzDKHgtGpimia1l7Fso1C39pHowtaykMFkgjS Ub86cuUdSNLvHXTq/qKXrOmyMSf/r7c2JO5vhFKQNGh2QkBub+vTpZCKS/7g4C/j9aLG AOV53/8AWm8FSmS6UQi3aZwprMSqspdbAUEGRvbz72qNIFG8qocgVvlFvBiGqVieQ0NL vn1zR5H4I2cenMt7fHIeZ3iEa/LazInRj+2iJsd4Ofgp0rrh1Di+OaTbUsAjRwUqhNjX HTFw4DxDkH88ahLg5uh8H8ENrNLnzwOHWCXduwT4A6qXakc9L8tJNQ+GofzVqtdznfNZ Odgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vsSmqeOWwZw9KE8qAhLEmryV/FXdBjZqeFOodkM2cBg=; fh=6c3iePwzSVcIevU/n11cXtkmPbvvYSh1prLosaYzn/o=; b=P/0Fe3TiuVWvnc7dQJsDhidFAlDF7U0uHGKfvbUc/C8S/ivmxiGhr/5TTc366OzMpV Mq2X8IU/TuUgdfVsH7H7/bKmp36D9TZZdhU/wG5Ka3HvM8kylwmfy3jiiGdrANFr8GUr I+FZbdfPuT4ECrZqxn6l3oE6pdXQiLWPuBypz8+p6CwTXUNvql/S41kemxAA37Un3d7o W3RlCcV41T08YHpy3VPLNJBQ8NRMjekJdEdrYEcNzr0WZ3tVmJRaLObcoTJEZgwin9Yq w3mIocJtVO5DX/1nDfWr93Ar7f512gHbx8zYRgSUtTcZ25CkTBd3CE1MykqBoZbs+pUP io2A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=msFK+kfm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.42.197.3]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3ff052799b6sm465104b6e.37.2025.03.28.13.05.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 13:05:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH 2/9] accel/tcg: Move get_page_addr_code* declarations Date: Fri, 28 Mar 2025 15:04:52 -0500 Message-ID: <20250328200459.483089-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250328200459.483089-1-richard.henderson@linaro.org> References: <20250328200459.483089-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2b; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move the declarations from exec/exec-all.h to the private accel/tcg/internal-common.h. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/internal-common.h | 34 ++++++++++++++++++++++++++++++++++ include/exec/exec-all.h | 34 ---------------------------------- accel/tcg/translator.c | 1 + 3 files changed, 35 insertions(+), 34 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 9b6ab3a8cc..2f00560d10 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -74,4 +74,38 @@ uint32_t curr_cflags(CPUState *cpu); void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); +/** + * get_page_addr_code_hostp() + * @env: CPUArchState + * @addr: guest virtual address of guest code + * + * See get_page_addr_code() (full-system version) for documentation on the + * return value. + * + * Sets *@hostp (when @hostp is non-NULL) as follows. + * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp + * to the host address where @addr's content is kept. + * + * Note: this function can trigger an exception. + */ +tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr, + void **hostp); + +/** + * get_page_addr_code() + * @env: CPUArchState + * @addr: guest virtual address of guest code + * + * If we cannot translate and execute from the entire RAM page, or if + * the region is not backed by RAM, returns -1. Otherwise, returns the + * ram_addr_t corresponding to the guest code at @addr. + * + * Note: this function can trigger an exception. + */ +static inline tb_page_addr_t get_page_addr_code(CPUArchState *env, + vaddr addr) +{ + return get_page_addr_code_hostp(env, addr, NULL); +} + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index fcad3446fe..f52a680f42 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -143,40 +143,6 @@ struct MemoryRegionSection *iotlb_to_section(CPUState *cpu, hwaddr index, MemTxAttrs attrs); #endif -/** - * get_page_addr_code_hostp() - * @env: CPUArchState - * @addr: guest virtual address of guest code - * - * See get_page_addr_code() (full-system version) for documentation on the - * return value. - * - * Sets *@hostp (when @hostp is non-NULL) as follows. - * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp - * to the host address where @addr's content is kept. - * - * Note: this function can trigger an exception. - */ -tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr, - void **hostp); - -/** - * get_page_addr_code() - * @env: CPUArchState - * @addr: guest virtual address of guest code - * - * If we cannot translate and execute from the entire RAM page, or if - * the region is not backed by RAM, returns -1. Otherwise, returns the - * ram_addr_t corresponding to the guest code at @addr. - * - * Note: this function can trigger an exception. - */ -static inline tb_page_addr_t get_page_addr_code(CPUArchState *env, - vaddr addr) -{ - return get_page_addr_code_hostp(env, addr, NULL); -} - #if !defined(CONFIG_USER_ONLY) MemoryRegionSection * diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 7ef04fc597..307a513487 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -17,6 +17,7 @@ #include "exec/translator.h" #include "exec/plugin-gen.h" #include "tcg/tcg-op-common.h" +#include "internal-common.h" #include "internal-target.h" #include "disas/disas.h" #include "tb-internal.h" From patchwork Fri Mar 28 20:04:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 876733 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp737340wrs; Fri, 28 Mar 2025 13:06:21 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXoZTL1Zge5bZmUCNo21iIaHi5RihDN0GkCwcJvQlyDxhq+j69hVR8dKjv45lezHWVYNWwnbQ==@linaro.org X-Google-Smtp-Source: AGHT+IHTqxRIL/WsKLq5u+4txrtDE0VRvuanEeYFaeJr8d/eah0Hfm4vTK8TyuYXGXOKR05AjDqq X-Received: by 2002:a05:6102:2b85:b0:4c1:9526:a635 with SMTP id ada2fe7eead31-4c6d398d5a0mr949490137.17.1743192381626; Fri, 28 Mar 2025 13:06:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743192381; cv=none; d=google.com; s=arc-20240605; b=OmDoMpBdUj7mx5nUA0IlJ2ABevQAiLUoEIZL3CjPB1L//r+dIbPXON5Uq2NRUGcJa+ UHb3vozlrx77xxi9eVEMeaQS86q7NwLuS6rPIkZutJmigNC0LxypIanJvexWbtQLTZua XqDO8hWWTT97dIAOlWhH6WBSqYuvLvCF7Gv8h7aWwjXL/D6QaFonWq9lKNGEnKQdMddG s2DqKyuWwNLAAluWBZEn7y8Jo24MvQE5YWIbK46ks5dfOjoXlIz6cn6RHD4WfPAEVSRa OWLDFznkHciM3d7fFn6ekNcZgHZ03GF2tdE+plC5PXeAQRLyCF10ZBFj4+Ho4RYthRtb 3wUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1dr/ia722bLIN9dEZ7twaM/nT3BoEXqpJL6WGPcn5bc=; fh=6c3iePwzSVcIevU/n11cXtkmPbvvYSh1prLosaYzn/o=; b=WaLqoV0vTsqOIJRlwkfDEKGHb8Y/b1sB+L5GCam2xHclqCQHWrA3Lhr/21Gd2XcQVV FAbn+q0i9/ur33Bq+9TLUrwBbfY6A8y9kWscArFSS41RPU2tcSkciazLA+5jsf5Kiv9k scEgZlCwTJLBT2XkWjL/HQ1WB5/9gAOTrIPHG2Ljazs+6W4C+6dlaCS8PRfw7AA8uTxo XHTzJhW+TcA1yECOhw/AO9XonVk8AWq13xTp4q+gUcYQMC64KPdWz5bxIxpGWYr4TTYn NGQSMdSyvkfXcRvn5pQz04qViz4oNi9RcAytkhOJojOiZ1xDitRnbFqIQUqHy/gcNTB9 nSBw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J6imUvrz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.42.197.3]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3ff052799b6sm465104b6e.37.2025.03.28.13.05.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 13:05:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH 3/9] accel/tcg: Remove page_protect Date: Fri, 28 Mar 2025 15:04:53 -0500 Message-ID: <20250328200459.483089-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250328200459.483089-1-richard.henderson@linaro.org> References: <20250328200459.483089-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Merge the user-only page_protect function with the user-only implementation of tb_lock_page0. This avoids pulling page-protection.h into tb-internal.h. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/tb-internal.h | 11 +++-------- include/user/page-protection.h | 1 - accel/tcg/user-exec.c | 2 +- 3 files changed, 4 insertions(+), 10 deletions(-) diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h index 68aa8d17f4..f7c2073e29 100644 --- a/accel/tcg/tb-internal.h +++ b/accel/tcg/tb-internal.h @@ -51,28 +51,23 @@ #endif /* CONFIG_SOFTMMU */ +void tb_lock_page0(tb_page_addr_t); + #ifdef CONFIG_USER_ONLY -#include "user/page-protection.h" /* * For user-only, page_protect sets the page read-only. * Since most execution is already on read-only pages, and we'd need to * account for other TBs on the same page, defer undoing any page protection * until we receive the write fault. */ -static inline void tb_lock_page0(tb_page_addr_t p0) -{ - page_protect(p0); -} - static inline void tb_lock_page1(tb_page_addr_t p0, tb_page_addr_t p1) { - page_protect(p1); + tb_lock_page0(p1); } static inline void tb_unlock_page1(tb_page_addr_t p0, tb_page_addr_t p1) { } static inline void tb_unlock_pages(TranslationBlock *tb) { } #else -void tb_lock_page0(tb_page_addr_t); void tb_lock_page1(tb_page_addr_t, tb_page_addr_t); void tb_unlock_page1(tb_page_addr_t, tb_page_addr_t); void tb_unlock_pages(TranslationBlock *); diff --git a/include/user/page-protection.h b/include/user/page-protection.h index 51daa18648..d5c8748d49 100644 --- a/include/user/page-protection.h +++ b/include/user/page-protection.h @@ -16,7 +16,6 @@ #include "exec/target_long.h" #include "exec/translation-block.h" -void page_protect(tb_page_addr_t page_addr); int page_unprotect(tb_page_addr_t address, uintptr_t pc); int page_get_flags(target_ulong address); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 667c5e0354..72a9809c2d 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -657,7 +657,7 @@ target_ulong page_find_range_empty(target_ulong min, target_ulong max, } } -void page_protect(tb_page_addr_t address) +void tb_lock_page0(tb_page_addr_t address) { PageFlagsNode *p; target_ulong start, last; From patchwork Fri Mar 28 20:04:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 876730 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp737141wrs; Fri, 28 Mar 2025 13:05:55 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU+PdiD0JfP7XNsnEwyDLiaHVdnC/yXiL9SDbEgcToBqGpvRQjayXu69cqA3gCXS2upVoieQg==@linaro.org X-Google-Smtp-Source: AGHT+IG08hv4AtFwpbkXdK/9mbF6+IPqhf2yVkEan0C4ioM+3b4zwv1nAt7DSdgVwPyTylxcWYPd X-Received: by 2002:a05:6102:3ec5:b0:4c3:6ba1:4129 with SMTP id ada2fe7eead31-4c6d394f529mr1042849137.20.1743192352337; Fri, 28 Mar 2025 13:05:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743192352; cv=none; d=google.com; s=arc-20240605; b=LPDeCh9gvZh5Pg416hU2Tzp2Ms/fWT2IZKQonnPj4qHQ19cQBE8ZcDTO2Rcx7WOKxY tKsIeUxrXYAXdJ9Go2IeUok+nVyy+R3L+4nT0VNGE0UOh132nDxFMrhPlniBeyGblL8B G/r2uNJTOhgpF5P0uWpICx40efpadPeFEXn+0eYcAib5qT9MYfGL3ajWcXFiMoyxI90S ukuJpQGYIqpquHX2BKmkeea48caF6rh4yIz+8+VYm2QF9CQn1Fmb5H8FatJGxi4I9fi8 9UOXOu+h0WzAOgdaAieTabCvwazJO2N6SRlE3X3JUscNBmTfJJj9gNb21+oDcyk/GXJl 7OtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yu5KF6BrH2yp81gEA850j0dS4wEWUhM6jM/Abi77cw4=; fh=6c3iePwzSVcIevU/n11cXtkmPbvvYSh1prLosaYzn/o=; b=cO38jqy174tnknRp3SjgOVBHrHO2RC1I9YfLX6cL7KdHeEiD05x5OsxD9Zzho/AYUg zbE5UgaFmOiQ2IV2wWuh24nAB8sqXspBiL+gYaiUBdd1RnC4pD7tY2WmF4p8TG0a5aMD v/yzG35IpXyJCqfmSnZa1/PdUGBxllUXhP7LMgYTWyYyBNqAlWQro85eG1iKerY9ceQN g29uggrVuXLSjtFXxS6o8iOfyH0KaU6ATmHiFq4lZT2xA3GYAndtAJN5doUnzVAFk0rA gpNXdcrxHCVd1mVx+D4PxjiOjIaLGhjnycLt6Nd4KSXyEFpn03BZQzbIBfb3VmlKutHF KkMw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=neN94agz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.42.197.3]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3ff052799b6sm465104b6e.37.2025.03.28.13.05.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 13:05:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH 4/9] accel/tcg: Remove cpu-all.h, exec-all.h from tb-internal.h Date: Fri, 28 Mar 2025 15:04:54 -0500 Message-ID: <20250328200459.483089-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250328200459.483089-1-richard.henderson@linaro.org> References: <20250328200459.483089-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Not used by tb-internal.h, but add an include for target_page.h in tb-maint.c. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/tb-internal.h | 2 -- accel/tcg/tb-maint.c | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h index f7c2073e29..f9a06bcbab 100644 --- a/accel/tcg/tb-internal.h +++ b/accel/tcg/tb-internal.h @@ -9,8 +9,6 @@ #ifndef ACCEL_TCG_TB_INTERNAL_TARGET_H #define ACCEL_TCG_TB_INTERNAL_TARGET_H -#include "exec/cpu-all.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" /* diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index d5899ad047..df3438e190 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -26,6 +26,7 @@ #include "exec/page-protection.h" #include "exec/mmap-lock.h" #include "exec/tb-flush.h" +#include "exec/target_page.h" #include "tb-internal.h" #include "system/tcg.h" #include "tcg/tcg.h" From patchwork Fri Mar 28 20:04:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 876734 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp737642wrs; Fri, 28 Mar 2025 13:07:00 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXglPIIsNB2Hc02Z1y9RQPIO6zNXn49n7X+wPlFjC2yhahYTpmd/MKRLOEzc9ItAsNzJ5skGQ==@linaro.org X-Google-Smtp-Source: AGHT+IG2D4U3WVpi1jAyufEfdmYJZ5ndU68Pt12200/37kUr/IWT1JkNu5Qeq02zX/K4bLfTsPEB X-Received: by 2002:a05:6122:4592:b0:520:51a4:b84f with SMTP id 71dfb90a1353d-5261d381934mr1108308e0c.4.1743192420050; Fri, 28 Mar 2025 13:07:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743192420; cv=none; d=google.com; s=arc-20240605; b=bsYgIQVqEczqLPjbe1F+3M08JlDN1eMwTEw1IoRG0UkSOju4zXOhPGXk/GRiQwyXXN ajI57xjy7qphbK76xefZQxIVtwK/y4wI7Kj5OWVad7NIzEGNZ3ypRfs8iS7KVi7ntmtq eQ2W1IUdT3zVLjEMsQrhQLUGL5bJbYDgvyNjL0hDqUC6SwGGoiBhJQwPPDaZJiZXXN8D GWgRNL8UjwAt9+AT2uHn2i5UiQQfRmCvyMg4Mnv0ACGmbnLTR6mUtO4XISTjVl4DxPr0 a7geNYMD459r56rSUizMxXaopI73nt8w8A76bahYSyajgoFFDIjaWSfnSm7pEt2uYDwM d2kA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oD3b+nDGpxnwQn/lSzkFZnkDRTkEZOWvlufBLJ/eR8Q=; fh=6c3iePwzSVcIevU/n11cXtkmPbvvYSh1prLosaYzn/o=; b=NLLEOIUQM2OxAFW69BXuTPYnxcOJMw1L/klheDAHLzfHwScU06T5klkC43b9GriF65 RWYwTvPoCRLcZjX9tDT9WC4oRXV9zYnQVuYnZ24d23cHKm8qQCEc/CQYDFP/sdEpo+1T rLPZTooGVr/PYXf2QpOFkVwRS5AOizDNCE29BT76DbhnMNuR6pHS/Vn0ib6wnFOTo1T+ llh5EbBwnmWbgPnj96+S2M6ikp9OYqVxcyhkWpYzsJdmv49MMtMR8vsnTE8cHkaJnWYE 9MSTN2i9CEaPh6RSy513SH3dZE98MACteur0pvKmYQHytcYnQN/PynMYCb/8BQxhSC82 oAeA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I1cuWsT3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.42.197.3]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3ff052799b6sm465104b6e.37.2025.03.28.13.05.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 13:05:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH 5/9] accel/tcg: Build translator.c twice Date: Fri, 28 Mar 2025 15:04:55 -0500 Message-ID: <20250328200459.483089-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250328200459.483089-1-richard.henderson@linaro.org> References: <20250328200459.483089-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Drop some unnecessary includes. Change the offsetof expressions to be based on CPUState instead of ArchCPU. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- accel/tcg/translator.c | 14 ++++++-------- accel/tcg/meson.build | 2 +- 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 307a513487..36a6a9e040 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -11,14 +11,13 @@ #include "qemu/bswap.h" #include "qemu/log.h" #include "qemu/error-report.h" -#include "exec/exec-all.h" #include "exec/cpu-ldst-common.h" #include "exec/cpu-mmu-index.h" +#include "exec/target_page.h" #include "exec/translator.h" #include "exec/plugin-gen.h" #include "tcg/tcg-op-common.h" #include "internal-common.h" -#include "internal-target.h" #include "disas/disas.h" #include "tb-internal.h" @@ -26,8 +25,7 @@ static void set_can_do_io(DisasContextBase *db, bool val) { QEMU_BUILD_BUG_ON(sizeof_field(CPUState, neg.can_do_io) != 1); tcg_gen_st8_i32(tcg_constant_i32(val), tcg_env, - offsetof(ArchCPU, parent_obj.neg.can_do_io) - - offsetof(ArchCPU, env)); + offsetof(CPUState, neg.can_do_io) - sizeof(CPUState)); } bool translator_io_start(DisasContextBase *db) @@ -50,8 +48,8 @@ static TCGOp *gen_tb_start(DisasContextBase *db, uint32_t cflags) if ((cflags & CF_USE_ICOUNT) || !(cflags & CF_NOIRQ)) { count = tcg_temp_new_i32(); tcg_gen_ld_i32(count, tcg_env, - offsetof(ArchCPU, parent_obj.neg.icount_decr.u32) - - offsetof(ArchCPU, env)); + offsetof(CPUState, neg.icount_decr.u32) - + sizeof(CPUState)); } if (cflags & CF_USE_ICOUNT) { @@ -80,8 +78,8 @@ static TCGOp *gen_tb_start(DisasContextBase *db, uint32_t cflags) if (cflags & CF_USE_ICOUNT) { tcg_gen_st16_i32(count, tcg_env, - offsetof(ArchCPU, parent_obj.neg.icount_decr.u16.low) - - offsetof(ArchCPU, env)); + offsetof(CPUState, neg.icount_decr.u16.low) - + sizeof(CPUState)); } return icount_start_insn; diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 72d4acfe5e..047afa49a2 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -8,6 +8,7 @@ tcg_ss.add(files( 'cpu-exec-common.c', 'tcg-runtime.c', 'tcg-runtime-gvec.c', + 'translator.c', )) if get_option('plugins') tcg_ss.add(files('plugin-gen.c')) @@ -22,7 +23,6 @@ tcg_specific_ss.add(files( 'cpu-exec.c', 'tb-maint.c', 'translate-all.c', - 'translator.c', )) tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c')) specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) From patchwork Fri Mar 28 20:04:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 876736 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp737741wrs; Fri, 28 Mar 2025 13:07:11 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW2JicrS2YzZAKbleIwrp+SZi+50XsowxIbIQtK9/rpvkGJXEGcHf4tXX5xQWmrxfJRNZAYwQ==@linaro.org X-Google-Smtp-Source: AGHT+IHzRTkYTeRjEAuc5D/kOqFjDLyyS6ULRk1k53tHhRHlOxDOleuTvwPCPUwYjs33E5mm02Wc X-Received: by 2002:a05:6102:3fa2:b0:4c1:9328:107d with SMTP id ada2fe7eead31-4c6d399a6a9mr1130377137.24.1743192430874; Fri, 28 Mar 2025 13:07:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743192430; cv=none; d=google.com; s=arc-20240605; b=Zs+L1ArB9R+1Lmjr1qzuTSgnYIEXTnCG6qmQUgbN8i3HvQJfdldsuF2QEucCS1OpWp Nr+pPdkdh93Fivt2oCdPEdYVgm9nRB8pVKVXoY0ZrtwzOGFqmxGb4EyVY0IW5LMnK9jj 1qG6A4H7eWwWClgtPU9+qP0YgF35QeUSQXkcjlbe7mTMy/zy6PQQKwl5Wv27LeXIATkG pMsSUPnzhm8D0O0WVwN1A9lY5J181nYUzsMOiIlF49CfU/tIgpcSnAmYxZtrbP9yru1Z aBFTnAX6zGGPYbRO+pl6MiJCwHDVPBfZn7vOL0ZQZS/KKHBAfvLM3L5/kGZYvmFjVhL8 EYhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UZg1pklGiSZQ4vU+3tGBO6lhROLm4HbFNDbqrkRsdUg=; fh=6c3iePwzSVcIevU/n11cXtkmPbvvYSh1prLosaYzn/o=; b=fpw/ftd7EPMy73R1xXITmxBnjv4QzO5e8Jv1iuSmw5wNEYcckAcPztogE4GRebErez IAA9HE9jjfjKklOOt3AkIaVoAdUlZ2/Mv/YzpEJHSs01VAcP7yAL/VE/jKuhxzw5bu00 dCIlXy7POgrPRzFJLWXL2G64Kshro9ZbDVoV0hALXOhLS5MpceHAbST7kQoJqMT558Tc 1vGQzVHl9NCXkQJV06sk81GvZGoSkl3Fe22fa186i87CxT8X3ToLqjERZZyiEHaYT6XG lsqVTgpFGPq2M1wSYkXtZgiHLaqFXbvbL2xDRLfTLQ7BgnmL1RMc/AOWq88AfHoeSnT5 /upg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u3bz9JHH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.42.197.3]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3ff052799b6sm465104b6e.37.2025.03.28.13.05.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 13:05:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH 6/9] accel/tcg: Split out tlb-bounds.h Date: Fri, 28 Mar 2025 15:04:56 -0500 Message-ID: <20250328200459.483089-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250328200459.483089-1-richard.henderson@linaro.org> References: <20250328200459.483089-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The CPU_TLB_DYN_{MIN,MAX}_BITS definitions are not required outside of cputlb.c and translate-all.c. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- accel/tcg/tb-internal.h | 27 --------------------------- accel/tcg/tlb-bounds.h | 32 ++++++++++++++++++++++++++++++++ accel/tcg/cputlb.c | 1 + accel/tcg/translate-all.c | 1 + 4 files changed, 34 insertions(+), 27 deletions(-) create mode 100644 accel/tcg/tlb-bounds.h diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h index f9a06bcbab..08538e2896 100644 --- a/accel/tcg/tb-internal.h +++ b/accel/tcg/tb-internal.h @@ -22,33 +22,6 @@ */ #define GETPC_ADJ 2 -#ifdef CONFIG_SOFTMMU - -#define CPU_TLB_DYN_MIN_BITS 6 -#define CPU_TLB_DYN_DEFAULT_BITS 8 - -# if HOST_LONG_BITS == 32 -/* Make sure we do not require a double-word shift for the TLB load */ -# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) -# else /* HOST_LONG_BITS == 64 */ -/* - * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == - * 2**34 == 16G of address space. This is roughly what one would expect a - * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel - * Skylake's Level-2 STLB has 16 1G entries. - * Also, make sure we do not size the TLB past the guest's address space. - */ -# ifdef TARGET_PAGE_BITS_VARY -# define CPU_TLB_DYN_MAX_BITS \ - MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) -# else -# define CPU_TLB_DYN_MAX_BITS \ - MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) -# endif -# endif - -#endif /* CONFIG_SOFTMMU */ - void tb_lock_page0(tb_page_addr_t); #ifdef CONFIG_USER_ONLY diff --git a/accel/tcg/tlb-bounds.h b/accel/tcg/tlb-bounds.h new file mode 100644 index 0000000000..efd34d4793 --- /dev/null +++ b/accel/tcg/tlb-bounds.h @@ -0,0 +1,32 @@ +/* + * softmmu size bounds + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ACCEL_TCG_TLB_BOUNDS_H +#define ACCEL_TCG_TLB_BOUNDS_H + +#define CPU_TLB_DYN_MIN_BITS 6 +#define CPU_TLB_DYN_DEFAULT_BITS 8 + +# if HOST_LONG_BITS == 32 +/* Make sure we do not require a double-word shift for the TLB load */ +# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) +# else /* HOST_LONG_BITS == 64 */ +/* + * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == + * 2**34 == 16G of address space. This is roughly what one would expect a + * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel + * Skylake's Level-2 STLB has 16 1G entries. + * Also, make sure we do not size the TLB past the guest's address space. + */ +# ifdef TARGET_PAGE_BITS_VARY +# define CPU_TLB_DYN_MAX_BITS \ + MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) +# else +# define CPU_TLB_DYN_MAX_BITS \ + MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) +# endif +# endif + +#endif /* ACCEL_TCG_TLB_BOUNDS_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 28c47d4872..a717f357d5 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -41,6 +41,7 @@ #include "trace.h" #include "tb-hash.h" #include "tb-internal.h" +#include "tlb-bounds.h" #include "internal-common.h" #include "internal-target.h" #ifdef CONFIG_PLUGIN diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bb161ae61a..87fb6c51d3 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -47,6 +47,7 @@ #include "exec/page-protection.h" #include "exec/mmap-lock.h" #include "tb-internal.h" +#include "tlb-bounds.h" #include "exec/translator.h" #include "exec/tb-flush.h" #include "qemu/bitmap.h" From patchwork Fri Mar 28 20:04:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 876738 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp737813wrs; Fri, 28 Mar 2025 13:07:22 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUZ20XgOIuvTcN2EDnfbAnf6n/Gcz1VtDdIB4JaBWohFNY18ApzpWWNRSWQIvOmqnDmNrmpmw==@linaro.org X-Google-Smtp-Source: AGHT+IHWca9ItZp3zE1ZzWnZG30WMErytbTYop3mHBxqp/tzkBEtRATqqN9P+dm1FJ0M1ApMRj17 X-Received: by 2002:ac8:7d86:0:b0:477:6e32:aae2 with SMTP id d75a77b69052e-477a15a4402mr14191581cf.0.1743192441786; Fri, 28 Mar 2025 13:07:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743192441; cv=none; d=google.com; s=arc-20240605; b=XtYe36Pmqaqz9oqFRMDpLb6oFSbz5LBo0a/S2fC4RXENEUA/pCVU9ntC4GxxiAcA9z yM4DRzeK2FjsS3NXtfIUutzyGR0yxQ0zeRVvKtiVkPyNBlg3hPbe6rHFkV2qPlgRB+R6 M18EebzTcAWHjkHpWHMDabneTnc55JV+GtxKGG2DBdiqCLgmrp8uQyd1WeKzq9209ZD1 TR1/daNwlWOeMPGcr4w2cOyLgO6ALK+HsBq8VMXWolZIATOnhxWa/Z3WyVauLEfCWf16 h81PjTRuZ2bUwEgDtg0fYdzAcRvoK0amZvSj9BDy02rYr4usWhtbgdZU4xXTLzlldi1K RcCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8Musv96uqDqGBH3VebH5aXYMcN88bZT/SnScT9B79DM=; fh=6c3iePwzSVcIevU/n11cXtkmPbvvYSh1prLosaYzn/o=; b=Yiu9MTItr9M0yHk4iFKE0+4ne932pTca6zl/wOqrMdbfcVjqv7oeFvmyuYp7+2G8eq 32WqNx04lD9E/YpVOY39fuyd1rAECyToAp4YW4dyc7plJ6Vf8R8Fe7cIqptz3/VBMBIr CkO/XHCslkEzgINleFGaLebNLcXrSrgIhCGoZA4u8AimlQ5e77BjeyQMi1IQf+IWIF7Q 8vvAXGifWCUTCYAZ+Pgdn+pzta+MWAp+A7+egMj0gM+kfKBL53hpcUkJ3nE9rYvxNENU +3ocvaM1+2BZbvXbF+/jARi/uh3k3FxU7rwDckK3Q/33VTzjNVYtsebcqagnsI5xq0Xb cdiw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z3c1Etry; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.42.197.3]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3ff052799b6sm465104b6e.37.2025.03.28.13.05.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 13:05:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH 7/9] include/exec: Redefine tlb-flags with absolute values Date: Fri, 28 Mar 2025 15:04:57 -0500 Message-ID: <20250328200459.483089-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250328200459.483089-1-richard.henderson@linaro.org> References: <20250328200459.483089-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Don't base the values on TARGET_PAGE_BITS_MIN, but do verify that TLB_FLAGS_MASK does not overlap minimum page size. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/exec/tlb-flags.h | 68 +++++++++++++++++++--------------------- accel/tcg/cputlb.c | 2 ++ 2 files changed, 34 insertions(+), 36 deletions(-) diff --git a/include/exec/tlb-flags.h b/include/exec/tlb-flags.h index 54a6bae768..357e79095c 100644 --- a/include/exec/tlb-flags.h +++ b/include/exec/tlb-flags.h @@ -19,54 +19,29 @@ #ifndef TLB_FLAGS_H #define TLB_FLAGS_H -#include "exec/cpu-defs.h" +/* + * Flags returned for lookup of a TLB virtual address. + */ #ifdef CONFIG_USER_ONLY /* - * Allow some level of source compatibility with softmmu. We do not - * support any of the more exotic features, so only invalid pages may - * be signaled by probe_access_flags(). + * Allow some level of source compatibility with softmmu. + * Invalid is set when the page does not have requested permissions. + * MMIO is set when we want the target helper to use the functional + * interface for load/store so that plugins see the access. */ -#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) -#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2)) -#define TLB_WATCHPOINT 0 +#define TLB_INVALID_MASK (1 << 0) +#define TLB_MMIO (1 << 1) +#define TLB_WATCHPOINT 0 #else -/* - * Flags stored in the low bits of the TLB virtual address. - * These are defined so that fast path ram access is all zeros. - * The flags all must be between TARGET_PAGE_BITS and - * maximum address alignment bit. - * - * Use TARGET_PAGE_BITS_MIN so that these bits are constant - * when TARGET_PAGE_BITS_VARY is in effect. - * - * The count, if not the placement of these bits is known - * to tcg/tcg-op-ldst.c, check_max_alignment(). - */ -/* Zero if TLB entry is valid. */ -#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) -/* - * Set if TLB entry references a clean RAM page. The iotlb entry will - * contain the page physical address. - */ -#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) -/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ -#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 3)) - -/* - * Use this mask to check interception with an alignment mask - * in a TCG backend. - */ -#define TLB_FLAGS_MASK \ - (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_FORCE_SLOW) - /* * Flags stored in CPUTLBEntryFull.slow_flags[x]. * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x]. */ + /* Set if TLB entry requires byte swap. */ #define TLB_BSWAP (1 << 0) /* Set if TLB entry contains a watchpoint. */ @@ -82,6 +57,27 @@ (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED | \ TLB_DISCARD_WRITE | TLB_MMIO) +/* + * Flags stored in CPUTLBEntry.addr_idx[x]. + * These must be above the largest alignment (64 bytes), + * and below the smallest page size (1024 bytes). + * This leaves bits [9:6] available for use. + */ + +/* Zero if TLB entry is valid. */ +#define TLB_INVALID_MASK (1 << 6) +/* Set if TLB entry references a clean RAM page. */ +#define TLB_NOTDIRTY (1 << 7) +/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ +#define TLB_FORCE_SLOW (1 << 8) + +/* + * Use this mask to check interception with an alignment mask + * in a TCG backend. + */ +#define TLB_FLAGS_MASK \ + (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_FORCE_SLOW) + /* The two sets of flags must not overlap. */ QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a717f357d5..39314e86f3 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -49,6 +49,8 @@ #endif #include "tcg/tcg-ldst.h" +QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & ((1u < TARGET_PAGE_BITS_MIN) - 1)); + /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ /* #define DEBUG_TLB_LOG */ From patchwork Fri Mar 28 20:04:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 876739 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp737845wrs; Fri, 28 Mar 2025 13:07:25 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVX3OzFuY5F3NxHDtsLYZAT2s4GlwlXZ9YpixS/w0oab87uE2AQOD2lLztITX4SNWyMmuOW8g==@linaro.org X-Google-Smtp-Source: AGHT+IGRD2LUx/XDP7LekgrHUs2c5Z8J48nUiCcBhxBp/2eJLjOWQCesrPM2V4moc3T6qUfbJvFt X-Received: by 2002:a05:6214:2aa5:b0:6e8:9e8f:cfb with SMTP id 6a1803df08f44-6eed6206676mr4788206d6.24.1743192445405; Fri, 28 Mar 2025 13:07:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743192445; cv=none; d=google.com; s=arc-20240605; b=CK/77oCmfeIS2gV1dXN3JFBXd9/Eag+auGGvj5KxZjK4zH73wxwageLARfOYY99W7A QcrZ0jDwsCOvoQ1h4U9llx8Vi4oX5oEx5oCJJzOA05eZvwSPpjcnN44QTJpz0gZb64yy itmZp0/NAzsz0nX0ZhiCB2Uo0LLNYWPcWymo1WAcvcmxtbQzlwzSr23yGSMwA1KrMPFl F6gqQkWvCNL6ZdQfyfig3aLN2ToD6GHPrAFngutVsUnJGAsuThK5h5b15YMKSlw3iPCf 4uZHyF+ApF1hbcdbT8iKaFGcQmhn4gQkSY6r/SdYc78E8RPJuErn6w0YPW+uOupU8xZF dcvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2gHs8eWFpnWN3yMoh+lxCbsbSFzac6+W/s5SOrn3Ec8=; fh=6c3iePwzSVcIevU/n11cXtkmPbvvYSh1prLosaYzn/o=; b=eF/k9nclJ7vhtqMqx03DGdq5Bo+Q3BqiBcE9AOOQCcBvY+98ZseevyGSsCP5gLZ+wH aNKPbTNNxTI4swRc/yIqqbtl/KeJIHkXUb+gm3jYSCprwUDR+qUdzaHpyw8/60vtn/a+ PREf9ntrP11J1NAgWiYM1m0H5Goew3zyK5W8NUx8UP5zGFldDDnGdcI8C/WOaPHogz6i g9qnI1BNQPLzuruQUzPULmVTs6/s1joj9djl6EMSXPiduHdwJvWZ0mUH6WzghAII+7WC xcIX0ZxO4J+uNhnUShzs5/GBfrXJO1V8Sg/zzhyW4mSxXgwZ/nzHWtO/KfVDfunyBxgv saAw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="m/IDPQH3"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.42.197.3]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3ff052799b6sm465104b6e.37.2025.03.28.13.05.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 13:05:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH 8/9] page-vary: Move and rename qemu_target_page_bits_min Date: Fri, 28 Mar 2025 15:04:58 -0500 Message-ID: <20250328200459.483089-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250328200459.483089-1-richard.henderson@linaro.org> References: <20250328200459.483089-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rename to migration_legacy_page_bits, to make it clear that we cannot change the value without causing a migration break. Move to page-vary.h and page-vary-target.c. Define via TARGET_PAGE_BITS if not TARGET_PAGE_BITS_VARY. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/exec/page-vary.h | 9 +++++++++ include/exec/target_page.h | 1 - migration/savevm.c | 6 +++--- page-target.c | 5 ----- page-vary-target.c | 9 +++++++++ 5 files changed, 21 insertions(+), 9 deletions(-) diff --git a/include/exec/page-vary.h b/include/exec/page-vary.h index 54ddde308a..101c25911c 100644 --- a/include/exec/page-vary.h +++ b/include/exec/page-vary.h @@ -49,4 +49,13 @@ bool set_preferred_target_page_bits(int bits); */ void finalize_target_page_bits(void); +/** + * migration_legacy_page_bits + * + * For migration compatibility with qemu v2.9, prior to the introduction + * of the configuration/target-page-bits section, return the value of + * TARGET_PAGE_BITS that the target had then. + */ +int migration_legacy_page_bits(void); + #endif /* EXEC_PAGE_VARY_H */ diff --git a/include/exec/target_page.h b/include/exec/target_page.h index 8e89e5cbe6..e4bd7f7767 100644 --- a/include/exec/target_page.h +++ b/include/exec/target_page.h @@ -63,7 +63,6 @@ static inline int qemu_target_page_bits(void) return TARGET_PAGE_BITS; } -int qemu_target_page_bits_min(void); size_t qemu_target_pages_to_MiB(size_t pages); #endif diff --git a/migration/savevm.c b/migration/savevm.c index c33200a33f..0c12e373b4 100644 --- a/migration/savevm.c +++ b/migration/savevm.c @@ -50,6 +50,7 @@ #include "system/cpus.h" #include "system/memory.h" #include "exec/target_page.h" +#include "exec/page-vary.h" #include "trace.h" #include "qemu/iov.h" #include "qemu/job.h" @@ -339,7 +340,7 @@ static int configuration_pre_load(void *opaque) * predates the variable-target-page-bits support and is using the * minimum possible value for this CPU. */ - state->target_page_bits = qemu_target_page_bits_min(); + state->target_page_bits = migration_legacy_page_bits(); return 0; } @@ -462,8 +463,7 @@ static const VMStateInfo vmstate_info_capability = { */ static bool vmstate_target_page_bits_needed(void *opaque) { - return qemu_target_page_bits() - > qemu_target_page_bits_min(); + return qemu_target_page_bits() > migration_legacy_page_bits(); } static const VMStateDescription vmstate_target_page_bits = { diff --git a/page-target.c b/page-target.c index 321e43d06f..8fcd5443b5 100644 --- a/page-target.c +++ b/page-target.c @@ -9,11 +9,6 @@ #include "qemu/osdep.h" #include "exec/target_page.h" -int qemu_target_page_bits_min(void) -{ - return TARGET_PAGE_BITS_MIN; -} - /* Convert target pages to MiB (2**20). */ size_t qemu_target_pages_to_MiB(size_t pages) { diff --git a/page-vary-target.c b/page-vary-target.c index 84ddeb7c26..6251d948cf 100644 --- a/page-vary-target.c +++ b/page-vary-target.c @@ -23,6 +23,15 @@ #include "exec/page-vary.h" #include "exec/target_page.h" +int migration_legacy_page_bits(void) +{ +#ifdef TARGET_PAGE_BITS_VARY + return TARGET_PAGE_BITS_MIN; +#else + return TARGET_PAGE_BITS; +#endif +} + bool set_preferred_target_page_bits(int bits) { #ifdef TARGET_PAGE_BITS_VARY From patchwork Fri Mar 28 20:04:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 876731 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp737140wrs; Fri, 28 Mar 2025 13:05:55 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWRCbfGRQOOzaUQMbwdt63mvZvJ89Ro3/9FpSpmaYfk0Ib8p3bxdodxq8MFrNeg7hznjhsA4w==@linaro.org X-Google-Smtp-Source: AGHT+IHBjPKCYB3ksq0ukMCngYv0LRdQE9fWzM73mADJBE+iZH1kGQyOf5D44/eRxJg5rRKSdLwP X-Received: by 2002:a05:6214:e62:b0:6e8:f8ef:d659 with SMTP id 6a1803df08f44-6eed5fb42admr8085916d6.10.1743192355277; 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[71.42.197.3]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3ff052799b6sm465104b6e.37.2025.03.28.13.05.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 13:05:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH 9/9] page-vary: Restrict scope of TARGET_PAGE_BITS_MIN Date: Fri, 28 Mar 2025 15:04:59 -0500 Message-ID: <20250328200459.483089-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250328200459.483089-1-richard.henderson@linaro.org> References: <20250328200459.483089-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The only place we really need to know the minimum is within page-vary-target.c. Rename the target/arm TARGET_PAGE_BITS_MIN to TARGE_PAGE_BITS_LEGACY to emphasize what it really means. Move the assertions related to minimum page size as well. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/exec/cpu-defs.h | 10 ++-------- include/exec/poison.h | 1 + include/exec/target_page.h | 1 - include/qemu/osdep.h | 6 ++++++ target/alpha/cpu-param.h | 1 - target/arm/cpu-param.h | 3 +-- target/ppc/cpu-param.h | 1 - accel/tcg/cputlb.c | 1 - page-vary-target.c | 39 +++++++++++++++++++++++++++++++++++--- 9 files changed, 46 insertions(+), 17 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 9f955f53fd..e01acb7c90 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -34,14 +34,8 @@ #ifndef TARGET_VIRT_ADDR_SPACE_BITS # error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h #endif -#ifndef TARGET_PAGE_BITS -# ifdef TARGET_PAGE_BITS_VARY -# ifndef TARGET_PAGE_BITS_MIN -# error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h -# endif -# else -# error TARGET_PAGE_BITS must be defined in cpu-param.h -# endif +#if !defined(TARGET_PAGE_BITS) && !defined(TARGET_PAGE_BITS_VARY) +# error TARGET_PAGE_BITS must be defined in cpu-param.h #endif #include "exec/target_long.h" diff --git a/include/exec/poison.h b/include/exec/poison.h index 4180a5a489..c4f7ee22bf 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -44,6 +44,7 @@ #pragma GCC poison TARGET_FMT_lu #pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS +#pragma GCC poison TARGET_PAGE_BITS_LEGACY #pragma GCC poison CONFIG_ALPHA_DIS #pragma GCC poison CONFIG_HPPA_DIS diff --git a/include/exec/target_page.h b/include/exec/target_page.h index e4bd7f7767..ca0ebbc8bb 100644 --- a/include/exec/target_page.h +++ b/include/exec/target_page.h @@ -41,7 +41,6 @@ extern const TargetPageBits target_page; # endif # define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) #else -# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS # define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) # define TARGET_PAGE_MASK ((TARGET_PAGE_TYPE)-1 << TARGET_PAGE_BITS) #endif diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 4397a90680..321a52d7f0 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -50,6 +50,12 @@ */ #pragma GCC poison TARGET_WORDS_BIGENDIAN +/* + * TARGET_PAGE_BITS_MIN was repaced by TARGET_PAGE_BITS_LEGACY + * for system mode. Prevent it from creeping back in. + */ +#pragma GCC poison TARGET_PAGE_BITS_MIN + #include "qemu/compiler.h" /* Older versions of C++ don't get definitions of various macros from diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index ff06e41497..63989e71c0 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -18,7 +18,6 @@ * a 4k minimum to match x86 host, which can minimize emulation issues. */ # define TARGET_PAGE_BITS_VARY -# define TARGET_PAGE_BITS_MIN 12 # define TARGET_VIRT_ADDR_SPACE_BITS 63 #else # define TARGET_PAGE_BITS 13 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 896b35bd6d..a7ae42d17d 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -24,7 +24,6 @@ # else /* Allow user-only to vary page size from 4k */ # define TARGET_PAGE_BITS_VARY -# define TARGET_PAGE_BITS_MIN 12 # endif # else # define TARGET_PAGE_BITS 12 @@ -35,7 +34,7 @@ * have to support 1K tiny pages. */ # define TARGET_PAGE_BITS_VARY -# define TARGET_PAGE_BITS_MIN 10 +# define TARGET_PAGE_BITS_LEGACY 10 #endif /* !CONFIG_USER_ONLY */ /* ARM processors have a weak memory model */ diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index 6c4525fdf3..553ad2f4c6 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -33,7 +33,6 @@ #ifdef CONFIG_USER_ONLY /* Allow user-only to vary page size from 4k */ # define TARGET_PAGE_BITS_VARY -# define TARGET_PAGE_BITS_MIN 12 #else # define TARGET_PAGE_BITS 12 #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 39314e86f3..0de46903dd 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -49,7 +49,6 @@ #endif #include "tcg/tcg-ldst.h" -QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & ((1u < TARGET_PAGE_BITS_MIN) - 1)); /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ diff --git a/page-vary-target.c b/page-vary-target.c index 6251d948cf..d83f9a6a90 100644 --- a/page-vary-target.c +++ b/page-vary-target.c @@ -23,19 +23,45 @@ #include "exec/page-vary.h" #include "exec/target_page.h" + +/* + * For system mode, the minimum comes from the number of bits + * required for maximum alignment (6) and the number of bits + * required for TLB_FLAGS_MASK (3). + * + * For user mode, TARGET_PAGE_BITS_VARY is a hack to allow the target + * page size to match the host page size. Mostly, this reduces the + * ordinary target page size to run on a host with 4KiB pages (i.e. x86). + * There is no true minimum required by the implementation, but keep the + * same minimum as for system mode for sanity. + * See linux-user/mmap.c, mmap_h_lt_g and mmap_h_gt_g. + */ +#define TARGET_PAGE_BITS__MIN 9 + +#ifndef TARGET_PAGE_BITS_VARY +QEMU_BUILD_BUG_ON(TARGET_PAGE_BITS < TARGET_PAGE_BITS__MIN); +#endif + +#ifndef CONFIG_USER_ONLY +#include "exec/tlb-flags.h" + +QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & ((1u < TARGET_PAGE_BITS__MIN) - 1)); + int migration_legacy_page_bits(void) { #ifdef TARGET_PAGE_BITS_VARY - return TARGET_PAGE_BITS_MIN; + QEMU_BUILD_BUG_ON(TARGET_PAGE_BITS_LEGACY < TARGET_PAGE_BITS__MIN); + return TARGET_PAGE_BITS_LEGACY; #else return TARGET_PAGE_BITS; #endif } +#endif bool set_preferred_target_page_bits(int bits) { + assert(bits >= TARGET_PAGE_BITS__MIN); #ifdef TARGET_PAGE_BITS_VARY - assert(bits >= TARGET_PAGE_BITS_MIN); return set_preferred_target_page_bits_common(bits); #else return true; @@ -44,5 +70,12 @@ bool set_preferred_target_page_bits(int bits) void finalize_target_page_bits(void) { - finalize_target_page_bits_common(TARGET_PAGE_BITS_MIN); +#ifndef TARGET_PAGE_BITS_VARY + finalize_target_page_bits_common(TARGET_PAGE_BITS); +#elif defined(CONFIG_USER_ONLY) + assert(target_page.bits != 0); + finalize_target_page_bits_common(target_page.bits); +#else + finalize_target_page_bits_common(TARGET_PAGE_BITS_LEGACY); +#endif }