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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9b3c2csm13776977f8f.46.2025.03.25.08.41.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 25 Mar 2025 08:41:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Pierrick Bouvier , Zhao Liu , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson , Richard Henderson Subject: [PATCH-for-10.1 1/8] cpus: Open code OBJECT_DECLARE_TYPE() in OBJECT_DECLARE_CPU_TYPE() Date: Tue, 25 Mar 2025 16:40:51 +0100 Message-ID: <20250325154058.92735-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250325154058.92735-1-philmd@linaro.org> References: <20250325154058.92735-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since the OBJECT_DECLARE_CPU_TYPE() macro uses the abstract ArchCPU type, when declaring multiple CPUs of the same ArchCPU type we get an error related to the indirect G_DEFINE_AUTOPTR_CLEANUP_FUNC() use within OBJECT_DECLARE_TYPE(): target/mips/cpu-qom.h:31:1: error: redefinition of 'glib_autoptr_clear_ArchCPU' OBJECT_DECLARE_CPU_TYPE(MIPS64CPU, MIPSCPUClass, MIPS64_CPU) ^ include/hw/core/cpu.h:82:5: note: expanded from macro 'OBJECT_DECLARE_CPU_TYPE' OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME); ^ include/qom/object.h:237:5: note: expanded from macro 'OBJECT_DECLARE_TYPE' G_DEFINE_AUTOPTR_CLEANUP_FUNC(InstanceType, object_unref) \ ^ /usr/include/glib-2.0/glib/gmacros.h:1371:3: note: expanded from macro 'G_DEFINE_AUTOPTR_CLEANUP_FUNC' _GLIB_DEFINE_AUTOPTR_CLEANUP_FUNCS(TypeName, TypeName, func) ^ /usr/include/glib-2.0/glib/gmacros.h:1354:36: note: expanded from macro '_GLIB_DEFINE_AUTOPTR_CLEANUP_FUNCS' static G_GNUC_UNUSED inline void _GLIB_AUTOPTR_CLEAR_FUNC_NAME(TypeName) (TypeName *_ptr) \ ^ /usr/include/glib-2.0/glib/gmacros.h:1338:49: note: expanded from macro '_GLIB_AUTOPTR_CLEAR_FUNC_NAME' #define _GLIB_AUTOPTR_CLEAR_FUNC_NAME(TypeName) glib_autoptr_clear_##TypeName ^ :54:1: note: expanded from here glib_autoptr_clear_ArchCPU ^ target/mips/cpu-qom.h:30:1: note: previous definition is here OBJECT_DECLARE_CPU_TYPE(MIPS32CPU, MIPSCPUClass, MIPS32_CPU) ^ Avoid that problem by expanding the OBJECT_DECLARE_TYPE() macro within OBJECT_DECLARE_CPU_TYPE(). Signed-off-by: Philippe Mathieu-Daudé Acked-by: Richard Henderson --- include/hw/core/cpu.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5d11d26556a..01e03f267cc 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -82,7 +82,12 @@ DECLARE_CLASS_CHECKERS(CPUClass, CPU, */ #define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \ typedef struct ArchCPU CpuInstanceType; \ - OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME); + typedef struct CpuClassType CpuClassType; \ + \ + G_DEFINE_AUTOPTR_CLEANUP_FUNC(CpuInstanceType, object_unref) \ + \ + DECLARE_OBJ_CHECKERS(CpuInstanceType, CpuClassType, \ + CPU_MODULE_OBJ_NAME, TYPE_##CPU_MODULE_OBJ_NAME) typedef struct CPUWatchpoint CPUWatchpoint; From patchwork Tue Mar 25 15:40:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 876009 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp2725229wrb; Tue, 25 Mar 2025 08:41:56 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXaRkdK/bQ1RoEM8yGLGDZeeZ/SwYBLkqwiWjna4BoXHXkR3trQM9cX7ZMBehJFmoKp9raVmg==@linaro.org X-Google-Smtp-Source: AGHT+IHaP1fI6AmVZzbCo4XrNG7nBx1yn4HbdrmPpJ4eaFeWH5BTxfRz5YROjtMx+e2rZmy3ylzM X-Received: by 2002:a05:622a:2489:b0:476:af54:5038 with SMTP id d75a77b69052e-4771ddaafa7mr247355471cf.22.1742917316138; Tue, 25 Mar 2025 08:41:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742917316; cv=none; d=google.com; s=arc-20240605; b=S1z7Teg3SeBLarrdobRxSBqquC/TB5grTfCcSsWntxMqlQBp1q8WVp0PXKmjwwwGwL adK6HZUut3UI9V3lyt0UYXdrSUPE0ZWBS8gqFJuv0sd/1bREziCWKZf70AOxPjRTelhb APrUUDi7x5xl0oUa29YgAJawcI9nz4tdJzuCD4yBwMxdTf8kEqCsDIj9RrC9nn3Z2bxG HUYyuCDcgVN6xbfTI/tKLNOZ5Lb2PnRmzpK6OeJS2ZeiVSBuH6uP23EQjJ8popL2XrwB DQkv9WKRypxMGcCiY9Cv12QWqdYqbKl/Cbt0MLhWJqXjpOxHGA6Wj6LJhJzDhnu+oSIt NtjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=B9EcvePMMiziHxvQ+1Uv0hWd3cavq64til709QLPVTs=; fh=K2SYTwc7Og3VuqX/TveJuCvsY6BHxWLBhQWLYUw+e9A=; b=kuKSuDqmNnUCk3dHx5aAwSqcgt+KbUKbFEnPfuAf8hLKPIQXuMP+jhAdQ8XB0GTCQr aYocB5v2p7vvTpv5AKny5EwqZVpwBvEaMjwRj/l+1QhemH+lCcGslv1Yx/Sp9/5x/hbn hW+878sPUPNxuDNkD2Y8+cAYRu1rcm2RASUMAq55ilJbIA5pAWMXv46jv4YUiEiavX5M yVA2/1cOqH2VYWoycZ+kOaW5/VQ2/EbsaIw56FTdVEBqQ8T92nrVOb7qdOjog7oqa+hD If6/0OYQMW7oc8z/i2xctpbljz2+QEOTHhvTyRFmjQyFmsu3+FdO5kmBJX5W+nsaw/BC FnZA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Gt4d5Zxd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9955c0sm13861946f8f.3.2025.03.25.08.41.09 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 25 Mar 2025 08:41:09 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Pierrick Bouvier , Zhao Liu , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson , Richard Henderson Subject: [PATCH-for-10.1 2/8] target/mips: Declare CPU QOM types using DEFINE_TYPES() macro Date: Tue, 25 Mar 2025 16:40:52 +0100 Message-ID: <20250325154058.92735-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250325154058.92735-1-philmd@linaro.org> References: <20250325154058.92735-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array declared with such macro are easier to review. In few commits we are going to add more types, so replace the type_register_static() to ease further reviews. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/mips/cpu.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index b207106dd79..097554fd8ae 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -597,17 +597,21 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) #endif /* CONFIG_TCG */ } -static const TypeInfo mips_cpu_type_info = { - .name = TYPE_MIPS_CPU, - .parent = TYPE_CPU, - .instance_size = sizeof(MIPSCPU), - .instance_align = __alignof(MIPSCPU), - .instance_init = mips_cpu_initfn, - .abstract = true, - .class_size = sizeof(MIPSCPUClass), - .class_init = mips_cpu_class_init, +static const TypeInfo mips_cpu_types[] = { + { + .name = TYPE_MIPS_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(MIPSCPU), + .instance_align = __alignof(MIPSCPU), + .instance_init = mips_cpu_initfn, + .abstract = true, + .class_size = sizeof(MIPSCPUClass), + .class_init = mips_cpu_class_init, + } }; +DEFINE_TYPES(mips_cpu_types) + static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data) { MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc); @@ -632,7 +636,6 @@ static void mips_cpu_register_types(void) { int i; - type_register_static(&mips_cpu_type_info); for (i = 0; i < mips_defs_number; i++) { mips_register_cpudef_type(&mips_defs[i]); } From patchwork Tue Mar 25 15:40:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 876011 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp2725248wrb; Tue, 25 Mar 2025 08:41:57 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUV1ESHZw780rvZ9G7O4brmknmBVJTrtIyvQY9zfVeJCo2jL8XgUC5iRpnVT7s9KV70kwv2uw==@linaro.org X-Google-Smtp-Source: AGHT+IFRQjNH5kPG7Fzr/SjPx4UhcQL0oXlHZo8B2rZjItFZgS9FDJvr0u1B3FGyT7v8CA5DC0QT X-Received: by 2002:a05:622a:1249:b0:476:8a1d:f18e with SMTP id d75a77b69052e-4771de48948mr274085831cf.36.1742917317010; Tue, 25 Mar 2025 08:41:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742917316; cv=none; d=google.com; s=arc-20240605; b=X2SUvE1giuqbkBxJIsRfw/VssNKHQ5t6y0ikTHmiNdvjf/TMNifS2qTnxAF3GTx22q Rirgq4syZxB3UZVu9MjfNalKeIA8s/1ZtoEe8b+FXIIX3McErTO5RMk2bY9PZHI/2a6n gqlxxgdY7lF6RUTEcek8CpZ2DPcrS3X2usiSr7lEkJ7UiRye693jxlA1+9JXOx9qanmk Zm2kZPcdsLWArwJzkGGRR0QiweVNeBLdl3HZJ3GFfvZXZ+C6quNVsszW3yrCr3HRxJpB TBR196rmHd447HW5HTJ2yrumm2WWbXSxC7B9RZfmWgWhA974vwU1Gjx1hxSJmPahcTfu G0pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mMYSIVb6yc31rz11SHW4h4aNXQhfD5IK5ryBRxbffZQ=; fh=rsGnRer8RsnMMmJ84TrqvBI0/yOANo3p2sBxrPWKp1M=; b=OR8ymI7hqOnvNImRYtXMbnsFZt4mx3Z9MB+yE0mwo3ou1BI1IE7xynA8KOZNQTKUpC XBmanqra+XvMyttfT4tTH/rP4N/oSvtLpOCAOEuIPJbGBVpucKtNhUP7+lt7+4450dv0 3n/YmK4uswAXCi0dlvzL0ECS0DrHTzJQw93WBagUY49vp+b3NQcBRuxnCQbBJ89E4bj4 zirFJ2d6nvR5s0D7fxAojs5bDP8nYz/APOaMikGynomrRLDtwLh6fSsG79jDQtCSB0ZA 1d7VaoGxtt9rck2D7LcLHSE9JQtkcRpHd5tTwGf3uajrskCMTKw6GT9RR5k/kJ//eT8L MCoQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p+j1ZCDe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d6eab9d0fsm16161625e9.1.2025.03.25.08.41.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 25 Mar 2025 08:41:14 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Pierrick Bouvier , Zhao Liu , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson Subject: [PATCH-for-10.1 3/8] target/mips: Make MIPS_CPU common to new MIPS32_CPU / MIPS64_CPU types Date: Tue, 25 Mar 2025 16:40:53 +0100 Message-ID: <20250325154058.92735-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250325154058.92735-1-philmd@linaro.org> References: <20250325154058.92735-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu-qom.h" can not use any target specific definitions. Currently "target/mips/cpu-qom.h" defines TYPE_MIPS_CPU depending on the mips(32)/mips64 build type. This doesn't scale in a heterogeneous context where we need to access both types concurrently. In order to do that, introduce the new MIPS32_CPU / MIPS64_CPU types, both inheriting a common TYPE_MIPS_CPU base type. Keep the current CPU types registered in mips_register_cpudef_type() as 32 or 64-bit, but instead of depending on the binary built being targeting 32/64-bit, check whether the CPU is 64-bit by looking at the CPU_MIPS64 bit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/mips/cpu-qom.h | 12 ++++++------ target/mips/cpu.c | 11 ++++++++++- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 0eea2a2598e..9acf647420c 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU MIPS CPU + * QEMU MIPS CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -22,12 +22,12 @@ #include "hw/core/cpu.h" -#ifdef TARGET_MIPS64 -#define TYPE_MIPS_CPU "mips64-cpu" -#else -#define TYPE_MIPS_CPU "mips-cpu" -#endif +#define TYPE_MIPS32_CPU "mips32-cpu" +#define TYPE_MIPS64_CPU "mips64-cpu" +#define TYPE_MIPS_CPU "mips-cpu" +OBJECT_DECLARE_CPU_TYPE(MIPS32CPU, MIPSCPUClass, MIPS32_CPU) +OBJECT_DECLARE_CPU_TYPE(MIPS64CPU, MIPSCPUClass, MIPS64_CPU) OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 097554fd8ae..5ed6b3402d3 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -607,6 +607,14 @@ static const TypeInfo mips_cpu_types[] = { .abstract = true, .class_size = sizeof(MIPSCPUClass), .class_init = mips_cpu_class_init, + }, { + .name = TYPE_MIPS32_CPU, + .parent = TYPE_MIPS_CPU, + .abstract = true, + }, { + .name = TYPE_MIPS64_CPU, + .parent = TYPE_MIPS_CPU, + .abstract = true, } }; @@ -623,7 +631,8 @@ static void mips_register_cpudef_type(const struct mips_def_t *def) char *typename = mips_cpu_type_name(def->name); TypeInfo ti = { .name = typename, - .parent = TYPE_MIPS_CPU, + .parent = def->insn_flags & CPU_MIPS64 + ? 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9ef098sm13767225f8f.84.2025.03.25.08.41.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 25 Mar 2025 08:41:19 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Pierrick Bouvier , Zhao Liu , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson Subject: [PATCH-for-10.1 4/8] target/mips: Prefix MMU API with 'mips_' Date: Tue, 25 Mar 2025 16:40:54 +0100 Message-ID: <20250325154058.92735-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250325154058.92735-1-philmd@linaro.org> References: <20250325154058.92735-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org MIPS MMU API declared in tcg-internal.h has public linkage. In order to avoid name clashing with other targets, prefix the API with 'mips_'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/mips/tcg/tcg-internal.h | 2 +- target/mips/cpu.c | 2 +- target/mips/tcg/system/tlb_helper.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 74fc1309a71..a8bf2a5da40 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -45,7 +45,7 @@ void do_raise_exception(CPUMIPSState *env, void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); -void mmu_init(CPUMIPSState *env, const mips_def_t *def); +void mips_mmu_init(CPUMIPSState *env, const mips_def_t *def); void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 5ed6b3402d3..d8930468b7d 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -485,7 +485,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) env->exception_base = (int32_t)0xBFC00000; #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - mmu_init(env, env->cpu_model); + mips_mmu_init(env, env->cpu_model); #endif fpu_init(env, env->cpu_model); mvp_init(env); diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/tlb_helper.c index ca4d6b27bc9..1ef2c32cfd4 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -466,7 +466,7 @@ static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) env->tlb->helper_tlbinvf = r4k_helper_tlbinvf; } -void mmu_init(CPUMIPSState *env, const mips_def_t *def) +void mips_mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); From patchwork Tue Mar 25 15:40:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 876012 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp2725364wrb; Tue, 25 Mar 2025 08:42:13 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVYmODkg1ZgeNUr5ymCoVngAicVJgetumOoK+tnHS4JBJDIyHR61fzI2c1HnuvWUzjmJCNXQw==@linaro.org X-Google-Smtp-Source: AGHT+IHSEvv+RQ41ES3G4kjGHK4nFHFEN8H8O8rj6FN0CA+6417R8xH2Vu+uSymvuPVINzvgMspe X-Received: by 2002:a05:622a:1f19:b0:476:add4:d2a9 with SMTP id d75a77b69052e-4771ddbf815mr270339081cf.30.1742917333200; Tue, 25 Mar 2025 08:42:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742917333; cv=none; d=google.com; s=arc-20240605; b=GP9XPaLiAL0zWfMGYIiWrup+0A1cF81HnWf/VIx2HOkvPeWDIIPWGtMNKRI7Sm0758 /m8SO+mOwT0/yIAxyjVfBzksPXGqRYANb9/JX2vhobWes2e12YwyxuuObyfQkfjv5Vp/ zRz7HMbsd/0txhEJ282RB1aTM1Xs27TNZF4nW52ecoZG4aGEF0DAKkYx9GmPJkktiCNJ WNxzMNll3C37Gx2+0XLypwfpkXxI03O6CrPf4gJdYBVLe16TSZKeSGGnLMJh5sbTCHwN CHrr0LgI2pTJAkCYCPKImrN5o7G4zfkN1Un6ecuLPCqYOSpft7H4DTunIaFJJHpaWM+Y wVgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PPypTK7DZGi7uNZ8Ij2igQ+CirZnbkfROskeOnb68NU=; fh=rsGnRer8RsnMMmJ84TrqvBI0/yOANo3p2sBxrPWKp1M=; b=F57q8CZ4hcRKPZc0hyKR5t9Ht+ShRrRxcqkOPtegRC5o8s822f1ve0ZBeAcc5RQ79p xnPRJpEbzoEXINft1wMeJbte7SxtUhtiE/iX1TiQIbfE5CyunTVkdYOx9r8QIZiz+RP/ Ft1OvsydOJ2X1AP60MeIla9jKUgMpCrZDFipHdO2oLdfAGsEdQsjJEbH55xAdkVECdPt cTbqjtjsnQ8B6Nr+/b4iyOAK5Xfdt2mg5D9dS/idq8WfuMS4iYIz6zqZz2nXYDJgCVhW 7ZIRn7S1II8Za2SnPri88MyUE67upJOa0AZsUVxoL8YwOq2SKuJlHIAdHxYC6DL8lC0/ fAUw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S+ORs9rg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9b5536sm14446174f8f.54.2025.03.25.08.41.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 25 Mar 2025 08:41:24 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Pierrick Bouvier , Zhao Liu , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson Subject: [PATCH-for-10.1 5/8] target/mips: Replace ldtul_p() -> ldn_p(sizeof(target_ulong)) Date: Tue, 25 Mar 2025 16:40:55 +0100 Message-ID: <20250325154058.92735-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250325154058.92735-1-philmd@linaro.org> References: <20250325154058.92735-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the single ldtul_p() call by a generic ldn_p() one. No logical change. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/mips/gdbstub.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index 169d47416a6..b9fc667373e 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -79,12 +79,13 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { CPUMIPSState *env = cpu_env(cs); target_ulong tmp; + size_t regsize = sizeof(tmp); - tmp = ldtul_p(mem_buf); + tmp = ldn_p(mem_buf, regsize); if (n < 32) { env->active_tc.gpr[n] = tmp; - return sizeof(target_ulong); + return regsize; } if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) { switch (n) { @@ -104,7 +105,7 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } break; } - return sizeof(target_ulong); + return regsize; } switch (n) { case 32: @@ -144,5 +145,5 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) break; } - return sizeof(target_ulong); + return regsize; } From patchwork Tue Mar 25 15:40:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 876010 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp2725233wrb; Tue, 25 Mar 2025 08:41:56 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVH/zhxK+ZHDbcfsc7zlG2p8/FoSB/Mywc1W+fr8KlQkiuVozREzWbOHbyY4gFtOs3XrkpEcw==@linaro.org X-Google-Smtp-Source: AGHT+IHlM0rH8qXWXgb3Z/zXiROGo/yLZMA/2ulYI1NczyfETtdWnD9UkFwR7VziuPEZguXi5YU7 X-Received: by 2002:a05:620a:c54:b0:7ac:b95b:7107 with SMTP id af79cd13be357-7c5e48ddf03mr36289385a.12.1742917316193; Tue, 25 Mar 2025 08:41:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742917316; cv=none; d=google.com; s=arc-20240605; b=CEAhb0VXi4mtJJqoFl0wx/IY9sryZeGzBgR32Mn9zPTvMo0fs3qZAVLkswPG6zAyD2 RAqTQs3ahYHjB7v3x4Yq4VUgjQ0dCdRXPp/xmlfN68joUKSMBuu26anJdZ4Da4E3gblj q5DpSArwVbAetA8RBLqjNUGAS6QRWRRvh1eVlGbi3xrxkMzAq7i8qtYkpL79vkhc5Gcv Shc9zDxzWQ6Wau9DXJCxAux6ECocehr9EAaF8GOiwksDnMFJCDil5NNAfN/aY2WWMSuh QLo5Xj9I5UJwkm+uccmvb20KnXRQZ3w3aRv2/tJssKE9Hk2pMlElZSpb0r8tfGdLzl8k x1Tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=lbsjfiae9VyxIEcsSbXzqvelTNR2Rg0DAwfeG/N1/LM=; fh=rsGnRer8RsnMMmJ84TrqvBI0/yOANo3p2sBxrPWKp1M=; b=j5sGSrzost770m9EGfF9Nt1iTWQt59jNohDLq5p5ODTwVdXooRtZStMo1RrF1acEBB vmuuAJ+76gZxYU0eMJL4JU7FMtPavfXT3RgZaBE5C3ZyBwML8Osm5vvyA6I0bfaCQxkg F9FBNCeH0guf247B1dSmlYfRD2XGdbFq/vzqftFZjR9soldVtDNAR5J4es3sjMMd/HFR LW/kEMu+fVo0N5U7y30kz58gk4ti/hRK+aPYfAlLXpnUmfj+Bhk+/rJ+Ew4sHf1Wq2sC lRacDnW/ou5fS2nlcAljMWXOe53hUeTilhni/agT4ulJ8ntcjiitKJELmutM4Sz3x+FY UjFQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uv0ogjUG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9b4ce9sm14213513f8f.53.2025.03.25.08.41.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 25 Mar 2025 08:41:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Pierrick Bouvier , Zhao Liu , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson Subject: [PATCH-for-10.1 6/8] target/mips: Introduce mips_cpu_is_64bit() helper Date: Tue, 25 Mar 2025 16:40:56 +0100 Message-ID: <20250325154058.92735-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250325154058.92735-1-philmd@linaro.org> References: <20250325154058.92735-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org mips_cpu_is_64bit() returns whether the CPU is a 32-bit or a 64-bit one. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/mips/cpu-qom.h | 2 ++ target/mips/cpu.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 9acf647420c..52996e7c354 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -33,4 +33,6 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX +bool mips_cpu_is_64bit(MIPSCPU *cpu); + #endif diff --git a/target/mips/cpu.c b/target/mips/cpu.c index d8930468b7d..05b3ce42af5 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -516,6 +516,12 @@ static void mips_cpu_initfn(Object *obj) #endif } +bool mips_cpu_is_64bit(MIPSCPU *cpu) +{ + return !!object_class_dynamic_cast(OBJECT_CLASS(CPU(cpu)->cc), + TYPE_MIPS64_CPU); +} + static char *mips_cpu_type_name(const char *cpu_model) { return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model); From patchwork Tue Mar 25 15:40:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 876013 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp2725533wrb; Tue, 25 Mar 2025 08:42:34 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXfO+hZL3g43dmv/HYpHC1Anm6XgFTckiCXWCnVFVjcNlBZahm/d8Jp4t55Jko+j4siRcYaiw==@linaro.org X-Google-Smtp-Source: AGHT+IHfmVkgjLsUPFMaB44FHg1KmpZykQ/JbMJwoseXiALrdwhS2TkszQV30ZAWlbjtUDD44KeX X-Received: by 2002:a05:620a:1790:b0:7c5:3efe:2440 with SMTP id af79cd13be357-7c5ba175485mr2803830785a.25.1742917353876; Tue, 25 Mar 2025 08:42:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742917353; cv=none; d=google.com; s=arc-20240605; b=Xz1n6L3vcHRoARaBQ5PLSLaYQatcAoIQNIF6Djc/9+CFyae0clTRax/F2Pu4E+m/4e gK9ILphp63E7ceGjJALhYqPk75BwEHNR07FevtEGlrkX3tuQ/G6WfsoDByf3OGs7on59 vdRohkZNRQ38o53WJY0/ntmKyuPTxuVtuDoc9ihUFtp1SgF7wao4jBxo1jVgQJiCHHK/ UJAA3sh3BiovTEYzZdQH2z7bIPhnn1h4FeCjURP8P4vjznBapkfIuuSndI+yFk41+CKn rft7ksn0MBcb4alqLKolDAytOpiNIQUdw/a7j/2cmMEaToVaA/s9fi7dBR+RPkqmUXc0 S4Tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=43G6xaQEasg9QNPZtMYOEGymQHF1cxnYCa0rqpPVw3M=; fh=rsGnRer8RsnMMmJ84TrqvBI0/yOANo3p2sBxrPWKp1M=; b=eZ2KZATmBB+9eC+v2b/tZaJ+ELHe/hZ1aHJwhgrWlDHaPPvcusuQQZc14XLWFzgV9M eAcmiQv8bhrZsuZP3m/vbF8PyrsCQUpogcjUmINJhUHu+VBIorAF4/0JvotqKuru6v8C wwK4b0NzWuf4VLaUnJ6WG9c6q4O/BQH/kh3FXEuQtyyF4KZ1ZR0yipYmreW/5OPcdCBW KC4Qt0JjmO/qfFbCsXSGqwwX6RKgbpglB1t8mL5S4tZaN3A0otHDnTiY9GQD/Jze3Gv4 Cn+k/jP9pwahg+tlXSoEpVQxj0ZnvoxxCDuagFTQuHefn5PjXRvwWRmDQndVhpOXQm+r p0Aw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PCWXh4de; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9efc9bsm13813579f8f.87.2025.03.25.08.41.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 25 Mar 2025 08:41:33 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Pierrick Bouvier , Zhao Liu , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson Subject: [PATCH-for-10.1 7/8] target/mips: Get CPU register size using mips_cpu_is_64bit() Date: Tue, 25 Mar 2025 16:40:57 +0100 Message-ID: <20250325154058.92735-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250325154058.92735-1-philmd@linaro.org> References: <20250325154058.92735-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPU registers size is static and depends on the type of CPU. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/mips/gdbstub.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index b9fc667373e..84fd3de4137 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -75,11 +75,16 @@ int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) return 0; } +static size_t mips_regsize(MIPSCPU *cpu) +{ + return mips_cpu_is_64bit(cpu) ? sizeof(uint64_t) : sizeof(uint32_t); +} + int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { CPUMIPSState *env = cpu_env(cs); target_ulong tmp; - size_t regsize = sizeof(tmp); + size_t regsize = mips_regsize(MIPS_CPU(cs)); tmp = ldn_p(mem_buf, regsize); From patchwork Tue Mar 25 15:40:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 876015 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp2725658wrb; Tue, 25 Mar 2025 08:42:47 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVp/aFdedjNaKa58M9Saz9y0912MS4N9pSR1DuJxZBaM0vGibvgVKhVBAdAgHGsUhqFEmg3iQ==@linaro.org X-Google-Smtp-Source: AGHT+IHoQ5H55PGquzVTSLwc5prdMrAMPn18uJ7UXdQNOzJ6WyyFVOXSFhJl2LkhyRBP0FVoQcj8 X-Received: by 2002:a05:622a:1144:b0:476:fd69:ccb with SMTP id d75a77b69052e-4771dd93d43mr315336811cf.27.1742917367248; Tue, 25 Mar 2025 08:42:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742917367; cv=none; d=google.com; s=arc-20240605; b=B3DRYNuF6NAK/d+KNeIkWX2TyeeHbhiUIxxe05YjNKlFNgjgnh7LQ2yStgv2Mp0l05 S8qAy4WTD+TfGzL08kRBJPAk9NkmnCodxB+YOFegYS3tmAru+XyJmb/bPMXhR6vi/tOE Q8VQp8Bvckm1my/D5yN+/F4+LynGMCGAddtDglwg6GqleQMKiS2Nvnu+3TkOip6T3XvX 3TQfOl4hDe7gAYwL2iLMTb/uBXUuxiC04h+xb7mtAztzzNU4wwhXsCgx8WHBtzTfM/BQ 8axMYBpbHBdg2GQrVVy8DgAkSpxKyPgRbhvYGL0AoB6X2Yd1fTbvPwrqIzrtJLPetl0B 2kDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Ov0qeNX9YGL0oYdATS3IENK9eMXw/drt5nInE25Olt4=; fh=rsGnRer8RsnMMmJ84TrqvBI0/yOANo3p2sBxrPWKp1M=; b=GQw3Dfu0PfM+j6WtsCunu3aGGPlj4Ax5f1dEFpZQdrrOfZuaD0uurLrfToSUuPFly3 AzYxxPXLwLaZhPyKgFZZ9tKhJ6RHVrTAo1iubvclYFyQTtJVjJZYWTu1VPUuvBfU5kUI PthVeNOFNq565i5TQUFCZQxPRo5zhHpjoLoWQGDNkFTKBI+c0rxpoMMuiBoQzkLZ1onH UB/9qsDswqQu38SltL7QsEW629C/RKfw5Lxucpn+eOaOTJAEZ3bpi9roOdf8C91PCtQ6 uXRR2TvDBqsAJYLM4b7XcKHNCQ8O/5i2HlB/sBrolNCRRp/Ap9GtGDV0ngCpNbCmzkEp Xyfg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=c7age1ug; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d43f556basm203127755e9.17.2025.03.25.08.41.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 25 Mar 2025 08:41:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Pierrick Bouvier , Zhao Liu , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson Subject: [PATCH-for-10.1 8/8] target/mips: Introduce mips_env_64bit_enabled() helper Date: Tue, 25 Mar 2025 16:40:58 +0100 Message-ID: <20250325154058.92735-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250325154058.92735-1-philmd@linaro.org> References: <20250325154058.92735-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org mips_env_64bit_enabled() returns whether the CPU is running in 32-bit or 64-bit (behavior which might change at runtime). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/mips/internal.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/mips/internal.h b/target/mips/internal.h index 28eb28936ba..8107a59b908 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -225,6 +225,11 @@ static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) } } +static inline bool mips_env_64bit_enabled(CPUMIPSState *env) +{ + return env->hflags & MIPS_HFLAG_64; +} + static inline bool mips_env_is_bigendian(CPUMIPSState *env) { return extract32(env->CP0_Config0, CP0C0_BE, 1);