From patchwork Tue Mar 25 06:50:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 875985 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp2503645wrb; Mon, 24 Mar 2025 23:52:11 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU1cZ4QCVyyXOqaMHcTin7KDziWKT8vA9B0C/xdyWZcVA4a40urlA4tHCfy2sWuypJnKcKYtw==@linaro.org X-Google-Smtp-Source: AGHT+IFfLwR5LI0hhtyWEk495POSDZMi38grlJehInhedhuLo78BdIP0RHvD84ldY7X9RBlblgnK X-Received: by 2002:a05:6214:76e:b0:6d8:a39e:32a4 with SMTP id 6a1803df08f44-6eb3f2e6d86mr241235556d6.25.1742885530998; Mon, 24 Mar 2025 23:52:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742885530; cv=none; d=google.com; s=arc-20240605; b=VVqFnUT2ZMICwtbdUZ5C7ocY4tyQjjDayBo5Y1kY2H37INeDJoDFC+lJeS2lRTSKcm hl0+XcL95FDsHNyI0mE8wUkE3TAXke5taeLMWq0pf0ChtnR0qc36Q7ITmiQj8OHvCg+w Kvn48E08PlOc0DYWpCB5YnqBT/Cx/MAohUbl6Q4k3GD+aRskPVTi1FQ1bxRlMOjJEFlZ r2yhkw9IHZYj+xB9zp9FrglfXiljh6TQptLNBfNgfYmkZzmJ8WXDuiM3Dnf4SgQOjgH2 Kn/2htfSYD7ZJ0cD73LeMiK8dvQLI03npXv0goTvQfu5oJFyilIEQNslYVQ6wInN/b2P ublg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=XXFtHXdVDsZz2xbX64+oDtApUwN7QXMGPv73jNcjxm4=; fh=NoJ7n5JVE2hviRF6uNBFRIJvWH7igafuy1AIwg26ToM=; b=W/v1EPjOh8k203nVQmm4vVUpnjpW3H+zqsq54bJIjHZrqvf1ae+ZiLDb4IkLnHPBOE yjl3gDT34t8gRgG69f3/4zZApV96RnQ/7QnvPI8ZUSQyxTCUAGj592naDm6fVi+PQflH 4nWIlqhdnlViNKfSHQ/Trb1hywHmGSrvmxD8nbEJdtoyw8zMIRfeXDrvH4GvLOuSrG1T 87K4WvwXGZliRKgvQKxEwHYR4LC1PEYNcOW3sRnTOtFc6yjBeyRU1Lr1jKxfvcXHZBQm AYJkp/bzuJLGhrVjacPjiehdLdtvtQxpzBjfvaGo1mI3FFqqUeRmyfMk+yQDWy45sAz4 dTww==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6eb3f01a7c2si87688116d6.338.2025.03.24.23.52.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Mar 2025 23:52:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1twy8F-0004nF-64; Tue, 25 Mar 2025 02:51:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twy7w-0004mK-Lv; Tue, 25 Mar 2025 02:51:08 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twy7u-0001i4-8I; Tue, 25 Mar 2025 02:51:08 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 1C0E1107D6B; Tue, 25 Mar 2025 09:49:29 +0300 (MSK) Received: from gandalf.tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with ESMTP id B2B611D5E78; Tue, 25 Mar 2025 09:50:38 +0300 (MSK) Received: by gandalf.tls.msk.ru (Postfix, from userid 1000) id B05F057038; Tue, 25 Mar 2025 09:50:38 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Richard Henderson , Peter Maydell , Michael Tokarev Subject: [Stable-8.2.10 43/51] target/arm: Make DisasContext.{fp, sve}_access_checked tristate Date: Tue, 25 Mar 2025 09:50:30 +0300 Message-Id: <20250325065038.3263786-2-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson The check for fp_excp_el in assert_fp_access_checked is incorrect. For SME, with StreamingMode enabled, the access is really against the streaming mode vectors, and access to the normal fp registers is allowed to be disabled. C.f. sme_enabled_check. Convert sve_access_checked to match, even though we don't currently check the exception state. Cc: qemu-stable@nongnu.org Fixes: 3d74825f4d6 ("target/arm: Add SME enablement checks") Signed-off-by: Richard Henderson Message-id: 20250307190415.982049-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell (cherry picked from commit 298a04998fa4a6dc977abe9234d98dfcdab98423) Signed-off-by: Michael Tokarev diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 5beac07b60..67d3219a30 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1212,14 +1212,14 @@ static bool fp_access_check_only(DisasContext *s) { if (s->fp_excp_el) { assert(!s->fp_access_checked); - s->fp_access_checked = true; + s->fp_access_checked = -1; gen_exception_insn_el(s, 0, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false, 0), s->fp_excp_el); return false; } - s->fp_access_checked = true; + s->fp_access_checked = 1; return true; } @@ -1253,13 +1253,13 @@ bool sve_access_check(DisasContext *s) syn_sve_access_trap(), s->sve_excp_el); goto fail_exit; } - s->sve_access_checked = true; + s->sve_access_checked = 1; return fp_access_check(s); fail_exit: /* Assert that we only raise one exception per instruction. */ assert(!s->sve_access_checked); - s->sve_access_checked = true; + s->sve_access_checked = -1; return false; } @@ -1288,8 +1288,9 @@ bool sme_enabled_check(DisasContext *s) * sme_excp_el by itself for cpregs access checks. */ if (!s->fp_excp_el || s->sme_excp_el < s->fp_excp_el) { - s->fp_access_checked = true; - return sme_access_check(s); + bool ret = sme_access_check(s); + s->fp_access_checked = (ret ? 1 : -1); + return ret; } return fp_access_check_only(s); } @@ -14101,8 +14102,8 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) s->insn = insn; s->base.pc_next = pc + 4; - s->fp_access_checked = false; - s->sve_access_checked = false; + s->fp_access_checked = 0; + s->sve_access_checked = 0; if (s->pstate_il) { /* diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h index 7b811b8ac5..3e402b3708 100644 --- a/target/arm/tcg/translate-a64.h +++ b/target/arm/tcg/translate-a64.h @@ -65,7 +65,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, static inline void assert_fp_access_checked(DisasContext *s) { #ifdef CONFIG_DEBUG_TCG - if (unlikely(!s->fp_access_checked || s->fp_excp_el)) { + if (unlikely(s->fp_access_checked <= 0)) { fprintf(stderr, "target-arm: FP access check missing for " "instruction 0x%08x\n", s->insn); abort(); diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 3c3bb3431a..9dfa638db2 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -91,15 +91,19 @@ typedef struct DisasContext { bool aarch64; bool thumb; bool lse2; - /* Because unallocated encodings generate different exception syndrome + /* + * Because unallocated encodings generate different exception syndrome * information from traps due to FP being disabled, we can't do a single * "is fp access disabled" check at a high level in the decode tree. * To help in catching bugs where the access check was forgotten in some * code path, we set this flag when the access check is done, and assert * that it is set at the point where we actually touch the FP regs. + * 0: not checked, + * 1: checked, access ok + * -1: checked, access denied */ - bool fp_access_checked; - bool sve_access_checked; + int8_t fp_access_checked; + int8_t sve_access_checked; /* ARMv8 single-step state (this is distinct from the QEMU gdbstub * single-step support). */ From patchwork Tue Mar 25 06:50:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 875986 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp2503709wrb; Mon, 24 Mar 2025 23:52:22 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU3nMYxF73xBEQ5qKkUbwnkeRlU3x46SP2Ja7jC6zhmAHpyafg4Zg8HUAUuwW4FqzbyZEyK2A==@linaro.org X-Google-Smtp-Source: AGHT+IGK9DaIa8Lsjasb9u9MrBb+30dWWYvwgMps6CqTp+YllGGjBRpUDg8elUFsoCZtc9ygMvxM X-Received: by 2002:a05:6214:1c0b:b0:6e8:9bcd:bba6 with SMTP id 6a1803df08f44-6eb3f27f3abmr242999756d6.7.1742885542434; Mon, 24 Mar 2025 23:52:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742885542; cv=none; d=google.com; s=arc-20240605; b=ldtlQXC2/ffvM9qdl31zv8h57ofKXsl2ygMNe5XbAsMq6auiUHSv9auxLcTK71SRKk HqoOYPhymNrc2E851QHCjpVNGX2REdKE6B82ZfBZOpivPXQXybVw+4Adfgk32mY5V4fL 7g7hkp0+ov/qK96xes8WPFDUE6UJfG0bGoKiOUwQGTrvq5NBBA+km9rYyqiIqVTEuq+g JwYj1JqvQxnWMmbncTKAsDCmqWGNZeSrgWItAR764VvJlvcQ17+10fDGyJ+vBzoNVwKI tT3mSjLBDtFRQN0oiHG2+7LRcRfOp7FBcyeJHi8uXVZJzXw/xATrZuP8hPURwTeICzbk dSMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=xuOuGwKr4bZHpICp53sVvoP4fBAdMr6LHgsvklvY5q0=; fh=NoJ7n5JVE2hviRF6uNBFRIJvWH7igafuy1AIwg26ToM=; b=jY05YjAqdS5TkaOh/gXkfkaT8SLW9aelyIrwIRGc0LRvHoMjxaGdPaUKYQv06MBN1W RacWdpLvSQx9Usf6OJMT3nJjTAebbe0HWTwdKbYDpvYgQTwqKxaUKb6/O4J7QH0OY9Sh nBTax40+yFy09/VkPAHrEGOACAFpIMwwtW68YFenqKYunCfUTgLsPmOBWIrzBct38MK7 Cp375+2N+O0GY8Q19KDCqFxT/ifs+/mrcLkzXioGND5oOExn8H3DvyKuCeOcKzxjBw10 yptkDMh4GcfRj/3y7uJori4xlcIkzrc8CfkMEYvS+VLYvTCA8jR6IR7Fnv+Khzelj8SY 6CzA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6eb3f01ddd2si92148326d6.364.2025.03.24.23.52.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Mar 2025 23:52:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1twy8Q-0004zr-7J; Tue, 25 Mar 2025 02:51:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twy7v-0004lo-Mw; Tue, 25 Mar 2025 02:51:08 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twy7t-0001iQ-UG; Tue, 25 Mar 2025 02:51:07 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 20219107D6C; Tue, 25 Mar 2025 09:49:29 +0300 (MSK) Received: from gandalf.tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with ESMTP id B6ED91D5E79; Tue, 25 Mar 2025 09:50:38 +0300 (MSK) Received: by gandalf.tls.msk.ru (Postfix, from userid 1000) id B2F155703A; Tue, 25 Mar 2025 09:50:38 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Richard Henderson , Peter Maydell , Michael Tokarev Subject: [Stable-8.2.10 44/51] target/arm: Simplify pstate_sm check in sve_access_check Date: Tue, 25 Mar 2025 09:50:31 +0300 Message-Id: <20250325065038.3263786-3-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson In StreamingMode, fp_access_checked is handled already. We cannot fall through to fp_access_check lest we fall foul of the double-check assertion. Cc: qemu-stable@nongnu.org Fixes: 285b1d5fcef ("target/arm: Handle SME in sve_access_check") Signed-off-by: Richard Henderson Message-id: 20250307190415.982049-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell [PMM: move declaration of 'ret' to top of block] Signed-off-by: Peter Maydell (cherry picked from commit cc7abc35dfa790ba6c20473c03745428c1c626b6) Signed-off-by: Michael Tokarev diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 67d3219a30..c7428eb674 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1244,23 +1244,23 @@ static bool fp_access_check(DisasContext *s) bool sve_access_check(DisasContext *s) { if (s->pstate_sm || !dc_isar_feature(aa64_sve, s)) { + bool ret; + assert(dc_isar_feature(aa64_sme, s)); - if (!sme_sm_enabled_check(s)) { - goto fail_exit; - } - } else if (s->sve_excp_el) { + ret = sme_sm_enabled_check(s); + s->sve_access_checked = (ret ? 1 : -1); + return ret; + } + if (s->sve_excp_el) { + /* Assert that we only raise one exception per instruction. */ + assert(!s->sve_access_checked); gen_exception_insn_el(s, 0, EXCP_UDEF, syn_sve_access_trap(), s->sve_excp_el); - goto fail_exit; + s->sve_access_checked = -1; + return false; } s->sve_access_checked = 1; return fp_access_check(s); - - fail_exit: - /* Assert that we only raise one exception per instruction. */ - assert(!s->sve_access_checked); - s->sve_access_checked = -1; - return false; } /* From patchwork Tue Mar 25 06:50:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 875991 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp2504954wrb; Mon, 24 Mar 2025 23:57:50 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWaaNU4Iwq0hUSRlOAgxePbeesuNI1+QICooUqYhF4dW8OvPKKWtlXm85EhCZAvv1dkl6KqNA==@linaro.org X-Google-Smtp-Source: AGHT+IGSOvnmDRRr6R8uuQSGDsU6BuJ+smZ5ZRi0GGv/yjr3M8hqXl5+iTye897Dc6SFZHN7mNG/ X-Received: by 2002:a5d:64c7:0:b0:38f:2413:2622 with SMTP id ffacd0b85a97d-3997f9405b9mr13616786f8f.47.1742885870814; Mon, 24 Mar 2025 23:57:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742885870; cv=none; d=google.com; s=arc-20240605; b=FDz8RMPdMxu10GTy762/RydzCx/h5AFmBtbW6h/6WEy8llh6Q5DANqycZnZrNv7Tge iVTDTB61dVMhUT8tg0+qnodzAh6AghDdXRzK2dL5EniUW+gT91/J9q4ZnWkXzkSt7x3i URKdLJ0bG6+3i45rg/ZYrPZZl4usyEs9tmnrZNrequDMu3lxMZn+8Rm7KVoWP2pSPp5W pJ3LwfqS3scUcxaxLQ4rO7cgvhGqn2b1QuZfMoftALzF2XYL8P15VgjoYL419StxB5tl ImvVkHJ08xqjNP1y5d/DTUoWI+q5LCkGBcXpzrDSC6/CGxhgs4c/NRUpfoOomfGWVH9F S9zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=bIBjdFjP9FaSonh4K2S9xHme3uzcGrPSMIPK1MTEUoE=; fh=ov5PGwK6o9oDGAZqMMM9bNm8kym9ov6lFbplfKYaKOA=; b=S8Fib3Lea1hgVyYH251puAiHISqeoGTAwZbzthOEEpaYhUE1GBkvhDy0qsaeU8ziMI aSGvFpe6Esl9YV+PiX+aRLwBKtDZFdGIBE9+ivRD/On+r+i8mrZ38wYW9iTptmoobKnm YY2xCGEWh7+LFaUCUceeHm7Wg8roDOAXNAKLml133NFpH9au7AHbHKbJ6RIkgYMLM5bo 00o+9ZGre1muzfI4nKT1LJ9nkvLW7zDSQWAimWQgsxWzcKYVHSPa95y6QwAFm20Atz5P lZBWqki+eKvvtcrIED5zB6c6v1xYK4V7Ji4LMRP/03vezmAFKqgWHqtHtZ5mcEJU74Q7 +OlQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ffacd0b85a97d-3997f9d9987si7023864f8f.582.2025.03.24.23.57.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Mar 2025 23:57:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1twy8m-0005Fi-6d; Tue, 25 Mar 2025 02:52:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twy8O-00050m-S5; Tue, 25 Mar 2025 02:51:37 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twy8M-0001qj-Hx; Tue, 25 Mar 2025 02:51:36 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 2FA14107D70; Tue, 25 Mar 2025 09:49:29 +0300 (MSK) Received: from gandalf.tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with ESMTP id C65B81D5E7D; Tue, 25 Mar 2025 09:50:38 +0300 (MSK) Received: by gandalf.tls.msk.ru (Postfix, from userid 1000) id BCE0257042; Tue, 25 Mar 2025 09:50:38 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Richard Henderson , Andreas Schwab , Alistair Francis , Michael Tokarev Subject: [Stable-8.2.10 49/51] linux-user/riscv: Fix handling of cpu mask in riscv_hwprobe syscall Date: Tue, 25 Mar 2025 09:50:35 +0300 Message-Id: <20250325065038.3263786-7-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson The third argument of the syscall contains the size of the cpu mask in bytes, not bits. Nor is the size rounded up to a multiple of sizeof(abi_ulong). Cc: qemu-stable@nongnu.org Reported-by: Andreas Schwab Fixes: 9e1c7d982d7 ("linux-user/riscv: Add syscall riscv_hwprobe") Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20250308225902.1208237-3-richard.henderson@linaro.org> Signed-off-by: Alistair Francis (cherry picked from commit 1a010d22b7adecf0fb1c069e1e535af1aa51e9cf) Signed-off-by: Michael Tokarev diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 4dff03d2bd..15caa698b2 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -8906,35 +8906,38 @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env, } } -static int cpu_set_valid(abi_long arg3, abi_long arg4) +/* + * If the cpumask_t of (target_cpus, cpusetsize) cannot be read: -EFAULT. + * If the cpumast_t has no bits set: -EINVAL. + * Otherwise the cpumask_t contains some bit set: 0. + * Unlike the kernel, we do not mask cpumask_t by the set of online cpus, + * nor bound the search by cpumask_size(). + */ +static int nonempty_cpu_set(abi_ulong cpusetsize, abi_ptr target_cpus) { - int ret, i, tmp; - size_t host_mask_size, target_mask_size; - unsigned long *host_mask; - - /* - * cpu_set_t represent CPU masks as bit masks of type unsigned long *. - * arg3 contains the cpu count. - */ - tmp = (8 * sizeof(abi_ulong)); - target_mask_size = ((arg3 + tmp - 1) / tmp) * sizeof(abi_ulong); - host_mask_size = (target_mask_size + (sizeof(*host_mask) - 1)) & - ~(sizeof(*host_mask) - 1); - - host_mask = alloca(host_mask_size); - - ret = target_to_host_cpu_mask(host_mask, host_mask_size, - arg4, target_mask_size); - if (ret != 0) { - return ret; - } + unsigned char *p = lock_user(VERIFY_READ, target_cpus, cpusetsize, 1); + int ret = -TARGET_EFAULT; - for (i = 0 ; i < host_mask_size / sizeof(*host_mask); i++) { - if (host_mask[i] != 0) { - return 0; + if (p) { + ret = -TARGET_EINVAL; + /* + * Since we only care about the empty/non-empty state of the cpumask_t + * not the individual bits, we do not need to repartition the bits + * from target abi_ulong to host unsigned long. + * + * Note that the kernel does not round up cpusetsize to a multiple of + * sizeof(abi_ulong). After bounding cpusetsize by cpumask_size(), + * it copies exactly cpusetsize bytes into a zeroed buffer. + */ + for (abi_ulong i = 0; i < cpusetsize; ++i) { + if (p[i]) { + ret = 0; + break; + } } + unlock_user(p, target_cpus, 0); } - return -TARGET_EINVAL; + return ret; } static abi_long do_riscv_hwprobe(CPUArchState *cpu_env, abi_long arg1, @@ -8951,7 +8954,7 @@ static abi_long do_riscv_hwprobe(CPUArchState *cpu_env, abi_long arg1, /* check cpu_set */ if (arg3 != 0) { - ret = cpu_set_valid(arg3, arg4); + ret = nonempty_cpu_set(arg3, arg4); if (ret != 0) { return ret; }