From patchwork Mon Mar 24 10:04:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 875831 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1711136988; Mon, 24 Mar 2025 10:04:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742810678; cv=none; b=XtB7oJiLCx6KC0Jr9wUYZgZDTd037A4DDMyzE+BZ8smQhmU3x9j4a29nFYS8V2oMQ3d9vo9mvKc8Omo4S4RNYNdVJVMIIaFbVpiJ50Ib5HzWTn+oknhxFhB7BY50dQ6YkJDdiATczb3W6+btCBwVOrnOKKX4TaRK7wGpGrtWhE4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742810678; c=relaxed/simple; bh=tFMGfw5P2Zzx9Mq2scZrMcZwQMbl6eBHv+dDOU7FTek=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=l0bdLdgiqch+Xn0pR4ueOs8O6X+1/tj99bw2jwLDC7xGruJwhwiugFEF5dZhCbnDmBJQ7upsc3JNODO7jQA3Jxjtt2PaIFHETb+/kZqsSXxPxpGTIefdZPxI67edAXyA/Rrw3N+3A7Ygd50XVIc4JHC5cmDBnQCOKPb22ykBUjk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=air3YVQ8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="air3YVQ8" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2FA74C4CEED; Mon, 24 Mar 2025 10:04:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742810678; bh=tFMGfw5P2Zzx9Mq2scZrMcZwQMbl6eBHv+dDOU7FTek=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=air3YVQ8BKc7vQQIwRx73TJwEyDytmYRvhKioMXPY21986+nYZyizZBgnPOp+kFwT wFjdwk5tqfOZPj76kh3ZQzUSD8viWx9DxpJRVY79ooRiotwqjxe/FQMg0uLqmOmq7d Yjylv9M6LWTz2YVJWw0hyd0kExRZRGExrFDELF9oEqBGY8v57ObOyWsXGjc9DYlled zEVB0SZvq3vS5oEwllgWsD05tyG2pW4IfMZA6Agna2cpqlih5U7FPVyZY+0p1U1P18 i9mDjTJZAEjkUr1HbsuxuGkQJIM9fqGB1rkayytcBhBE+kF1f5qVBNU0Lw+np6TOty 8q5WDxrZVYooQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CE30C3600C; Mon, 24 Mar 2025 10:04:38 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Mon, 24 Mar 2025 15:34:35 +0530 Subject: [PATCH v2 1/3] PCI: Add sysfs support for exposing PTM context Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250324-pcie-ptm-v2-1-c7d8c3644b4a@linaro.org> References: <20250324-pcie-ptm-v2-0-c7d8c3644b4a@linaro.org> In-Reply-To: <20250324-pcie-ptm-v2-0-c7d8c3644b4a@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=14688; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=zezY3dQQZG9zcCyHsgrmPX2/nGvny3C7hcw/qPf1FvI=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBn4S4zON2kO+RMzKhuoFyMVxaiWoVISY6DtnKXN nTq9j/tkc2JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZ+EuMwAKCRBVnxHm/pHO 9fV7CACT2jZT2NRmMrydFWQKno4ChWtij80L/6dPxufzh3YabwitzSsFYsabHVox6PNWIUB9xxp Psk6N/c98TPS5AlydjotpoVAAngywkpWpETh9xX/T7IoPOMx1ZEC8xl4h/aC/+MkOOECqmo3ehq 1+Flno6RddqfqHD5fq+5vvXJAyToETWTF1Pvc3Dxvrq+MITMZvdpOg/jd2mAxx6CxSkACBilpGi GejAAIYplxv11hh/qZnoRAnMZD+FViqyhsxKdZkVQpUqBkxKque5EoQvovkyPm7omZLGjt9xGnu qu8QC8ufmNAotGSYmoGefG7BqYYtmyiQK5YbJCQ3SE78ndcb X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Precision Time Management (PTM) mechanism defined in PCIe spec r6.0, sec 6.22 allows precise coordination of timing information across multiple components in a PCIe hierarchy with independent local time clocks. PCI core already supports enabling PTM in the root port and endpoint devices through PTM Extended Capability registers. But the PTM context supported by the PTM capable components such as Root Complex (RC) and Endpoint (EP) controllers were not exposed as of now. Hence, add the sysfs support to expose the PTM context to userspace from both PCIe RC and EP controllers. Controller drivers are expected to call pcie_ptm_create_sysfs() to create the sysfs attributes for the PTM context and call pcie_ptm_destroy_sysfs() to destroy them. The drivers should also populate the relevant callbacks in the 'struct pcie_ptm_ops' structure based on the controller implementation. Below PTM context are exposed through sysfs: PCIe RC ======= 1. PTM Local clock 2. PTM T2 timestamp 3. PTM T3 timestamp 4. PTM Context valid PCIe EP ======= 1. PTM Local clock 2. PTM T1 timestamp 3. PTM T4 timestamp 4. PTM Master clock 5. PTM Context update Signed-off-by: Manivannan Sadhasivam --- Documentation/ABI/testing/sysfs-platform-pcie-ptm | 70 ++++++ MAINTAINERS | 1 + drivers/pci/pcie/ptm.c | 268 ++++++++++++++++++++++ include/linux/pci.h | 35 +++ 4 files changed, 374 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-platform-pcie-ptm b/Documentation/ABI/testing/sysfs-platform-pcie-ptm new file mode 100644 index 0000000000000000000000000000000000000000..010c3e32e2b8eaf352a8e1aad7420d8a3e948dae --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-pcie-ptm @@ -0,0 +1,70 @@ +What: /sys/devices/platform/*/ptm/local_clock +Date: February 2025 +Contact: Manivannan Sadhasivam +Description: + (RO) PTM local clock in nanoseconds. Applicable for both Root + Complex and Endpoint controllers. + +What: /sys/devices/platform/*/ptm/master_clock +Date: February 2025 +Contact: Manivannan Sadhasivam +Description: + (RO) PTM master clock in nanoseconds. Applicable only for + Endpoint controllers. + +What: /sys/devices/platform/*/ptm/t1 +Date: February 2025 +Contact: Manivannan Sadhasivam +Description: + (RO) PTM T1 timestamp in nanoseconds. Applicable only for + Endpoint controllers. + +What: /sys/devices/platform/*/ptm/t2 +Date: February 2025 +Contact: Manivannan Sadhasivam +Description: + (RO) PTM T2 timestamp in nanoseconds. Applicable only for + Root Complex controllers. + +What: /sys/devices/platform/*/ptm/t3 +Date: February 2025 +Contact: Manivannan Sadhasivam +Description: + (RO) PTM T3 timestamp in nanoseconds. Applicable only for + Root Complex controllers. + +What: /sys/devices/platform/*/ptm/t4 +Date: February 2025 +Contact: Manivannan Sadhasivam +Description: + (RO) PTM T4 timestamp in nanoseconds. Applicable only for + Endpoint controllers. + +What: /sys/devices/platform/*/ptm/context_update +Date: February 2025 +Contact: Manivannan Sadhasivam +Description: + (RW) Control the PTM context update mode. Applicable only for + Endpoint controllers. + + Following values are supported: + + * auto = PTM context auto update trigger for every 10ms + + * manual = PTM context manual update. Writing 'manual' to this + file triggers PTM context update (default) + +What: /sys/devices/platform/*/ptm/context_valid +Date: February 2025 +Contact: Manivannan Sadhasivam +Description: + (RW) Control the PTM context validity (local clock timing). + Applicable only for Root Complex controllers. PTM context is + invalidated by hardware if the Root Complex enters low power + mode or changes link frequency. + + Following values are supported: + + * 0 = PTM context invalid (default) + + * 1 = PTM context valid diff --git a/MAINTAINERS b/MAINTAINERS index b4d09d52a750b320f689c1365791cdfa6e719fde..f1bac092877df739328347481bd14f6701a7df19 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18213,6 +18213,7 @@ Q: https://patchwork.kernel.org/project/linux-pci/list/ B: https://bugzilla.kernel.org C: irc://irc.oftc.net/linux-pci T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git +F: Documentation/ABI/testing/sysfs-platform-pcie-ptm F: Documentation/devicetree/bindings/pci/ F: drivers/pci/controller/ F: drivers/pci/pci-bridge-emul.c diff --git a/drivers/pci/pcie/ptm.c b/drivers/pci/pcie/ptm.c index 7cfb6c0d5dcb6de2a759b56d6877c95102b3d10f..bfa632b76a87ad304e966a8edfb5dba14d58a23c 100644 --- a/drivers/pci/pcie/ptm.c +++ b/drivers/pci/pcie/ptm.c @@ -10,6 +10,8 @@ #include #include "../pci.h" +struct device *ptm_device; + /* * If the next upstream device supports PTM, return it; otherwise return * NULL. PTM Messages are local, so both link partners must support it. @@ -252,3 +254,269 @@ bool pcie_ptm_enabled(struct pci_dev *dev) return dev->ptm_enabled; } EXPORT_SYMBOL(pcie_ptm_enabled); + +static ssize_t context_update_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct pcie_ptm *ptm = dev_get_drvdata(dev); + int ret; + + if (!ptm->ops->context_update_store) + return -EOPNOTSUPP; + + ret = ptm->ops->context_update_store(ptm->pdata, buf); + if (ret) + return ret; + + return count; +} + +static ssize_t context_update_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pcie_ptm *ptm = dev_get_drvdata(dev); + + if (!ptm->ops->context_update_show) + return -EOPNOTSUPP; + + return ptm->ops->context_update_show(ptm->pdata, buf); +} + +static ssize_t context_valid_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct pcie_ptm *ptm = dev_get_drvdata(dev); + unsigned long arg; + int ret; + + if (kstrtoul(buf, 0, &arg) < 0) + return -EINVAL; + + if (!ptm->ops->context_valid_store) + return -EOPNOTSUPP; + + ret = ptm->ops->context_valid_store(ptm->pdata, !!arg); + if (ret) + return ret; + + return count; +} + +static ssize_t context_valid_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pcie_ptm *ptm = dev_get_drvdata(dev); + + if (!ptm->ops->context_valid_show) + return -EOPNOTSUPP; + + return ptm->ops->context_valid_show(ptm->pdata, buf); +} + +static ssize_t local_clock_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pcie_ptm *ptm = dev_get_drvdata(dev); + + if (!ptm->ops->local_clock_show) + return -EOPNOTSUPP; + + return ptm->ops->local_clock_show(ptm->pdata, buf); +} + +static ssize_t master_clock_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pcie_ptm *ptm = dev_get_drvdata(dev); + + if (!ptm->ops->master_clock_show) + return -EOPNOTSUPP; + + return ptm->ops->master_clock_show(ptm->pdata, buf); +} + +static ssize_t t1_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pcie_ptm *ptm = dev_get_drvdata(dev); + + if (!ptm->ops->t1_show) + return -EOPNOTSUPP; + + return ptm->ops->t1_show(ptm->pdata, buf); +} + +static ssize_t t2_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pcie_ptm *ptm = dev_get_drvdata(dev); + + if (!ptm->ops->t2_show) + return -EOPNOTSUPP; + + return ptm->ops->t2_show(ptm->pdata, buf); +} + +static ssize_t t3_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pcie_ptm *ptm = dev_get_drvdata(dev); + + if (!ptm->ops->t3_show) + return -EOPNOTSUPP; + + return ptm->ops->t3_show(ptm->pdata, buf); +} + +static ssize_t t4_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pcie_ptm *ptm = dev_get_drvdata(dev); + + if (!ptm->ops->t4_show) + return -EOPNOTSUPP; + + return ptm->ops->t4_show(ptm->pdata, buf); +} + +static DEVICE_ATTR_RW(context_update); +static DEVICE_ATTR_RW(context_valid); +static DEVICE_ATTR_RO(local_clock); +static DEVICE_ATTR_RO(master_clock); +static DEVICE_ATTR_RO(t1); +static DEVICE_ATTR_RO(t2); +static DEVICE_ATTR_RO(t3); +static DEVICE_ATTR_RO(t4); + +static struct attribute *pcie_ptm_attrs[] = { + &dev_attr_context_update.attr, + &dev_attr_context_valid.attr, + &dev_attr_local_clock.attr, + &dev_attr_master_clock.attr, + &dev_attr_t1.attr, + &dev_attr_t2.attr, + &dev_attr_t3.attr, + &dev_attr_t4.attr, + NULL +}; + +static umode_t pcie_ptm_attr_visible(struct kobject *kobj, struct attribute *attr, + int n) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct pcie_ptm *ptm = dev_get_drvdata(dev); + + if ((attr == &dev_attr_t1.attr && ptm->ops->t1_visible && + ptm->ops->t1_visible(ptm->pdata)) || + (attr == &dev_attr_t2.attr && ptm->ops->t2_visible && + ptm->ops->t2_visible(ptm->pdata)) || + (attr == &dev_attr_t3.attr && ptm->ops->t3_visible && + ptm->ops->t3_visible(ptm->pdata)) || + (attr == &dev_attr_t4.attr && ptm->ops->t4_visible && + ptm->ops->t4_visible(ptm->pdata)) || + (attr == &dev_attr_local_clock.attr && + ptm->ops->local_clock_visible && + ptm->ops->local_clock_visible(ptm->pdata)) || + (attr == &dev_attr_master_clock.attr && + ptm->ops->master_clock_visible && + ptm->ops->master_clock_visible(ptm->pdata)) || + (attr == &dev_attr_context_update.attr && + ptm->ops->context_update_visible && + ptm->ops->context_update_visible(ptm->pdata)) || + (attr == &dev_attr_context_valid.attr && + ptm->ops->context_valid_visible && + ptm->ops->context_valid_visible(ptm->pdata))) + return attr->mode; + + return 0; +} + +static const struct attribute_group pcie_ptm_attr_group = { + .attrs = pcie_ptm_attrs, + .is_visible = pcie_ptm_attr_visible, +}; + +static const struct attribute_group *pcie_ptm_attr_groups[] = { + &pcie_ptm_attr_group, + NULL, +}; + +static void pcie_ptm_release(struct device *dev) +{ + struct pcie_ptm *ptm = container_of(dev, struct pcie_ptm, dev); + + kfree(ptm); +} + +/* + * pcie_ptm_create_sysfs() - Create sysfs entries for the PTM context + * @dev: PTM capable component device + * @pdata: Private data of the PTM capable component device + * @ops: PTM callback structure + * + * Create sysfs entries for exposing the PTM context of the PTM capable + * components such as Root Complex and Endpoint controllers. + */ +int pcie_ptm_create_sysfs(struct device *dev, void *pdata, + struct pcie_ptm_ops *ops) +{ + struct pcie_ptm *ptm; + int ret; + + /* Caller must provide check_capability() callback */ + if (!ops->check_capability) + return -EINVAL; + + /* Check for PTM capability before creating sysfs attrbutes */ + ret = ops->check_capability(pdata); + if (!ret) { + dev_dbg(dev, "PTM capability not present\n"); + return -ENODATA; + } + + ptm = kzalloc(sizeof(*ptm), GFP_KERNEL); + if (!ptm) + return -ENOMEM; + + ptm->pdata = pdata; + ptm->ops = ops; + + device_initialize(&ptm->dev); + ptm->dev.groups = pcie_ptm_attr_groups; + ptm->dev.release = pcie_ptm_release; + ptm->dev.parent = dev; + dev_set_drvdata(&ptm->dev, ptm); + device_set_pm_not_required(&ptm->dev); + + ret = dev_set_name(&ptm->dev, "ptm"); + if (ret) + goto err_put_device; + + ret = device_add(&ptm->dev); + if (ret) + goto err_put_device; + + ptm_device = &ptm->dev; + + return 0; + +err_put_device: + put_device(&ptm->dev); + + return ret; +} +EXPORT_SYMBOL(pci_ptm_init); + +/* + * pcie_ptm_destroy_sysfs() - Destroy sysfs entries for the PTM context + */ +void pcie_ptm_destroy_sysfs(void) +{ + if (ptm_device) { + device_unregister(ptm_device); + ptm_device = NULL; + } +} +EXPORT_SYMBOL(pcie_ptm_destroy_sysfs); diff --git a/include/linux/pci.h b/include/linux/pci.h index 47b31ad724fa5bf7abd7c3dc572947551b0f2148..42bb3cf0212e96fd65a1f01410ef70c82491c9eb 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1857,16 +1857,51 @@ static inline bool pci_aer_available(void) { return false; } bool pci_ats_disabled(void); +struct pcie_ptm_ops { + int (*check_capability)(void *drvdata); + int (*context_update_store)(void *drvdata, const char *buf); + ssize_t (*context_update_show)(void *drvdata, char *buf); + int (*context_valid_store)(void *drvdata, bool valid); + ssize_t (*context_valid_show)(void *drvdata, char *buf); + ssize_t (*local_clock_show)(void *drvdata, char *buf); + ssize_t (*master_clock_show)(void *drvdata, char *buf); + ssize_t (*t1_show)(void *drvdata, char *buf); + ssize_t (*t2_show)(void *drvdata, char *buf); + ssize_t (*t3_show)(void *drvdata, char *buf); + ssize_t (*t4_show)(void *drvdata, char *buf); + + bool (*context_update_visible)(void *drvdata); + bool (*context_valid_visible)(void *drvdata); + bool (*local_clock_visible)(void *drvdata); + bool (*master_clock_visible)(void *drvdata); + bool (*t1_visible)(void *drvdata); + bool (*t2_visible)(void *drvdata); + bool (*t3_visible)(void *drvdata); + bool (*t4_visible)(void *drvdata); +}; + +struct pcie_ptm { + struct device dev; + struct pcie_ptm_ops *ops; + void *pdata; +}; + #ifdef CONFIG_PCIE_PTM int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); void pci_disable_ptm(struct pci_dev *dev); bool pcie_ptm_enabled(struct pci_dev *dev); +int pcie_ptm_create_sysfs(struct device *dev, void *pdata, struct pcie_ptm_ops *ops); +void pcie_ptm_destroy_sysfs(void); #else static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) { return -EINVAL; } static inline void pci_disable_ptm(struct pci_dev *dev) { } static inline bool pcie_ptm_enabled(struct pci_dev *dev) { return false; } +static inline int pcie_ptm_create_sysfs(struct device *dev, void *pdata, + struct pcie_ptm_ops *ops) +{ return 0; } +static inline void pcie_ptm_destroy_sysfs(void) { } #endif void pci_cfg_access_lock(struct pci_dev *dev); From patchwork Mon Mar 24 10:04:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 876091 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEC7019C542; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ID7w09Sx" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4EC3CC4AF0C; Mon, 24 Mar 2025 10:04:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742810678; bh=AVSjKBtBaOpk+lLRbW0/2ZysYOxqeHDouXkZrG+dMgA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ID7w09SxV6Rjg1coHJb0YknmHtis3mkKJyYhU6bxaxP8eJsfujY7GqfFLgekHJCfT J4evfOFAJUZiCbsnJ/Skv1Lxw9UoQ2gUWy3iMUuv98AweM8k+ipXWNstS20ynI4Pjt 7UvJFUQaEn0gc99MpT0mcuhYFahrh6JBI4LjE0k7VW7XpjYdPv4ZW39oRSFf05+2Wg 1aT13i9b/LjC//Is3ejkqh0G7eIY2G/EwvNTdiS0IRuFGZFPo62bIuQnOmItbkF/CL eKJm9Jd3g+x2KLklAkl6Vny2kTErbGZQVqfi3VBR/3XBZiJeBlIA+oPt4/4il5a8T7 X4PiHAwXRevLQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 448E6C36005; Mon, 24 Mar 2025 10:04:38 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Mon, 24 Mar 2025 15:34:36 +0530 Subject: [PATCH v2 2/3] PCI: dwc: Add sysfs support for PTM context Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250324-pcie-ptm-v2-2-c7d8c3644b4a@linaro.org> References: <20250324-pcie-ptm-v2-0-c7d8c3644b4a@linaro.org> In-Reply-To: <20250324-pcie-ptm-v2-0-c7d8c3644b4a@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=14763; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=QeazHBVh/L0Qmh1L1EgNAubfunKPCWG5rl2kIN1kdcY=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBn4S4zz0YjUW26AE0yVKs+57/x1lwD2BzPf4P47 awEWCbheG6JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZ+EuMwAKCRBVnxHm/pHO 9bTiB/0VKjpW5JgjTfSmfaKac1gXRy54fWUsQO9dqWOaASLwv/eE0pbD9fl782poOBT5sWonNK0 Yww9Vay2nXSQx85Ht708R2oUeAGG6vrtAgfXMGdcG8/WsdncSKfHEor/Uid1c5yA+51O6biaQzn ApgijQqtFPZIT2RWyI70BcH7E508kBBfMBniCw6ZbynBfzweFPGV7ppfiwPTVv/Hp/4BN/Hm8Tv HAA5WMyVeL+zq7Zkas9VtdTNaPh11CQ8PE3VOorsbHsWcqedlHhgwgGRSPxgkWAfot5ICOVpsLg xlMZACmBhkGbVvTlQO7FBXdYhs2/mOAC8ife4PZ+EK1aKCYt X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Synopsys Designware PCIe IPs support PTM capability as defined in the PCIe spec r6.0, sec 6.22. The PTM context information is exposed through Vendor Specific Extended Capability (VSEC) registers on supported controller implementation. Hence, add support for exposing these context information to userspace through the sysfs interface for the DWC controllers (both RC and EP). Currently, only Qcom controllers are supported. For adding support for DWC vendor controllers, dwc_pcie_ptm_vsec_ids[] needs to be extended. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/Makefile | 2 +- drivers/pci/controller/dwc/pcie-designware-ep.c | 3 + drivers/pci/controller/dwc/pcie-designware-host.c | 3 + drivers/pci/controller/dwc/pcie-designware-sysfs.c | 254 +++++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.c | 6 + drivers/pci/controller/dwc/pcie-designware.h | 21 ++ include/linux/pcie-dwc.h | 8 + 7 files changed, 296 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index 54565eedc52cc36bc393e257d093c4671aff7b39..ca7c1ff7a6807bf0aec24778dc10c02c7e8680c7 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PCIE_DW) += pcie-designware.o +obj-$(CONFIG_PCIE_DW) += pcie-designware.o pcie-designware-sysfs.o obj-$(CONFIG_PCIE_DW_DEBUGFS) += pcie-designware-debugfs.o obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 5a6174e107c20c897cfa142687e219c5ecafb8c6..d1a07cebc4c21f1a81048730bcf40fa8e1dba0b1 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -705,6 +705,7 @@ void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + pcie_designware_sysfs_exit(pci); dwc_pcie_debugfs_deinit(pci); dw_pcie_edma_remove(pci); } @@ -880,6 +881,8 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) dwc_pcie_debugfs_init(pci); + pcie_designware_sysfs_init(pci, DW_PCIE_EP_TYPE); + return 0; err_remove_edma: diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 6501fb062c70e56eb301ca71fcd642f7be33a252..faaabc5446ebde5adcdf5ab03e0cf3569636b79b 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -550,6 +550,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) dwc_pcie_debugfs_init(pci); + pcie_designware_sysfs_init(pci, DW_PCIE_RC_TYPE); + return 0; err_stop_link: @@ -574,6 +576,7 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + pcie_designware_sysfs_exit(pci); dwc_pcie_debugfs_deinit(pci); pci_stop_root_bus(pp->bridge->bus); diff --git a/drivers/pci/controller/dwc/pcie-designware-sysfs.c b/drivers/pci/controller/dwc/pcie-designware-sysfs.c new file mode 100644 index 0000000000000000000000000000000000000000..1723444e408c90dee0c8d0b526c6887969451d6c --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-designware-sysfs.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2025 Linaro Ltd. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include + +#include "pcie-designware.h" + +static int dw_pcie_ptm_check_capability(void *drvdata) +{ + struct dw_pcie *pci = drvdata; + + pci->ptm_vsec_offset = dw_pcie_find_ptm_capability(pci); + + return pci->ptm_vsec_offset; +} + +static int dw_pcie_ptm_context_update_store(void *drvdata, const char *buf) +{ + struct dw_pcie *pci = drvdata; + u32 val; + + if (sysfs_streq(buf, "auto")) { + val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); + val |= PTM_REQ_AUTO_UPDATE_ENABLED; + dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); + } else if (sysfs_streq(buf, "manual")) { + val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); + val &= ~PTM_REQ_AUTO_UPDATE_ENABLED; + val |= PTM_REQ_START_UPDATE; + dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); + } else { + return -EINVAL; + } + + return 0; +} + +static ssize_t dw_pcie_ptm_context_update_show(void *drvdata, char *buf) +{ + struct dw_pcie *pci = drvdata; + u32 val; + + val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); + if (FIELD_GET(PTM_REQ_AUTO_UPDATE_ENABLED, val)) + return sysfs_emit(buf, "auto\n"); + + /* + * PTM_REQ_START_UPDATE is a self clearing register bit. So if + * PTM_REQ_AUTO_UPDATE_ENABLED is not set, then it implies that + * manual update is used. + */ + return sysfs_emit(buf, "manual\n"); +} + +static int dw_pcie_ptm_context_valid_store(void *drvdata, bool valid) +{ + struct dw_pcie *pci = drvdata; + u32 val; + + if (valid) { + val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); + val |= PTM_RES_CCONTEXT_VALID; + dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); + } else { + val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); + val &= ~PTM_RES_CCONTEXT_VALID; + dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); + } + + return 0; +} + +static ssize_t dw_pcie_ptm_context_valid_show(void *drvdata, char *buf) +{ + struct dw_pcie *pci = drvdata; + u32 val; + + val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); + + return sysfs_emit(buf, "%u\n", !!FIELD_GET(PTM_RES_CCONTEXT_VALID, val)); +} + +static ssize_t dw_pcie_ptm_local_clock_show(void *drvdata, char *buf) +{ + struct dw_pcie *pci = drvdata; + u32 msb, lsb; + + do { + msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_LOCAL_MSB); + lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_LOCAL_LSB); + } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_LOCAL_MSB)); + + return sysfs_emit(buf, "%llu\n", ((u64) msb) << 32 | lsb); +} + +static ssize_t dw_pcie_ptm_master_clock_show(void *drvdata, char *buf) +{ + struct dw_pcie *pci = drvdata; + u32 msb, lsb; + + do { + msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_MASTER_MSB); + lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_MASTER_LSB); + } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_MASTER_MSB)); + + return sysfs_emit(buf, "%llu\n", ((u64) msb) << 32 | lsb); +} + +static ssize_t dw_pcie_ptm_t1_show(void *drvdata, char *buf) +{ + struct dw_pcie *pci = drvdata; + u32 msb, lsb; + + do { + msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_MSB); + lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_LSB); + } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_MSB)); + + return sysfs_emit(buf, "%llu\n", ((u64) msb) << 32 | lsb); +} + +static ssize_t dw_pcie_ptm_t2_show(void *drvdata, char *buf) +{ + struct dw_pcie *pci = drvdata; + u32 msb, lsb; + + do { + msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_MSB); + lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_LSB); + } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_MSB)); + + return sysfs_emit(buf, "%llu\n", ((u64) msb) << 32 | lsb); +} + +static ssize_t dw_pcie_ptm_t3_show(void *drvdata, char *buf) +{ + struct dw_pcie *pci = drvdata; + u32 msb, lsb; + + do { + msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_MSB); + lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_LSB); + } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_MSB)); + + return sysfs_emit(buf, "%llu\n", ((u64) msb) << 32 | lsb); +} + +static ssize_t dw_pcie_ptm_t4_show(void *drvdata, char *buf) +{ + struct dw_pcie *pci = drvdata; + u32 msb, lsb; + + do { + msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_MSB); + lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_LSB); + } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_MSB)); + + return sysfs_emit(buf, "%llu\n", ((u64) msb) << 32 | lsb); +} + +static bool dw_pcie_ptm_context_update_visible(void *drvdata) +{ + struct dw_pcie *pci = drvdata; + + return (pci->mode == DW_PCIE_EP_TYPE) ? true : false; +} + +static bool dw_pcie_ptm_context_valid_visible(void *drvdata) +{ + struct dw_pcie *pci = drvdata; + + return (pci->mode == DW_PCIE_RC_TYPE) ? true : false; +} + +static bool dw_pcie_ptm_local_clock_visible(void *drvdata) +{ + /* PTM local clock is always visible */ + return true; +} + +static bool dw_pcie_ptm_master_clock_visible(void *drvdata) +{ + struct dw_pcie *pci = drvdata; + + return (pci->mode == DW_PCIE_EP_TYPE) ? true : false; +} + +static bool dw_pcie_ptm_t1_visible(void *drvdata) +{ + struct dw_pcie *pci = drvdata; + + return (pci->mode == DW_PCIE_EP_TYPE) ? true : false; +} + +static bool dw_pcie_ptm_t2_visible(void *drvdata) +{ + struct dw_pcie *pci = drvdata; + + return (pci->mode == DW_PCIE_RC_TYPE) ? true : false; +} + +static bool dw_pcie_ptm_t3_visible(void *drvdata) +{ + struct dw_pcie *pci = drvdata; + + return (pci->mode == DW_PCIE_RC_TYPE) ? true : false; +} + +static bool dw_pcie_ptm_t4_visible(void *drvdata) +{ + struct dw_pcie *pci = drvdata; + + return (pci->mode == DW_PCIE_EP_TYPE) ? true : false; +} + +struct pcie_ptm_ops dw_pcie_ptm_ops = { + .check_capability = dw_pcie_ptm_check_capability, + .context_update_store = dw_pcie_ptm_context_update_store, + .context_update_show = dw_pcie_ptm_context_update_show, + .context_valid_store = dw_pcie_ptm_context_valid_store, + .context_valid_show = dw_pcie_ptm_context_valid_show, + .local_clock_show = dw_pcie_ptm_local_clock_show, + .master_clock_show = dw_pcie_ptm_master_clock_show, + .t1_show = dw_pcie_ptm_t1_show, + .t2_show = dw_pcie_ptm_t2_show, + .t3_show = dw_pcie_ptm_t3_show, + .t4_show = dw_pcie_ptm_t4_show, + .context_update_visible = dw_pcie_ptm_context_update_visible, + .context_valid_visible = dw_pcie_ptm_context_valid_visible, + .local_clock_visible = dw_pcie_ptm_local_clock_visible, + .master_clock_visible = dw_pcie_ptm_master_clock_visible, + .t1_visible = dw_pcie_ptm_t1_visible, + .t2_visible = dw_pcie_ptm_t2_visible, + .t3_visible = dw_pcie_ptm_t3_visible, + .t4_visible = dw_pcie_ptm_t4_visible, +}; + +void pcie_designware_sysfs_init(struct dw_pcie *pci, + enum dw_pcie_device_mode mode) +{ + pci->mode = mode; + pcie_ptm_create_sysfs(pci->dev, pci, &dw_pcie_ptm_ops); +} + +void pcie_designware_sysfs_exit(struct dw_pcie *pci) +{ + pcie_ptm_destroy_sysfs(); +} diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 3d1d95d9e38057dd1389e2d57d701ce4f4fa6f7f..1e858c15991f0f87e0711b9a9eec9c44d43fef4b 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -329,6 +329,12 @@ u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci) } EXPORT_SYMBOL_GPL(dw_pcie_find_rasdes_capability); +u16 dw_pcie_find_ptm_capability(struct dw_pcie *pci) +{ + return dw_pcie_find_vsec_capability(pci, dwc_pcie_ptm_vsec_ids); +} +EXPORT_SYMBOL_GPL(dw_pcie_find_ptm_capability); + int dw_pcie_read(void __iomem *addr, int size, u32 *val) { if (!IS_ALIGNED((uintptr_t)addr, size)) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 2d1de81d47b67fc0df941484b1d92d986b2b4dbd..27a729b9c13f17dd635bc2976a0b5d4c7aeff5f9 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -260,6 +260,21 @@ #define PCIE_RAS_DES_EVENT_COUNTER_DATA 0xc +/* PTM register definitions */ +#define PTM_RES_REQ_CTRL 0x8 +#define PTM_RES_CCONTEXT_VALID BIT(0) +#define PTM_REQ_AUTO_UPDATE_ENABLED BIT(0) +#define PTM_REQ_START_UPDATE BIT(1) + +#define PTM_LOCAL_LSB 0x10 +#define PTM_LOCAL_MSB 0x14 +#define PTM_T1_T2_LSB 0x18 +#define PTM_T1_T2_MSB 0x1c +#define PTM_T3_T4_LSB 0x28 +#define PTM_T3_T4_MSB 0x2c +#define PTM_MASTER_LSB 0x38 +#define PTM_MASTER_MSB 0x3c + /* * The default address offset between dbi_base and atu_base. Root controller * drivers are not required to initialize atu_base if the offset matches this @@ -500,6 +515,8 @@ struct dw_pcie { struct reset_control_bulk_data app_rsts[DW_PCIE_NUM_APP_RSTS]; struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; struct gpio_desc *pe_rst; + u16 ptm_vsec_offset; + enum dw_pcie_device_mode mode; bool suspended; struct debugfs_info *debugfs; }; @@ -516,6 +533,7 @@ void dw_pcie_version_detect(struct dw_pcie *pci); u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci); +u16 dw_pcie_find_ptm_capability(struct dw_pcie *pci); int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val); @@ -537,6 +555,9 @@ void dw_pcie_setup(struct dw_pcie *pci); void dw_pcie_iatu_detect(struct dw_pcie *pci); int dw_pcie_edma_detect(struct dw_pcie *pci); void dw_pcie_edma_remove(struct dw_pcie *pci); +void pcie_designware_sysfs_init(struct dw_pcie *pci, + enum dw_pcie_device_mode mode); +void pcie_designware_sysfs_exit(struct dw_pcie *pci); static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) { diff --git a/include/linux/pcie-dwc.h b/include/linux/pcie-dwc.h index 8ff778e7aec0ef60462ea69245c76a91c81b76b9..b15057fa6c0ef1794b72c9279b49787fe56302c4 100644 --- a/include/linux/pcie-dwc.h +++ b/include/linux/pcie-dwc.h @@ -35,4 +35,12 @@ static const struct dwc_pcie_vsec_id dwc_pcie_rasdes_vsec_ids[] = { {} }; +static const struct dwc_pcie_vsec_id dwc_pcie_ptm_vsec_ids[] = { + { .vendor_id = PCI_VENDOR_ID_QCOM, /* EP */ + .vsec_id = 0x03, .vsec_rev = 0x1 }, + { .vendor_id = PCI_VENDOR_ID_QCOM, /* RC */ + .vsec_id = 0x04, .vsec_rev = 0x1 }, + { } +}; + #endif /* LINUX_PCIE_DWC_H */ From patchwork Mon Mar 24 10:04:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 875830 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BECBF19E7D0; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="D6H2RGj5" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6B62CC4CEE4; Mon, 24 Mar 2025 10:04:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742810678; bh=tiFBT4izYq0mO62xpAVSkd1XSTz0IJZxX8Q1ISdVDLc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=D6H2RGj5OEpuVc/lWpqdMEWt0Al65wCk+ZzTtlCq0Uj2B2eUnGeXVw3UKfWVdHzZl rMXzskAK+fMRrN89fRpJD74+kNynbhJzqUx9ISbFbXFKJ75szVhcnBVNO8JIdT8NbC uzs8q/1oLUAqA40aDHZkZQI1ytZHncpOZx9a5o5GUD/ZF8uiFgfTCMSzyae2jjNC/y 6vrMi5jH8qGwv6t7N0OhNXk0oIkzc2woTdr3f8nU8nQSZTKJaVFX2QeLECVSOg5lH8 df6rrz/ND9T1Qmn/hlNUIOXBuDeHFakbruhJXWUACXL9vkUBVId8RqLeUxgOXvagDW a2825xibbDXWQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E22CC3600C; Mon, 24 Mar 2025 10:04:38 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Mon, 24 Mar 2025 15:34:37 +0530 Subject: [PATCH v2 3/3] PCI: qcom-ep: Mask PTM_UPDATING interrupt Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250324-pcie-ptm-v2-3-c7d8c3644b4a@linaro.org> References: <20250324-pcie-ptm-v2-0-c7d8c3644b4a@linaro.org> In-Reply-To: <20250324-pcie-ptm-v2-0-c7d8c3644b4a@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1764; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=S+C5W5xt7FcF/117DRTgds/MCdeKQEYkVZEdwTlTN4o=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBn4S4z77panSiJ5a5utTxcnz9RDExFPZrdJE+t7 7aQw3DzWiCJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZ+EuMwAKCRBVnxHm/pHO 9SkSB/9DzYwUpInvbToiGbQhOXX0ojfZSZ264VjDinBjQJRBMOGDEzY68XUGw5+CTkf7a59LHK9 uoV7eim/pA6woy+3duYaAa4KkaUT/b7Y5u8xiWR1hEOUz1nx5+9KX+eGsEbeBtfzWDgL94wRZ4M VRHwwSR6qG8GWt+Nligg4gQ2ht8qpSALXWZmAHyx8sOLpjMmhpoGnIjf4WKR1TqQYEhQa9Q/dCe zqqneATiXNz639c0YiV/ALUI9BesXSkH8NfuzvLzAfct69WulfFJERGROkE65UshxY8PeJDg23Y WkVdja/Xq2WSHfo9shIhlXw2a6nFrJP8gs7DARwUs6Hzy0mC X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam When PTM is enabled, PTM_UPDATING interrupt will be fired for each PTM context update, which will be once every 10ms in the case of auto context update. Since the interrupt is not strictly needed for making use of PTM, mask it to avoid the overhead of processing it. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index c08f64d7a825fa5da22976c8020f96ee5faa5462..940edb7be1b920840556246613f186769aca4159 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -60,6 +60,7 @@ #define PARF_DEVICE_TYPE 0x1000 #define PARF_BDF_TO_SID_CFG 0x2c00 #define PARF_INT_ALL_5_MASK 0x2dcc +#define PARF_INT_ALL_3_MASK 0x2e18 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ #define PARF_INT_ALL_LINK_DOWN BIT(1) @@ -132,6 +133,9 @@ /* PARF_INT_ALL_5_MASK fields */ #define PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR BIT(0) +/* PARF_INT_ALL_3_MASK fields */ +#define PARF_INT_ALL_3_PTM_UPDATING BIT(4) + /* ELBI registers */ #define ELBI_SYS_STTS 0x08 #define ELBI_CS2_ENABLE 0xa4 @@ -497,6 +501,10 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_5_MASK); } + val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_3_MASK); + val &= ~PARF_INT_ALL_3_PTM_UPDATING; + writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_3_MASK); + ret = dw_pcie_ep_init_registers(&pcie_ep->pci.ep); if (ret) { dev_err(dev, "Failed to complete initialization: %d\n", ret);