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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 01/17] hw/core/cpu: Use size_t for memory_rw_debug len argument Date: Sun, 23 Mar 2025 10:37:13 -0700 Message-ID: <20250323173730.3213964-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Match the prototype of cpu_memory_rw_debug(). Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/hw/core/cpu.h | 2 +- target/sparc/cpu.h | 2 +- target/sparc/mmu_helper.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5d11d26556..abd8764e83 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -154,7 +154,7 @@ struct CPUClass { int (*mmu_index)(CPUState *cpu, bool ifetch); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, - uint8_t *buf, int len, bool is_write); + uint8_t *buf, size_t len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); void (*query_cpu_fast)(CPUState *cpu, CpuInfoFast *value); int64_t (*get_arch_id)(CPUState *cpu); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 462bcb6c0e..68f8c21e7c 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -604,7 +604,7 @@ void dump_mmu(CPUSPARCState *env); #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, - uint8_t *buf, int len, bool is_write); + uint8_t *buf, size_t len, bool is_write); #endif /* translate.c */ diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 7548d01777..3821cd91ec 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -389,7 +389,7 @@ void dump_mmu(CPUSPARCState *env) * that the sparc ABI is followed. */ int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address, - uint8_t *buf, int len, bool is_write) + uint8_t *buf, size_t len, bool is_write) { CPUSPARCState *env = cpu_env(cs); target_ulong addr = address; From patchwork Sun Mar 23 17:37:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 875628 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp1807854wrb; Sun, 23 Mar 2025 10:41:25 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUehWeQaGmrtn4KKJpVbU+pOeRzTRwtG3nclFOr/fqZg+sFkDp8qQXTnwIA5GAs1iUZish6LQ==@linaro.org X-Google-Smtp-Source: AGHT+IFg1SfFz8lDWHroCwc+pxq7VpFhvUXAnMYH5Go0wi/6kFMwIlMBctZy4iSTgsHlnDTwBFyv X-Received: by 2002:a05:622a:1c09:b0:472:1aed:c8b4 with SMTP id d75a77b69052e-4771de60f7bmr194730751cf.34.1742751685031; Sun, 23 Mar 2025 10:41:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742751685; cv=none; d=google.com; s=arc-20240605; b=C7H/H72mzFk4RzbSZ5PuWvuBS+UvMcOHZVCZYeH5lOYURmVIbVpRdRB/7gqAVRRgZ3 A6WvYOintfAIxjaWr2vxLPE6g+J/hTD9UWDLu/ScON69hzPLl2gjzJm1yRA5nSHnQoS3 I9gg80GUJJvPdxpSXYphWrJ33MsWzTlpFgLQEelif9qDy3166m0VJIGWMa/074AA3pRT SiK4mPpmyataqNGXhmJv+OZIdzNVoPi6CQq5GUOLXXmXihk2wmKc+tj23dSzEAUicNJs nxpMEzMd29g0y6q6UgMteIDrld7H/zaG3JNHoqCXaqknjqy4skgyiyXoAu/II3u4o9xA A6xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=n93sFLgifoxtvFypKbIjFGlyxMVTs87sLBcre3AkoOA=; fh=l/LnLMR6RjAGNMCU7GGMle3tRpEScqEsfdBaROYEnBw=; b=AE9NIbGA+svMWGfQygynhy4IaDsQJk+iFJn7SrpZsgw62wByPvm5pWj4PO8KOi75Cq Xc9UwsSuYB6sEE0MtL9iG5PPhJcHAQlS0K5CaTMnd2xqdnJ5YQw/kgAJZVRAajAqlH2M NZLiTyBBvXVTGZkIy43fYKotwLeEc+zKr1Udac086TsiISJ/ntS2mYyWDUvWx6cNFuzS +MloA+k/od4IithT6yoGddGZ25oKtoKs+6E1IF7BhFFt1453He2aSt1FVnbaD89yFLIG 7mjFlQjvhsS2jFkw1+WdjhsWju7NXCPgUvEuHoJ/qD+G3NadWMlTzwcy17M21OLIX3hv GTvA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QFKBLjBA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org, qemu-stable@nongnu.org Subject: [PATCH 02/17] target/avr: Fix buffer read in avr_print_insn Date: Sun, 23 Mar 2025 10:37:14 -0700 Message-ID: <20250323173730.3213964-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Do not unconditionally attempt to read 4 bytes, as there may only be 2 bytes remaining in the translator cache. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/disas.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/target/avr/disas.c b/target/avr/disas.c index b7689e8d7c..d341030174 100644 --- a/target/avr/disas.c +++ b/target/avr/disas.c @@ -68,28 +68,35 @@ static bool decode_insn(DisasContext *ctx, uint16_t insn); int avr_print_insn(bfd_vma addr, disassemble_info *info) { - DisasContext ctx; + DisasContext ctx = { info }; DisasContext *pctx = &ctx; bfd_byte buffer[4]; uint16_t insn; int status; - ctx.info = info; - - status = info->read_memory_func(addr, buffer, 4, info); + status = info->read_memory_func(addr, buffer, 2, info); if (status != 0) { info->memory_error_func(status, addr, info); return -1; } insn = bfd_getl16(buffer); - ctx.next_word = bfd_getl16(buffer + 2); - ctx.next_word_used = false; + + status = info->read_memory_func(addr + 2, buffer + 2, 2, info); + if (status == 0) { + ctx.next_word = bfd_getl16(buffer + 2); + } if (!decode_insn(&ctx, insn)) { output(".db", "0x%02x, 0x%02x", buffer[0], buffer[1]); } - return ctx.next_word_used ? 4 : 2; + if (!ctx.next_word_used) { + return 2; + } else if (status == 0) { + return 4; + } + info->memory_error_func(status, addr + 2, info); + return -1; } From patchwork Sun Mar 23 17:37:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 875631 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp1807882wrb; Sun, 23 Mar 2025 10:41:31 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXJR8i+yX6cRuUSozpbvimiVnuq/PqwMz71AKBHFB9QkZ3zRrZHLTN43vPxTO8KGSzSQ0uK6Q==@linaro.org X-Google-Smtp-Source: AGHT+IGAxJW+O6+kT6py+URdPfeOXkaZnmTMusmhcGDhysSb91xDNU3g0+Z4ogoxEKz7y0+srtek X-Received: by 2002:a05:620a:1788:b0:7c5:5003:81b0 with SMTP id af79cd13be357-7c5ba15c1c4mr1465145385a.23.1742751691473; Sun, 23 Mar 2025 10:41:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742751691; cv=none; d=google.com; s=arc-20240605; b=R/ZLJr9QJ62ZDcKV9Uw8rSldwd7eypzGTvO4/qRY83d503W8eD3TmTg164geIOOohh 77lmGDd3z/5/lB9UlPlCALZ3ctFgpPxYri4eSjfXbN2UCYE9zimukrdgmY6/ACVW08u0 yIqAS+cM7/9QQQxrGX+QKdtktB6vnbB0dP8j4E0OworcWtBFqswO5iJnQ/O8koYegbEQ NzetpZxkltczIemVcfcPTHs9C3Ku0epKa0vMQiZOa1bNvNIdYyGlC8f1DGtDGwOwlQuT e8WA/9+nyqHGVr9MxJy6RoK1pphpfxAvR07ICnU07yTkY7CRa/OTVy8pI2PEjkp0YyzF JBDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YGgDZgK8X2BSYVWSdj2GCRC9iMdojOu2NC7i0DOuuAA=; fh=l/LnLMR6RjAGNMCU7GGMle3tRpEScqEsfdBaROYEnBw=; b=J5I+ULZ6iyMIkVzgRlCfVK+pzLq6goW6t2BMhVboeO3pmkVOEuaftnWxtTMOsmHo3R 0vfP1ypACWwD0wqmgH9HoyU0BmoFE5xn7xNCE/8WYr/R753all/g6R0FjJo8gHYH8ET9 K72ghFPoOiiKSMmPMEQ/ouRgv5d7oX/i2ejjjZIHdcAzMWmKmal4hy2UEeuj7oZccFeM lpCS3x5egQdISFxk+sTJXPUzuTWmYDl0eAkFZ87JqOtS7lAjtk8UqLKvl4NsPcX1LQ3n C4E8tIfreurG/0CZ2QGfDVPT8QeMPxo0VvoURtR3tiPhrFwGFJKKuJ7PwVJcSUY/NqL3 ET2w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vNYqetvc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org, qemu-stable@nongnu.org Subject: [PATCH 03/17] target/avr: Improve decode of LDS, STS Date: Sun, 23 Mar 2025 10:37:15 -0700 Message-ID: <20250323173730.3213964-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The comment about not being able to define a field with zero bits is out of date since 94597b6146f3 ("decodetree: Allow !function with no input bits"). This fixes the missing load of imm in the disassembler. Cc: qemu-stable@nongnu.org Fixes: 9d8caa67a24 ("target/avr: Add support for disassembling via option '-d in_asm'") Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/translate.c | 2 -- target/avr/insn.decode | 7 ++----- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index 4ab71d8138..e7f8ced9b3 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -1578,7 +1578,6 @@ static bool trans_LDS(DisasContext *ctx, arg_LDS *a) TCGv Rd = cpu_r[a->rd]; TCGv addr = tcg_temp_new_i32(); TCGv H = cpu_rampD; - a->imm = next_word(ctx); tcg_gen_mov_tl(addr, H); /* addr = H:M:L */ tcg_gen_shli_tl(addr, addr, 16); @@ -1783,7 +1782,6 @@ static bool trans_STS(DisasContext *ctx, arg_STS *a) TCGv Rd = cpu_r[a->rd]; TCGv addr = tcg_temp_new_i32(); TCGv H = cpu_rampD; - a->imm = next_word(ctx); tcg_gen_mov_tl(addr, H); /* addr = H:M:L */ tcg_gen_shli_tl(addr, addr, 16); diff --git a/target/avr/insn.decode b/target/avr/insn.decode index 482c23ad0c..cc302249db 100644 --- a/target/avr/insn.decode +++ b/target/avr/insn.decode @@ -118,11 +118,8 @@ BRBC 1111 01 ....... ... @op_bit_imm @io_rd_imm .... . .. ..... .... &rd_imm rd=%rd imm=%io_imm @ldst_d .. . . .. . rd:5 . ... &rd_imm imm=%ldst_d_imm -# The 16-bit immediate is completely in the next word. -# Fields cannot be defined with no bits, so we cannot play -# the same trick and append to a zero-bit value. -# Defer reading the immediate until trans_{LDS,STS}. -@ldst_s .... ... rd:5 .... imm=0 +%ldst_imm !function=next_word +@ldst_s .... ... rd:5 .... imm=%ldst_imm MOV 0010 11 . ..... .... @op_rd_rr MOVW 0000 0001 .... .... &rd_rr rd=%rd_d rr=%rr_d From patchwork Sun Mar 23 17:37:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 875620 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp1807090wrb; Sun, 23 Mar 2025 10:38:31 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWiKFX00E/Pj842UcVfDYvZinK/m9RLBvcn26r4+kHAuSJpxvXc63gAPzEMKe0yIkQuZMqQTA==@linaro.org X-Google-Smtp-Source: AGHT+IEwsnmqQbpw/efoBXVrS2vN9TOLbKhoFeT7I/RKbuaR4wEfYZKVZPZKNj+GF6Oqdap7XCKF X-Received: by 2002:a05:620a:179f:b0:7c5:9b2b:83c0 with SMTP id af79cd13be357-7c5ba13403bmr1436127385a.7.1742751511271; Sun, 23 Mar 2025 10:38:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742751511; cv=none; d=google.com; s=arc-20240605; b=BOlyMzs9FPOzNLsLWTp1lOpD/kBtPqRfCa5iwLkPrFDiBJMRGCiVJ5C6KVt+cWw2gh tVtT8ZV4yuNrNfj67T5YKCv24sJFQvvrPRuAM8wST7MYQJUW0AlfQ5ALe8UVda47CWsI /50OmNZVTYlEDwED/ZZe0NXt4Oh8qrwYmSj22YVg1SmFZxvyj0dscthm3KvC7p4weyTa la547Rjfc/i/+cTb6v3q5FbZElSzR0ZKgLtunLC0gXvivtHtESRuCPreFt0mDfzF9aPp O2oamyvN0wq7KTRY5/tezppnVHIorH7SEflNGLeHq+Nd/5KQv9XnbkL3Xhq54Nu2dB1g 0f3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=V9RNNm4TR2xsqepmbMUFAdeBIjBUZTQEvJCdv4fdD0o=; fh=Pq5/+ra/32jR7ARhXA/UPD87Ay4JBQ4WSaLIekKYvL0=; b=X9Al4Hiff8UGKv5qpShyXcNpMR79YSif3dfaZGW0Zt4sAwVhT1IxCK7IrZeVy16deJ YNvlQRF+1d9ucpcIC0lrClpl8//ixY68FD+TY8tt7oYZZEnsRLjBowsB6Wh/Vfixv2Z0 aIbxbJV+Xm6j/tYDJWeZKDtQsrWszoiCBsPkwjMv6j5CmtvG07sTWPHZvgxBp3lsHQ6S g9rIvnDqoeB1z1O9tEiBXCpA2BjXuiUIVIpnT7xPBcytLBCe780X0Id8LRbJeuJCi2LI 9zqAFcV7HANRy0h2gJKwXpggv1OU++QrWCHG9V45SB1QxR+L8J/wb8K6ICI7j3h+jbs3 3ivQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xhJ0pfPC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 04/17] target/avr: Remove OFFSET_CPU_REGISTERS Date: Sun, 23 Mar 2025 10:37:16 -0700 Message-ID: <20250323173730.3213964-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This define isn't really used. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/avr/cpu.h | 2 -- target/avr/helper.c | 3 +-- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 06f5ae4d1b..84a8f5cc8c 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -60,8 +60,6 @@ #define OFFSET_CODE 0x00000000 /* CPU registers, IO registers, and SRAM */ #define OFFSET_DATA 0x00800000 -/* CPU registers specifically, these are mapped at the start of data */ -#define OFFSET_CPU_REGISTERS OFFSET_DATA /* * IO registers, including status register, stack pointer, and memory * mapped peripherals, mapped just after CPU registers diff --git a/target/avr/helper.c b/target/avr/helper.c index 3412312ad5..e5bf16c6b7 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -340,8 +340,7 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr) env->fullacc = false; /* Following logic assumes this: */ - assert(OFFSET_CPU_REGISTERS == OFFSET_DATA); - assert(OFFSET_IO_REGISTERS == OFFSET_CPU_REGISTERS + + assert(OFFSET_IO_REGISTERS == OFFSET_DATA + NUMBER_OF_CPU_REGISTERS); if (addr < NUMBER_OF_CPU_REGISTERS) { From patchwork Sun Mar 23 17:37:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 875630 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp1807856wrb; Sun, 23 Mar 2025 10:41:25 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUVAu96nRECrtqTD2xCZQfkWWh9L3qBgitJFba/HTkZIBsuR2xeNlpLycpw2R1Uf0pgmzhEZQ==@linaro.org X-Google-Smtp-Source: AGHT+IHpWMbSfApd8OFkFhKpxghdh88zPl6gH8U+SVbZhv5tHxhHgWKr2O7o751ckHtiE3hFeVef X-Received: by 2002:a05:620a:1a8e:b0:7c5:562d:cd01 with SMTP id af79cd13be357-7c5ba16245emr1282818885a.16.1742751685092; Sun, 23 Mar 2025 10:41:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742751685; cv=none; d=google.com; s=arc-20240605; b=UQLJBk/xHclcp+Nes3TEQ57yvMoaLMGEHbSASDDsn1Kr+4Q7pX1EHC1iLRc6SnEspO 9Ps6qFzQXPJe5Iay2qvNYbgi6tC4Tm01eMRL8nx/VCTF+zIMmk3hUNPmybLytB0TRqzy Uxa++mPKNh4JxIEQvpbbxvkwjDNzh4A5vYQDmcwawL4U4Gvx0Ni8wYtot2QBPvpKFSe4 S9SyN/jlN8IuK6XWurWrrzlvCAKiR37PqlwVmpvAYfjuWe/1lwgQQjSZvZ//ZBC/VfDu pjaOfcv5OfeJkJlEgq45Ubz5knV0Y+cUIMy74WTzmGhx0a1UIYosVkgpE3I5bTOTrERH +GKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9/Tq8455Xl28q7efQW3SLtflxU6Hj8gr8oQW0BIa1vs=; fh=Pq5/+ra/32jR7ARhXA/UPD87Ay4JBQ4WSaLIekKYvL0=; b=MvwYwiPR5PV/FVm42D1fN4I+Wt/IgBp6lRrZ6OvmkXZkXe6pX4jqxm005rO/X+BsmZ TEOC0cnosEZLhQtRX27I3OlLcbWSsxt9Vg21JR3yHlxxFBlPayiVTqKcmDsNm4pr9sQs YAgnApYd3ErkEQXq9SxeBrvn9bXMOJ6YeMgDtfOFOt5JgT44hnPOMQ510+CToksK5qmy rLhsA+9w01twn3K258BcJqfqLtFmZGXDZwVZjHKKWQzpEW54ifvbE7oWS2uJL5+14Tc0 NJORSvApwHjZqTIP+wFJWlYmkLNesRlpcsAIZ9sCrvkFOiGEXiOzTBsgTG31pIM9B0yb jefg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BuMIbuMu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 05/17] target/avr: Move cpu register accesses into system memory Date: Sun, 23 Mar 2025 10:37:17 -0700 Message-ID: <20250323173730.3213964-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Integrate the i/o 0x00-0x1f and 0x38-0x3f loopbacks into the cpu registers with normal address space accesses. We no longer need to trap accesses to the first page within avr_cpu_tlb_fill but can wait until a write occurs. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/cpu.h | 7 ++ target/avr/helper.h | 3 - target/avr/cpu.c | 16 +++ target/avr/helper.c | 239 +++++++++++++++++------------------------ target/avr/translate.c | 42 ++++---- 5 files changed, 146 insertions(+), 161 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 84a8f5cc8c..be27b0152b 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -23,6 +23,7 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/memory.h" #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" @@ -142,6 +143,9 @@ struct ArchCPU { CPUAVRState env; + MemoryRegion cpu_reg1; + MemoryRegion cpu_reg2; + /* Initial value of stack pointer */ uint32_t init_sp; }; @@ -242,6 +246,9 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +extern const MemoryRegionOps avr_cpu_reg1; +extern const MemoryRegionOps avr_cpu_reg2; + #include "exec/cpu-all.h" #endif /* QEMU_AVR_CPU_H */ diff --git a/target/avr/helper.h b/target/avr/helper.h index 4d02e648fa..e8d13e925f 100644 --- a/target/avr/helper.h +++ b/target/avr/helper.h @@ -23,7 +23,4 @@ DEF_HELPER_1(debug, noreturn, env) DEF_HELPER_1(break, noreturn, env) DEF_HELPER_1(sleep, noreturn, env) DEF_HELPER_1(unsupported, noreturn, env) -DEF_HELPER_3(outb, void, env, i32, i32) -DEF_HELPER_2(inb, tl, env, i32) DEF_HELPER_3(fullwr, void, env, i32, i32) -DEF_HELPER_2(fullrd, tl, env, i32) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 834c7082aa..0b14b36c17 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -23,6 +23,7 @@ #include "qemu/qemu-print.h" #include "exec/exec-all.h" #include "exec/translation-block.h" +#include "exec/address-spaces.h" #include "cpu.h" #include "disas/dis-asm.h" #include "tcg/debug-assert.h" @@ -110,6 +111,8 @@ static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) static void avr_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); + CPUAVRState *env = cpu_env(cs); + AVRCPU *cpu = env_archcpu(env); AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev); Error *local_err = NULL; @@ -122,6 +125,19 @@ static void avr_cpu_realizefn(DeviceState *dev, Error **errp) cpu_reset(cs); mcc->parent_realize(dev, errp); + + /* + * Two blocks in the low data space loop back into cpu registers. + */ + memory_region_init_io(&cpu->cpu_reg1, OBJECT(cpu), &avr_cpu_reg1, env, + "avr-cpu-reg1", 32); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA, &cpu->cpu_reg1); + + memory_region_init_io(&cpu->cpu_reg2, OBJECT(cpu), &avr_cpu_reg2, env, + "avr-cpu-reg2", 8); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA + 0x58, &cpu->cpu_reg2); } static void avr_cpu_set_int(void *opaque, int irq, int level) diff --git a/target/avr/helper.c b/target/avr/helper.c index e5bf16c6b7..df7e2109d4 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -108,7 +108,7 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - int prot, page_size = TARGET_PAGE_SIZE; + int prot; uint32_t paddr; address &= TARGET_PAGE_MASK; @@ -133,23 +133,9 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, /* Access to memory. */ paddr = OFFSET_DATA + address; prot = PAGE_READ | PAGE_WRITE; - if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* - * Access to CPU registers, exit and rebuilt this TB to use - * full access in case it touches specially handled registers - * like SREG or SP. For probing, set page_size = 1, in order - * to force tlb_fill to be called for the next access. - */ - if (probe) { - page_size = 1; - } else { - cpu_env(cs)->fullacc = 1; - cpu_loop_exit_restore(cs, retaddr); - } - } } - tlb_set_page(cs, address, paddr, prot, mmu_idx, page_size); + tlb_set_page(cs, address, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); return true; } @@ -203,134 +189,78 @@ void helper_wdr(CPUAVRState *env) } /* - * This function implements IN instruction - * - * It does the following - * a. if an IO register belongs to CPU, its value is read and returned - * b. otherwise io address is translated to mem address and physical memory - * is read. - * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation - * + * The first 32 bytes of the data space are mapped to the cpu regs. + * We cannot write these from normal store operations because TCG + * does not expect global temps to be modified -- a global may be + * live in a host cpu register across the store. We can however + * read these, as TCG does make sure the global temps are saved + * in case the load operation traps. */ -target_ulong helper_inb(CPUAVRState *env, uint32_t port) + +static uint64_t avr_cpu_reg1_read(void *opaque, hwaddr addr, unsigned size) { - target_ulong data = 0; + CPUAVRState *env = opaque; - switch (port) { - case 0x38: /* RAMPD */ - data = 0xff & (env->rampD >> 16); - break; - case 0x39: /* RAMPX */ - data = 0xff & (env->rampX >> 16); - break; - case 0x3a: /* RAMPY */ - data = 0xff & (env->rampY >> 16); - break; - case 0x3b: /* RAMPZ */ - data = 0xff & (env->rampZ >> 16); - break; - case 0x3c: /* EIND */ - data = 0xff & (env->eind >> 16); - break; - case 0x3d: /* SPL */ - data = env->sp & 0x00ff; - break; - case 0x3e: /* SPH */ - data = env->sp >> 8; - break; - case 0x3f: /* SREG */ - data = cpu_get_sreg(env); - break; - default: - /* not a special register, pass to normal memory access */ - data = address_space_ldub(&address_space_memory, - OFFSET_IO_REGISTERS + port, - MEMTXATTRS_UNSPECIFIED, NULL); - } - - return data; + assert(addr < 32); + return env->r[addr]; } /* - * This function implements OUT instruction - * - * It does the following - * a. if an IO register belongs to CPU, its value is written into the register - * b. otherwise io address is translated to mem address and physical memory - * is written. - * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation - * + * The range 0x58-0x5f of the data space are mapped to cpu regs. + * As above, we cannot write these from normal store operations. */ -void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data) -{ - data &= 0x000000ff; - switch (port) { - case 0x38: /* RAMPD */ - if (avr_feature(env, AVR_FEATURE_RAMPD)) { - env->rampD = (data & 0xff) << 16; - } - break; - case 0x39: /* RAMPX */ - if (avr_feature(env, AVR_FEATURE_RAMPX)) { - env->rampX = (data & 0xff) << 16; - } - break; - case 0x3a: /* RAMPY */ - if (avr_feature(env, AVR_FEATURE_RAMPY)) { - env->rampY = (data & 0xff) << 16; - } - break; - case 0x3b: /* RAMPZ */ - if (avr_feature(env, AVR_FEATURE_RAMPZ)) { - env->rampZ = (data & 0xff) << 16; - } - break; - case 0x3c: /* EIDN */ - env->eind = (data & 0xff) << 16; - break; - case 0x3d: /* SPL */ - env->sp = (env->sp & 0xff00) | (data); - break; - case 0x3e: /* SPH */ - if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { - env->sp = (env->sp & 0x00ff) | (data << 8); - } - break; - case 0x3f: /* SREG */ - cpu_set_sreg(env, data); - break; - default: - /* not a special register, pass to normal memory access */ - address_space_stb(&address_space_memory, OFFSET_IO_REGISTERS + port, - data, MEMTXATTRS_UNSPECIFIED, NULL); +static uint64_t avr_cpu_reg2_read(void *opaque, hwaddr addr, unsigned size) +{ + CPUAVRState *env = opaque; + + switch (addr) { + case 0: /* RAMPD */ + return 0xff & (env->rampD >> 16); + case 1: /* RAMPX */ + return 0xff & (env->rampX >> 16); + case 2: /* RAMPY */ + return 0xff & (env->rampY >> 16); + case 3: /* RAMPZ */ + return 0xff & (env->rampZ >> 16); + case 4: /* EIND */ + return 0xff & (env->eind >> 16); + case 5: /* SPL */ + return env->sp & 0x00ff; + case 6: /* SPH */ + return 0xff & (env->sp >> 8); + case 7: /* SREG */ + return cpu_get_sreg(env); } + g_assert_not_reached(); } -/* - * this function implements LD instruction when there is a possibility to read - * from a CPU register - */ -target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr) +static void avr_cpu_trap_write(void *opaque, hwaddr addr, + uint64_t data64, unsigned size) { - uint8_t data; + CPUAVRState *env = opaque; + CPUState *cs = env_cpu(env); - env->fullacc = false; - - if (addr < NUMBER_OF_CPU_REGISTERS) { - /* CPU registers */ - data = env->r[addr]; - } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* IO registers */ - data = helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS); - } else { - /* memory */ - data = address_space_ldub(&address_space_memory, OFFSET_DATA + addr, - MEMTXATTRS_UNSPECIFIED, NULL); - } - return data; + env->fullacc = true; + cpu_loop_exit_restore(cs, cs->mem_io_pc); } +const MemoryRegionOps avr_cpu_reg1 = { + .read = avr_cpu_reg1_read, + .write = avr_cpu_trap_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid.min_access_size = 1, + .valid.max_access_size = 1, +}; + +const MemoryRegionOps avr_cpu_reg2 = { + .read = avr_cpu_reg2_read, + .write = avr_cpu_trap_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid.min_access_size = 1, + .valid.max_access_size = 1, +}; + /* * this function implements ST instruction when there is a possibility to write * into a CPU register @@ -339,19 +269,50 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr) { env->fullacc = false; - /* Following logic assumes this: */ - assert(OFFSET_IO_REGISTERS == OFFSET_DATA + - NUMBER_OF_CPU_REGISTERS); - - if (addr < NUMBER_OF_CPU_REGISTERS) { + switch (addr) { + case 0 ... 31: /* CPU registers */ env->r[addr] = data; - } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* IO registers */ - helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data); - } else { - /* memory */ + break; + + case 0x58: /* RAMPD */ + if (avr_feature(env, AVR_FEATURE_RAMPD)) { + env->rampD = data << 16; + } + break; + case 0x59: /* RAMPX */ + if (avr_feature(env, AVR_FEATURE_RAMPX)) { + env->rampX = data << 16; + } + break; + case 0x5a: /* RAMPY */ + if (avr_feature(env, AVR_FEATURE_RAMPY)) { + env->rampY = data << 16; + } + break; + case 0x5b: /* RAMPZ */ + if (avr_feature(env, AVR_FEATURE_RAMPZ)) { + env->rampZ = data << 16; + } + break; + case 0x5c: /* EIDN */ + env->eind = data << 16; + break; + case 0x5d: /* SPL */ + env->sp = (env->sp & 0xff00) | data; + break; + case 0x5e: /* SPH */ + if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { + env->sp = (env->sp & 0x00ff) | (data << 8); + } + break; + case 0x5f: /* SREG */ + cpu_set_sreg(env, data); + break; + + default: address_space_stb(&address_space_memory, OFFSET_DATA + addr, data, MEMTXATTRS_UNSPECIFIED, NULL); + break; } } diff --git a/target/avr/translate.c b/target/avr/translate.c index e7f8ced9b3..0490936cd5 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -194,6 +194,9 @@ static bool avr_have_feature(DisasContext *ctx, int feature) static bool decode_insn(DisasContext *ctx, uint16_t insn); #include "decode-insn.c.inc" +static void gen_inb(DisasContext *ctx, TCGv data, int port); +static void gen_outb(DisasContext *ctx, TCGv data, int port); + /* * Arithmetic Instructions */ @@ -1293,9 +1296,8 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a) static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) { TCGv data = tcg_temp_new_i32(); - TCGv port = tcg_constant_i32(a->reg); - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, 1 << a->bit); ctx->skip_cond = TCG_COND_EQ; ctx->skip_var0 = data; @@ -1311,9 +1313,8 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a) { TCGv data = tcg_temp_new_i32(); - TCGv port = tcg_constant_i32(a->reg); - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, 1 << a->bit); ctx->skip_cond = TCG_COND_NE; ctx->skip_var0 = data; @@ -1502,11 +1503,18 @@ static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr) static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) { - if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { - gen_helper_fullrd(data, tcg_env, addr); - } else { - tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); - } + tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); +} + +static void gen_inb(DisasContext *ctx, TCGv data, int port) +{ + gen_data_load(ctx, data, tcg_constant_i32(port + NUMBER_OF_CPU_REGISTERS)); +} + +static void gen_outb(DisasContext *ctx, TCGv data, int port) +{ + gen_helper_fullwr(tcg_env, data, + tcg_constant_i32(port + NUMBER_OF_CPU_REGISTERS)); } /* @@ -2126,9 +2134,8 @@ static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a) static bool trans_IN(DisasContext *ctx, arg_IN *a) { TCGv Rd = cpu_r[a->rd]; - TCGv port = tcg_constant_i32(a->imm); - gen_helper_inb(Rd, tcg_env, port); + gen_inb(ctx, Rd, a->imm); return true; } @@ -2139,9 +2146,8 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a) static bool trans_OUT(DisasContext *ctx, arg_OUT *a) { TCGv Rd = cpu_r[a->rd]; - TCGv port = tcg_constant_i32(a->imm); - gen_helper_outb(tcg_env, port, Rd); + gen_outb(ctx, Rd, a->imm); return true; } @@ -2407,11 +2413,10 @@ static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a) static bool trans_SBI(DisasContext *ctx, arg_SBI *a) { TCGv data = tcg_temp_new_i32(); - TCGv port = tcg_constant_i32(a->reg); - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_ori_tl(data, data, 1 << a->bit); - gen_helper_outb(tcg_env, port, data); + gen_outb(ctx, data, a->reg); return true; } @@ -2422,11 +2427,10 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a) static bool trans_CBI(DisasContext *ctx, arg_CBI *a) { TCGv data = tcg_temp_new_i32(); - TCGv port = tcg_constant_i32(a->reg); - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, ~(1 << a->bit)); - gen_helper_outb(tcg_env, port, data); + gen_outb(ctx, data, a->reg); return true; } From patchwork Sun Mar 23 17:37:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 875622 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp1807140wrb; Sun, 23 Mar 2025 10:38:40 -0700 (PDT) X-Forwarded-Encrypted: i=2; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 06/17] target/avr: Use cpu_stb_mmuidx_ra in helper_fullwr Date: Sun, 23 Mar 2025 10:37:18 -0700 Message-ID: <20250323173730.3213964-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Avoid direct use of address_space_memory. Make use of the softmmu cache of the i/o page. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/helper.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/avr/helper.c b/target/avr/helper.c index df7e2109d4..7cfd3d1093 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -23,10 +23,10 @@ #include "qemu/error-report.h" #include "cpu.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/getpc.h" #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" -#include "exec/address-spaces.h" #include "exec/helper-proto.h" bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) @@ -67,6 +67,11 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } +static void do_stb(CPUAVRState *env, uint32_t addr, uint8_t data, uintptr_t ra) +{ + cpu_stb_mmuidx_ra(env, addr, data, MMU_DATA_IDX, ra); +} + void avr_cpu_do_interrupt(CPUState *cs) { CPUAVRState *env = cpu_env(cs); @@ -311,8 +316,7 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr) break; default: - address_space_stb(&address_space_memory, OFFSET_DATA + addr, data, - MEMTXATTRS_UNSPECIFIED, NULL); + do_stb(env, addr, data, GETPC()); break; } } From patchwork Sun Mar 23 17:37:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 875619 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp1807054wrb; Sun, 23 Mar 2025 10:38:20 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUWLhabsMKXq1mtgYZ3Ku6GYmSmMHBNuYH5sZ93DdM2bBVsJv+cXn8DxwZQGKSzTpq6005ZbQ==@linaro.org X-Google-Smtp-Source: AGHT+IE+CewLjP+IfGNiGlMMHqfNhj4rnPrXC24iTchXyQMmNuYSbPW7eBSjgADLd/aMtQni1piZ X-Received: by 2002:a05:620a:22b3:b0:7c5:a424:1f67 with SMTP id af79cd13be357-7c5ba184095mr1028041485a.29.1742751500432; Sun, 23 Mar 2025 10:38:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742751500; cv=none; d=google.com; s=arc-20240605; b=Za9rYG8yduyO5SNWMbHOqOPjxY8u+pOWu0RNK32oId1HRH2Z+Nia3fAExdLBYMnJLu qWmpfzusU8fP5xtmZ97AvRvnr7s+iBimJsxbFBkJcmAowEkdFn1QEGGYVAHOKy13PFZ6 PR8zYV4mGPU9E2kqxfw6p+1zrNBa2rkW7fOwAD05weBLnW56bRBwdDjHojG1rq22loEc oB146HRR1yH9U+7NkTxVQl1QTgAgq8lBhd+pyjSDprKWNMQskBv+rD4MUOeLBlc+WSG0 owQ1i4v0hjT+/BNE6KQjyR93k4uo2sW+xGGJtxRcUXioUgCJS+AXcLZhELPj1o1O3miU c8Sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=kuaWE3TjFjqiJm1M4aj1btd/FSbEJW/CWHj5+bscQKY=; fh=Pq5/+ra/32jR7ARhXA/UPD87Ay4JBQ4WSaLIekKYvL0=; b=DO1WHyoYr2gLBMokLGzW0BqIjbEqITy24XqeJ0YfxE5X+hjbK+1XWrUpGTMjnZ9tjN K1Fq0HMdaDb0rMP4HVRfPKmfR6fGBwLchGqwWSzSktRvkFORALRBUsuYFtuX/SmRR3bX OJEmwNwuQ2fdgsaP3iRuWzUl5RWVUdwyWQh2BjJz6cnKxDml9RwAoyRLqqwyoqXDqATc DGetBcAvotoBTiBgKpOXuOjlIZM/VQfbOUHreyOdu1UrHVsSocXrAqjvVXtnEPR5OXeB aGyzv+zXVpHpMAKGWPi2lVBv6lD9vrG50Ajbgzveab+bNnixt3fLLkw/WQt0fgHCebdz A6Rw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XA7+3wFz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 07/17] target/avr: Use do_stb in avr_cpu_do_interrupt Date: Sun, 23 Mar 2025 10:37:19 -0700 Message-ID: <20250323173730.3213964-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/avr/helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/avr/helper.c b/target/avr/helper.c index 7cfd3d1093..9608e59584 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -88,14 +88,14 @@ void avr_cpu_do_interrupt(CPUState *cs) } if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { - cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); - cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); - cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16); + do_stb(env, env->sp--, ret, 0); + do_stb(env, env->sp--, ret >> 8, 0); + do_stb(env, env->sp--, ret >> 16, 0); } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) { - cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); - cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); + do_stb(env, env->sp--, ret, 0); + do_stb(env, env->sp--, ret >> 8, 0); } else { - cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); + do_stb(env, env->sp--, ret, 0); } env->pc_w = base + vector * size; From patchwork Sun Mar 23 17:37:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 875617 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp1806989wrb; Sun, 23 Mar 2025 10:38:06 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW1p/pUbMHKOqMSbvw7YsxAlGYDeiwigB7vZ8fplA66ab82/0UTJJZEMI+fu1dhsjgkG8LIyw==@linaro.org X-Google-Smtp-Source: AGHT+IHUhbsVuukJN51BKo6oKIyjW/oNLWEfLXzpjaw1tQevZiKIuwagFBbnDVNfw0dbwxNvEVmz X-Received: by 2002:a05:622a:1f0a:b0:476:a74d:f23b with SMTP id d75a77b69052e-4771de62897mr172595461cf.48.1742751486494; Sun, 23 Mar 2025 10:38:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742751486; cv=none; d=google.com; s=arc-20240605; b=aU865XVBg/bu9zHWspytx9/EqR2BUXfa4s7GdRnT2anrowhNh0P60PQATYCapgbRYf vM+GaJw2lExNQMsOfTObblHs9epLTpGPRTUJ6dTAp+pFdbnGNytmOlZOxUt2BAxXUGkL fwCLbS2ULyK1uCrdopQ/sSmDVizXmMZR+FZr34pPATqLb9sXjchzXJLHfOlNPUHsdGd4 IA0itgLnvQGvyY6iaVt2EETExiLDssFIVSrYQLj51jNIkMULu4JAL24KpDbUFpmyzWL9 DC2P3mUCEyuiFjhw0AOd8PwAIaAGzdRrlxxLnlLNtDwFLXkr8DUDb4mwk7TK3WjRYg1O p2Lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rA9BN8KH+TQHBF8y80g6NTHRuQA2RHpbRpcidozR5So=; fh=Pq5/+ra/32jR7ARhXA/UPD87Ay4JBQ4WSaLIekKYvL0=; b=Ex8T+U5GaE8Q2bmAa94QTxcCnU1DrIfKjSrDSNoDz1XSsR07EXh0e0ZohpmBdIQG8T apnExVUjBeZOR7gTVlxBn8jqDymPMmYnEqC2I2tPewLsY47ynJrTZB23NwFj64g7U6ww GOc8TBp4aVgTOgjRNNfSQdCVH7UylDYFWrUYS+1eLQw05vpIKaLc3KJYf16LEIqUN9dX CjoGLNqp6zqDmYEKC14SS8hfdcUzZlGozJefhjMEo8VWpkhgc+MHeI422IW+omOmkh41 ZJzAeLoW4dOapiz6UYFZUDXQKnA7gVXJHfpMWqPZi9lzrVmt6yBGlkHpOZbDX8kFbU4p ZzWA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mf1Z64jO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 08/17] target/avr: Add offset-io cpu property Date: Sun, 23 Mar 2025 10:37:20 -0700 Message-ID: <20250323173730.3213964-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Communicate the offset of io within the first page between the board, the cpu, and the translator. So far this is always 0. This will be used to optimize memory layout. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/cpu.h | 2 ++ hw/avr/atmega.c | 2 ++ target/avr/cpu.c | 1 + target/avr/translate.c | 2 ++ 4 files changed, 7 insertions(+) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index be27b0152b..0f5e1a53bc 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -148,6 +148,8 @@ struct ArchCPU { /* Initial value of stack pointer */ uint32_t init_sp; + /* Offset of the beginning of I/O within the first page. */ + uint32_t offset_io; }; /** diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index f6844bf118..273582b8af 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -236,6 +236,8 @@ static void atmega_realize(DeviceState *dev, Error **errp) object_property_set_uint(OBJECT(&s->cpu), "init-sp", mc->io_size + mc->sram_size - 1, &error_abort); + object_property_set_uint(OBJECT(&s->cpu), "offset-io", + 0, &error_abort); qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); cpudev = DEVICE(&s->cpu); diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 0b14b36c17..080f6f30d3 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -169,6 +169,7 @@ static void avr_cpu_initfn(Object *obj) static const Property avr_cpu_properties[] = { DEFINE_PROP_UINT32("init-sp", AVRCPU, init_sp, 0), + DEFINE_PROP_UINT32("offset-io", AVRCPU, offset_io, 0), }; static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) diff --git a/target/avr/translate.c b/target/avr/translate.c index 0490936cd5..e9fef1aaad 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -92,6 +92,7 @@ struct DisasContext { /* Routine used to access memory */ int memidx; + uint32_t offset_io; /* * some AVR instructions can make the following instruction to be skipped @@ -2664,6 +2665,7 @@ static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->cs = cs; ctx->env = cpu_env(cs); ctx->npc = ctx->base.pc_first / 2; + ctx->offset_io = env_archcpu(ctx->env)->offset_io; ctx->skip_cond = TCG_COND_NEVER; if (tb_flags & TB_FLAGS_SKIP) { From patchwork Sun Mar 23 17:37:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 875621 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp1807091wrb; Sun, 23 Mar 2025 10:38:31 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXfwfB3jnWLTa3tv8hv9sbIOc2Vy1bilWdc7d6P4hHSbHZ8grP7kLJ3tG5TKr5xHgxP5R25mQ==@linaro.org X-Google-Smtp-Source: AGHT+IHNDAl+lv21LM2yUaOtAGvo8kF4Z/+zRTAJgfwlw7WDbhQ0RwH2DhRv3R8+m2712Xb2aHze X-Received: by 2002:a05:622a:4247:b0:476:b783:c94b with SMTP id d75a77b69052e-4771de421c6mr146965201cf.40.1742751511329; Sun, 23 Mar 2025 10:38:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742751511; cv=none; d=google.com; s=arc-20240605; b=L35RZqC7r4zY5ng54e0dVTQmWDpOEX4R4Os7GNAu0Yi0siqnUjjgmUAQRedx8OOW6H YTT96pz4bGwpz8E5NNfwFwYxaEN/sFUj5V56+MHlIPaDO8b9IhldsnE24VHDoHKBJvgX 7Ux4ASwAo4SCIWVqs7VS0v0r9pKst0Avy2LO1F4YIJ/jfQP5A3KmzVLsTgS+u0dhv9C/ a14a98CVTSnicURiKT5kqSNiwdKOmnxgbl4ekAQXCp2m9v6CxuopTY0z7CBv7DsF/Td+ bY7TbKr75GdoOu6ks3FieDmDMpmYU7ajxhXwiSpILGFhVkUM0S874SyNkvEYdQA0ZZP+ YREg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mKxBSROc4fhAqj5Wcj6941rZxM/sEBCStnSlK0YH6kE=; fh=Pq5/+ra/32jR7ARhXA/UPD87Ay4JBQ4WSaLIekKYvL0=; b=iCkdcPYXa4FYpDxbYH8Toa2MXMdYI1c180V3HuHj3xm3Z73gNIxdkQr8oLMfQ5FQWY bP1SyAx7nRzFpfnXMCOuUwBIZLrxwMnnFIwcr+sLaJ8gzWmAhCoJ9jcLY7des65mDq8A /O4lUczpviVU+QibFFV23mR+Rc/f7Fj3w0KnUX9O/W9XQUI5/4ONGDw8ETfobgB7M5Ki rxPfJACrwfPt3RfgF9nWVs6xBTi2CMTjeRG9IzNSwRtkBxWkECxnYcDceeoU3KAthuT1 81vqyVtl1/cPnojpYPmcORKcWCTcSCFm8FDsn8yWwDyRN64crbEEW+lWi17r1x+BfYvA MPsQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BSCOsNn+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 09/17] target/avr: Introduce gen_data_{load,store}_raw Date: Sun, 23 Mar 2025 10:37:21 -0700 Message-ID: <20250323173730.3213964-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Prepare for offset_io being non-zero; also allow folding stack pointer offsets into the arithmetic. So far, all offsets are 0. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/translate.c | 42 ++++++++++++++++++++++++++++++++---------- 1 file changed, 32 insertions(+), 10 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index e9fef1aaad..6bb4154dff 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -198,6 +198,28 @@ static bool decode_insn(DisasContext *ctx, uint16_t insn); static void gen_inb(DisasContext *ctx, TCGv data, int port); static void gen_outb(DisasContext *ctx, TCGv data, int port); +static void gen_data_store_raw(DisasContext *ctx, TCGv data, + TCGv addr, int offset, MemOp mop) +{ + if (ctx->offset_io + offset) { + TCGv t = tcg_temp_new(); + tcg_gen_addi_tl(t, addr, ctx->offset_io + offset); + addr = t; + } + tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, mop); +} + +static void gen_data_load_raw(DisasContext *ctx, TCGv data, + TCGv addr, int offset, MemOp mop) +{ + if (ctx->offset_io + offset) { + TCGv t = tcg_temp_new(); + tcg_gen_addi_tl(t, addr, ctx->offset_io + offset); + addr = t; + } + tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, mop); +} + /* * Arithmetic Instructions */ @@ -940,21 +962,21 @@ static void gen_push_ret(DisasContext *ctx, int ret) if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { TCGv t0 = tcg_constant_i32(ret & 0x0000ff); - tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB); + gen_data_store_raw(ctx, t0, cpu_sp, 0, MO_UB); tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { TCGv t0 = tcg_constant_i32(ret & 0x00ffff); tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); - tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW); + gen_data_store_raw(ctx, t0, cpu_sp, 0, MO_BEUW); tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { TCGv lo = tcg_constant_i32(ret & 0x0000ff); TCGv hi = tcg_constant_i32((ret & 0xffff00) >> 8); - tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB); + gen_data_store_raw(ctx, lo, cpu_sp, 0, MO_UB); tcg_gen_subi_tl(cpu_sp, cpu_sp, 2); - tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW); + gen_data_store_raw(ctx, hi, cpu_sp, 0, MO_BEUW); tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); } } @@ -963,20 +985,20 @@ static void gen_pop_ret(DisasContext *ctx, TCGv ret) { if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); - tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB); + gen_data_load_raw(ctx, ret, cpu_sp, 0, MO_UB); } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); - tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW); + gen_data_load_raw(ctx, ret, cpu_sp, 0, MO_BEUW); tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { TCGv lo = tcg_temp_new_i32(); TCGv hi = tcg_temp_new_i32(); tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); - tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW); + gen_data_load_raw(ctx, hi, cpu_sp, 0, MO_BEUW); tcg_gen_addi_tl(cpu_sp, cpu_sp, 2); - tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB); + gen_data_load_raw(ctx, lo, cpu_sp, 0, MO_UB); tcg_gen_deposit_tl(ret, lo, hi, 8, 16); } @@ -1498,13 +1520,13 @@ static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr) if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { gen_helper_fullwr(tcg_env, data, addr); } else { - tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, MO_UB); + gen_data_store_raw(ctx, data, addr, 0, MO_UB); } } static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) { - tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); + gen_data_load_raw(ctx, data, addr, 0, MO_UB); } static void gen_inb(DisasContext *ctx, TCGv data, int port) From patchwork Sun Mar 23 17:37:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 875634 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp1808535wrb; Sun, 23 Mar 2025 10:44:13 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVblgkWBfyG0ZrN5xvAKVX6F0mCgFjiGinyA8mEoUsa8cpH4QPh9QUOtBwcvAUG8bWxMavQrg==@linaro.org X-Google-Smtp-Source: AGHT+IFqjr995Cy7BpxryRSgfVgM0WKVla1ZaZY2rTp7HeqGYVXh7NXVLl3CnMIERSblkrAoHT6P X-Received: by 2002:a05:6214:5099:b0:6d1:7433:3670 with SMTP id 6a1803df08f44-6eb3f284a82mr137691716d6.4.1742751853682; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 10/17] target/avr: Update cpu_sp after push and pop Date: Sun, 23 Mar 2025 10:37:22 -0700 Message-ID: <20250323173730.3213964-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Not that AVR has memory paging traps, but it's better form to allow the memory operation to finish before updating the cpu register. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/translate.c | 32 +++++++++++++++----------------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index 6bb4154dff..3446007be1 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -967,40 +967,38 @@ static void gen_push_ret(DisasContext *ctx, int ret) } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { TCGv t0 = tcg_constant_i32(ret & 0x00ffff); - tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); - gen_data_store_raw(ctx, t0, cpu_sp, 0, MO_BEUW); - tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); + gen_data_store_raw(ctx, t0, cpu_sp, -1, MO_BEUW); + tcg_gen_subi_tl(cpu_sp, cpu_sp, 2); } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { TCGv lo = tcg_constant_i32(ret & 0x0000ff); TCGv hi = tcg_constant_i32((ret & 0xffff00) >> 8); gen_data_store_raw(ctx, lo, cpu_sp, 0, MO_UB); - tcg_gen_subi_tl(cpu_sp, cpu_sp, 2); - gen_data_store_raw(ctx, hi, cpu_sp, 0, MO_BEUW); - tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); + gen_data_store_raw(ctx, hi, cpu_sp, -2, MO_BEUW); + tcg_gen_subi_tl(cpu_sp, cpu_sp, 3); + } else { + g_assert_not_reached(); } } static void gen_pop_ret(DisasContext *ctx, TCGv ret) { if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { + gen_data_load_raw(ctx, ret, cpu_sp, 1, MO_UB); tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); - gen_data_load_raw(ctx, ret, cpu_sp, 0, MO_UB); } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { - tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); - gen_data_load_raw(ctx, ret, cpu_sp, 0, MO_BEUW); - tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); + gen_data_load_raw(ctx, ret, cpu_sp, 1, MO_BEUW); + tcg_gen_addi_tl(cpu_sp, cpu_sp, 2); } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { - TCGv lo = tcg_temp_new_i32(); TCGv hi = tcg_temp_new_i32(); - tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); - gen_data_load_raw(ctx, hi, cpu_sp, 0, MO_BEUW); + gen_data_load_raw(ctx, hi, cpu_sp, 1, MO_BEUW); + gen_data_load_raw(ctx, ret, cpu_sp, 3, MO_UB); + tcg_gen_addi_tl(cpu_sp, cpu_sp, 3); - tcg_gen_addi_tl(cpu_sp, cpu_sp, 2); - gen_data_load_raw(ctx, lo, cpu_sp, 0, MO_UB); - - tcg_gen_deposit_tl(ret, lo, hi, 8, 16); + tcg_gen_deposit_tl(ret, ret, hi, 8, 16); + } else { + g_assert_not_reached(); } } From patchwork Sun Mar 23 17:37:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 875623 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp1807235wrb; Sun, 23 Mar 2025 10:39:01 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUX/g+HcF/6Z69CyM343trRkQQ5d1yfuhTlW4C+MdXyRb0/v1f6ErBWcejOg9N6ZFUZV1aUfw==@linaro.org X-Google-Smtp-Source: AGHT+IF+JHciII74UnucsEeWdLGeCqMcrjpl7rKxTipEYxiDhMQDBO+6Z4g5znt8rxHcVYE0FHJC X-Received: by 2002:a05:622a:a018:b0:477:1edc:fb0f with SMTP id d75a77b69052e-4771edcffd3mr121140231cf.0.1742751541423; Sun, 23 Mar 2025 10:39:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742751541; cv=none; d=google.com; s=arc-20240605; b=NUPWEvsVzs7KQyufO26QwuJGKlTXz/1U80nkdo7evfDD/yCpCJ9GQA6Ef+zXfMfAEK f+Ls7MXPNuNm3qe0+xMnijbnWOngCnyS+yqJceiF0W0oMJckl14/oZh7VLN8pq/IKZNX oTchwbswJqokbMER2c+3kthzT2xyLUvmCKISD9BeRajTZ09ZneUn/iXIdEEOlj8D1pe1 mGQIV5Ul7ckyBaLsofL7SYy/+XFeaq/A52sBRIWaA1p5NjcaHgJxPKHbTEtUpo9lPkg9 4HIewhG+fSXsibz9mZVKE+pgiWoRxRKIWnjavHDDeQ4yO4Nrd4FUVKhAgSuTEXcpLt3M tN8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oGR007VvjFffVl8PvgR+T2VNJf200xt2PbQ7cdgNESw=; fh=Pq5/+ra/32jR7ARhXA/UPD87Ay4JBQ4WSaLIekKYvL0=; b=NVI6MBU/YKOjzQmFGjtC0xBykT1PNEdZyIKImC58r5FdPyHj6m6oQ63lNjJpzLoPsr O5uKxruVtT5m9ed630W4PoXDIVmCJvi0Hmt6R0ts5uBjoa7MMDWolQCHAcXCnbTJQX1u hQ8Dy6yw9TeXCJGMPzYXcNXxEWsiBSCqoqFw1uRA1EGupPE907+Vl7SFcEiRtLruSmVd XxXQIDVLdVvQMTcdkHHmv3xTxHFD/rKVihriuDcdKpCUrJ572FxA6ZnSpHM7Yl7+Gacs bFBOLdrl317/DzKKiSTkP3ktdw9yMHf28YVZP2tyatzCj3kcxSqGlSG9tyeYCpzF2uki rVMA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Two8K1g2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 11/17] target/avr: Implement CPUState.memory_rw_debug Date: Sun, 23 Mar 2025 10:37:23 -0700 Message-ID: <20250323173730.3213964-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Prepare for offset_io being non-zero when accessing from gdb. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/avr/cpu.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 080f6f30d3..e4011004b4 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -68,6 +68,35 @@ static void avr_restore_state_to_opc(CPUState *cs, cpu_env(cs)->pc_w = data[0]; } +static int avr_memory_rw_debug(CPUState *cpu, vaddr addr, + uint8_t *buf, size_t len, bool is_write) +{ + if (addr < OFFSET_DATA) { + size_t len_code; + int ret; + + if (addr + len <= OFFSET_DATA) { + return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); + } + + len_code = addr + len - OFFSET_DATA; + ret = cpu_memory_rw_debug(cpu, addr, buf, len_code, is_write); + if (ret != 0) { + return ret; + } + addr = OFFSET_DATA; + len -= len_code; + } + + /* + * Data is biased such that SRAM begins at TARGET_PAGE_SIZE, + * and I/O is immediately prior. This leave a hole between + * OFFSET_DATA and the relative start of the address space. + */ + addr += env_archcpu(cpu_env(cpu))->offset_io; + return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); +} + static void avr_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs = CPU(obj); @@ -262,6 +291,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_write_register = avr_cpu_gdb_write_register; cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint; cc->gdb_core_xml_file = "avr-cpu.xml"; + cc->memory_rw_debug = avr_memory_rw_debug; cc->tcg_ops = &avr_tcg_ops; } From patchwork Sun Mar 23 17:37:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 875632 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp1807978wrb; Sun, 23 Mar 2025 10:41:59 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWPCrNt+xxnRjeGj+lJo9/25S19cbzqvdOA+sYFoOZOGAas1nNoi6vf8ZTS2pelGlzDUVJwGA==@linaro.org X-Google-Smtp-Source: AGHT+IGINdE+shAMrzwmaX+SL9e67z6bFn1cI700rhZkoLp/ZTMqi8km3ukpLApC/SchwbRu4Fp4 X-Received: by 2002:a05:620a:2486:b0:7c5:6d21:8be8 with SMTP id af79cd13be357-7c5ba15c361mr1125187485a.16.1742751719182; Sun, 23 Mar 2025 10:41:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742751719; cv=none; d=google.com; s=arc-20240605; b=C2iVXNH/YFkvSNEVzGjrLwXOWC10TVqBnFWg+mPtJZxnqSE4rncrmyNpp0kouftfvL FhvYJyH3fop9X00yzkZUgndlWb5gHxuxovPtV2PI87VqA3CDcuFSTStXe42AqepJ6HOk vI9Vh8rjjkHfHYPKMgeub7752HBvcAIf6p3D1UdkLmeeJNBVlvHGQNv9syQ0hedLSZVk 5Fmz/asP8yjPyAVaqZ2yEcuTT3EsIs9GCaEVP+V84u0wG5cI3hTur6GyxykioQVPRlNW qLRWirbXo6ii+jPsVXLCjIFscxVLmSEtISBueqqPIMQkPaXWfcLqp8pyatRG5tZ0W4zl 5xIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=n5/rrT9rGaCRyYHGfR9L9lev75C870EJXXZh29se8QE=; fh=Pq5/+ra/32jR7ARhXA/UPD87Ay4JBQ4WSaLIekKYvL0=; b=bTX2JDzsy8HEte5exJn/hA/oGujVQACXUAXrO7GyhvlcfguKTEtROt1FEYfLFQLVDq sBmrTC9SP5aIr8Q5iKe/soRTWNxzlDNssuArA0g7yIZTaAp5LQnt4Rv0wG6POpD9vL/Y PzZahRJkl3jOoi1Yc8WnyHTbHcNTpMuFVjWva1ZmXtSCeXL2bHtJFXhkek/IUz1NrHGi 3xsVwVBP83YtIzTqJXtZ2keiCrNwkXPjqx7yk6iJoEVN5Q5f9VSy0ANteovsw9scUAGx qklP05361P6XktgO9xXyZZP27WaXYzhRlOJB1XHimRGriULbnuoC3iTgBuDL1RHr4Onv LL0A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=V0kcn3Qf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 12/17] target/avr: Handle offset_io in helper.c Date: Sun, 23 Mar 2025 10:37:24 -0700 Message-ID: <20250323173730.3213964-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Prepare for offset_io being non-zero in do_stb. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/avr/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/avr/helper.c b/target/avr/helper.c index 9608e59584..3323f32c22 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -69,7 +69,8 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) static void do_stb(CPUAVRState *env, uint32_t addr, uint8_t data, uintptr_t ra) { - cpu_stb_mmuidx_ra(env, addr, data, MMU_DATA_IDX, ra); + cpu_stb_mmuidx_ra(env, addr + env_archcpu(env)->offset_io, + data, MMU_DATA_IDX, ra); } void avr_cpu_do_interrupt(CPUState *cs) From patchwork Sun Mar 23 17:37:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 875633 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp1807991wrb; Sun, 23 Mar 2025 10:42:04 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX+o4hCOqz5kXUVP+Ef9eKIEVFMOsrERaPC3Z9+NKMyPVFSK0xBOVwe3xh3mE+leBwK0VCA0g==@linaro.org X-Google-Smtp-Source: AGHT+IFlPCz4lGx37/QOLJdJGQjLEWv1/naMc6VcE+9nwNy2nEd/gAwWj8VrcmwkzIlWiwEDg7Ma X-Received: by 2002:a05:622a:989:b0:474:eff7:a478 with SMTP id d75a77b69052e-4771de6458fmr131618791cf.46.1742751724227; Sun, 23 Mar 2025 10:42:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742751724; cv=none; d=google.com; s=arc-20240605; b=LOffC2WwrXBS/IQ0yH5YLsm/APDk9WLh5fcWoz+dnVdxcEdFKI8SmEjYHmDg+gGA46 lMN/mLDlRKbgl/NvBenuwYfJdMbj9STcFDoKB4/Cy4vwpSHVlFF0mJJaFtDxhQG+9X2/ 7pzUbMNtWtsIt7nqysm0EeO7iJ1IiWgx0PMhSNoiDRAGIURwgOUt1gYz+xpNlCFQZKuC YF0fBLv1Wf4kk3Ih9T/rHMjotImzO3caDOQLuiOCozBvbnVtSrMKt7O8NJRPYNsufn2o xhvODgsXczuvXbxB34LLLuPCLsoEGc6UyfeNXDzits4lOjRusbJARQb+K+eZvw09titQ AKUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ewSa7YLsmr/V8RFNcj2I2xqcVJc7xLcAd7Q9LXiEnxw=; fh=Pq5/+ra/32jR7ARhXA/UPD87Ay4JBQ4WSaLIekKYvL0=; b=W0a/rJjLX0yznhkpJupoPbVEk5A0zTRiItQpY16of/JXNygk/RSdrC0UG2DiyA6CuR LQCIWlVRk3NB7Xh/VSaKsZI7tTwPqWluAgTxKuvNqHCZuFc7j4etaHylVmRGUpzyNs3j Tj43uTSWM1oA7sAFnd397wvru91qL8WqWXFIue9umaRjWJP8nAYctCeWF4lhrRoQSAIl rZxx+VVBU/vT6d4TxAwJ/jscXna9wsiu964kc0Ntvon2IbHzoFrefGsMTOy1C6aHh1EG SOlF6OnQ0lerUf7nTNFQ/PiamyoP3xsNmdSDyu4dTRu6YH4YmzZxkwTQEbQvd0LPq9d8 fvHw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BegQvGA2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 13/17] target/avr: Handle offset_io in avr_cpu_realizefn Date: Sun, 23 Mar 2025 10:37:25 -0700 Message-ID: <20250323173730.3213964-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/avr/cpu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index e4011004b4..538fcbc215 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -161,12 +161,14 @@ static void avr_cpu_realizefn(DeviceState *dev, Error **errp) memory_region_init_io(&cpu->cpu_reg1, OBJECT(cpu), &avr_cpu_reg1, env, "avr-cpu-reg1", 32); memory_region_add_subregion(get_system_memory(), - OFFSET_DATA, &cpu->cpu_reg1); + OFFSET_DATA + cpu->offset_io, + &cpu->cpu_reg1); memory_region_init_io(&cpu->cpu_reg2, OBJECT(cpu), &avr_cpu_reg2, env, "avr-cpu-reg2", 8); memory_region_add_subregion(get_system_memory(), - OFFSET_DATA + 0x58, &cpu->cpu_reg2); + OFFSET_DATA + cpu->offset_io + 0x58, + &cpu->cpu_reg2); } static void avr_cpu_set_int(void *opaque, int irq, int level) From patchwork Sun Mar 23 17:37:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 875627 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp1807811wrb; Sun, 23 Mar 2025 10:41:18 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVpTgHP3uNHwF/UUCZYo8VMI9/Rcb9uCjRcn1U0dQWPNYMKh3IVqCtsktV2bPQV1glFyTHczQ==@linaro.org X-Google-Smtp-Source: AGHT+IGnAmScmT9XUsXLjnHR2+MF59NP6f/pChZ/IGNuZJ2pIupxLdsFt17O3Q8Xp2a1E/XrjFGU X-Received: by 2002:a05:622a:4d0d:b0:476:9ac6:2f6c with SMTP id d75a77b69052e-4771dd8979bmr177565391cf.18.1742751677843; Sun, 23 Mar 2025 10:41:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742751677; cv=none; d=google.com; s=arc-20240605; b=BQ6sObAOiG7Y5VkpCS5AKE+doz4hEf/bNttFYTKq1FXFViR9yCSt/OOJ2vFwHlQ5X3 C3FLrNyYym9AMPRBb5djAMxqCGDPLCMu0DjFgfVHd/GWf/DbAtfIHax+5zjFvwzxKFY2 hSCyxLbfpmegwnUCdYtLRQHiiLFf2LD/mmq25qs/3bg6g6xkj9YBPp+8lpcJCSGrtEk0 MERmpHD6FCg1neR3SkCVXiM19gZgryflX6qAoPnJ28x3Dq3zv4TdvArsnCbvT85fYYu1 rCSLHi42xkDK3T2ynBmriXDP4i/BGbimI8ZhT+kmjh9scHDkAaDNHbALxadJJy9fo+JK 7QfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1diLEzRhOjCtwJkuJyBuZiDuZxnU+3/mKXg0OjzXEDE=; fh=Pq5/+ra/32jR7ARhXA/UPD87Ay4JBQ4WSaLIekKYvL0=; b=cz0DDSYUB1IyaxwI74IDP6hI4blVBoVRTp06HlJgdyCkTUEi8QRxYO5Vy/dprSeCxH zm1evqwx17DSVS3UZU/hGiZqJADK3esi9ifCmTD5htlokZ95heDv5Og1xddnYGHXKdMs 9mP8PYI0VscU3O7cgyUkHcI+B1T/fWFiZdwVMsuhfjZaB+GY4qodpbnrhdBzIjDbz9kh sBCYoNCGux4ibwAK7ljCaysF2Rk0nzPFSJT82wvAZbmCc0QE7R8Jws/nwNx124gzCsuM ey+66TSUQM0Y03PcxEww8hflkaweqElc7nh7ii8EAcDeeCIbHQxpB04U2N9Qufqs+8BD Qk/g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lX7wCGfp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 14/17] hw/avr: Set offset_io and increase page size to 1k Date: Sun, 23 Mar 2025 10:37:26 -0700 Message-ID: <20250323173730.3213964-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/cpu-param.h | 8 +------ hw/avr/atmega.c | 54 ++++++++++++++++++++++++++---------------- 2 files changed, 35 insertions(+), 27 deletions(-) diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 81f3f49ee1..f5248ce9e7 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -21,13 +21,7 @@ #ifndef AVR_CPU_PARAM_H #define AVR_CPU_PARAM_H -/* - * TARGET_PAGE_BITS cannot be more than 8 bits because - * 1. all IO registers occupy [0x0000 .. 0x00ff] address range, and they - * should be implemented as a device and not memory - * 2. SRAM starts at the address 0x0100 - */ -#define TARGET_PAGE_BITS 8 +#define TARGET_PAGE_BITS 10 #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index 273582b8af..d4fc9c4aee 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -14,6 +14,7 @@ #include "qapi/error.h" #include "exec/memory.h" #include "exec/address-spaces.h" +#include "exec/target_page.h" #include "system/system.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" @@ -222,6 +223,7 @@ static void atmega_realize(DeviceState *dev, Error **errp) DeviceState *cpudev; SysBusDevice *sbd; char *devname; + uint32_t offset_io, offset_sram; size_t i; assert(mc->io_size <= 0x200); @@ -231,13 +233,25 @@ static void atmega_realize(DeviceState *dev, Error **errp) return; } + /* + * Bias the virtual data section so that the start of RAM is at + * the start of the second page of the physical data section. + * This puts all of the I/O at the end of the first page of the + * physical data section. + */ + offset_io = TARGET_PAGE_SIZE - mc->io_size; + offset_sram = TARGET_PAGE_SIZE; + /* CPU */ object_initialize_child(OBJECT(dev), "cpu", &s->cpu, mc->cpu_type); object_property_set_uint(OBJECT(&s->cpu), "init-sp", mc->io_size + mc->sram_size - 1, &error_abort); object_property_set_uint(OBJECT(&s->cpu), "offset-io", - 0, &error_abort); + offset_io, &error_abort); + + offset_io += OFFSET_DATA; + offset_sram += OFFSET_DATA; qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); cpudev = DEVICE(&s->cpu); @@ -245,8 +259,7 @@ static void atmega_realize(DeviceState *dev, Error **errp) /* SRAM */ memory_region_init_ram(&s->sram, OBJECT(dev), "sram", mc->sram_size, &error_abort); - memory_region_add_subregion(get_system_memory(), - OFFSET_DATA + mc->io_size, &s->sram); + memory_region_add_subregion(get_system_memory(), offset_sram, &s->sram); /* Flash */ memory_region_init_rom(&s->flash, OBJECT(dev), @@ -258,13 +271,14 @@ static void atmega_realize(DeviceState *dev, Error **errp) * * 0x00 - 0x1f: Registers * 0x20 - 0x5f: I/O memory - * 0x60 - 0xff: Extended I/O + * 0x60 - 0x[1]ff: Extended I/O */ s->io = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); qdev_prop_set_string(s->io, "name", "I/O"); qdev_prop_set_uint64(s->io, "size", mc->io_size); sysbus_realize_and_unref(SYS_BUS_DEVICE(s->io), &error_fatal); - sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->io), 0, OFFSET_DATA, -1234); + + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->io), 0, offset_io, -1234); /* Power Reduction */ for (i = 0; i < POWER_MAX; i++) { @@ -277,7 +291,7 @@ static void atmega_realize(DeviceState *dev, Error **errp) TYPE_AVR_MASK); sysbus_realize(SYS_BUS_DEVICE(&s->pwr[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwr[i]), 0, - OFFSET_DATA + mc->dev[idx].addr); + offset_io + mc->dev[idx].addr); g_free(devname); } @@ -289,7 +303,7 @@ static void atmega_realize(DeviceState *dev, Error **errp) } devname = g_strdup_printf("atmega-gpio-%c", 'a' + (char)i); create_unimplemented_device(devname, - OFFSET_DATA + mc->dev[idx].addr, 3); + offset_io + mc->dev[idx].addr, 3); g_free(devname); } @@ -305,7 +319,7 @@ static void atmega_realize(DeviceState *dev, Error **errp) qdev_prop_set_chr(DEVICE(&s->usart[i]), "chardev", serial_hd(i)); sbd = SYS_BUS_DEVICE(&s->usart[i]); sysbus_realize(sbd, &error_abort); - sysbus_mmio_map(sbd, 0, OFFSET_DATA + mc->dev[USART(i)].addr); + sysbus_mmio_map(sbd, 0, offset_io + mc->dev[USART(i)].addr); connect_peripheral_irq(mc, sbd, 0, cpudev, USART_RXC_IRQ(i)); connect_peripheral_irq(mc, sbd, 1, cpudev, USART_DRE_IRQ(i)); connect_peripheral_irq(mc, sbd, 2, cpudev, USART_TXC_IRQ(i)); @@ -321,12 +335,12 @@ static void atmega_realize(DeviceState *dev, Error **errp) } if (!mc->dev[idx].is_timer16) { create_unimplemented_device("avr-timer8", - OFFSET_DATA + mc->dev[idx].addr, 5); + offset_io + mc->dev[idx].addr, 5); create_unimplemented_device("avr-timer8-intmask", - OFFSET_DATA + offset_io + mc->dev[idx].intmask_addr, 1); create_unimplemented_device("avr-timer8-intflag", - OFFSET_DATA + offset_io + mc->dev[idx].intflag_addr, 1); continue; } @@ -337,9 +351,9 @@ static void atmega_realize(DeviceState *dev, Error **errp) s->xtal_freq_hz, &error_abort); sbd = SYS_BUS_DEVICE(&s->timer[i]); sysbus_realize(sbd, &error_abort); - sysbus_mmio_map(sbd, 0, OFFSET_DATA + mc->dev[idx].addr); - sysbus_mmio_map(sbd, 1, OFFSET_DATA + mc->dev[idx].intmask_addr); - sysbus_mmio_map(sbd, 2, OFFSET_DATA + mc->dev[idx].intflag_addr); + sysbus_mmio_map(sbd, 0, offset_io + mc->dev[idx].addr); + sysbus_mmio_map(sbd, 1, offset_io + mc->dev[idx].intmask_addr); + sysbus_mmio_map(sbd, 2, offset_io + mc->dev[idx].intflag_addr); connect_peripheral_irq(mc, sbd, 0, cpudev, TIMER_CAPT_IRQ(i)); connect_peripheral_irq(mc, sbd, 1, cpudev, TIMER_COMPA_IRQ(i)); connect_peripheral_irq(mc, sbd, 2, cpudev, TIMER_COMPB_IRQ(i)); @@ -349,12 +363,12 @@ static void atmega_realize(DeviceState *dev, Error **errp) g_free(devname); } - create_unimplemented_device("avr-twi", OFFSET_DATA + 0x0b8, 6); - create_unimplemented_device("avr-adc", OFFSET_DATA + 0x078, 8); - create_unimplemented_device("avr-ext-mem-ctrl", OFFSET_DATA + 0x074, 2); - create_unimplemented_device("avr-watchdog", OFFSET_DATA + 0x060, 1); - create_unimplemented_device("avr-spi", OFFSET_DATA + 0x04c, 3); - create_unimplemented_device("avr-eeprom", OFFSET_DATA + 0x03f, 3); + create_unimplemented_device("avr-twi", offset_io + 0x0b8, 6); + create_unimplemented_device("avr-adc", offset_io + 0x078, 8); + create_unimplemented_device("avr-ext-mem-ctrl", offset_io + 0x074, 2); + create_unimplemented_device("avr-watchdog", offset_io + 0x060, 1); + create_unimplemented_device("avr-spi", offset_io + 0x04c, 3); + create_unimplemented_device("avr-eeprom", offset_io + 0x03f, 3); } static const Property atmega_props[] = { From patchwork Sun Mar 23 17:37:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 875625 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp1807537wrb; Sun, 23 Mar 2025 10:40:14 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXUPRQxqOARnwGUP1UJbCI575mnZxz2JVW6ZYZAWXhs0Mj2nS3aLrCRTASnB/5SgfxgGuBbFQ==@linaro.org X-Google-Smtp-Source: AGHT+IH8vaWua21Kkk2pXCrd3WG5hTDRvIADp6b60NysdBzctkpVIapPZAOxcFDrYxe+9JwtccnD X-Received: by 2002:ad4:5aaf:0:b0:6d8:99cf:d2e3 with SMTP id 6a1803df08f44-6eb3f2eb079mr153197246d6.22.1742751614475; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 15/17] hw/avr: Pass mcu_type to class_base_init via .class_data Date: Sun, 23 Mar 2025 10:37:27 -0700 Message-ID: <20250323173730.3213964-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We want to be able to do more common work on MachineClass. Pass the class name as a string in .class_data. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/avr/arduino.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/avr/arduino.c b/hw/avr/arduino.c index 48ef478346..29cb776848 100644 --- a/hw/avr/arduino.c +++ b/hw/avr/arduino.c @@ -69,6 +69,13 @@ static void arduino_machine_class_init(ObjectClass *oc, void *data) mc->no_parallel = 1; } +static void arduino_machine_class_base_init(ObjectClass *oc, void *data) +{ + ArduinoMachineClass *amc = ARDUINO_MACHINE_CLASS(oc); + + amc->mcu_type = data; +} + static void arduino_duemilanove_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -80,7 +87,6 @@ static void arduino_duemilanove_class_init(ObjectClass *oc, void *data) */ mc->desc = "Arduino Duemilanove (ATmega168)", mc->alias = "2009"; - amc->mcu_type = TYPE_ATMEGA168_MCU; amc->xtal_hz = 16 * 1000 * 1000; }; @@ -95,7 +101,6 @@ static void arduino_uno_class_init(ObjectClass *oc, void *data) */ mc->desc = "Arduino UNO (ATmega328P)"; mc->alias = "uno"; - amc->mcu_type = TYPE_ATMEGA328_MCU; amc->xtal_hz = 16 * 1000 * 1000; }; @@ -110,7 +115,6 @@ static void arduino_mega_class_init(ObjectClass *oc, void *data) */ mc->desc = "Arduino Mega (ATmega1280)"; mc->alias = "mega"; - amc->mcu_type = TYPE_ATMEGA1280_MCU; amc->xtal_hz = 16 * 1000 * 1000; }; @@ -125,7 +129,6 @@ static void arduino_mega2560_class_init(ObjectClass *oc, void *data) */ mc->desc = "Arduino Mega 2560 (ATmega2560)"; mc->alias = "mega2560"; - amc->mcu_type = TYPE_ATMEGA2560_MCU; amc->xtal_hz = 16 * 1000 * 1000; /* CSTCE16M0V53-R0 */ }; @@ -134,24 +137,29 @@ static const TypeInfo arduino_machine_types[] = { .name = MACHINE_TYPE_NAME("arduino-duemilanove"), .parent = TYPE_ARDUINO_MACHINE, .class_init = arduino_duemilanove_class_init, + .class_data = (void *)TYPE_ATMEGA168_MCU, }, { .name = MACHINE_TYPE_NAME("arduino-uno"), .parent = TYPE_ARDUINO_MACHINE, .class_init = arduino_uno_class_init, + .class_data = (void *)TYPE_ATMEGA328_MCU, }, { .name = MACHINE_TYPE_NAME("arduino-mega"), .parent = TYPE_ARDUINO_MACHINE, .class_init = arduino_mega_class_init, + .class_data = (void *)TYPE_ATMEGA1280_MCU, }, { .name = MACHINE_TYPE_NAME("arduino-mega-2560-v3"), .parent = TYPE_ARDUINO_MACHINE, .class_init = arduino_mega2560_class_init, + .class_data = (void *)TYPE_ATMEGA2560_MCU, }, { .name = TYPE_ARDUINO_MACHINE, .parent = TYPE_MACHINE, .instance_size = sizeof(ArduinoMachineState), .class_size = sizeof(ArduinoMachineClass), .class_init = arduino_machine_class_init, + .class_base_init = arduino_machine_class_base_init, .abstract = true, } }; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 16/17] hw/avr: Move AtmegaMcuClass to atmega.h Date: Sun, 23 Mar 2025 10:37:28 -0700 Message-ID: <20250323173730.3213964-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- hw/avr/atmega.h | 20 ++++++++++++++++++++ hw/avr/atmega.c | 22 +--------------------- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h index a99ee15c7e..f031e6c10a 100644 --- a/hw/avr/atmega.h +++ b/hw/avr/atmega.h @@ -23,6 +23,10 @@ #define TYPE_ATMEGA1280_MCU "ATmega1280" #define TYPE_ATMEGA2560_MCU "ATmega2560" +typedef struct AtmegaMcuClass AtmegaMcuClass; +DECLARE_CLASS_CHECKERS(AtmegaMcuClass, ATMEGA_MCU, + TYPE_ATMEGA_MCU) + typedef struct AtmegaMcuState AtmegaMcuState; DECLARE_INSTANCE_CHECKER(AtmegaMcuState, ATMEGA_MCU, TYPE_ATMEGA_MCU) @@ -32,6 +36,22 @@ DECLARE_INSTANCE_CHECKER(AtmegaMcuState, ATMEGA_MCU, #define TIMER_MAX 6 #define GPIO_MAX 12 +struct AtmegaMcuClass { + /*< private >*/ + SysBusDeviceClass parent_class; + /*< public >*/ + const char *uc_name; + const char *cpu_type; + size_t flash_size; + size_t eeprom_size; + size_t sram_size; + size_t io_size; + size_t gpio_count; + size_t adc_count; + const uint8_t *irq; + const struct peripheral_cfg *dev; +}; + struct AtmegaMcuState { /*< private >*/ SysBusDevice parent_obj; diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index d4fc9c4aee..96e36743bc 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -36,7 +36,7 @@ enum AtmegaPeripheral { #define TIMER(n) (n + TIMER0) #define POWER(n) (n + POWER0) -typedef struct { +typedef struct peripheral_cfg { uint16_t addr; enum AtmegaPeripheral power_index; uint8_t power_bit; @@ -46,26 +46,6 @@ typedef struct { bool is_timer16; } peripheral_cfg; -struct AtmegaMcuClass { - /*< private >*/ - SysBusDeviceClass parent_class; - /*< public >*/ - const char *uc_name; - const char *cpu_type; - size_t flash_size; - size_t eeprom_size; - size_t sram_size; - size_t io_size; - size_t gpio_count; - size_t adc_count; - const uint8_t *irq; - const peripheral_cfg *dev; -}; -typedef struct AtmegaMcuClass AtmegaMcuClass; - -DECLARE_CLASS_CHECKERS(AtmegaMcuClass, ATMEGA_MCU, - TYPE_ATMEGA_MCU) - static const peripheral_cfg dev168_328[PERIFMAX] = { [USART0] = { 0xc0, POWER0, 1 }, [TIMER2] = { 0xb0, POWER0, 6, 0x70, 0x37, false }, From patchwork Sun Mar 23 17:37:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 875629 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f4c:0:b0:38f:210b:807b with SMTP id cm12csp1807857wrb; Sun, 23 Mar 2025 10:41:25 -0700 (PDT) X-Forwarded-Encrypted: i=2; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 17/17] target/avr: Enable TARGET_PAGE_BITS_VARY Date: Sun, 23 Mar 2025 10:37:29 -0700 Message-ID: <20250323173730.3213964-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Increase TARGET_PHYS_ADDR_SPACE_BITS to allow flexibility in the page size without triggering an assert. Select the page size based on the size of sram. This leaves sram on exactly one page and minimizes the number of pages required to span the flash. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/cpu-param.h | 11 +++++++++-- hw/avr/arduino.c | 15 +++++++++++++++ 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index f5248ce9e7..a18bf39bb9 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -21,8 +21,15 @@ #ifndef AVR_CPU_PARAM_H #define AVR_CPU_PARAM_H -#define TARGET_PAGE_BITS 10 -#define TARGET_PHYS_ADDR_SPACE_BITS 24 +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 10 + +/* + * The real value for TARGET_PHYS_ADDR_SPACE_BITS is 24, but selecting + * an overly small value will assert in tb-maint.c when selecting the + * shape of the page_table tree. This allows an 8k page size. + */ +#define TARGET_PHYS_ADDR_SPACE_BITS 28 #define TARGET_VIRT_ADDR_SPACE_BITS 24 #define TCG_GUEST_DEFAULT_MO 0 diff --git a/hw/avr/arduino.c b/hw/avr/arduino.c index 29cb776848..f309aa5597 100644 --- a/hw/avr/arduino.c +++ b/hw/avr/arduino.c @@ -71,9 +71,24 @@ static void arduino_machine_class_init(ObjectClass *oc, void *data) static void arduino_machine_class_base_init(ObjectClass *oc, void *data) { + MachineClass *mc = MACHINE_CLASS(oc); ArduinoMachineClass *amc = ARDUINO_MACHINE_CLASS(oc); + AtmegaMcuClass *acc; + int page_bits; amc->mcu_type = data; + + /* Find the mcu class that we will instantiate. */ + acc = ATMEGA_MCU_CLASS(object_class_by_name(amc->mcu_type)); + + /* + * Select a page size based on the size of sram. + * This will result in a page size between 1k and 8k + * and minimize the number of pages to span flash. + */ + page_bits = ctz32(acc->sram_size); + assert(page_bits >= TARGET_PAGE_BITS_MIN && page_bits <= 13); + mc->minimum_page_bits = page_bits; } static void arduino_duemilanove_class_init(ObjectClass *oc, void *data)