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Fri, 21 Mar 2025 12:50:08 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 21 Mar 2025 05:50:04 -0700 From: Luo Jie Date: Fri, 21 Mar 2025 20:49:52 +0800 Subject: [PATCH 1/4] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250321-qcom_ipq5424_cmnpll-v1-1-3ea8e5262da4@quicinc.com> References: <20250321-qcom_ipq5424_cmnpll-v1-0-3ea8e5262da4@quicinc.com> In-Reply-To: <20250321-qcom_ipq5424_cmnpll-v1-0-3ea8e5262da4@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio CC: , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1742561400; l=1947; i=quic_luoj@quicinc.com; s=20250209; h=from:subject:message-id; bh=qZH3282QieBZWznwmdlXw14lTXzF3H90frj6mMvR9AE=; b=NZUCRAjNnDTPldZl8UItgX/+jgRcrmrcm2ku44V1TdrdAtsITC5z7csqZlUn5X8/U6SThU31F h2WksWC0h60AzoCMwCIioT+HqE61LF1LA8miJD+5R3LVCoKAhm4kpip X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=pzwy8bU5tJZ5UKGTv28n+QOuktaWuriznGmriA9Qkfc= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ZfnG8EQIj0YooFGfCNmV1Y6Hj6Y7taAL X-Authority-Analysis: v=2.4 cv=FYE3xI+6 c=1 sm=1 tr=0 ts=67dd6080 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=leb7mbaFTONhKzR9nrMA:9 a=QEXdDO2ut3YA:10 a=RVmHIydaz68A:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: ZfnG8EQIj0YooFGfCNmV1Y6Hj6Y7taAL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-21_05,2025-03-20_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 bulkscore=0 phishscore=0 spamscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503210094 The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference input clock. The output clocks are the same as IPQ9574 SoC, except for the clock rate of output clocks to PPE and NSS. Also, add macros for clock rates that are applicable specifically only for IPQ5424. Signed-off-by: Luo Jie --- .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 + include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 10 +++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml index f869b3739be8..bbaf896ae908 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml @@ -25,6 +25,7 @@ properties: compatible: enum: - qcom,ipq9574-cmn-pll + - qcom,ipq5424-cmn-pll reg: maxItems: 1 diff --git a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h index 936e92b3b62c..e30d57001c38 100644 --- a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h +++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H @@ -19,4 +19,12 @@ #define ETH1_50MHZ_CLK 7 #define ETH2_50MHZ_CLK 8 #define ETH_25MHZ_CLK 9 + +/* + * The CMN PLL output clock rates that are specifically applicable for IPQ5424 + * SoC. For IPQ5424, the other output clocks and their rates are same as IPQ9574. + */ +#define NSS_300MHZ_CLK 4 +#define PPE_375MHZ_CLK 5 + #endif From patchwork Fri Mar 21 12:49:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 875281 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1D9722B59A; Fri, 21 Mar 2025 12:50:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742561417; cv=none; b=mBH4gkIHBqd3Z7tl24BDk3ivOhOVVYZNiFHej5boOmGGfBnxvAmuHlsdBfNONj2J4SleSsYmyjk1lyG/pMjM3rrLF/+mt5f5jSX/Gag0isD42ECdBexWlIuA+HsvypnVa5DRokNByH/rjBYEyWjJJGSmjT3mqvmdkxAxE8LLAgg= ARC-Message-Signature: i=1; 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Fri, 21 Mar 2025 12:50:11 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 21 Mar 2025 05:50:08 -0700 From: Luo Jie Date: Fri, 21 Mar 2025 20:49:53 +0800 Subject: [PATCH 2/4] clk: qcom: cmnpll: Add IPQ5424 SoC support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250321-qcom_ipq5424_cmnpll-v1-2-3ea8e5262da4@quicinc.com> References: <20250321-qcom_ipq5424_cmnpll-v1-0-3ea8e5262da4@quicinc.com> In-Reply-To: <20250321-qcom_ipq5424_cmnpll-v1-0-3ea8e5262da4@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio CC: , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1742561400; l=3458; i=quic_luoj@quicinc.com; s=20250209; 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Other output clocks from CMN PLL on this SoC, and their rates are same as IPQ9574. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 34 +++++++++++++++++++++++++++++----- 1 file changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 432d4c4b7aa6..ce5e83124c6d 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ /* @@ -16,6 +16,10 @@ * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS * with 31.25 MHZ. * + * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ, + * and an output clock to NSS at 300 MHZ. The other output clocks from CMN PLL + * on IPQ5424 are the same as IPQ9574. + * * +---------+ * | GCC | * +--+---+--+ @@ -115,6 +119,20 @@ static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), + { /* Sentinel */ }, +}; + +static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = { + CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), + CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), + CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), + CLK_PLL_OUTPUT(NSS_300MHZ_CLK, "nss-300mhz", 300000000UL), + CLK_PLL_OUTPUT(PPE_375MHZ_CLK, "ppe-375mhz", 375000000UL), + CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), + { /* Sentinel */ }, }; /* @@ -297,7 +315,7 @@ static struct clk_hw *ipq_cmn_pll_clk_hw_register(struct platform_device *pdev) static int ipq_cmn_pll_register_clks(struct platform_device *pdev) { - const struct cmn_pll_fixed_output_clk *fixed_clk; + const struct cmn_pll_fixed_output_clk *p, *fixed_clk; struct clk_hw_onecell_data *hw_data; struct device *dev = &pdev->dev; struct clk_hw *cmn_pll_hw; @@ -305,8 +323,13 @@ static int ipq_cmn_pll_register_clks(struct platform_device *pdev) struct clk_hw *hw; int ret, i; - fixed_clk = ipq9574_output_clks; - num_clks = ARRAY_SIZE(ipq9574_output_clks); + fixed_clk = device_get_match_data(dev); + if (!fixed_clk) + return -EINVAL; + + num_clks = 0; + for (p = fixed_clk; p->name; p++) + num_clks++; hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks + 1), GFP_KERNEL); @@ -415,7 +438,8 @@ static const struct dev_pm_ops ipq_cmn_pll_pm_ops = { }; static const struct of_device_id ipq_cmn_pll_clk_ids[] = { - { .compatible = "qcom,ipq9574-cmn-pll", }, + { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks }, + { .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks }, { } }; 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The reference clock of CMN PLL is routed from XO to the CMN PLL through the internal WiFi block. .XO (48 MHZ or 96 MHZ or 192 MHZ)-->WiFi (multiplier/divider)--> 48 MHZ to CMN PLL. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 16 +++++++++++++++- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 26 +++++++++++++++++++++++++- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index 0fd0ebe0251d..b4d1aa00c944 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -2,7 +2,7 @@ /* * IPQ5424 RDP466 board device tree source * - * Copyright (c) 2024 The Linux Foundation. All rights reserved. + * Copyright (c) 2024-2025 The Linux Foundation. All rights reserved. */ /dts-v1/; @@ -213,7 +213,21 @@ &usb3 { status = "okay"; }; +/* + * The bootstrap pins for the board select the XO clock frequency that + * supports 48 MHZ, 96 MHZ or 192 MHZ. This setting automatically + * enables the right dividers, to ensure the reference clock output + * from WiFi to the CMN PLL is 48 MHZ. + */ +&ref_48mhz_clk { + clock-div = <1>; + clock-mult = <1>; +}; + &xo_board { clock-frequency = <24000000>; }; +&xo_clk { + clock-frequency = <48000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 5d6ed2172b1b..844788990f43 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -3,10 +3,11 @@ * IPQ5424 device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include +#include #include #include #include @@ -17,6 +18,12 @@ / { interrupt-parent = <&intc>; clocks { + ref_48mhz_clk: ref-48mhz-clk { + compatible = "fixed-factor-clock"; + clocks = <&xo_clk>; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -26,6 +33,11 @@ xo_board: xo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; + + xo_clk: xo-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; }; cpus: cpus { @@ -157,6 +169,18 @@ soc@0 { #size-cells = <2>; ranges = <0 0 0 0 0x10 0>; + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq5424-cmn-pll"; + reg = <0 0x0009b000 0 0x800>; + clocks = <&ref_48mhz_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names = "ref", "ahb", "sys"; + #clock-cells = <1>; + assigned-clocks = <&cmn_pll CMN_PLL_CLK>; + assigned-clock-rates-u64 = /bits/ 64 <12000000000>; + }; + efuse@a4000 { compatible = "qcom,ipq5424-qfprom", "qcom,qfprom"; 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Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 7 ++++++- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index b4d1aa00c944..e503b6677a3e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -224,8 +224,13 @@ &ref_48mhz_clk { clock-mult = <1>; }; +/* + * The frequency of xo_board is fixed to 24 MHZ, which is routed + * from WiFi output clock 48 MHZ divided by 2. + */ &xo_board { - clock-frequency = <24000000>; + clock-div = <2>; + clock-mult = <1>; }; &xo_clk { diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 844788990f43..6974339c126f 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -30,7 +30,8 @@ sleep_clk: sleep-clk { }; xo_board: xo-board-clk { - compatible = "fixed-clock"; + compatible = "fixed-factor-clock"; + clocks = <&ref_48mhz_clk>; #clock-cells = <0>; };