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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Stub the RPMh clock controller on SC7280 Signed-off-by: Caleb Connolly Reviewed-by: Neil Armstrong --- drivers/clk/clk-stub.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c index 5fbbb07b7f7b93e619baf596064c4b3a3bfeecc0..343fa5cd3fe1704c6bb15a8c9852b9b4e4990351 100644 --- a/drivers/clk/clk-stub.c +++ b/drivers/clk/clk-stub.c @@ -49,8 +49,9 @@ static struct clk_ops stub_clk_ops = { }; static const struct udevice_id stub_clk_ids[] = { { .compatible = "qcom,rpmcc" }, + { .compatible = "qcom,sc7280-rpmh-clk" }, { .compatible = "qcom,sm8150-rpmh-clk" }, { .compatible = "qcom,sm8250-rpmh-clk" }, { .compatible = "qcom,sm8550-rpmh-clk" }, { .compatible = "qcom,sm8650-rpmh-clk" }, From patchwork Mon Mar 17 16:15:02 2025 Content-Type: text/plain; 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Mon, 17 Mar 2025 09:15:10 -0700 (PDT) Received: from [192.168.1.116] ([2a0a:ef40:1d11:ab01:670b:cd84:4753:5ae9]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395c888167bsm15382001f8f.45.2025.03.17.09.15.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 09:15:09 -0700 (PDT) From: Caleb Connolly Date: Mon, 17 Mar 2025 16:15:02 +0000 Subject: [PATCH 2/2] clk/qcom: sc7280: add missing UFS and MMC clocks MIME-Version: 1.0 Message-Id: <20250317-sc7280-mmc-ufs-clocks-v1-2-38e05c16511b@linaro.org> References: <20250317-sc7280-mmc-ufs-clocks-v1-0-38e05c16511b@linaro.org> In-Reply-To: <20250317-sc7280-mmc-ufs-clocks-v1-0-38e05c16511b@linaro.org> To: Lukasz Majewski , Sean Anderson , Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1569; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=274yFWAVcD4QFEJiDqDnn7YTJyP05G6pVVzrkKyid4c=; b=owEBbQKS/ZANAwAKAQWDMSsZX2S2AcsmYgBn2EqKcWxQWGgAQ7PxFwbdwBp45pdhuXc5mpnRK SWZaQGymbqJAjMEAAEKAB0WIQS2UaFGPGq+0GkMVc0FgzErGV9ktgUCZ9hKigAKCRAFgzErGV9k tjHOD/4lribEv8GZnZkJrYi7ITq1W/yGuT/9/nqh0LtFGpteFvEs2iDnukvtDxl7KI0pUsu19c0 1DE+xXIcVVHB5h3idGUMv1PYFamOXlMLZcj4DIMOxbGGGienEHbaKS34ftbAvlZrWxNQ7DV8dDf MiS7E5LywQUlsLm+2aNC9VFce8ronn84jm2E3nlD3oM0C+MDrOYW1w48YXgSMivo39FL2G2+CsR 79BJFFPBVoUEnBPCYLOBkXGItIsHRLAUvYDYFPPqgLnEpg+WvasvcdL3itEtpjznx4RUAWrGLqP UibV/ewdBMWuJyYzkUDW0OeX4F/RZH9WLDU8R2X183Bm9S3KlKR1rFJnwYLjWI07RTh2df0QioP HCLgKJOZIhKj4bebkEVwhJxaJIrhzy4e1Zlpg0E8z7I/dl14bm2XR9fstKXiN9X9sHgJXkbKxMT WVVGBWcDV4o1yx1XC89aQskfx8EwDGB2CtDTb5JgKsw9Z18DyXb1g2+NcMBwpLbuxqwxUzMXCxY CtdGiPz/nHbWmhVQk3uHHiqcBp6DjO92La40RElpeEKfYETw/3AhKnmwBRP6tgc1fmAc0bIEy1X VVqUpzCyydNC+pIlLHjrhpSndwKplh9/sY+dh61PcrZuLHn2MJHYKBytdFHOmbaevCabSsefOnJ UyutLDSWQcfxWlA== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean These are all usually enabled, hence we don't (yet) bother configuring their RCG src clocks. Add them to remove the errors about missing clocks when the UFS and MMC drivers probe. Signed-off-by: Caleb Connolly Reviewed-by: Neil Armstrong --- drivers/clk/qcom/clock-sc7280.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c index 8691f08109b39639d8a5defe75161049399bf682..9aff8a847ad1bd59b7ec7246f5719e4d7c32ec65 100644 --- a/drivers/clk/qcom/clock-sc7280.c +++ b/drivers/clk/qcom/clock-sc7280.c @@ -106,8 +106,19 @@ static const struct gate_clk sc7280_clks[] = { GATE_CLK(GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK, 0x52008, BIT(28)), GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, BIT(10)), GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, BIT(11)), GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, BIT(13)), + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)), + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0)), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, BIT(0)), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, BIT(0)), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x77020, BIT(0)), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770b8, BIT(0)), + GATE_CLK(GCC_UFS_1_CLKREF_EN, 0x8c000, BIT(0)), + GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0)), + GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)), }; static int sc7280_enable(struct clk *clk) {