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Thu, 13 Mar 2025 13:10:03 GMT Received: from hu-kaushalk-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 13 Mar 2025 06:09:58 -0700 From: Kaushal Kumar To: , , , , , , , , , , CC: , , , , , Kaushal Kumar Subject: [PATCH 1/6] dt-bindings: mtd: qcom,nandc: Document the SDX75 NAND Date: Thu, 13 Mar 2025 18:39:13 +0530 Message-ID: <20250313130918.4238-2-quic_kaushalk@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250313130918.4238-1-quic_kaushalk@quicinc.com> References: <20250313130918.4238-1-quic_kaushalk@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: rfgKCddoWgJMhbTu7oN301xM7z9HAIbj X-Authority-Analysis: v=2.4 cv=DNSP4zNb c=1 sm=1 tr=0 ts=67d2d92d cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=Kq_rJIWMMWslwROvJEYA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: rfgKCddoWgJMhbTu7oN301xM7z9HAIbj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_06,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1011 phishscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 spamscore=0 bulkscore=0 impostorscore=0 suspectscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503130103 Document the QPIC NAND controller v2.1.1 being used in SDX75 SoC and it uses BAM DMA. SDX75 NAND controller has DMA-coherent and iommu support so define them in the properties section, without which 'dtbs_check' reports the following error: nand-controller@1cc8000: Unevaluated properties are not allowed ('dma-coherent', 'iommus' were unexpected) Signed-off-by: Kaushal Kumar --- .../devicetree/bindings/mtd/qcom,nandc.yaml | 23 ++++++++++++++----- 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml index 35b4206ea918..8b77e8837205 100644 --- a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml +++ b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml @@ -11,12 +11,17 @@ maintainers: properties: compatible: - enum: - - qcom,ipq806x-nand - - qcom,ipq4019-nand - - qcom,ipq6018-nand - - qcom,ipq8074-nand - - qcom,sdx55-nand + OneOf: + - items: + - enum: + - qcom,sdx75-nand + - const: qcom,sdx55-nand + - items: + - const: qcom,ipq806x-nand + - const: qcom,ipq4019-nand + - const: qcom,ipq6018-nand + - const: qcom,ipq8074-nand + - const: qcom,sdx55-nand reg: maxItems: 1 @@ -31,6 +36,12 @@ properties: - const: core - const: aon + dma-coherent: true + + iommus: + minItems: 1 + maxItems: 3 + qcom,cmd-crci: $ref: /schemas/types.yaml#/definitions/uint32 description: From patchwork Thu Mar 13 13:09:14 2025 Content-Type: text/plain; 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Signed-off-by: Kaushal Kumar --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index b0a8a0fe5f39..e3a0ee661c4a 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -880,6 +880,20 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + qpic_bam: dma-controller@1c9c000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x01c9c000 0x0 0x1c000>; + interrupts = ; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + iommus = <&apps_smmu 0x100 0x3>; + dma-coherent; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; From patchwork Thu Mar 13 13:09:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaushal Kumar X-Patchwork-Id: 873192 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A3CF267720; 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Since there is no "aon" clock in SDX75, a dummy clock is provided. Signed-off-by: Kaushal Kumar --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index e3a0ee661c4a..9c43b14a0594 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -37,6 +37,12 @@ clock-frequency = <32764>; #clock-cells = <0>; }; + + nand_clk_dummy: nand-clk-dummy { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; }; cpus { @@ -894,6 +900,24 @@ status = "disabled"; }; + qpic_nand: nand-controller@1cc8000 { + compatible = "qcom,sdx75-nand", "qcom,sdx55-nand"; + reg = <0x0 0x01cc8000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rpmhcc RPMH_QPIC_CLK>, + <&nand_clk_dummy>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + iommus = <&apps_smmu 0x100 0x3>; + dma-coherent; + status = "disabled"; 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Signed-off-by: Kaushal Kumar --- arch/arm64/boot/dts/qcom/sdx75-idp.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts index f1bbe7ab01ab..26f7e38b8a6e 100644 --- a/arch/arm64/boot/dts/qcom/sdx75-idp.dts +++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts @@ -278,6 +278,10 @@ vdd3-supply = <&vreg_l10b_3p08>; }; +&qpic_bam { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; From patchwork Thu Mar 13 13:09:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaushal Kumar X-Patchwork-Id: 873191 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1939A267F62; Thu, 13 Mar 2025 13:10:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Kaushal Kumar --- arch/arm64/boot/dts/qcom/sdx75-idp.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts index 26f7e38b8a6e..06cacec3461f 100644 --- a/arch/arm64/boot/dts/qcom/sdx75-idp.dts +++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts @@ -282,6 +282,20 @@ status = "okay"; }; +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + /* efs2 partition is secured */ + secure-regions = /bits/ 64 <0x680000 0xb00000>; + }; +}; + &qupv3_id_0 { status = "okay"; };