From patchwork Fri Mar 6 09:57:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 184237 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp7231319ile; Fri, 6 Mar 2020 01:59:50 -0800 (PST) X-Google-Smtp-Source: ADFU+vushYz20mJv4hzX86uzJYoXhJce1UR9nzckW19QPbuxWB+NHpsVh5Cc6A2ZUCu272q/IwN5 X-Received: by 2002:aa7:c550:: with SMTP id s16mr2314822edr.370.1583488790582; Fri, 06 Mar 2020 01:59:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583488790; cv=none; d=google.com; s=arc-20160816; b=q8LZVPZJlgY9NpWTRCCG8UKLcixKD01qb9ClsjBdpmzkAKgNRUqbo8sMvQS0p3HTsc qvB/71qYcHwmu0DORt/KiiIkK94Ox2m6Lwfu05eWJ1Oityqw8v98j5JtlaKC0NWFlDxy cOEenuR5w4c7N1XHxJsdCtXHueevgLrVvxCMfSft97crj62LEFSqm2sGBWkYXNFDoKMr GsZViRax46MwH6DPBkHt0AbKjJ1827wL+V38efx2+vktdSgWbMo+K9gNDXmxJfVE84g4 lwU3pR/3Z87Sgl6V1ic+kQ5CkKAwuz8vsy1XzLG9TOZ2eS2zwHRjCTAwWu3JV5BKFxBr xAog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=iH69F+1bHovb2FtykibUQ/uB83A9jEN0+4NK0isxprc=; b=u0/SIgr2iQ1PA4A1PVHA3K8WOmixGjHG4eCFkNxJbyJ2aFRfI07+9Rq2T/8279wJee 8c2IH1PyUUUgtlc873u06eQpIgruXXvRjsZShO16Yf3Zm+V1OHA66A6fWInuMysWGoId oG9nY9Y/aoEqKboPhhkgRCd4DOMBx6lJgAEhYXhvr9Q3hrivZ01aqBL/l8m5IHcMQzg6 c4bYtZpURvOL+VmT83YLJpZm1AimQB6UfyoP4xU4pO/kVijl/B8hdWfJJKB1umkyNGSx i64En9t4B6r6y3MzMZybZvcvQw71y5nMi3BPGx91Gi/A2WStgaVyUJWTWWM5UF2vfjIJ +hpQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id g9si1418302edn.14.2020.03.06.01.59.50; Fri, 06 Mar 2020 01:59:50 -0800 (PST) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BDA361BFEE; Fri, 6 Mar 2020 10:59:45 +0100 (CET) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by dpdk.org (Postfix) with ESMTP id 0E0271BFEB; Fri, 6 Mar 2020 10:59:45 +0100 (CET) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id A1BD9200AD8; Fri, 6 Mar 2020 10:59:44 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 1F789200AD2; Fri, 6 Mar 2020 10:59:42 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 342024029B; Fri, 6 Mar 2020 17:59:38 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, stable@dpdk.org, Rohit Raj Date: Fri, 6 Mar 2020 15:27:27 +0530 Message-Id: <20200306095742.18080-2-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200306095742.18080-1-hemant.agrawal@nxp.com> References: <20200302145829.27808-1-hemant.agrawal@nxp.com> <20200306095742.18080-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 01/16] net/dpaa2: fix 10g port negotiation issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Rohit Raj Fixed 10g port negotiation issue with another 10G/non 10G port. Initialize the port link speed. Fixes: c5acbb5ea20e ("net/dpaa2: support link status event") Cc: stable@dpdk.org Signed-off-by: Rohit Raj --- drivers/net/dpaa2/dpaa2_ethdev.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index 2cde55e7c..4fc550a88 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -553,9 +553,6 @@ dpaa2_eth_dev_configure(struct rte_eth_dev *dev) if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK); - /* update the current status */ - dpaa2_dev_link_update(dev, 0); - return 0; } @@ -1757,6 +1754,7 @@ dpaa2_dev_set_link_up(struct rte_eth_dev *dev) /* changing tx burst function to start enqueues */ dev->tx_pkt_burst = dpaa2_dev_tx; dev->data->dev_link.link_status = state.up; + dev->data->dev_link.link_speed = state.rate; if (state.up) DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id); From patchwork Fri Mar 6 09:57:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 184238 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp7231469ile; Fri, 6 Mar 2020 02:00:03 -0800 (PST) X-Google-Smtp-Source: ADFU+vtjrS5hbMzS1Yrohv0Js6NC1N1APwBP9LyuqrawRN9xMswSfkOBBMm32+w+BH5xOAFOJOCM X-Received: by 2002:a05:6402:1d1a:: with SMTP id dg26mr2217903edb.260.1583488803118; Fri, 06 Mar 2020 02:00:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583488803; cv=none; d=google.com; s=arc-20160816; b=LlAQuG3kAz1y5beMJGYUUFcaMI+zI4gylrPbT5ECxaHxbqJ2pl80PhEVQgSqyDEwik S1xT84HRyrn/iEBaVDDFPCPc7P13jU2+ISR/orFfdF+w+9V9dlhdWxHxHuqQ2Yl1gTIX kn0LYtjq6LsAHcmoWl7L57GCEFpf6CpdNuuCzQ3mF5vYhP1/dm6d4yWCnXi/VFm2Uzm3 LJfIVgUyHDCWTTG2VuvZ4TJst+mil0KN7GOGOuMf7Y9q445oNR9qIAFDkUJ+agE+4gDX O/CTOWqoHYBxD2pqrvITx5yD6k9755QkOXwiiopxmPCBXh8epSXlEdiPBcWwpyy/wuDz ueLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=/Z0Lv5Ag9Pn/SNHwwnoj9gwOh+Z/OQgdZjsTu2OP4eU=; b=iKTQ+dgM8L2v4ExhQx1lluo1ECoiOJeLx7qMTsyfWPg6197vV9lykIkG9N5xInVisr u0vVXr3n6JbqwOG4PiXUA6qKHo0THzReUdkfHnMcrptsR9Q3Qs45N/yBGJEdgbFIkw74 Ozj8hdy5K9Y0ue38n4fKJlaFIXdxwD+7QYSBnlnk2Oa22NETG60RJ/RVMeI+XQmk2oYj 8tS+ZsbDZP2ci59DLuq1KUD6n2ds4Exhfe3MPiB/lH1Ps9aoAKoVhrjW18XsYD70FYIC kcbqrcOi6IlTbe3Y7816cQt3B0Jj5wWbMqnA1pIrSmBPAjt5/90pD3wepoB+1utCWBYf 1Ogg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id v22si1332775edq.37.2020.03.06.02.00.02; Fri, 06 Mar 2020 02:00:03 -0800 (PST) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 560CF1C002; Fri, 6 Mar 2020 10:59:48 +0100 (CET) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by dpdk.org (Postfix) with ESMTP id 2931F1BFF2; Fri, 6 Mar 2020 10:59:46 +0100 (CET) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id A4350200AD2; Fri, 6 Mar 2020 10:59:45 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 1EDA9200ADA; Fri, 6 Mar 2020 10:59:43 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 4EFC7402D5; Fri, 6 Mar 2020 17:59:39 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, stable@dpdk.org, Apeksha Gupta Date: Fri, 6 Mar 2020 15:27:28 +0530 Message-Id: <20200306095742.18080-3-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200306095742.18080-1-hemant.agrawal@nxp.com> References: <20200302145829.27808-1-hemant.agrawal@nxp.com> <20200306095742.18080-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 02/16] bus/fslmc: fix dereferencing null pointer X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Apeksha Gupta This patch fixees the nxp internal coverity reported null pointer dereferncing issue. Fixes: 6fef517e17cf ("bus/fslmc: add qman HW fq query count API") Cc: stable@dpdk.org Signed-off-by: Apeksha Gupta --- drivers/bus/fslmc/qbman/qbman_debug.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/bus/fslmc/qbman/qbman_debug.c b/drivers/bus/fslmc/qbman/qbman_debug.c index 0bb2ce880..34374ae4b 100644 --- a/drivers/bus/fslmc/qbman/qbman_debug.c +++ b/drivers/bus/fslmc/qbman/qbman_debug.c @@ -20,26 +20,27 @@ struct qbman_fq_query_desc { uint8_t verb; uint8_t reserved[3]; uint32_t fqid; - uint8_t reserved2[57]; + uint8_t reserved2[56]; }; int qbman_fq_query_state(struct qbman_swp *s, uint32_t fqid, struct qbman_fq_query_np_rslt *r) { struct qbman_fq_query_desc *p; + struct qbman_fq_query_np_rslt *var; p = (struct qbman_fq_query_desc *)qbman_swp_mc_start(s); if (!p) return -EBUSY; p->fqid = fqid; - *r = *(struct qbman_fq_query_np_rslt *)qbman_swp_mc_complete(s, p, - QBMAN_FQ_QUERY_NP); - if (!r) { + var = qbman_swp_mc_complete(s, p, QBMAN_FQ_QUERY_NP); + if (!var) { pr_err("qbman: Query FQID %d NP fields failed, no response\n", fqid); return -EIO; } + *r = *var; /* Decode the outcome */ QBMAN_BUG_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != QBMAN_FQ_QUERY_NP); From patchwork Fri Mar 6 09:57:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 184239 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp7231612ile; Fri, 6 Mar 2020 02:00:12 -0800 (PST) X-Google-Smtp-Source: ADFU+vvruudRqeHIlsDBdn9sq2CR82aJho2JgJpvVl594aDuouxdtnbMUu5fvgQf8ZTsfMJe8JMJ X-Received: by 2002:a05:6402:6c9:: with SMTP id n9mr2249500edy.325.1583488812297; Fri, 06 Mar 2020 02:00:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583488812; cv=none; d=google.com; s=arc-20160816; b=NDa6RY93Auz39xRmlWebAEgm0+hUtro0iBDkaiGW88V3S7OUSWlrH0mHgh7NFaUGAb cLE8OBPJ7z3mTAZX0229G48Kd3uh9pG67pQxRGGHHEw7T3Wg2Q0w4fjHbsaz8i5LGrMu rDUjXz1wEJ3n/ZI0YDtbKWbQLIsnaXYI+Y/9bcissdflPseHICqdOvU6KR6qsweWhyZT aBL+SEx+J61ynvwk4kgve/cOHya3fpa6fV+/dslk/DPoL4PeGv6s1BpDjgkKR7QpZQPR FRoEC5pk/Hiw/PTVbuMIGsco98yrtKFbBVwC4DPbZ6kr06OWzL6Dd4ldDTKyBO1XKA2E w14A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=P/6rkDKgrnYVj8XnNq+73eBXq6hRHcWuzVYow8ogSMo=; b=q4gRP5sRbXxmLGralSSdNSTxUYT3i7RN8Mgi8SCQQHsEtPVmCYrxWLISvTT9SrvqMO oDwJLLCG59Otwl1C2kI+iWJGXQj9sJjLCOYrr9fqhh4TuV7dohz5JsQurJxkByw9eZoS PqHRKLRZu+x6MhvcoqyWuJTktcL5z8esOallR9Nmjc7faFp3aWpGulf2UWCJL2I9bGYd aciqv+yZtbt0aButdRBJBMjAne59yzyDJ9a85CjHGIV5nfySm73DOKGQyinWV2ZHPtnV SbSuF+CkWnusb4cYJdI9suuHj1wQhcnXmISVy2dNl+OqMectwIWIjAGQWCKESaKZ3gUH iZkw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id j18si1011318ejy.467.2020.03.06.02.00.12; Fri, 06 Mar 2020 02:00:12 -0800 (PST) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 410451BFF9; Fri, 6 Mar 2020 10:59:50 +0100 (CET) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by dpdk.org (Postfix) with ESMTP id 2E3541BFF3 for ; Fri, 6 Mar 2020 10:59:46 +0100 (CET) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id E31872008DC; Fri, 6 Mar 2020 10:59:45 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 981AD200217; Fri, 6 Mar 2020 10:59:43 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 510A3402E2; Fri, 6 Mar 2020 17:59:40 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Gagandeep Singh Date: Fri, 6 Mar 2020 15:27:29 +0530 Message-Id: <20200306095742.18080-4-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200306095742.18080-1-hemant.agrawal@nxp.com> References: <20200302145829.27808-1-hemant.agrawal@nxp.com> <20200306095742.18080-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 03/16] bus/fslmc: combine thread specific variables X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Gagandeep Singh This is to reduce the thread local storage. Note that though these variables are part of *.map file but they are internal to tbe fslmc and dpaa2 drivers and not exposed outside. Signed-off-by: Gagandeep Singh --- drivers/bus/fslmc/fslmc_bus.c | 2 -- drivers/bus/fslmc/portal/dpaa2_hw_dpio.h | 7 +++++++ drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 8 ++++++++ drivers/bus/fslmc/rte_fslmc.h | 18 ------------------ 4 files changed, 15 insertions(+), 20 deletions(-) -- 2.17.1 diff --git a/drivers/bus/fslmc/fslmc_bus.c b/drivers/bus/fslmc/fslmc_bus.c index b3e964aa9..1f657822f 100644 --- a/drivers/bus/fslmc/fslmc_bus.c +++ b/drivers/bus/fslmc/fslmc_bus.c @@ -37,8 +37,6 @@ rte_fslmc_get_device_count(enum rte_dpaa2_dev_type device_type) return rte_fslmc_bus.device_count[device_type]; } -RTE_DEFINE_PER_LCORE(struct dpaa2_portal_dqrr, dpaa2_held_bufs); - static void cleanup_fslmc_device_list(void) { diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h index 2829c9380..9da4af782 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h @@ -28,6 +28,13 @@ RTE_DECLARE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io); #define DPAA2_PER_LCORE_ETHRX_DPIO RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev #define DPAA2_PER_LCORE_ETHRX_PORTAL DPAA2_PER_LCORE_ETHRX_DPIO->sw_portal +#define DPAA2_PER_LCORE_DQRR_SIZE \ + RTE_PER_LCORE(_dpaa2_io).dpio_dev->dpaa2_held_bufs.dqrr_size +#define DPAA2_PER_LCORE_DQRR_HELD \ + RTE_PER_LCORE(_dpaa2_io).dpio_dev->dpaa2_held_bufs.dqrr_held +#define DPAA2_PER_LCORE_DQRR_MBUF(i) \ + RTE_PER_LCORE(_dpaa2_io).dpio_dev->dpaa2_held_bufs.mbuf[i] + /* Variable to store DPAA2 DQRR size */ extern uint8_t dpaa2_dqrr_size; /* Variable to store DPAA2 EQCR size */ diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h index ab2b213f8..bde1441f4 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h @@ -87,6 +87,13 @@ struct eqresp_metadata { struct rte_mempool *mp; }; +#define DPAA2_PORTAL_DEQUEUE_DEPTH 32 +struct dpaa2_portal_dqrr { + struct rte_mbuf *mbuf[DPAA2_PORTAL_DEQUEUE_DEPTH]; + uint64_t dqrr_held; + uint8_t dqrr_size; +}; + struct dpaa2_dpio_dev { TAILQ_ENTRY(dpaa2_dpio_dev) next; /**< Pointer to Next device instance */ @@ -112,6 +119,7 @@ struct dpaa2_dpio_dev { struct rte_intr_handle intr_handle; /* Interrupt related info */ int32_t epoll_fd; /**< File descriptor created for interrupt polling */ int32_t hw_id; /**< An unique ID of this DPIO device instance */ + struct dpaa2_portal_dqrr dpaa2_held_bufs; }; struct dpaa2_dpbp_dev { diff --git a/drivers/bus/fslmc/rte_fslmc.h b/drivers/bus/fslmc/rte_fslmc.h index 96ba8dc25..a59f0077e 100644 --- a/drivers/bus/fslmc/rte_fslmc.h +++ b/drivers/bus/fslmc/rte_fslmc.h @@ -137,24 +137,6 @@ struct rte_fslmc_bus { /**< Count of all devices scanned */ }; -#define DPAA2_PORTAL_DEQUEUE_DEPTH 32 - -/* Create storage for dqrr entries per lcore */ -struct dpaa2_portal_dqrr { - struct rte_mbuf *mbuf[DPAA2_PORTAL_DEQUEUE_DEPTH]; - uint64_t dqrr_held; - uint8_t dqrr_size; -}; - -RTE_DECLARE_PER_LCORE(struct dpaa2_portal_dqrr, dpaa2_held_bufs); - -#define DPAA2_PER_LCORE_DQRR_SIZE \ - RTE_PER_LCORE(dpaa2_held_bufs).dqrr_size -#define DPAA2_PER_LCORE_DQRR_HELD \ - RTE_PER_LCORE(dpaa2_held_bufs).dqrr_held -#define DPAA2_PER_LCORE_DQRR_MBUF(i) \ - RTE_PER_LCORE(dpaa2_held_bufs).mbuf[i] - /** * Register a DPAA2 driver. * From patchwork Fri Mar 6 09:57:30 2020 Content-Type: text/plain; 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[92.243.14.124]) by mx.google.com with ESMTP id c9si1295078edt.135.2020.03.06.02.00.22; Fri, 06 Mar 2020 02:00:22 -0800 (PST) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 020521C01B; Fri, 6 Mar 2020 10:59:52 +0100 (CET) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id 1E58B1BFF3 for ; Fri, 6 Mar 2020 10:59:47 +0100 (CET) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id CFDBA1A0A80; Fri, 6 Mar 2020 10:59:46 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 8265C1A0AA7; Fri, 6 Mar 2020 10:59:44 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 40D33402E5; Fri, 6 Mar 2020 17:59:41 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Nipun Gupta Date: Fri, 6 Mar 2020 15:27:30 +0530 Message-Id: <20200306095742.18080-5-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200306095742.18080-1-hemant.agrawal@nxp.com> References: <20200302145829.27808-1-hemant.agrawal@nxp.com> <20200306095742.18080-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 04/16] bus/fslmc: rework portal allocation to a per thread basis X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nipun Gupta The patch reworks the portal allocation which was previously being done on per lcore basis to a per thread basis. Now user can also create its own threads and use DPAA2 portals for packet I/O. Signed-off-by: Nipun Gupta --- drivers/bus/fslmc/Makefile | 1 + drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 210 ++++++++++++----------- drivers/bus/fslmc/portal/dpaa2_hw_dpio.h | 3 - 3 files changed, 114 insertions(+), 100 deletions(-) -- 2.17.1 diff --git a/drivers/bus/fslmc/Makefile b/drivers/bus/fslmc/Makefile index 6d2286088..b38305fb4 100644 --- a/drivers/bus/fslmc/Makefile +++ b/drivers/bus/fslmc/Makefile @@ -18,6 +18,7 @@ CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/mc CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/qbman/include CFLAGS += -I$(RTE_SDK)/drivers/common/dpaax CFLAGS += -I$(RTE_SDK)/lib/librte_eal/common +LDLIBS += -lpthread LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring LDLIBS += -lrte_ethdev LDLIBS += -lrte_common_dpaax diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c index 739ce434b..e765a382f 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c @@ -62,6 +62,9 @@ uint8_t dpaa2_dqrr_size; /* Variable to store DPAA2 EQCR size */ uint8_t dpaa2_eqcr_size; +/* Variable to hold the portal_key, once created.*/ +static pthread_key_t dpaa2_portal_key; + /*Stashing Macros default for LS208x*/ static int dpaa2_core_cluster_base = 0x04; static int dpaa2_cluster_sz = 2; @@ -87,6 +90,32 @@ static int dpaa2_cluster_sz = 2; * Cluster 4 (ID = x07) : CPU14, CPU15; */ +static int +dpaa2_get_core_id(void) +{ + rte_cpuset_t cpuset; + int i, ret, cpu_id = -1; + + ret = pthread_getaffinity_np(pthread_self(), sizeof(cpu_set_t), + &cpuset); + if (ret) { + DPAA2_BUS_ERR("pthread_getaffinity_np() failed"); + return ret; + } + + for (i = 0; i < RTE_MAX_LCORE; i++) { + if (CPU_ISSET(i, &cpuset)) { + if (cpu_id == -1) + cpu_id = i; + else + /* Multiple cpus are affined */ + return -1; + } + } + + return cpu_id; +} + static int dpaa2_core_cluster_sdest(int cpu_id) { @@ -97,7 +126,7 @@ dpaa2_core_cluster_sdest(int cpu_id) #ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV static void -dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id, int lcoreid) +dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id, int cpu_id) { #define STRING_LEN 28 #define COMMAND_LEN 50 @@ -130,7 +159,7 @@ dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id, int lcoreid) return; } - cpu_mask = cpu_mask << dpaa2_cpu[lcoreid]; + cpu_mask = cpu_mask << dpaa2_cpu[cpu_id]; snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity", cpu_mask, token); ret = system(command); @@ -144,7 +173,7 @@ dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id, int lcoreid) fclose(file); } -static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev, int lcoreid) +static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev, int cpu_id) { struct epoll_event epoll_ev; int eventfd, dpio_epoll_fd, ret; @@ -181,36 +210,42 @@ static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev, int lcoreid) } dpio_dev->epoll_fd = dpio_epoll_fd; - dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id, lcoreid); + dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id, cpu_id); return 0; } + +static void dpaa2_dpio_intr_deinit(struct dpaa2_dpio_dev *dpio_dev) +{ + int ret; + + ret = rte_dpaa2_intr_disable(&dpio_dev->intr_handle, 0); + if (ret) + DPAA2_BUS_ERR("DPIO interrupt disable failed"); + + close(dpio_dev->epoll_fd); +} #endif static int -dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int lcoreid) +dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev) { int sdest, ret; int cpu_id; /* Set the Stashing Destination */ - if (lcoreid < 0) { - lcoreid = rte_get_master_lcore(); - if (lcoreid < 0) { - DPAA2_BUS_ERR("Getting CPU Index failed"); - return -1; - } + cpu_id = dpaa2_get_core_id(); + if (cpu_id < 0) { + DPAA2_BUS_ERR("Thread not affined to a single core"); + return -1; } - cpu_id = dpaa2_cpu[lcoreid]; - /* Set the STASH Destination depending on Current CPU ID. * Valid values of SDEST are 4,5,6,7. Where, */ - sdest = dpaa2_core_cluster_sdest(cpu_id); - DPAA2_BUS_DEBUG("Portal= %d CPU= %u lcore id =%u SDEST= %d", - dpio_dev->index, cpu_id, lcoreid, sdest); + DPAA2_BUS_DEBUG("Portal= %d CPU= %u SDEST= %d", + dpio_dev->index, cpu_id, sdest); ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token, sdest); @@ -220,7 +255,7 @@ dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int lcoreid) } #ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV - if (dpaa2_dpio_intr_init(dpio_dev, lcoreid)) { + if (dpaa2_dpio_intr_init(dpio_dev, cpu_id)) { DPAA2_BUS_ERR("Interrupt registration failed for dpio"); return -1; } @@ -229,7 +264,7 @@ dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int lcoreid) return 0; } -static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int lcoreid) +static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void) { struct dpaa2_dpio_dev *dpio_dev = NULL; int ret; @@ -245,108 +280,74 @@ static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int lcoreid) DPAA2_BUS_DEBUG("New Portal %p (%d) affined thread - %lu", dpio_dev, dpio_dev->index, syscall(SYS_gettid)); - ret = dpaa2_configure_stashing(dpio_dev, lcoreid); - if (ret) + ret = dpaa2_configure_stashing(dpio_dev); + if (ret) { DPAA2_BUS_ERR("dpaa2_configure_stashing failed"); + return NULL; + } return dpio_dev; } +static void dpaa2_put_qbman_swp(struct dpaa2_dpio_dev *dpio_dev) +{ +#ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV + dpaa2_dpio_intr_deinit(dpio_dev); +#endif + if (dpio_dev) + rte_atomic16_clear(&dpio_dev->ref_count); +} + int dpaa2_affine_qbman_swp(void) { - unsigned int lcore_id = rte_lcore_id(); + struct dpaa2_dpio_dev *dpio_dev; uint64_t tid = syscall(SYS_gettid); - if (lcore_id == LCORE_ID_ANY) - lcore_id = rte_get_master_lcore(); - /* if the core id is not supported */ - else if (lcore_id >= RTE_MAX_LCORE) - return -1; - - if (dpaa2_io_portal[lcore_id].dpio_dev) { - DPAA2_BUS_DP_INFO("DPAA Portal=%p (%d) is being shared" - " between thread %" PRIu64 " and current " - "%" PRIu64 "\n", - dpaa2_io_portal[lcore_id].dpio_dev, - dpaa2_io_portal[lcore_id].dpio_dev->index, - dpaa2_io_portal[lcore_id].net_tid, - tid); - RTE_PER_LCORE(_dpaa2_io).dpio_dev - = dpaa2_io_portal[lcore_id].dpio_dev; - rte_atomic16_inc(&dpaa2_io_portal - [lcore_id].dpio_dev->ref_count); - dpaa2_io_portal[lcore_id].net_tid = tid; - - DPAA2_BUS_DP_DEBUG("Old Portal=%p (%d) affined thread - " - "%" PRIu64 "\n", - dpaa2_io_portal[lcore_id].dpio_dev, - dpaa2_io_portal[lcore_id].dpio_dev->index, - tid); - return 0; - } - /* Populate the dpaa2_io_portal structure */ - dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(lcore_id); - - if (dpaa2_io_portal[lcore_id].dpio_dev) { - RTE_PER_LCORE(_dpaa2_io).dpio_dev - = dpaa2_io_portal[lcore_id].dpio_dev; - dpaa2_io_portal[lcore_id].net_tid = tid; + if (!RTE_PER_LCORE(_dpaa2_io).dpio_dev) { + dpio_dev = dpaa2_get_qbman_swp(); + if (!dpio_dev) { + DPAA2_BUS_ERR("No software portal resource left"); + return -1; + } + RTE_PER_LCORE(_dpaa2_io).dpio_dev = dpio_dev; - return 0; - } else { - return -1; + DPAA2_BUS_INFO( + "DPAA Portal=%p (%d) is affined to thread %" PRIu64, + dpio_dev, dpio_dev->index, tid); } + return 0; } int dpaa2_affine_qbman_ethrx_swp(void) { - unsigned int lcore_id = rte_lcore_id(); + struct dpaa2_dpio_dev *dpio_dev; uint64_t tid = syscall(SYS_gettid); - if (lcore_id == LCORE_ID_ANY) - lcore_id = rte_get_master_lcore(); - /* if the core id is not supported */ - else if (lcore_id >= RTE_MAX_LCORE) - return -1; + /* Populate the dpaa2_io_portal structure */ + if (!RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev) { + dpio_dev = dpaa2_get_qbman_swp(); + if (!dpio_dev) { + DPAA2_BUS_ERR("No software portal resource left"); + return -1; + } + RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev = dpio_dev; - if (dpaa2_io_portal[lcore_id].ethrx_dpio_dev) { - DPAA2_BUS_DP_INFO( - "DPAA Portal=%p (%d) is being shared between thread" - " %" PRIu64 " and current %" PRIu64 "\n", - dpaa2_io_portal[lcore_id].ethrx_dpio_dev, - dpaa2_io_portal[lcore_id].ethrx_dpio_dev->index, - dpaa2_io_portal[lcore_id].sec_tid, - tid); - RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev - = dpaa2_io_portal[lcore_id].ethrx_dpio_dev; - rte_atomic16_inc(&dpaa2_io_portal - [lcore_id].ethrx_dpio_dev->ref_count); - dpaa2_io_portal[lcore_id].sec_tid = tid; - - DPAA2_BUS_DP_DEBUG( - "Old Portal=%p (%d) affined thread" - " - %" PRIu64 "\n", - dpaa2_io_portal[lcore_id].ethrx_dpio_dev, - dpaa2_io_portal[lcore_id].ethrx_dpio_dev->index, - tid); - return 0; + DPAA2_BUS_INFO( + "DPAA Portal=%p (%d) is affined for eth rx to thread %" + PRIu64, dpio_dev, dpio_dev->index, tid); } + return 0; +} - /* Populate the dpaa2_io_portal structure */ - dpaa2_io_portal[lcore_id].ethrx_dpio_dev = - dpaa2_get_qbman_swp(lcore_id); - - if (dpaa2_io_portal[lcore_id].ethrx_dpio_dev) { - RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev - = dpaa2_io_portal[lcore_id].ethrx_dpio_dev; - dpaa2_io_portal[lcore_id].sec_tid = tid; - return 0; - } else { - return -1; - } +static void __attribute__((destructor(102))) dpaa2_portal_finish(void *arg) +{ + RTE_SET_USED(arg); + + dpaa2_put_qbman_swp(RTE_PER_LCORE(_dpaa2_io).dpio_dev); + dpaa2_put_qbman_swp(RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev); } /* @@ -398,6 +399,7 @@ dpaa2_create_dpio_device(int vdev_fd, struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)}; struct qbman_swp_desc p_des; struct dpio_attr attr; + int ret; static int check_lcore_cpuset; if (obj_info->num_regions < NUM_DPIO_REGIONS) { @@ -547,12 +549,26 @@ dpaa2_create_dpio_device(int vdev_fd, TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next); + if (!dpaa2_portal_key) { + /* create the key, supplying a function that'll be invoked + * when a portal affined thread will be deleted. + */ + ret = pthread_key_create(&dpaa2_portal_key, + dpaa2_portal_finish); + if (ret) { + DPAA2_BUS_DEBUG("Unable to create pthread key (%d)", + ret); + goto err; + } + } + return 0; err: if (dpio_dev->dpio) { dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); + rte_free(dpio_dev->eqresp); rte_free(dpio_dev->dpio); } diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h index 9da4af782..8af0474a1 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h @@ -14,9 +14,6 @@ struct dpaa2_io_portal_t { struct dpaa2_dpio_dev *dpio_dev; struct dpaa2_dpio_dev *ethrx_dpio_dev; - uint64_t net_tid; - uint64_t sec_tid; - void *eventdev; }; /*! Global per thread DPIO portal */ From patchwork Fri Mar 6 09:57:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 184241 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp7231922ile; Fri, 6 Mar 2020 02:00:31 -0800 (PST) X-Google-Smtp-Source: ADFU+vud4rHuyUUh2X8opNBmpMGONAxtFX9tibDNSI2OJ9+7kQSxF5FwleES9EVtJTrb/8xGdAU/ X-Received: by 2002:a17:906:b30f:: with SMTP id n15mr2204610ejz.236.1583488831308; Fri, 06 Mar 2020 02:00:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583488831; cv=none; d=google.com; s=arc-20160816; b=Ou1w7AVXR141fDpcFNnTD90AJwZRbUf15nfuSc146WHpQ2F6sGAMhrPoLNWj0vovPc 2u+QtDR7X1m5RalSsj8s6WXoe1NYHpFhV/kr1rU4lVZMSUyXPflTW7TEVJMBKlX9P4SQ gUTQHJWs3Y04EGm8RKCcmZ7mj4BeSSlpHgeTdnJaYmolT+jDTXPwLPXr2NCwzdYZcOg+ aF20XyKiutdMvyZUUYuybj319drh4afmhWIRRDSedkymziD7NhzkwSZuXZ+sZZxZWkKz Ku6HEli7HK+IwBO74R5Y7PMsl07rctjxL58mRhM65OWGquzmRAWtUberB75ubqzPj+Mv tYhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=Zzun9V5RN15MMkqrRrwz00rFsKuKWipu9MHL6XMxTwY=; b=Dimcc19jQ+cfEhIjuNyxJlIVl80emplk0hWltxY/EyDD+hORLt9se7ihYyaBa+sfHP QGl+g9QN56A+1t0tupc8iZMBLnPKc8r8qWWTVpnDmxfzbKJ/1pe+kDmSDFGIiC4GDzkt OmzrTV4BFH579oNpyNLOP3EzFM5Q+PMeE/Dkk2ERHTVNQgZG3xuHWlLtQQZUCXjRJTvZ Bcb59TaRLNa8TVYjMZLTsjT1sM+m6xpIvpx/LNSGK9+h/yi1JbXNYQp5JTFPH2g49/sL /nHRIvIokd8C/zyczgiY0tdH4o01LRHGhZ7M8a+U38XHufNO6sxSJMICJWZ+qPHrUe9k 9gqg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id y9si1339853edp.421.2020.03.06.02.00.31; Fri, 06 Mar 2020 02:00:31 -0800 (PST) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B57FE1C029; Fri, 6 Mar 2020 10:59:53 +0100 (CET) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id AB6691BFD6 for ; Fri, 6 Mar 2020 10:59:48 +0100 (CET) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 89ECA1A0AA9; Fri, 6 Mar 2020 10:59:48 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 057C81A0A62; Fri, 6 Mar 2020 10:59:46 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 32E5540294; Fri, 6 Mar 2020 17:59:42 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Nipun Gupta , Hemant Agrawal Date: Fri, 6 Mar 2020 15:27:31 +0530 Message-Id: <20200306095742.18080-6-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200306095742.18080-1-hemant.agrawal@nxp.com> References: <20200302145829.27808-1-hemant.agrawal@nxp.com> <20200306095742.18080-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 05/16] bus/fslmc: support handle portal alloc failure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add the error handling on failure. Signed-off-by: Nipun Gupta Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 28 ++++++++++++++---------- 1 file changed, 16 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c index e765a382f..1a1453ea3 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c @@ -264,6 +264,16 @@ dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev) return 0; } +static void dpaa2_put_qbman_swp(struct dpaa2_dpio_dev *dpio_dev) +{ + if (dpio_dev) { +#ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV + dpaa2_dpio_intr_deinit(dpio_dev); +#endif + rte_atomic16_clear(&dpio_dev->ref_count); + } +} + static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void) { struct dpaa2_dpio_dev *dpio_dev = NULL; @@ -274,8 +284,10 @@ static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void) if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count)) break; } - if (!dpio_dev) + if (!dpio_dev) { + DPAA2_BUS_ERR("No software portal resource left"); return NULL; + } DPAA2_BUS_DEBUG("New Portal %p (%d) affined thread - %lu", dpio_dev, dpio_dev->index, syscall(SYS_gettid)); @@ -283,21 +295,13 @@ static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void) ret = dpaa2_configure_stashing(dpio_dev); if (ret) { DPAA2_BUS_ERR("dpaa2_configure_stashing failed"); + rte_atomic16_clear(&dpio_dev->ref_count); return NULL; } return dpio_dev; } -static void dpaa2_put_qbman_swp(struct dpaa2_dpio_dev *dpio_dev) -{ -#ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV - dpaa2_dpio_intr_deinit(dpio_dev); -#endif - if (dpio_dev) - rte_atomic16_clear(&dpio_dev->ref_count); -} - int dpaa2_affine_qbman_swp(void) { @@ -308,7 +312,7 @@ dpaa2_affine_qbman_swp(void) if (!RTE_PER_LCORE(_dpaa2_io).dpio_dev) { dpio_dev = dpaa2_get_qbman_swp(); if (!dpio_dev) { - DPAA2_BUS_ERR("No software portal resource left"); + DPAA2_BUS_ERR("Error in software portal allocation"); return -1; } RTE_PER_LCORE(_dpaa2_io).dpio_dev = dpio_dev; @@ -330,7 +334,7 @@ dpaa2_affine_qbman_ethrx_swp(void) if (!RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev) { dpio_dev = dpaa2_get_qbman_swp(); if (!dpio_dev) { - DPAA2_BUS_ERR("No software portal resource left"); + DPAA2_BUS_ERR("Error in software portal allocation"); return -1; } RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev = dpio_dev; From patchwork Fri Mar 6 09:57:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 184242 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp7232152ile; Fri, 6 Mar 2020 02:00:45 -0800 (PST) X-Google-Smtp-Source: ADFU+vsdVaV0SxxyEDQXGcWxu9e93lrLwo7hCa+A35YfVAQl0PvMtTtmxeUITKIH6xnGhGKGDgCo X-Received: by 2002:a05:6402:2214:: with SMTP id cq20mr2190920edb.302.1583488844833; Fri, 06 Mar 2020 02:00:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583488844; cv=none; d=google.com; s=arc-20160816; b=yGR0uK7qxG/n1wUL8zihwJHq0PWLX5ne/w3Q4aZeTaVxfaTJLI+ub4VMnxZp49GlDq WzVLh7GuzRHSmAKyy+L9gGz6vgZOeGIAyiodHj2JSg4r9q7wT/W8NsqvFzC4r/d66RZr UEMhKSb2qhkeGXzrZlAI7wY+N2ueoSCouHmazMCWpE6tSXRS2z5CsvGMZY/l2jfWi2f9 5uwnxrXWXPCtZ3FMYw0OJ7krQMexTmql7QeuFdI3biYeHVFD4y1W4V3OO9uB91XK17gY rnkbRD3//YOfFcT9KeF9IAINS4AZmctmDHJduI0z+HT83KIVqrfVEbuisbSVhtLfC3h2 tedg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=flnDolx4+AgifEEonUxUXPuA2wkg88lpPccymmgBjh4=; b=XdLpkyXRQti3Foa+D4VLIuYue5I2GbFZ7rGgsQPPXAf1xOjTWtBcHQELfmozZAhuN+ DbVNAM0bo2W/hCYdL4+77jlLkKooTNvFJr12hHmLmXSwqptZIa2GTjpYL3LK3mu5lOXO 13D15XUaSvCKr0gEdHuPnt1TDZ/SnHQBJ9B4lHwVlwCeRyfUon7fCmHmFYIXnCT7fyGl qOeS/5+HwHsEPggrA18mA5L3uvTzgfDQeXrhAclFJBIXFQ92C1KqsjuYT4rrp1uhp3Gp mnp4sVIzVymFqigAzmWFd/T5VdEOQdcvfEKtOYPBYdhXbxC+vZ43osVpxqJ/esBtAFhO Y1mw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id j5si1544721edv.89.2020.03.06.02.00.44; Fri, 06 Mar 2020 02:00:44 -0800 (PST) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 874C21C030; Fri, 6 Mar 2020 10:59:55 +0100 (CET) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id 800111BFF5 for ; Fri, 6 Mar 2020 10:59:49 +0100 (CET) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 644FB1A0AB0; Fri, 6 Mar 2020 10:59:49 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 50C1D1A0AA0; Fri, 6 Mar 2020 10:59:47 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 38E07402F3; Fri, 6 Mar 2020 17:59:43 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Nipun Gupta Date: Fri, 6 Mar 2020 15:27:32 +0530 Message-Id: <20200306095742.18080-7-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200306095742.18080-1-hemant.agrawal@nxp.com> References: <20200302145829.27808-1-hemant.agrawal@nxp.com> <20200306095742.18080-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 06/16] bus/fslmc: limit pthread destructor called for dpaa2 only X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nipun Gupta The destructor was being called for non-dpaa2 as well Signed-off-by: Nipun Gupta --- drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c index 1a1453ea3..054d45306 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c @@ -299,6 +299,13 @@ static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void) return NULL; } + ret = pthread_setspecific(dpaa2_portal_key, (void *)dpio_dev); + if (ret) { + DPAA2_BUS_ERR("pthread_setspecific failed with ret: %d", ret); + dpaa2_put_qbman_swp(dpio_dev); + return NULL; + } + return dpio_dev; } @@ -346,12 +353,14 @@ dpaa2_affine_qbman_ethrx_swp(void) return 0; } -static void __attribute__((destructor(102))) dpaa2_portal_finish(void *arg) +static void dpaa2_portal_finish(void *arg) { RTE_SET_USED(arg); dpaa2_put_qbman_swp(RTE_PER_LCORE(_dpaa2_io).dpio_dev); dpaa2_put_qbman_swp(RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev); + + pthread_setspecific(dpaa2_portal_key, NULL); } /* From patchwork Fri Mar 6 09:57:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 184243 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp7232327ile; Fri, 6 Mar 2020 02:00:54 -0800 (PST) X-Google-Smtp-Source: ADFU+vuTICNktVCefzktxJnR6GD9SCk8Kw2o3MjAXX0ivtwCHu7nAElM7cCz3TuaTNEKOR+FUlOD X-Received: by 2002:a17:906:44f:: with SMTP id e15mr879939eja.58.1583488854210; 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[92.243.14.124]) by mx.google.com with ESMTP id o3si998201eje.261.2020.03.06.02.00.53; Fri, 06 Mar 2020 02:00:54 -0800 (PST) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C872A1C02C; Fri, 6 Mar 2020 10:59:56 +0100 (CET) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id 525E21C00E for ; Fri, 6 Mar 2020 10:59:50 +0100 (CET) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 2F5391A0AA7; Fri, 6 Mar 2020 10:59:50 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 9CECF1A0AAF; Fri, 6 Mar 2020 10:59:47 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 35900402FA; Fri, 6 Mar 2020 17:59:44 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Nipun Gupta Date: Fri, 6 Mar 2020 15:27:33 +0530 Message-Id: <20200306095742.18080-8-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200306095742.18080-1-hemant.agrawal@nxp.com> References: <20200302145829.27808-1-hemant.agrawal@nxp.com> <20200306095742.18080-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 07/16] bus/fslmc: support portal migration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nipun Gupta The patch adds support for portal migration by disabling stashing for the portals which is used in the non-affined threads, or on threads affined to multiple cores Signed-off-by: Nipun Gupta --- drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 83 +---- .../fslmc/qbman/include/fsl_qbman_portal.h | 8 +- drivers/bus/fslmc/qbman/qbman_portal.c | 340 +++++++++++++++++- drivers/bus/fslmc/qbman/qbman_portal.h | 19 +- drivers/bus/fslmc/qbman/qbman_sys.h | 135 ++++++- 5 files changed, 502 insertions(+), 83 deletions(-) -- 2.17.1 diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c index 054d45306..2102d2981 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c @@ -53,10 +53,6 @@ static uint32_t io_space_count; /* Variable to store DPAA2 platform type */ uint32_t dpaa2_svr_family; -/* Physical core id for lcores running on dpaa2. */ -/* DPAA2 only support 1 lcore to 1 phy cpu mapping */ -static unsigned int dpaa2_cpu[RTE_MAX_LCORE]; - /* Variable to store DPAA2 DQRR size */ uint8_t dpaa2_dqrr_size; /* Variable to store DPAA2 EQCR size */ @@ -159,7 +155,7 @@ dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id, int cpu_id) return; } - cpu_mask = cpu_mask << dpaa2_cpu[cpu_id]; + cpu_mask = cpu_mask << cpu_id; snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity", cpu_mask, token); ret = system(command); @@ -228,17 +224,9 @@ static void dpaa2_dpio_intr_deinit(struct dpaa2_dpio_dev *dpio_dev) #endif static int -dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev) +dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id) { int sdest, ret; - int cpu_id; - - /* Set the Stashing Destination */ - cpu_id = dpaa2_get_core_id(); - if (cpu_id < 0) { - DPAA2_BUS_ERR("Thread not affined to a single core"); - return -1; - } /* Set the STASH Destination depending on Current CPU ID. * Valid values of SDEST are 4,5,6,7. Where, @@ -277,6 +265,7 @@ static void dpaa2_put_qbman_swp(struct dpaa2_dpio_dev *dpio_dev) static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void) { struct dpaa2_dpio_dev *dpio_dev = NULL; + int cpu_id; int ret; /* Get DPIO dev handle from list using index */ @@ -292,11 +281,19 @@ static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void) DPAA2_BUS_DEBUG("New Portal %p (%d) affined thread - %lu", dpio_dev, dpio_dev->index, syscall(SYS_gettid)); - ret = dpaa2_configure_stashing(dpio_dev); - if (ret) { - DPAA2_BUS_ERR("dpaa2_configure_stashing failed"); - rte_atomic16_clear(&dpio_dev->ref_count); - return NULL; + /* Set the Stashing Destination */ + cpu_id = dpaa2_get_core_id(); + if (cpu_id < 0) { + DPAA2_BUS_WARN("Thread not affined to a single core"); + if (dpaa2_svr_family != SVR_LX2160A) + qbman_swp_update(dpio_dev->sw_portal, 1); + } else { + ret = dpaa2_configure_stashing(dpio_dev, cpu_id); + if (ret) { + DPAA2_BUS_ERR("dpaa2_configure_stashing failed"); + rte_atomic16_clear(&dpio_dev->ref_count); + return NULL; + } } ret = pthread_setspecific(dpaa2_portal_key, (void *)dpio_dev); @@ -363,46 +360,6 @@ static void dpaa2_portal_finish(void *arg) pthread_setspecific(dpaa2_portal_key, NULL); } -/* - * This checks for not supported lcore mappings as well as get the physical - * cpuid for the lcore. - * one lcore can only map to 1 cpu i.e. 1@10-14 not supported. - * one cpu can be mapped to more than one lcores. - */ -static int -dpaa2_check_lcore_cpuset(void) -{ - unsigned int lcore_id, i; - int ret = 0; - - for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) - dpaa2_cpu[lcore_id] = 0xffffffff; - - for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) { - rte_cpuset_t cpuset = rte_lcore_cpuset(lcore_id); - - for (i = 0; i < CPU_SETSIZE; i++) { - if (!CPU_ISSET(i, &cpuset)) - continue; - if (i >= RTE_MAX_LCORE) { - DPAA2_BUS_ERR("ERR:lcore map to core %u (>= %u) not supported", - i, RTE_MAX_LCORE); - ret = -1; - continue; - } - RTE_LOG(DEBUG, EAL, "lcore id = %u cpu=%u\n", - lcore_id, i); - if (dpaa2_cpu[lcore_id] != 0xffffffff) { - DPAA2_BUS_ERR("ERR:lcore map to multi-cpu not supported"); - ret = -1; - continue; - } - dpaa2_cpu[lcore_id] = i; - } - } - return ret; -} - static int dpaa2_create_dpio_device(int vdev_fd, struct vfio_device_info *obj_info, @@ -413,7 +370,6 @@ dpaa2_create_dpio_device(int vdev_fd, struct qbman_swp_desc p_des; struct dpio_attr attr; int ret; - static int check_lcore_cpuset; if (obj_info->num_regions < NUM_DPIO_REGIONS) { DPAA2_BUS_ERR("Not sufficient number of DPIO regions"); @@ -433,13 +389,6 @@ dpaa2_create_dpio_device(int vdev_fd, /* Using single portal for all devices */ dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX]; - if (!check_lcore_cpuset) { - check_lcore_cpuset = 1; - - if (dpaa2_check_lcore_cpuset() < 0) - goto err; - } - dpio_dev->dpio = rte_zmalloc(NULL, sizeof(struct fsl_mc_io), RTE_CACHE_LINE_SIZE); if (!dpio_dev->dpio) { diff --git a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h index 88f0a9968..0d6364d99 100644 --- a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h +++ b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * * Copyright (C) 2014 Freescale Semiconductor, Inc. - * Copyright 2015-2019 NXP + * Copyright 2015-2020 NXP * */ #ifndef _FSL_QBMAN_PORTAL_H @@ -43,6 +43,12 @@ extern uint32_t dpaa2_svr_family; */ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d); +/** + * qbman_swp_update() - Update portal cacheability attributes. + * @p: the given qbman swp portal + */ +int qbman_swp_update(struct qbman_swp *p, int stash_off); + /** * qbman_swp_finish() - Create and destroy a functional object representing * the given QBMan portal descriptor. diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c index d4223bdc8..747ccfbac 100644 --- a/drivers/bus/fslmc/qbman/qbman_portal.c +++ b/drivers/bus/fslmc/qbman/qbman_portal.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2018-2019 NXP + * Copyright 2018-2020 NXP * */ @@ -82,6 +82,10 @@ qbman_swp_enqueue_ring_mode_cinh_direct(struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd); static int +qbman_swp_enqueue_ring_mode_cinh_direct(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd); +static int qbman_swp_enqueue_ring_mode_mem_back(struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd); @@ -99,6 +103,12 @@ qbman_swp_enqueue_multiple_cinh_direct(struct qbman_swp *s, uint32_t *flags, int num_frames); static int +qbman_swp_enqueue_multiple_cinh_direct(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + uint32_t *flags, + int num_frames); +static int qbman_swp_enqueue_multiple_mem_back(struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd, @@ -118,6 +128,12 @@ qbman_swp_enqueue_multiple_fd_cinh_direct(struct qbman_swp *s, uint32_t *flags, int num_frames); static int +qbman_swp_enqueue_multiple_fd_cinh_direct(struct qbman_swp *s, + const struct qbman_eq_desc *d, + struct qbman_fd **fd, + uint32_t *flags, + int num_frames); +static int qbman_swp_enqueue_multiple_fd_mem_back(struct qbman_swp *s, const struct qbman_eq_desc *d, struct qbman_fd **fd, @@ -135,6 +151,11 @@ qbman_swp_enqueue_multiple_desc_cinh_direct(struct qbman_swp *s, const struct qbman_fd *fd, int num_frames); static int +qbman_swp_enqueue_multiple_desc_cinh_direct(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + int num_frames); +static int qbman_swp_enqueue_multiple_desc_mem_back(struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd, @@ -143,9 +164,12 @@ qbman_swp_enqueue_multiple_desc_mem_back(struct qbman_swp *s, static int qbman_swp_pull_direct(struct qbman_swp *s, struct qbman_pull_desc *d); static int +qbman_swp_pull_cinh_direct(struct qbman_swp *s, struct qbman_pull_desc *d); +static int qbman_swp_pull_mem_back(struct qbman_swp *s, struct qbman_pull_desc *d); const struct qbman_result *qbman_swp_dqrr_next_direct(struct qbman_swp *s); +const struct qbman_result *qbman_swp_dqrr_next_cinh_direct(struct qbman_swp *s); const struct qbman_result *qbman_swp_dqrr_next_mem_back(struct qbman_swp *s); static int @@ -153,6 +177,10 @@ qbman_swp_release_direct(struct qbman_swp *s, const struct qbman_release_desc *d, const uint64_t *buffers, unsigned int num_buffers); static int +qbman_swp_release_cinh_direct(struct qbman_swp *s, + const struct qbman_release_desc *d, + const uint64_t *buffers, unsigned int num_buffers); +static int qbman_swp_release_mem_back(struct qbman_swp *s, const struct qbman_release_desc *d, const uint64_t *buffers, unsigned int num_buffers); @@ -327,6 +355,28 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) return p; } +int qbman_swp_update(struct qbman_swp *p, int stash_off) +{ + const struct qbman_swp_desc *d = &p->desc; + struct qbman_swp_sys *s = &p->sys; + int ret; + + /* Nothing needs to be done for QBMAN rev > 5000 with fast access */ + if ((qman_version & QMAN_REV_MASK) >= QMAN_REV_5000 + && (d->cena_access_mode == qman_cena_fastest_access)) + return 0; + + ret = qbman_swp_sys_update(s, d, p->dqrr.dqrr_size, stash_off); + if (ret) { + pr_err("qbman_swp_sys_init() failed %d\n", ret); + return ret; + } + + p->stash_off = stash_off; + + return 0; +} + void qbman_swp_finish(struct qbman_swp *p) { #ifdef QBMAN_CHECKING @@ -462,6 +512,27 @@ void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint8_t cmd_verb) #endif } +void qbman_swp_mc_submit_cinh(struct qbman_swp *p, void *cmd, uint8_t cmd_verb) +{ + uint8_t *v = cmd; +#ifdef QBMAN_CHECKING + QBMAN_BUG_ON(!(p->mc.check != swp_mc_can_submit)); +#endif + /* TBD: "|=" is going to hurt performance. Need to move as many fields + * out of word zero, and for those that remain, the "OR" needs to occur + * at the caller side. This debug check helps to catch cases where the + * caller wants to OR but has forgotten to do so. + */ + QBMAN_BUG_ON((*v & cmd_verb) != *v); + dma_wmb(); + *v = cmd_verb | p->mc.valid_bit; + qbman_cinh_write_complete(&p->sys, QBMAN_CENA_SWP_CR, cmd); + clean(cmd); +#ifdef QBMAN_CHECKING + p->mc.check = swp_mc_can_poll; +#endif +} + void *qbman_swp_mc_result(struct qbman_swp *p) { uint32_t *ret, verb; @@ -500,6 +571,27 @@ void *qbman_swp_mc_result(struct qbman_swp *p) return ret; } +void *qbman_swp_mc_result_cinh(struct qbman_swp *p) +{ + uint32_t *ret, verb; +#ifdef QBMAN_CHECKING + QBMAN_BUG_ON(p->mc.check != swp_mc_can_poll); +#endif + ret = qbman_cinh_read_shadow(&p->sys, + QBMAN_CENA_SWP_RR(p->mc.valid_bit)); + /* Remove the valid-bit - + * command completed iff the rest is non-zero + */ + verb = ret[0] & ~QB_VALID_BIT; + if (!verb) + return NULL; + p->mc.valid_bit ^= QB_VALID_BIT; +#ifdef QBMAN_CHECKING + p->mc.check = swp_mc_can_start; +#endif + return ret; +} + /***********/ /* Enqueue */ /***********/ @@ -640,6 +732,16 @@ static inline void qbman_write_eqcr_am_rt_register(struct qbman_swp *p, QMAN_RT_MODE); } +static void memcpy_byte_by_byte(void *to, const void *from, size_t n) +{ + const uint8_t *src = from; + volatile uint8_t *dest = to; + size_t i; + + for (i = 0; i < n; i++) + dest[i] = src[i]; +} + static int qbman_swp_enqueue_array_mode_direct(struct qbman_swp *s, const struct qbman_eq_desc *d, @@ -754,7 +856,7 @@ static int qbman_swp_enqueue_ring_mode_cinh_direct( return -EBUSY; } - p = qbman_cena_write_start_wo_shadow(&s->sys, + p = qbman_cinh_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_EQCR(s->eqcr.pi & half_mask)); memcpy(&p[1], &cl[1], 28); memcpy(&p[8], fd, sizeof(*fd)); @@ -762,8 +864,6 @@ static int qbman_swp_enqueue_ring_mode_cinh_direct( /* Set the verb byte, have to substitute in the valid-bit */ p[0] = cl[0] | s->eqcr.pi_vb; - qbman_cena_write_complete_wo_shadow(&s->sys, - QBMAN_CENA_SWP_EQCR(s->eqcr.pi & half_mask)); s->eqcr.pi++; s->eqcr.pi &= full_mask; s->eqcr.available--; @@ -815,7 +915,10 @@ static int qbman_swp_enqueue_ring_mode(struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd) { - return qbman_swp_enqueue_ring_mode_ptr(s, d, fd); + if (!s->stash_off) + return qbman_swp_enqueue_ring_mode_ptr(s, d, fd); + else + return qbman_swp_enqueue_ring_mode_cinh_direct(s, d, fd); } int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d, @@ -1025,7 +1128,12 @@ inline int qbman_swp_enqueue_multiple(struct qbman_swp *s, uint32_t *flags, int num_frames) { - return qbman_swp_enqueue_multiple_ptr(s, d, fd, flags, num_frames); + if (!s->stash_off) + return qbman_swp_enqueue_multiple_ptr(s, d, fd, flags, + num_frames); + else + return qbman_swp_enqueue_multiple_cinh_direct(s, d, fd, flags, + num_frames); } static int qbman_swp_enqueue_multiple_fd_direct(struct qbman_swp *s, @@ -1233,7 +1341,12 @@ inline int qbman_swp_enqueue_multiple_fd(struct qbman_swp *s, uint32_t *flags, int num_frames) { - return qbman_swp_enqueue_multiple_fd_ptr(s, d, fd, flags, num_frames); + if (!s->stash_off) + return qbman_swp_enqueue_multiple_fd_ptr(s, d, fd, flags, + num_frames); + else + return qbman_swp_enqueue_multiple_fd_cinh_direct(s, d, fd, + flags, num_frames); } static int qbman_swp_enqueue_multiple_desc_direct(struct qbman_swp *s, @@ -1426,7 +1539,13 @@ inline int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s, const struct qbman_fd *fd, int num_frames) { - return qbman_swp_enqueue_multiple_desc_ptr(s, d, fd, num_frames); + if (!s->stash_off) + return qbman_swp_enqueue_multiple_desc_ptr(s, d, fd, + num_frames); + else + return qbman_swp_enqueue_multiple_desc_cinh_direct(s, d, fd, + num_frames); + } /*************************/ @@ -1574,6 +1693,30 @@ static int qbman_swp_pull_direct(struct qbman_swp *s, return 0; } +static int qbman_swp_pull_cinh_direct(struct qbman_swp *s, + struct qbman_pull_desc *d) +{ + uint32_t *p; + uint32_t *cl = qb_cl(d); + + if (!atomic_dec_and_test(&s->vdq.busy)) { + atomic_inc(&s->vdq.busy); + return -EBUSY; + } + + d->pull.tok = s->sys.idx + 1; + s->vdq.storage = (void *)(size_t)d->pull.rsp_addr_virt; + p = qbman_cinh_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR); + memcpy_byte_by_byte(&p[1], &cl[1], 12); + + /* Set the verb byte, have to substitute in the valid-bit */ + lwsync(); + p[0] = cl[0] | s->vdq.valid_bit; + s->vdq.valid_bit ^= QB_VALID_BIT; + + return 0; +} + static int qbman_swp_pull_mem_back(struct qbman_swp *s, struct qbman_pull_desc *d) { @@ -1601,7 +1744,10 @@ static int qbman_swp_pull_mem_back(struct qbman_swp *s, inline int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d) { - return qbman_swp_pull_ptr(s, d); + if (!s->stash_off) + return qbman_swp_pull_ptr(s, d); + else + return qbman_swp_pull_cinh_direct(s, d); } /****************/ @@ -1638,7 +1784,10 @@ void qbman_swp_prefetch_dqrr_next(struct qbman_swp *s) */ inline const struct qbman_result *qbman_swp_dqrr_next(struct qbman_swp *s) { - return qbman_swp_dqrr_next_ptr(s); + if (!s->stash_off) + return qbman_swp_dqrr_next_ptr(s); + else + return qbman_swp_dqrr_next_cinh_direct(s); } const struct qbman_result *qbman_swp_dqrr_next_direct(struct qbman_swp *s) @@ -1718,6 +1867,81 @@ const struct qbman_result *qbman_swp_dqrr_next_direct(struct qbman_swp *s) return p; } +const struct qbman_result *qbman_swp_dqrr_next_cinh_direct(struct qbman_swp *s) +{ + uint32_t verb; + uint32_t response_verb; + uint32_t flags; + const struct qbman_result *p; + + /* Before using valid-bit to detect if something is there, we have to + * handle the case of the DQRR reset bug... + */ + if (s->dqrr.reset_bug) { + /* We pick up new entries by cache-inhibited producer index, + * which means that a non-coherent mapping would require us to + * invalidate and read *only* once that PI has indicated that + * there's an entry here. The first trip around the DQRR ring + * will be much less efficient than all subsequent trips around + * it... + */ + uint8_t pi = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_DQPI) & + QMAN_DQRR_PI_MASK; + + /* there are new entries if pi != next_idx */ + if (pi == s->dqrr.next_idx) + return NULL; + + /* if next_idx is/was the last ring index, and 'pi' is + * different, we can disable the workaround as all the ring + * entries have now been DMA'd to so valid-bit checking is + * repaired. Note: this logic needs to be based on next_idx + * (which increments one at a time), rather than on pi (which + * can burst and wrap-around between our snapshots of it). + */ + QBMAN_BUG_ON((s->dqrr.dqrr_size - 1) < 0); + if (s->dqrr.next_idx == (s->dqrr.dqrr_size - 1u)) { + pr_debug("DEBUG: next_idx=%d, pi=%d, clear reset bug\n", + s->dqrr.next_idx, pi); + s->dqrr.reset_bug = 0; + } + } + p = qbman_cinh_read_wo_shadow(&s->sys, + QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)); + + verb = p->dq.verb; + + /* If the valid-bit isn't of the expected polarity, nothing there. Note, + * in the DQRR reset bug workaround, we shouldn't need to skip these + * check, because we've already determined that a new entry is available + * and we've invalidated the cacheline before reading it, so the + * valid-bit behaviour is repaired and should tell us what we already + * knew from reading PI. + */ + if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) + return NULL; + + /* There's something there. Move "next_idx" attention to the next ring + * entry (and prefetch it) before returning what we found. + */ + s->dqrr.next_idx++; + if (s->dqrr.next_idx == s->dqrr.dqrr_size) { + s->dqrr.next_idx = 0; + s->dqrr.valid_bit ^= QB_VALID_BIT; + } + /* If this is the final response to a volatile dequeue command + * indicate that the vdq is no longer busy + */ + flags = p->dq.stat; + response_verb = verb & QBMAN_RESPONSE_VERB_MASK; + if ((response_verb == QBMAN_RESULT_DQ) && + (flags & QBMAN_DQ_STAT_VOLATILE) && + (flags & QBMAN_DQ_STAT_EXPIRED)) + atomic_inc(&s->vdq.busy); + + return p; +} + const struct qbman_result *qbman_swp_dqrr_next_mem_back(struct qbman_swp *s) { uint32_t verb; @@ -2096,6 +2320,37 @@ static int qbman_swp_release_direct(struct qbman_swp *s, return 0; } +static int qbman_swp_release_cinh_direct(struct qbman_swp *s, + const struct qbman_release_desc *d, + const uint64_t *buffers, + unsigned int num_buffers) +{ + uint32_t *p; + const uint32_t *cl = qb_cl(d); + uint32_t rar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_RAR); + + pr_debug("RAR=%08x\n", rar); + if (!RAR_SUCCESS(rar)) + return -EBUSY; + + QBMAN_BUG_ON(!num_buffers || (num_buffers > 7)); + + /* Start the release command */ + p = qbman_cinh_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_RCR(RAR_IDX(rar))); + + /* Copy the caller's buffer pointers to the command */ + memcpy_byte_by_byte(&p[2], buffers, num_buffers * sizeof(uint64_t)); + + /* Set the verb byte, have to substitute in the valid-bit and the + * number of buffers. + */ + lwsync(); + p[0] = cl[0] | RAR_VB(rar) | num_buffers; + + return 0; +} + static int qbman_swp_release_mem_back(struct qbman_swp *s, const struct qbman_release_desc *d, const uint64_t *buffers, @@ -2134,7 +2389,11 @@ inline int qbman_swp_release(struct qbman_swp *s, const uint64_t *buffers, unsigned int num_buffers) { - return qbman_swp_release_ptr(s, d, buffers, num_buffers); + if (!s->stash_off) + return qbman_swp_release_ptr(s, d, buffers, num_buffers); + else + return qbman_swp_release_cinh_direct(s, d, buffers, + num_buffers); } /*******************/ @@ -2157,8 +2416,8 @@ struct qbman_acquire_rslt { uint64_t buf[7]; }; -int qbman_swp_acquire(struct qbman_swp *s, uint16_t bpid, uint64_t *buffers, - unsigned int num_buffers) +static int qbman_swp_acquire_direct(struct qbman_swp *s, uint16_t bpid, + uint64_t *buffers, unsigned int num_buffers) { struct qbman_acquire_desc *p; struct qbman_acquire_rslt *r; @@ -2202,6 +2461,61 @@ int qbman_swp_acquire(struct qbman_swp *s, uint16_t bpid, uint64_t *buffers, return (int)r->num; } +static int qbman_swp_acquire_cinh_direct(struct qbman_swp *s, uint16_t bpid, + uint64_t *buffers, unsigned int num_buffers) +{ + struct qbman_acquire_desc *p; + struct qbman_acquire_rslt *r; + + if (!num_buffers || (num_buffers > 7)) + return -EINVAL; + + /* Start the management command */ + p = qbman_swp_mc_start(s); + + if (!p) + return -EBUSY; + + /* Encode the caller-provided attributes */ + p->bpid = bpid; + p->num = num_buffers; + + /* Complete the management command */ + r = qbman_swp_mc_complete_cinh(s, p, QBMAN_MC_ACQUIRE); + if (!r) { + pr_err("qbman: acquire from BPID %d failed, no response\n", + bpid); + return -EIO; + } + + /* Decode the outcome */ + QBMAN_BUG_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != QBMAN_MC_ACQUIRE); + + /* Determine success or failure */ + if (r->rslt != QBMAN_MC_RSLT_OK) { + pr_err("Acquire buffers from BPID 0x%x failed, code=0x%02x\n", + bpid, r->rslt); + return -EIO; + } + + QBMAN_BUG_ON(r->num > num_buffers); + + /* Copy the acquired buffers to the caller's array */ + u64_from_le32_copy(buffers, &r->buf[0], r->num); + + return (int)r->num; +} + +int qbman_swp_acquire(struct qbman_swp *s, uint16_t bpid, uint64_t *buffers, + unsigned int num_buffers) +{ + if (!s->stash_off) + return qbman_swp_acquire_direct(s, bpid, buffers, num_buffers); + else + return qbman_swp_acquire_cinh_direct(s, bpid, buffers, + num_buffers); +} + /*****************/ /* FQ management */ /*****************/ diff --git a/drivers/bus/fslmc/qbman/qbman_portal.h b/drivers/bus/fslmc/qbman/qbman_portal.h index 3aaacae52..1cf791830 100644 --- a/drivers/bus/fslmc/qbman/qbman_portal.h +++ b/drivers/bus/fslmc/qbman/qbman_portal.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2018-2019 NXP + * Copyright 2018-2020 NXP * */ @@ -102,6 +102,7 @@ struct qbman_swp { uint32_t ci; int available; } eqcr; + uint8_t stash_off; }; /* -------------------------- */ @@ -118,7 +119,9 @@ struct qbman_swp { */ void *qbman_swp_mc_start(struct qbman_swp *p); void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint8_t cmd_verb); +void qbman_swp_mc_submit_cinh(struct qbman_swp *p, void *cmd, uint8_t cmd_verb); void *qbman_swp_mc_result(struct qbman_swp *p); +void *qbman_swp_mc_result_cinh(struct qbman_swp *p); /* Wraps up submit + poll-for-result */ static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd, @@ -135,6 +138,20 @@ static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd, return cmd; } +static inline void *qbman_swp_mc_complete_cinh(struct qbman_swp *swp, void *cmd, + uint8_t cmd_verb) +{ + int loopvar = 1000; + + qbman_swp_mc_submit_cinh(swp, cmd, cmd_verb); + do { + cmd = qbman_swp_mc_result_cinh(swp); + } while (!cmd && loopvar--); + QBMAN_BUG_ON(!loopvar); + + return cmd; +} + /* ---------------------- */ /* Descriptors/cachelines */ /* ---------------------- */ diff --git a/drivers/bus/fslmc/qbman/qbman_sys.h b/drivers/bus/fslmc/qbman/qbman_sys.h index 55449edf3..61f817c47 100644 --- a/drivers/bus/fslmc/qbman/qbman_sys.h +++ b/drivers/bus/fslmc/qbman/qbman_sys.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /* qbman_sys_decl.h and qbman_sys.h are the two platform-specific files in the * driver. They are only included via qbman_private.h, which is itself a @@ -190,6 +190,34 @@ static inline void qbman_cinh_write(struct qbman_swp_sys *s, uint32_t offset, #endif } +static inline void *qbman_cinh_write_start_wo_shadow(struct qbman_swp_sys *s, + uint32_t offset) +{ +#ifdef QBMAN_CINH_TRACE + pr_info("qbman_cinh_write_start(%p:%d:0x%03x)\n", + s->addr_cinh, s->idx, offset); +#endif + QBMAN_BUG_ON(offset & 63); + return (s->addr_cinh + offset); +} + +static inline void qbman_cinh_write_complete(struct qbman_swp_sys *s, + uint32_t offset, void *cmd) +{ + const uint32_t *shadow = cmd; + int loop; +#ifdef QBMAN_CINH_TRACE + pr_info("qbman_cinh_write_complete(%p:%d:0x%03x) %p\n", + s->addr_cinh, s->idx, offset, shadow); + hexdump(cmd, 64); +#endif + for (loop = 15; loop >= 1; loop--) + __raw_writel(shadow[loop], s->addr_cinh + + offset + loop * 4); + lwsync(); + __raw_writel(shadow[0], s->addr_cinh + offset); +} + static inline uint32_t qbman_cinh_read(struct qbman_swp_sys *s, uint32_t offset) { uint32_t reg = __raw_readl(s->addr_cinh + offset); @@ -200,6 +228,35 @@ static inline uint32_t qbman_cinh_read(struct qbman_swp_sys *s, uint32_t offset) return reg; } +static inline void *qbman_cinh_read_shadow(struct qbman_swp_sys *s, + uint32_t offset) +{ + uint32_t *shadow = (uint32_t *)(s->cena + offset); + unsigned int loop; +#ifdef QBMAN_CINH_TRACE + pr_info(" %s (%p:%d:0x%03x) %p\n", __func__, + s->addr_cinh, s->idx, offset, shadow); +#endif + + for (loop = 0; loop < 16; loop++) + shadow[loop] = __raw_readl(s->addr_cinh + offset + + loop * 4); +#ifdef QBMAN_CINH_TRACE + hexdump(shadow, 64); +#endif + return shadow; +} + +static inline void *qbman_cinh_read_wo_shadow(struct qbman_swp_sys *s, + uint32_t offset) +{ +#ifdef QBMAN_CINH_TRACE + pr_info("qbman_cinh_read(%p:%d:0x%03x)\n", + s->addr_cinh, s->idx, offset); +#endif + return s->addr_cinh + offset; +} + static inline void *qbman_cena_write_start(struct qbman_swp_sys *s, uint32_t offset) { @@ -476,6 +533,82 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s, return 0; } +static inline int qbman_swp_sys_update(struct qbman_swp_sys *s, + const struct qbman_swp_desc *d, + uint8_t dqrr_size, + int stash_off) +{ + uint32_t reg; + int i; + int cena_region_size = 4*1024; + uint8_t est = 1; +#ifdef RTE_ARCH_64 + uint8_t wn = CENA_WRITE_ENABLE; +#else + uint8_t wn = CINH_WRITE_ENABLE; +#endif + + if (stash_off) + wn = CINH_WRITE_ENABLE; + + QBMAN_BUG_ON(d->idx < 0); +#ifdef QBMAN_CHECKING + /* We should never be asked to initialise for a portal that isn't in + * the power-on state. (Ie. don't forget to reset portals when they are + * decommissioned!) + */ + reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG); + QBMAN_BUG_ON(reg); +#endif + if ((d->qman_version & QMAN_REV_MASK) >= QMAN_REV_5000 + && (d->cena_access_mode == qman_cena_fastest_access)) + memset(s->addr_cena, 0, cena_region_size); + else { + /* Invalidate the portal memory. + * This ensures no stale cache lines + */ + for (i = 0; i < cena_region_size; i += 64) + dccivac(s->addr_cena + i); + } + + if (dpaa2_svr_family == SVR_LS1080A) + est = 0; + + if (s->eqcr_mode == qman_eqcr_vb_array) { + reg = qbman_set_swp_cfg(dqrr_size, wn, + 0, 3, 2, 3, 1, 1, 1, 1, 1, 1); + } else { + if ((d->qman_version & QMAN_REV_MASK) >= QMAN_REV_5000 && + (d->cena_access_mode == qman_cena_fastest_access)) + reg = qbman_set_swp_cfg(dqrr_size, wn, + 1, 3, 2, 0, 1, 1, 1, 1, 1, 1); + else + reg = qbman_set_swp_cfg(dqrr_size, wn, + est, 3, 2, 2, 1, 1, 1, 1, 1, 1); + } + + if ((d->qman_version & QMAN_REV_MASK) >= QMAN_REV_5000 + && (d->cena_access_mode == qman_cena_fastest_access)) + reg |= 1 << SWP_CFG_CPBS_SHIFT | /* memory-backed mode */ + 1 << SWP_CFG_VPM_SHIFT | /* VDQCR read triggered mode */ + 1 << SWP_CFG_CPM_SHIFT; /* CR read triggered mode */ + + qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg); + reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG); + if (!reg) { + pr_err("The portal %d is not enabled!\n", s->idx); + return -1; + } + + if ((d->qman_version & QMAN_REV_MASK) >= QMAN_REV_5000 + && (d->cena_access_mode == qman_cena_fastest_access)) { + qbman_cinh_write(s, QBMAN_CINH_SWP_EQCR_PI, QMAN_RT_MODE); + qbman_cinh_write(s, QBMAN_CINH_SWP_RCR_PI, QMAN_RT_MODE); + } + + return 0; +} + static inline void qbman_swp_sys_finish(struct qbman_swp_sys *s) { free(s->cena); From patchwork Fri Mar 6 09:57:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 184244 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp7232518ile; Fri, 6 Mar 2020 02:01:05 -0800 (PST) X-Google-Smtp-Source: ADFU+vsSxl8FDAVA6jOLiMPSMFvzgJ7gkOrqVavJJZuyMKVqNQvE4v7pPD6mVLIGtkbjtQkWTDF7 X-Received: by 2002:a17:906:5604:: with SMTP id f4mr2205134ejq.255.1583488865127; Fri, 06 Mar 2020 02:01:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583488865; cv=none; d=google.com; s=arc-20160816; b=A/JVEDKzmyVx7+aInzPySkkU0EBYlurTa72M1AsaTIFtsZsISFL+bJAAq1GPVNfYTw MvQ4L7f+8sxnCvXXuoOMQXmZ2BfeptNSxKwTnBywwwXvl4lrBw3BP1X6pN9VeY7ehehV kYeFLu9Fhz601H/tWLubcbIWayfGM6o8IRy0sy88DmOENcBJHc+AjTJ+WsGUqQ224Sgi 9Bpbr8gTuswt4xo+vLPv//bp3rtoSeajfJWr3TLWe/hn33TDcNkgFJL+6wb+FXNNANeu cyHyZj7RYjB5+X7vJaFbDVo79hmNtQ36XdWxYJhTm5tqBldSQCYMzqxQH1v2rBe7f5Iz 7wUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=CAvWqo0VQ3fzJHuuRsNVMT0OBJ2gufOrQZrrDsGIX9c=; b=mYZ7p+olDtjKQLPSG59vrhEbPwCAA8I/TRPFhYxAyEgLohwABK+OHliIrHVb02hXpL gE3AA0a2Jg28BjdFAB4mVMyTFJkRT25UVmaW+PBZX8Ed5QDFAsaJ1mL0DAG9DX5ccHAi 0hnBMf0MRy5CdnEqvqQpaUely9RKF+2C3jqoF3ViVa9Lpb8V594+V4WU99vcAlmDcYOW HsEnurK20tKxl6SV2TbRRaFuIdlz35Sva6tb5I9WaPkPFcp5FR48rj98ViWUuwE1F/e8 uR9Nq8HRx6y4R+QVbPHrvcTcDf7Y9TFoKSWG48l3nKWpV+n+0fzx/VbZS9rLedGGC1Mr mcHQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id y19si1004016ejq.189.2020.03.06.02.01.04; Fri, 06 Mar 2020 02:01:05 -0800 (PST) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2F96D1C066; Fri, 6 Mar 2020 10:59:58 +0100 (CET) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id F21461C00E for ; Fri, 6 Mar 2020 10:59:50 +0100 (CET) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id D2B821A0A62; Fri, 6 Mar 2020 10:59:50 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 818F31A0AA4; Fri, 6 Mar 2020 10:59:48 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 44EEA4029B; Fri, 6 Mar 2020 17:59:45 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Nipun Gupta Date: Fri, 6 Mar 2020 15:27:34 +0530 Message-Id: <20200306095742.18080-9-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200306095742.18080-1-hemant.agrawal@nxp.com> References: <20200302145829.27808-1-hemant.agrawal@nxp.com> <20200306095742.18080-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 08/16] drivers: enhance portal allocation failure log X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nipun Gupta The change adds printing the thread id when portal allocation failure occurs Signed-off-by: Nipun Gupta --- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 8 ++++++-- drivers/event/dpaa2/dpaa2_eventdev.c | 8 ++++++-- drivers/mempool/dpaa2/dpaa2_hw_mempool.c | 12 +++++++++--- drivers/net/dpaa2/dpaa2_ethdev.c | 4 +++- drivers/net/dpaa2/dpaa2_rxtx.c | 16 ++++++++++++---- drivers/raw/dpaa2_cmdif/dpaa2_cmdif.c | 8 ++++++-- drivers/raw/dpaa2_qdma/dpaa2_qdma.c | 12 +++++++++--- 7 files changed, 51 insertions(+), 17 deletions(-) -- 2.17.1 diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index 6ed2701ab..cf08003cc 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -1459,7 +1459,9 @@ dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops, if (!DPAA2_PER_LCORE_DPIO) { ret = dpaa2_affine_qbman_swp(); if (ret) { - DPAA2_SEC_ERR("Failure in affining portal"); + DPAA2_SEC_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); return 0; } } @@ -1641,7 +1643,9 @@ dpaa2_sec_dequeue_burst(void *qp, struct rte_crypto_op **ops, if (!DPAA2_PER_LCORE_DPIO) { ret = dpaa2_affine_qbman_swp(); if (ret) { - DPAA2_SEC_ERR("Failure in affining portal"); + DPAA2_SEC_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); return 0; } } diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c index 1833d659d..bb02ea9fb 100644 --- a/drivers/event/dpaa2/dpaa2_eventdev.c +++ b/drivers/event/dpaa2/dpaa2_eventdev.c @@ -74,7 +74,9 @@ dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[], /* Affine current thread context to a qman portal */ ret = dpaa2_affine_qbman_swp(); if (ret < 0) { - DPAA2_EVENTDEV_ERR("Failure in affining portal"); + DPAA2_EVENTDEV_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); return 0; } } @@ -273,7 +275,9 @@ dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[], /* Affine current thread context to a qman portal */ ret = dpaa2_affine_qbman_swp(); if (ret < 0) { - DPAA2_EVENTDEV_ERR("Failure in affining portal"); + DPAA2_EVENTDEV_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); return 0; } } diff --git a/drivers/mempool/dpaa2/dpaa2_hw_mempool.c b/drivers/mempool/dpaa2/dpaa2_hw_mempool.c index 48887beb7..fa9b53e64 100644 --- a/drivers/mempool/dpaa2/dpaa2_hw_mempool.c +++ b/drivers/mempool/dpaa2/dpaa2_hw_mempool.c @@ -69,7 +69,9 @@ rte_hw_mbuf_create_pool(struct rte_mempool *mp) if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); if (ret) { - DPAA2_MEMPOOL_ERR("Failure in affining portal"); + DPAA2_MEMPOOL_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); goto err1; } } @@ -198,7 +200,9 @@ rte_dpaa2_mbuf_release(struct rte_mempool *pool __rte_unused, if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); if (ret != 0) { - DPAA2_MEMPOOL_ERR("Failed to allocate IO portal"); + DPAA2_MEMPOOL_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); return; } } @@ -317,7 +321,9 @@ rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool, if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); if (ret != 0) { - DPAA2_MEMPOOL_ERR("Failed to allocate IO portal"); + DPAA2_MEMPOOL_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); return ret; } } diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index 4fc550a88..4a61c6f78 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -887,7 +887,9 @@ dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); if (ret) { - DPAA2_PMD_ERR("Failure in affining portal"); + DPAA2_PMD_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); return -EINVAL; } } diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c index 52d913d9e..d809e0f4b 100644 --- a/drivers/net/dpaa2/dpaa2_rxtx.c +++ b/drivers/net/dpaa2/dpaa2_rxtx.c @@ -760,7 +760,9 @@ dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); if (ret) { - DPAA2_PMD_ERR("Failure in affining portal\n"); + DPAA2_PMD_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); return 0; } } @@ -872,7 +874,9 @@ uint16_t dpaa2_dev_tx_conf(void *queue) if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); if (ret) { - DPAA2_PMD_ERR("Failure in affining portal\n"); + DPAA2_PMD_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); return 0; } } @@ -1011,7 +1015,9 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); if (ret) { - DPAA2_PMD_ERR("Failure in affining portal"); + DPAA2_PMD_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); return 0; } } @@ -1272,7 +1278,9 @@ dpaa2_dev_tx_ordered(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); if (ret) { - DPAA2_PMD_ERR("Failure in affining portal"); + DPAA2_PMD_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); return 0; } } diff --git a/drivers/raw/dpaa2_cmdif/dpaa2_cmdif.c b/drivers/raw/dpaa2_cmdif/dpaa2_cmdif.c index 997d1c873..7c21c6a52 100644 --- a/drivers/raw/dpaa2_cmdif/dpaa2_cmdif.c +++ b/drivers/raw/dpaa2_cmdif/dpaa2_cmdif.c @@ -70,7 +70,9 @@ dpaa2_cmdif_enqueue_bufs(struct rte_rawdev *dev, if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); if (ret) { - DPAA2_CMDIF_ERR("Failure in affining portal\n"); + DPAA2_CMDIF_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); return 0; } } @@ -133,7 +135,9 @@ dpaa2_cmdif_dequeue_bufs(struct rte_rawdev *dev, if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); if (ret) { - DPAA2_CMDIF_ERR("Failure in affining portal\n"); + DPAA2_CMDIF_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); return 0; } } diff --git a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c index c90595400..d5202d652 100644 --- a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c +++ b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c @@ -666,7 +666,9 @@ dpdmai_dev_enqueue_multi(struct dpaa2_dpdmai_dev *dpdmai_dev, if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); if (ret) { - DPAA2_QDMA_ERR("Failure in affining portal"); + DPAA2_QDMA_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); return 0; } } @@ -788,7 +790,9 @@ dpdmai_dev_dequeue_multijob_prefetch( if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); if (ret) { - DPAA2_QDMA_ERR("Failure in affining portal"); + DPAA2_QDMA_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); return 0; } } @@ -929,7 +933,9 @@ dpdmai_dev_dequeue_multijob_no_prefetch( if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); if (ret) { - DPAA2_QDMA_ERR("Failure in affining portal"); + DPAA2_QDMA_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); return 0; } } From patchwork Fri Mar 6 09:57:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 184245 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp7232727ile; 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[92.243.14.124]) by mx.google.com with ESMTP id k7si1013810ejr.138.2020.03.06.02.01.17; Fri, 06 Mar 2020 02:01:17 -0800 (PST) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 19D401C07E; Fri, 6 Mar 2020 11:00:00 +0100 (CET) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id 1C1D11C01F for ; Fri, 6 Mar 2020 10:59:52 +0100 (CET) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id F226A1A0AA4; Fri, 6 Mar 2020 10:59:51 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6333B1A0AAB; Fri, 6 Mar 2020 10:59:49 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 31896402D5; Fri, 6 Mar 2020 17:59:46 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Nipun Gupta Date: Fri, 6 Mar 2020 15:27:35 +0530 Message-Id: <20200306095742.18080-10-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200306095742.18080-1-hemant.agrawal@nxp.com> References: <20200302145829.27808-1-hemant.agrawal@nxp.com> <20200306095742.18080-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 09/16] bus/fslmc: rename the cinh read functions used for ls1088 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nipun Gupta This patch changes the qbman I/O function names as they are only reading from cinh register, but writing to cena registers. This gives way to add functions which purely work in cinh mode Signed-off-by: Nipun Gupta --- drivers/bus/fslmc/qbman/qbman_portal.c | 250 +++++++++++++++++++++++-- 1 file changed, 233 insertions(+), 17 deletions(-) -- 2.17.1 diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c index 747ccfbac..207faada3 100644 --- a/drivers/bus/fslmc/qbman/qbman_portal.c +++ b/drivers/bus/fslmc/qbman/qbman_portal.c @@ -78,7 +78,7 @@ qbman_swp_enqueue_ring_mode_direct(struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd); static int -qbman_swp_enqueue_ring_mode_cinh_direct(struct qbman_swp *s, +qbman_swp_enqueue_ring_mode_cinh_read_direct(struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd); static int @@ -97,7 +97,7 @@ qbman_swp_enqueue_multiple_direct(struct qbman_swp *s, uint32_t *flags, int num_frames); static int -qbman_swp_enqueue_multiple_cinh_direct(struct qbman_swp *s, +qbman_swp_enqueue_multiple_cinh_read_direct(struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd, uint32_t *flags, @@ -122,7 +122,7 @@ qbman_swp_enqueue_multiple_fd_direct(struct qbman_swp *s, uint32_t *flags, int num_frames); static int -qbman_swp_enqueue_multiple_fd_cinh_direct(struct qbman_swp *s, +qbman_swp_enqueue_multiple_fd_cinh_read_direct(struct qbman_swp *s, const struct qbman_eq_desc *d, struct qbman_fd **fd, uint32_t *flags, @@ -146,7 +146,7 @@ qbman_swp_enqueue_multiple_desc_direct(struct qbman_swp *s, const struct qbman_fd *fd, int num_frames); static int -qbman_swp_enqueue_multiple_desc_cinh_direct(struct qbman_swp *s, +qbman_swp_enqueue_multiple_desc_cinh_read_direct(struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd, int num_frames); @@ -309,15 +309,15 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) && (d->cena_access_mode == qman_cena_fastest_access)) { p->eqcr.pi_ring_size = 32; qbman_swp_enqueue_array_mode_ptr = - qbman_swp_enqueue_array_mode_mem_back; + qbman_swp_enqueue_array_mode_mem_back; qbman_swp_enqueue_ring_mode_ptr = - qbman_swp_enqueue_ring_mode_mem_back; + qbman_swp_enqueue_ring_mode_mem_back; qbman_swp_enqueue_multiple_ptr = - qbman_swp_enqueue_multiple_mem_back; + qbman_swp_enqueue_multiple_mem_back; qbman_swp_enqueue_multiple_fd_ptr = - qbman_swp_enqueue_multiple_fd_mem_back; + qbman_swp_enqueue_multiple_fd_mem_back; qbman_swp_enqueue_multiple_desc_ptr = - qbman_swp_enqueue_multiple_desc_mem_back; + qbman_swp_enqueue_multiple_desc_mem_back; qbman_swp_pull_ptr = qbman_swp_pull_mem_back; qbman_swp_dqrr_next_ptr = qbman_swp_dqrr_next_mem_back; qbman_swp_release_ptr = qbman_swp_release_mem_back; @@ -325,13 +325,13 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) if (dpaa2_svr_family == SVR_LS1080A) { qbman_swp_enqueue_ring_mode_ptr = - qbman_swp_enqueue_ring_mode_cinh_direct; + qbman_swp_enqueue_ring_mode_cinh_read_direct; qbman_swp_enqueue_multiple_ptr = - qbman_swp_enqueue_multiple_cinh_direct; + qbman_swp_enqueue_multiple_cinh_read_direct; qbman_swp_enqueue_multiple_fd_ptr = - qbman_swp_enqueue_multiple_fd_cinh_direct; + qbman_swp_enqueue_multiple_fd_cinh_read_direct; qbman_swp_enqueue_multiple_desc_ptr = - qbman_swp_enqueue_multiple_desc_cinh_direct; + qbman_swp_enqueue_multiple_desc_cinh_read_direct; } for (mask_size = p->eqcr.pi_ring_size; mask_size > 0; mask_size >>= 1) @@ -835,7 +835,7 @@ static int qbman_swp_enqueue_ring_mode_direct(struct qbman_swp *s, return 0; } -static int qbman_swp_enqueue_ring_mode_cinh_direct( +static int qbman_swp_enqueue_ring_mode_cinh_read_direct( struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd) @@ -873,6 +873,44 @@ static int qbman_swp_enqueue_ring_mode_cinh_direct( return 0; } +static int qbman_swp_enqueue_ring_mode_cinh_direct( + struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd) +{ + uint32_t *p; + const uint32_t *cl = qb_cl(d); + uint32_t eqcr_ci, full_mask, half_mask; + + half_mask = (s->eqcr.pi_ci_mask>>1); + full_mask = s->eqcr.pi_ci_mask; + if (!s->eqcr.available) { + eqcr_ci = s->eqcr.ci; + s->eqcr.ci = qbman_cinh_read(&s->sys, + QBMAN_CINH_SWP_EQCR_CI) & full_mask; + s->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size, + eqcr_ci, s->eqcr.ci); + if (!s->eqcr.available) + return -EBUSY; + } + + p = qbman_cinh_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_EQCR(s->eqcr.pi & half_mask)); + memcpy_byte_by_byte(&p[1], &cl[1], 28); + memcpy_byte_by_byte(&p[8], fd, sizeof(*fd)); + lwsync(); + + /* Set the verb byte, have to substitute in the valid-bit */ + p[0] = cl[0] | s->eqcr.pi_vb; + s->eqcr.pi++; + s->eqcr.pi &= full_mask; + s->eqcr.available--; + if (!(s->eqcr.pi & half_mask)) + s->eqcr.pi_vb ^= QB_VALID_BIT; + + return 0; +} + static int qbman_swp_enqueue_ring_mode_mem_back(struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd) @@ -999,7 +1037,7 @@ static int qbman_swp_enqueue_multiple_direct(struct qbman_swp *s, return num_enqueued; } -static int qbman_swp_enqueue_multiple_cinh_direct( +static int qbman_swp_enqueue_multiple_cinh_read_direct( struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd, @@ -1069,6 +1107,67 @@ static int qbman_swp_enqueue_multiple_cinh_direct( return num_enqueued; } +static int qbman_swp_enqueue_multiple_cinh_direct( + struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + uint32_t *flags, + int num_frames) +{ + uint32_t *p = NULL; + const uint32_t *cl = qb_cl(d); + uint32_t eqcr_ci, eqcr_pi, half_mask, full_mask; + int i, num_enqueued = 0; + + half_mask = (s->eqcr.pi_ci_mask>>1); + full_mask = s->eqcr.pi_ci_mask; + if (!s->eqcr.available) { + eqcr_ci = s->eqcr.ci; + s->eqcr.ci = qbman_cinh_read(&s->sys, + QBMAN_CINH_SWP_EQCR_CI) & full_mask; + s->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size, + eqcr_ci, s->eqcr.ci); + if (!s->eqcr.available) + return 0; + } + + eqcr_pi = s->eqcr.pi; + num_enqueued = (s->eqcr.available < num_frames) ? + s->eqcr.available : num_frames; + s->eqcr.available -= num_enqueued; + /* Fill in the EQCR ring */ + for (i = 0; i < num_enqueued; i++) { + p = qbman_cinh_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask)); + memcpy_byte_by_byte(&p[1], &cl[1], 28); + memcpy_byte_by_byte(&p[8], &fd[i], sizeof(*fd)); + eqcr_pi++; + } + + lwsync(); + + /* Set the verb byte, have to substitute in the valid-bit */ + eqcr_pi = s->eqcr.pi; + for (i = 0; i < num_enqueued; i++) { + p = qbman_cinh_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask)); + p[0] = cl[0] | s->eqcr.pi_vb; + if (flags && (flags[i] & QBMAN_ENQUEUE_FLAG_DCA)) { + struct qbman_eq_desc *d = (struct qbman_eq_desc *)p; + + d->eq.dca = (1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT) | + ((flags[i]) & QBMAN_EQCR_DCA_IDXMASK); + } + eqcr_pi++; + if (!(eqcr_pi & half_mask)) + s->eqcr.pi_vb ^= QB_VALID_BIT; + } + + s->eqcr.pi = eqcr_pi & full_mask; + + return num_enqueued; +} + static int qbman_swp_enqueue_multiple_mem_back(struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd, @@ -1205,7 +1304,7 @@ static int qbman_swp_enqueue_multiple_fd_direct(struct qbman_swp *s, return num_enqueued; } -static int qbman_swp_enqueue_multiple_fd_cinh_direct( +static int qbman_swp_enqueue_multiple_fd_cinh_read_direct( struct qbman_swp *s, const struct qbman_eq_desc *d, struct qbman_fd **fd, @@ -1275,6 +1374,67 @@ static int qbman_swp_enqueue_multiple_fd_cinh_direct( return num_enqueued; } +static int qbman_swp_enqueue_multiple_fd_cinh_direct( + struct qbman_swp *s, + const struct qbman_eq_desc *d, + struct qbman_fd **fd, + uint32_t *flags, + int num_frames) +{ + uint32_t *p = NULL; + const uint32_t *cl = qb_cl(d); + uint32_t eqcr_ci, eqcr_pi, half_mask, full_mask; + int i, num_enqueued = 0; + + half_mask = (s->eqcr.pi_ci_mask>>1); + full_mask = s->eqcr.pi_ci_mask; + if (!s->eqcr.available) { + eqcr_ci = s->eqcr.ci; + s->eqcr.ci = qbman_cinh_read(&s->sys, + QBMAN_CINH_SWP_EQCR_CI) & full_mask; + s->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size, + eqcr_ci, s->eqcr.ci); + if (!s->eqcr.available) + return 0; + } + + eqcr_pi = s->eqcr.pi; + num_enqueued = (s->eqcr.available < num_frames) ? + s->eqcr.available : num_frames; + s->eqcr.available -= num_enqueued; + /* Fill in the EQCR ring */ + for (i = 0; i < num_enqueued; i++) { + p = qbman_cinh_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask)); + memcpy_byte_by_byte(&p[1], &cl[1], 28); + memcpy_byte_by_byte(&p[8], fd[i], sizeof(struct qbman_fd)); + eqcr_pi++; + } + + lwsync(); + + /* Set the verb byte, have to substitute in the valid-bit */ + eqcr_pi = s->eqcr.pi; + for (i = 0; i < num_enqueued; i++) { + p = qbman_cinh_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask)); + p[0] = cl[0] | s->eqcr.pi_vb; + if (flags && (flags[i] & QBMAN_ENQUEUE_FLAG_DCA)) { + struct qbman_eq_desc *d = (struct qbman_eq_desc *)p; + + d->eq.dca = (1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT) | + ((flags[i]) & QBMAN_EQCR_DCA_IDXMASK); + } + eqcr_pi++; + if (!(eqcr_pi & half_mask)) + s->eqcr.pi_vb ^= QB_VALID_BIT; + } + + s->eqcr.pi = eqcr_pi & full_mask; + + return num_enqueued; +} + static int qbman_swp_enqueue_multiple_fd_mem_back(struct qbman_swp *s, const struct qbman_eq_desc *d, struct qbman_fd **fd, @@ -1413,7 +1573,7 @@ static int qbman_swp_enqueue_multiple_desc_direct(struct qbman_swp *s, return num_enqueued; } -static int qbman_swp_enqueue_multiple_desc_cinh_direct( +static int qbman_swp_enqueue_multiple_desc_cinh_read_direct( struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd, @@ -1478,6 +1638,62 @@ static int qbman_swp_enqueue_multiple_desc_cinh_direct( return num_enqueued; } +static int qbman_swp_enqueue_multiple_desc_cinh_direct( + struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + int num_frames) +{ + uint32_t *p; + const uint32_t *cl; + uint32_t eqcr_ci, eqcr_pi, half_mask, full_mask; + int i, num_enqueued = 0; + + half_mask = (s->eqcr.pi_ci_mask>>1); + full_mask = s->eqcr.pi_ci_mask; + if (!s->eqcr.available) { + eqcr_ci = s->eqcr.ci; + s->eqcr.ci = qbman_cinh_read(&s->sys, + QBMAN_CINH_SWP_EQCR_CI) & full_mask; + s->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size, + eqcr_ci, s->eqcr.ci); + if (!s->eqcr.available) + return 0; + } + + eqcr_pi = s->eqcr.pi; + num_enqueued = (s->eqcr.available < num_frames) ? + s->eqcr.available : num_frames; + s->eqcr.available -= num_enqueued; + /* Fill in the EQCR ring */ + for (i = 0; i < num_enqueued; i++) { + p = qbman_cinh_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask)); + cl = qb_cl(&d[i]); + memcpy_byte_by_byte(&p[1], &cl[1], 28); + memcpy_byte_by_byte(&p[8], &fd[i], sizeof(*fd)); + eqcr_pi++; + } + + lwsync(); + + /* Set the verb byte, have to substitute in the valid-bit */ + eqcr_pi = s->eqcr.pi; + for (i = 0; i < num_enqueued; i++) { + p = qbman_cinh_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask)); + cl = qb_cl(&d[i]); + p[0] = cl[0] | s->eqcr.pi_vb; + eqcr_pi++; + if (!(eqcr_pi & half_mask)) + s->eqcr.pi_vb ^= QB_VALID_BIT; + } + + s->eqcr.pi = eqcr_pi & full_mask; + + return num_enqueued; +} + static int qbman_swp_enqueue_multiple_desc_mem_back(struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd, From patchwork Fri Mar 6 09:57:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 184246 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp7232890ile; Fri, 6 Mar 2020 02:01:27 -0800 (PST) X-Google-Smtp-Source: ADFU+vvxetX2aWr2kdhuFIQbqya0jQ8dYR5fCGNgDeG2N4zGW0ztpLBtb90NrUnpnfVY3IoFcpcy X-Received: by 2002:a05:6402:1d2d:: with SMTP id dh13mr2228910edb.276.1583488887304; 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[92.243.14.124]) by mx.google.com with ESMTP id f14si1172471edv.521.2020.03.06.02.01.27; Fri, 06 Mar 2020 02:01:27 -0800 (PST) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E06381C0AB; Fri, 6 Mar 2020 11:00:01 +0100 (CET) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by dpdk.org (Postfix) with ESMTP id 74CC81C021 for ; Fri, 6 Mar 2020 10:59:52 +0100 (CET) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 592A12008DC; Fri, 6 Mar 2020 10:59:52 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 45321200ADA; Fri, 6 Mar 2020 10:59:50 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 07A72402E5; Fri, 6 Mar 2020 17:59:46 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Nipun Gupta Date: Fri, 6 Mar 2020 15:27:36 +0530 Message-Id: <20200306095742.18080-11-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200306095742.18080-1-hemant.agrawal@nxp.com> References: <20200302145829.27808-1-hemant.agrawal@nxp.com> <20200306095742.18080-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 10/16] net/dpaa: return error on multiple mp config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nipun Gupta multiple buffer pools are not supported on a single device. Signed-off-by: Nipun Gupta --- drivers/mempool/dpaa/dpaa_mempool.c | 1 + drivers/net/dpaa/dpaa_ethdev.c | 6 ++++++ 2 files changed, 7 insertions(+) -- 2.17.1 diff --git a/drivers/mempool/dpaa/dpaa_mempool.c b/drivers/mempool/dpaa/dpaa_mempool.c index 3a2528331..00db6f9bc 100644 --- a/drivers/mempool/dpaa/dpaa_mempool.c +++ b/drivers/mempool/dpaa/dpaa_mempool.c @@ -132,6 +132,7 @@ dpaa_mbuf_free_pool(struct rte_mempool *mp) DPAA_MEMPOOL_INFO("BMAN pool freed for bpid =%d", bp_info->bpid); rte_free(mp->pool_data); + bp_info->bp = NULL; mp->pool_data = NULL; } } diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c index fce9ce2fe..0384532d2 100644 --- a/drivers/net/dpaa/dpaa_ethdev.c +++ b/drivers/net/dpaa/dpaa_ethdev.c @@ -587,6 +587,12 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)", queue_idx, rxq->fqid); + if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && + dpaa_intf->bp_info->mp != mp) { + DPAA_PMD_WARN("Multiple pools on same interface not supported"); + return -EINVAL; + } + /* Max packet can fit in single buffer */ if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) { ; From patchwork Fri Mar 6 09:57:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 184247 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp7233020ile; Fri, 6 Mar 2020 02:01:34 -0800 (PST) X-Google-Smtp-Source: ADFU+vuLMC48rw92YpLxUqdH5OVN57r9qWZXaZl+B14SEzF2xtNtGr/Qm/SZymqeFr3OWp376rWL X-Received: by 2002:a17:906:5c04:: with SMTP id e4mr2173062ejq.80.1583488894604; Fri, 06 Mar 2020 02:01:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583488894; cv=none; d=google.com; s=arc-20160816; b=gjgva6iqby/T2bF5y8rfNEmS+oxq7UThL2iYbIhZByjBoGd5XkUWCPd8qkBhj/qMAU ZnhWNLr0rxe+y97ye5Na2OAPPOV/IJo4k/EQVmdTOy9oyvTA8vZAr30fPfj9VSWAmSie NERUdVr8coDNmZPdh1jywc91icXVO+0232nI/G4Wr4IyLaygFZfuXbh6pf+JHWTyjxn0 GCCgtcsT6myeuZ/3iG8Pc5Fhl1YTvikMOcOH5cM8JcjKELeaOYkKW8mNAGKet2/fwd8h 10eN+U/V0dO8nOILp/nQ++N6kaYP1qh5bYDBn111IJFsThpbbe9yTMXZnI738ycotrnS qcYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=gcayX1ZLeuVWa0DsGwtrZZSp2kqCEBdW8wDMpHrKdyE=; b=GXjdX3qigH8Qvk8NFlRWapCc9CpeeLehtff0FFZYdr8eJKoMCxpCrDMIu2bRFKQtDc r+N4SQ/0Rno0tAezMDSDKPi44gQ7b24+x5pfIkE0gyybt6jHcPnmkWW++I8Zaz6d8V8c HUvysaOZlnrDlSkV2J3vBVaaEpr9c2h+tgUU/IqZgM7wmoyQ5kgOXMgbksIV3/IzKsrg pgKFxMJNDnZQHv+3UJLSrAXW5ktrfb2tV2OW4IWpb/iNxChBa4p4m1QXsUQYCvFeUgG8 ajUDZQPx3JEye4XjFajMyMJk9P8py5gNs+aO1FXLv1fjqYyekStc79Br2By0L0p6gnC0 BsSw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id n13si1070328eju.479.2020.03.06.02.01.34; Fri, 06 Mar 2020 02:01:34 -0800 (PST) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 10A931C08D; Fri, 6 Mar 2020 11:00:04 +0100 (CET) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id 9F2401C022 for ; Fri, 6 Mar 2020 10:59:53 +0100 (CET) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 8366A1A0A62; Fri, 6 Mar 2020 10:59:53 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 3418F1A0A80; Fri, 6 Mar 2020 10:59:51 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id E60BE402FF; Fri, 6 Mar 2020 17:59:47 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Gagandeep Singh Date: Fri, 6 Mar 2020 15:27:37 +0530 Message-Id: <20200306095742.18080-12-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200306095742.18080-1-hemant.agrawal@nxp.com> References: <20200302145829.27808-1-hemant.agrawal@nxp.com> <20200306095742.18080-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 11/16] net/dpaa: enable Tx queue taildrop X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Gagandeep Singh Enable congestion handling/tail drop for TX queues. Signed-off-by: Gagandeep Singh --- drivers/bus/dpaa/base/qbman/qman.c | 43 +++++++++ drivers/bus/dpaa/include/fsl_qman.h | 15 +++ drivers/bus/dpaa/rte_bus_dpaa_version.map | 2 + drivers/net/dpaa/dpaa_ethdev.c | 111 ++++++++++++++++++++-- drivers/net/dpaa/dpaa_ethdev.h | 2 +- drivers/net/dpaa/dpaa_rxtx.c | 71 ++++++++++++++ drivers/net/dpaa/dpaa_rxtx.h | 3 + 7 files changed, 240 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/drivers/bus/dpaa/base/qbman/qman.c b/drivers/bus/dpaa/base/qbman/qman.c index b53eb9e5e..494aca1d0 100644 --- a/drivers/bus/dpaa/base/qbman/qman.c +++ b/drivers/bus/dpaa/base/qbman/qman.c @@ -40,6 +40,8 @@ spin_unlock(&__fq478->fqlock); \ } while (0) +static qman_cb_free_mbuf qman_free_mbuf_cb; + static inline void fq_set(struct qman_fq *fq, u32 mask) { dpaa_set_bits(mask, &fq->flags); @@ -790,6 +792,47 @@ static inline void fq_state_change(struct qman_portal *p, struct qman_fq *fq, FQUNLOCK(fq); } +void +qman_ern_register_cb(qman_cb_free_mbuf cb) +{ + qman_free_mbuf_cb = cb; +} + + +void +qman_ern_poll_free(void) +{ + struct qman_portal *p = get_affine_portal(); + u8 verb, num = 0; + const struct qm_mr_entry *msg; + const struct qm_fd *fd; + struct qm_mr_entry swapped_msg; + + qm_mr_pvb_update(&p->p); + msg = qm_mr_current(&p->p); + + while (msg != NULL) { + swapped_msg = *msg; + hw_fd_to_cpu(&swapped_msg.ern.fd); + verb = msg->ern.verb & QM_MR_VERB_TYPE_MASK; + fd = &swapped_msg.ern.fd; + + if (unlikely(verb & 0x20)) { + printf("HW ERN notification, Nothing to do\n"); + } else { + if ((fd->bpid & 0xff) != 0xff) + qman_free_mbuf_cb(fd); + } + + num++; + qm_mr_next(&p->p); + qm_mr_pvb_update(&p->p); + msg = qm_mr_current(&p->p); + } + + qm_mr_cci_consume(&p->p, num); +} + static u32 __poll_portal_slow(struct qman_portal *p, u32 is) { const struct qm_mr_entry *msg; diff --git a/drivers/bus/dpaa/include/fsl_qman.h b/drivers/bus/dpaa/include/fsl_qman.h index 4deea5e75..fc00417fb 100644 --- a/drivers/bus/dpaa/include/fsl_qman.h +++ b/drivers/bus/dpaa/include/fsl_qman.h @@ -1152,6 +1152,10 @@ typedef void (*qman_cb_mr)(struct qman_portal *qm, struct qman_fq *fq, /* This callback type is used when handling DCP ERNs */ typedef void (*qman_cb_dc_ern)(struct qman_portal *qm, const struct qm_mr_entry *msg); + +/* This callback function will be used to free mbufs of ERN */ +typedef uint16_t (*qman_cb_free_mbuf)(const struct qm_fd *fd); + /* * s/w-visible states. Ie. tentatively scheduled + truly scheduled + active + * held-active + held-suspended are just "sched". Things like "retired" will not @@ -1778,6 +1782,17 @@ int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd, u32 flags); int qman_enqueue_multi(struct qman_fq *fq, const struct qm_fd *fd, u32 *flags, int frames_to_send); +/** + * qman_ern_poll_free - Polling on MR and calling a callback function to free + * mbufs when SW ERNs received. + */ +void qman_ern_poll_free(void); + +/** + * qman_ern_register_cb - Register a callback function to free buffers. + */ +void qman_ern_register_cb(qman_cb_free_mbuf cb); + /** * qman_enqueue_multi_fq - Enqueue multiple frames to their respective frame * queues. diff --git a/drivers/bus/dpaa/rte_bus_dpaa_version.map b/drivers/bus/dpaa/rte_bus_dpaa_version.map index e6ca4361e..ed319539c 100644 --- a/drivers/bus/dpaa/rte_bus_dpaa_version.map +++ b/drivers/bus/dpaa/rte_bus_dpaa_version.map @@ -61,6 +61,8 @@ DPDK_20.0 { qman_enqueue; qman_enqueue_multi; qman_enqueue_multi_fq; + qman_ern_poll_free; + qman_ern_register_cb; qman_fq_fqid; qman_fq_portal_irqsource_add; qman_fq_portal_irqsource_remove; diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c index 0384532d2..2ae79c9f5 100644 --- a/drivers/net/dpaa/dpaa_ethdev.c +++ b/drivers/net/dpaa/dpaa_ethdev.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. - * Copyright 2017-2019 NXP + * Copyright 2017-2020 NXP * */ /* System headers */ @@ -86,9 +86,12 @@ static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE; static int dpaa_push_queue_idx; /* Queue index which are in push mode*/ -/* Per FQ Taildrop in frame count */ +/* Per RX FQ Taildrop in frame count */ static unsigned int td_threshold = CGR_RX_PERFQ_THRESH; +/* Per TX FQ Taildrop in frame count, disabled by default */ +static unsigned int td_tx_threshold; + struct rte_dpaa_xstats_name_off { char name[RTE_ETH_XSTATS_NAME_SIZE]; uint32_t offset; @@ -275,7 +278,11 @@ static int dpaa_eth_dev_start(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); /* Change tx callback to the real one */ - dev->tx_pkt_burst = dpaa_eth_queue_tx; + if (dpaa_intf->cgr_tx) + dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; + else + dev->tx_pkt_burst = dpaa_eth_queue_tx; + fman_if_enable_rx(dpaa_intf->fif); return 0; @@ -869,6 +876,7 @@ int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)", queue_idx, dpaa_intf->tx_queues[queue_idx].fqid); dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx]; + return 0; } @@ -1239,9 +1247,19 @@ static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx, /* Initialise a Tx FQ */ static int dpaa_tx_queue_init(struct qman_fq *fq, - struct fman_if *fman_intf) + struct fman_if *fman_intf, + struct qman_cgr *cgr_tx) { struct qm_mcc_initfq opts = {0}; + struct qm_mcc_initcgr cgr_opts = { + .we_mask = QM_CGR_WE_CS_THRES | + QM_CGR_WE_CSTD_EN | + QM_CGR_WE_MODE, + .cgr = { + .cstd_en = QM_CGR_EN, + .mode = QMAN_CGR_MODE_FRAME + } + }; int ret; ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | @@ -1260,6 +1278,27 @@ static int dpaa_tx_queue_init(struct qman_fq *fq, opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi; opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo; DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid); + + if (cgr_tx) { + /* Enable tail drop with cgr on this queue */ + qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, + td_tx_threshold, 0); + cgr_tx->cb = NULL; + ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT, + &cgr_opts); + if (ret) { + DPAA_PMD_WARN( + "rx taildrop init fail on rx fqid 0x%x(ret=%d)", + fq->fqid, ret); + goto without_cgr; + } + opts.we_mask |= QM_INITFQ_WE_CGID; + opts.fqd.cgid = cgr_tx->cgrid; + opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; + DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n", + td_tx_threshold); + } +without_cgr: ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); if (ret) DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret); @@ -1312,6 +1351,7 @@ dpaa_dev_init(struct rte_eth_dev *eth_dev) struct fman_if *fman_intf; struct fman_if_bpool *bp, *tmp_bp; uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES]; + uint32_t cgrid_tx[MAX_DPAA_CORES]; PMD_INIT_FUNC_TRACE(); @@ -1321,7 +1361,10 @@ dpaa_dev_init(struct rte_eth_dev *eth_dev) eth_dev->dev_ops = &dpaa_devops; /* Plugging of UCODE burst API not supported in Secondary */ eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; - eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; + if (dpaa_intf->cgr_tx) + eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; + else + eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP qman_set_fq_lookup_table( dpaa_intf->rx_queues->qman_fq_lookup_table); @@ -1368,6 +1411,21 @@ dpaa_dev_init(struct rte_eth_dev *eth_dev) return -ENOMEM; } + memset(cgrid, 0, sizeof(cgrid)); + memset(cgrid_tx, 0, sizeof(cgrid_tx)); + + /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means + * Tx tail drop is disabled. + */ + if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) { + td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD")); + DPAA_PMD_DEBUG("Tail drop threshold env configured: %u", + td_tx_threshold); + /* if a very large value is being configured */ + if (td_tx_threshold > UINT16_MAX) + td_tx_threshold = CGR_RX_PERFQ_THRESH; + } + /* If congestion control is enabled globally*/ if (td_threshold) { dpaa_intf->cgr_rx = rte_zmalloc(NULL, @@ -1416,9 +1474,36 @@ dpaa_dev_init(struct rte_eth_dev *eth_dev) goto free_rx; } + /* If congestion control is enabled globally*/ + if (td_tx_threshold) { + dpaa_intf->cgr_tx = rte_zmalloc(NULL, + sizeof(struct qman_cgr) * MAX_DPAA_CORES, + MAX_CACHELINE); + if (!dpaa_intf->cgr_tx) { + DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n"); + ret = -ENOMEM; + goto free_rx; + } + + ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES, + 1, 0); + if (ret != MAX_DPAA_CORES) { + DPAA_PMD_WARN("insufficient CGRIDs available"); + ret = -EINVAL; + goto free_rx; + } + } else { + dpaa_intf->cgr_tx = NULL; + } + + for (loop = 0; loop < MAX_DPAA_CORES; loop++) { + if (dpaa_intf->cgr_tx) + dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop]; + ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop], - fman_intf); + fman_intf, + dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL); if (ret) goto free_tx; dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf; @@ -1495,6 +1580,7 @@ dpaa_dev_init(struct rte_eth_dev *eth_dev) free_rx: rte_free(dpaa_intf->cgr_rx); + rte_free(dpaa_intf->cgr_tx); rte_free(dpaa_intf->rx_queues); dpaa_intf->rx_queues = NULL; dpaa_intf->nb_rx_queues = 0; @@ -1535,6 +1621,17 @@ dpaa_dev_uninit(struct rte_eth_dev *dev) rte_free(dpaa_intf->cgr_rx); dpaa_intf->cgr_rx = NULL; + /* Release TX congestion Groups */ + if (dpaa_intf->cgr_tx) { + for (loop = 0; loop < MAX_DPAA_CORES; loop++) + qman_delete_cgr(&dpaa_intf->cgr_tx[loop]); + + qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid, + MAX_DPAA_CORES); + rte_free(dpaa_intf->cgr_tx); + dpaa_intf->cgr_tx = NULL; + } + rte_free(dpaa_intf->rx_queues); dpaa_intf->rx_queues = NULL; @@ -1640,6 +1737,8 @@ rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused, eth_dev->device = &dpaa_dev->device; dpaa_dev->eth_dev = eth_dev; + qman_ern_register_cb(dpaa_free_mbuf); + /* Invoke PMD device initialization function */ diag = dpaa_dev_init(eth_dev); if (diag == 0) { diff --git a/drivers/net/dpaa/dpaa_ethdev.h b/drivers/net/dpaa/dpaa_ethdev.h index da06f1faa..3eab029fd 100644 --- a/drivers/net/dpaa/dpaa_ethdev.h +++ b/drivers/net/dpaa/dpaa_ethdev.h @@ -110,6 +110,7 @@ struct dpaa_if { struct qman_fq *rx_queues; struct qman_cgr *cgr_rx; struct qman_fq *tx_queues; + struct qman_cgr *cgr_tx; struct qman_fq debug_queues[2]; uint16_t nb_rx_queues; uint16_t nb_tx_queues; @@ -181,5 +182,4 @@ dpaa_rx_cb_atomic(void *event, struct qman_fq *fq, const struct qm_dqrr_entry *dqrr, void **bufs); - #endif diff --git a/drivers/net/dpaa/dpaa_rxtx.c b/drivers/net/dpaa/dpaa_rxtx.c index 5dba1db8b..5dedff25e 100644 --- a/drivers/net/dpaa/dpaa_rxtx.c +++ b/drivers/net/dpaa/dpaa_rxtx.c @@ -398,6 +398,69 @@ dpaa_eth_fd_to_mbuf(const struct qm_fd *fd, uint32_t ifid) return mbuf; } +uint16_t +dpaa_free_mbuf(const struct qm_fd *fd) +{ + struct rte_mbuf *mbuf; + struct dpaa_bp_info *bp_info; + uint8_t format; + void *ptr; + + bp_info = DPAA_BPID_TO_POOL_INFO(fd->bpid); + format = (fd->opaque & DPAA_FD_FORMAT_MASK) >> DPAA_FD_FORMAT_SHIFT; + if (unlikely(format == qm_fd_sg)) { + struct rte_mbuf *first_seg, *prev_seg, *cur_seg, *temp; + struct qm_sg_entry *sgt, *sg_temp; + void *vaddr, *sg_vaddr; + int i = 0; + uint16_t fd_offset = fd->offset; + + vaddr = DPAA_MEMPOOL_PTOV(bp_info, qm_fd_addr(fd)); + if (!vaddr) { + DPAA_PMD_ERR("unable to convert physical address"); + return -1; + } + sgt = vaddr + fd_offset; + sg_temp = &sgt[i++]; + hw_sg_to_cpu(sg_temp); + temp = (struct rte_mbuf *) + ((char *)vaddr - bp_info->meta_data_size); + sg_vaddr = DPAA_MEMPOOL_PTOV(bp_info, + qm_sg_entry_get64(sg_temp)); + + first_seg = (struct rte_mbuf *)((char *)sg_vaddr - + bp_info->meta_data_size); + first_seg->nb_segs = 1; + prev_seg = first_seg; + while (i < DPAA_SGT_MAX_ENTRIES) { + sg_temp = &sgt[i++]; + hw_sg_to_cpu(sg_temp); + sg_vaddr = DPAA_MEMPOOL_PTOV(bp_info, + qm_sg_entry_get64(sg_temp)); + cur_seg = (struct rte_mbuf *)((char *)sg_vaddr - + bp_info->meta_data_size); + first_seg->nb_segs += 1; + prev_seg->next = cur_seg; + if (sg_temp->final) { + cur_seg->next = NULL; + break; + } + prev_seg = cur_seg; + } + + rte_pktmbuf_free_seg(temp); + rte_pktmbuf_free_seg(first_seg); + return 0; + } + + ptr = DPAA_MEMPOOL_PTOV(bp_info, qm_fd_addr(fd)); + mbuf = (struct rte_mbuf *)((char *)ptr - bp_info->meta_data_size); + + rte_pktmbuf_free(mbuf); + + return 0; +} + /* Specific for LS1043 */ void dpaa_rx_cb_no_prefetch(struct qman_fq **fq, struct qm_dqrr_entry **dqrr, @@ -1011,6 +1074,14 @@ dpaa_eth_queue_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs) return sent; } +uint16_t +dpaa_eth_queue_tx_slow(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs) +{ + qman_ern_poll_free(); + + return dpaa_eth_queue_tx(q, bufs, nb_bufs); +} + uint16_t dpaa_eth_tx_drop_all(void *q __rte_unused, struct rte_mbuf **bufs __rte_unused, uint16_t nb_bufs __rte_unused) diff --git a/drivers/net/dpaa/dpaa_rxtx.h b/drivers/net/dpaa/dpaa_rxtx.h index 75b093c1e..d41add704 100644 --- a/drivers/net/dpaa/dpaa_rxtx.h +++ b/drivers/net/dpaa/dpaa_rxtx.h @@ -254,6 +254,8 @@ struct annotations_t { uint16_t dpaa_eth_queue_rx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs); +uint16_t dpaa_eth_queue_tx_slow(void *q, struct rte_mbuf **bufs, + uint16_t nb_bufs); uint16_t dpaa_eth_queue_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs); uint16_t dpaa_eth_tx_drop_all(void *q __rte_unused, @@ -266,6 +268,7 @@ int dpaa_eth_mbuf_to_sg_fd(struct rte_mbuf *mbuf, struct qm_fd *fd, uint32_t bpid); +uint16_t dpaa_free_mbuf(const struct qm_fd *fd); void dpaa_rx_cb(struct qman_fq **fq, struct qm_dqrr_entry **dqrr, void **bufs, int num_bufs); From patchwork Fri Mar 6 09:57:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 184248 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp7233268ile; Fri, 6 Mar 2020 02:01:46 -0800 (PST) X-Google-Smtp-Source: ADFU+vtFTXuwDDq1m3zm2prhALuz7R9bUV2jRL4ZBt4iN6CIqeTATItCr3mEC/QdECpL61c0P9tQ X-Received: by 2002:a17:906:c02:: with SMTP id s2mr2199723ejf.40.1583488906341; Fri, 06 Mar 2020 02:01:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583488906; cv=none; d=google.com; s=arc-20160816; b=VGfxk5l6cpXpNuXbw91Ro6WHB5TZJtOYR6tBfbFaoYkcXrTolEzUsBwGrvCLnK1RMG O0FeEJGCnAAvfUw93xLavCQQnsx11ljjX1Ze5r1PKz+JVxSH5x1P/pR8mnfvE2Wc/j7r lH2M8kfl0bcNKI5DUhpm/5BKuYbT90Lb8/mnfJAywezeR4nj2loFjie6o8T7eira0lGK 090yU7bJORU8PtO3Jsw/YerArbA9Hu2W6KD8z6dRQuZrSU3HKbwXAPjJL+A+N0JtsECW 4DcAysmiS7k9AeMNkIz3VP2xIp1Zd7i4Esx4Cowu3MZe4CoJexTwtqQdYM2DD3vCVDFy /Wng== ARC-Message-Signature: i=1; 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[92.243.14.124]) by mx.google.com with ESMTP id u4si1255865edx.69.2020.03.06.02.01.46; Fri, 06 Mar 2020 02:01:46 -0800 (PST) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B46CF1C06B; Fri, 6 Mar 2020 11:00:05 +0100 (CET) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id 1F0FB1BFF3 for ; Fri, 6 Mar 2020 10:59:55 +0100 (CET) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 031241A0AB0; Fri, 6 Mar 2020 10:59:55 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 3DD831A0AA0; Fri, 6 Mar 2020 10:59:52 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id D84CE40294; Fri, 6 Mar 2020 17:59:48 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Sachin Saxena , Gagandeep Singh Date: Fri, 6 Mar 2020 15:27:38 +0530 Message-Id: <20200306095742.18080-13-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200306095742.18080-1-hemant.agrawal@nxp.com> References: <20200302145829.27808-1-hemant.agrawal@nxp.com> <20200306095742.18080-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 12/16] net/dpaa: add 2.5G support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sachin Saxena Handle 2.5Gbps ethernet ports as well. Signed-off-by: Sachin Saxena Signed-off-by: Gagandeep Singh --- drivers/bus/dpaa/base/fman/fman.c | 6 ++++-- drivers/bus/dpaa/base/fman/netcfg_layer.c | 3 ++- drivers/bus/dpaa/include/fman.h | 1 + drivers/net/dpaa/dpaa_ethdev.c | 9 ++++++++- 4 files changed, 15 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/bus/dpaa/base/fman/fman.c b/drivers/bus/dpaa/base/fman/fman.c index 6d77a7e39..ae26041ca 100644 --- a/drivers/bus/dpaa/base/fman/fman.c +++ b/drivers/bus/dpaa/base/fman/fman.c @@ -263,7 +263,7 @@ fman_if_init(const struct device_node *dpa_node) fman_dealloc_bufs_mask_hi = 0; fman_dealloc_bufs_mask_lo = 0; } - /* Is the MAC node 1G, 10G? */ + /* Is the MAC node 1G, 2.5G, 10G? */ __if->__if.is_memac = 0; if (of_device_is_compatible(mac_node, "fsl,fman-1g-mac")) @@ -279,7 +279,9 @@ fman_if_init(const struct device_node *dpa_node) /* Right now forcing memac to 1g in case of error*/ __if->__if.mac_type = fman_mac_1g; } else { - if (strstr(char_prop, "sgmii")) + if (strstr(char_prop, "sgmii-2500")) + __if->__if.mac_type = fman_mac_2_5g; + else if (strstr(char_prop, "sgmii")) __if->__if.mac_type = fman_mac_1g; else if (strstr(char_prop, "rgmii")) { __if->__if.mac_type = fman_mac_1g; diff --git a/drivers/bus/dpaa/base/fman/netcfg_layer.c b/drivers/bus/dpaa/base/fman/netcfg_layer.c index 36eca88cd..b7009f229 100644 --- a/drivers/bus/dpaa/base/fman/netcfg_layer.c +++ b/drivers/bus/dpaa/base/fman/netcfg_layer.c @@ -44,7 +44,8 @@ dump_netcfg(struct netcfg_info *cfg_ptr) printf("\n+ Fman %d, MAC %d (%s);\n", __if->fman_idx, __if->mac_idx, - (__if->mac_type == fman_mac_1g) ? "1G" : "10G"); + (__if->mac_type == fman_mac_1g) ? "1G" : + (__if->mac_type == fman_mac_2_5g) ? "2.5G" : "10G"); printf("\tmac_addr: %02x:%02x:%02x:%02x:%02x:%02x\n", (&__if->mac_addr)->addr_bytes[0], diff --git a/drivers/bus/dpaa/include/fman.h b/drivers/bus/dpaa/include/fman.h index c02d32d22..12e598b2d 100644 --- a/drivers/bus/dpaa/include/fman.h +++ b/drivers/bus/dpaa/include/fman.h @@ -71,6 +71,7 @@ TAILQ_HEAD(rte_fman_if_list, __fman_if); enum fman_mac_type { fman_offline = 0, fman_mac_1g, + fman_mac_2_5g, fman_mac_10g, }; diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c index 2ae79c9f5..1d23fc674 100644 --- a/drivers/net/dpaa/dpaa_ethdev.c +++ b/drivers/net/dpaa/dpaa_ethdev.c @@ -356,8 +356,13 @@ static int dpaa_eth_dev_info(struct rte_eth_dev *dev, if (dpaa_intf->fif->mac_type == fman_mac_1g) { dev_info->speed_capa = ETH_LINK_SPEED_1G; + } else if (dpaa_intf->fif->mac_type == fman_mac_2_5g) { + dev_info->speed_capa = ETH_LINK_SPEED_1G + | ETH_LINK_SPEED_2_5G; } else if (dpaa_intf->fif->mac_type == fman_mac_10g) { - dev_info->speed_capa = (ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G); + dev_info->speed_capa = ETH_LINK_SPEED_1G + | ETH_LINK_SPEED_2_5G + | ETH_LINK_SPEED_10G; } else { DPAA_PMD_ERR("invalid link_speed: %s, %d", dpaa_intf->name, dpaa_intf->fif->mac_type); @@ -384,6 +389,8 @@ static int dpaa_eth_link_update(struct rte_eth_dev *dev, if (dpaa_intf->fif->mac_type == fman_mac_1g) link->link_speed = ETH_SPEED_NUM_1G; + else if (dpaa_intf->fif->mac_type == fman_mac_2_5g) + link->link_speed = ETH_SPEED_NUM_2_5G; else if (dpaa_intf->fif->mac_type == fman_mac_10g) link->link_speed = ETH_SPEED_NUM_10G; else From patchwork Fri Mar 6 09:57:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 184249 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp7233460ile; Fri, 6 Mar 2020 02:01:55 -0800 (PST) X-Google-Smtp-Source: ADFU+vuOLNjNL0sRzjy4mFPT2eiyxhU2jz6c/3kXOMpT3PALA7aQawFeseAotEONjB5hWzc0NFkh X-Received: by 2002:a50:bb23:: with SMTP id y32mr2336767ede.226.1583488915201; Fri, 06 Mar 2020 02:01:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583488915; cv=none; d=google.com; s=arc-20160816; b=lKbg2RVY6AqRMms7iJZugJYJ2qMM1Vu/OGWCdYv4AQT6mdj8wOO/rgG9hxpBqag26r PLJ+mKbXf0ZGX8qgmo/89HBF1lfRYTDKimd1Bkx9g+Rqd4pEFDQ+AKlP9cEm+BfCOVgh 7Ujm5Q7Yys4zJYSpA4D5BIVBQw6ZbmjjyuEugTAUr0pet5+Do2uO2IH4eIw4Hldq24Q1 7ZDRQFCfOQrpS49ZLR10TTTQyi6y9UHRPM5I9zGuuL36Mt+EohJJuLMEojHBhaVFpm9i S7A26yAd9irGG0o3z60FMgttSLoowYBnyroC9UNfasQRFLNgy5vKydQiEIwVZmmuR4ig udcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=l6wrjDd1dta0vW2d7bKDheKJsxS/GCZDVRNbSBLaN4o=; b=RDDXSRODqUhy5KChRoSnA0U/peLMdr6zJL8GayW/LsrhrdPPmpGgsl02dvVW6MLO2J FIbbxoa8TmUAqSYnEuraOYzQhQ1pfW/kQ0I9FKrHv6fQ9EUvXBSGf7XYjFqCk0d9fJno hiart4VYoRU/Q0bW0sYEc7oXsm7lI34tSJsNZV88qCCh/s3PcmYajssTBdvxbHV2O8ed qSjOzB/5GVoUYTYuRx4pnMRiGc9Hg8SUdnBg27INnn1fkirQXGKBJ9+ifIliw0Lum2N4 2LqmOLgNYA6LjgTIrxECfQ0SIRi9UgTAUK9TKo+l3kB3YyVgxalRpxy3GhZBOgBaw2+U rcEQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id q22si1265066edc.209.2020.03.06.02.01.55; Fri, 06 Mar 2020 02:01:55 -0800 (PST) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 432541C0B6; Fri, 6 Mar 2020 11:00:07 +0100 (CET) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id 2E2441C02C for ; Fri, 6 Mar 2020 10:59:55 +0100 (CET) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 0A3821A0AB3; Fri, 6 Mar 2020 10:59:55 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id B166F1A0AA7; Fri, 6 Mar 2020 10:59:52 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id DD868402A0; Fri, 6 Mar 2020 17:59:49 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Nipun Gupta Date: Fri, 6 Mar 2020 15:27:39 +0530 Message-Id: <20200306095742.18080-14-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200306095742.18080-1-hemant.agrawal@nxp.com> References: <20200302145829.27808-1-hemant.agrawal@nxp.com> <20200306095742.18080-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 13/16] net/dpaa: update process specific device info X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nipun Gupta For DPAA devices the memory maps stored in the FMAN interface information is per process. Store them in the device process specific area. Signed-off-by: Nipun Gupta --- drivers/net/dpaa/dpaa_ethdev.c | 207 ++++++++++++++++----------------- drivers/net/dpaa/dpaa_ethdev.h | 1 - 2 files changed, 102 insertions(+), 106 deletions(-) -- 2.17.1 diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c index 1d23fc674..abe247acd 100644 --- a/drivers/net/dpaa/dpaa_ethdev.c +++ b/drivers/net/dpaa/dpaa_ethdev.c @@ -149,7 +149,6 @@ dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts) static int dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) { - struct dpaa_if *dpaa_intf = dev->data->dev_private; uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE; uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; @@ -185,7 +184,7 @@ dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; - fman_if_set_maxfrm(dpaa_intf->fif, frame_size); + fman_if_set_maxfrm(dev->process_private, frame_size); return 0; } @@ -193,7 +192,6 @@ dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) static int dpaa_eth_dev_configure(struct rte_eth_dev *dev) { - struct dpaa_if *dpaa_intf = dev->data->dev_private; struct rte_eth_conf *eth_conf = &dev->data->dev_conf; uint64_t rx_offloads = eth_conf->rxmode.offloads; uint64_t tx_offloads = eth_conf->txmode.offloads; @@ -232,14 +230,14 @@ dpaa_eth_dev_configure(struct rte_eth_dev *dev) max_len = DPAA_MAX_RX_PKT_LEN; } - fman_if_set_maxfrm(dpaa_intf->fif, max_len); + fman_if_set_maxfrm(dev->process_private, max_len); dev->data->mtu = max_len - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE; } if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) { DPAA_PMD_DEBUG("enabling scatter mode"); - fman_if_set_sg(dpaa_intf->fif, 1); + fman_if_set_sg(dev->process_private, 1); dev->data->scattered_rx = 1; } @@ -283,18 +281,18 @@ static int dpaa_eth_dev_start(struct rte_eth_dev *dev) else dev->tx_pkt_burst = dpaa_eth_queue_tx; - fman_if_enable_rx(dpaa_intf->fif); + fman_if_enable_rx(dev->process_private); return 0; } static void dpaa_eth_dev_stop(struct rte_eth_dev *dev) { - struct dpaa_if *dpaa_intf = dev->data->dev_private; + struct fman_if *fif = dev->process_private; PMD_INIT_FUNC_TRACE(); - fman_if_disable_rx(dpaa_intf->fif); + fman_if_disable_rx(fif); dev->tx_pkt_burst = dpaa_eth_tx_drop_all; } @@ -342,6 +340,7 @@ static int dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) { struct dpaa_if *dpaa_intf = dev->data->dev_private; + struct fman_if *fif = dev->process_private; DPAA_PMD_DEBUG(": %s", dpaa_intf->name); @@ -354,18 +353,18 @@ static int dpaa_eth_dev_info(struct rte_eth_dev *dev, dev_info->max_vmdq_pools = ETH_16_POOLS; dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL; - if (dpaa_intf->fif->mac_type == fman_mac_1g) { + if (fif->mac_type == fman_mac_1g) { dev_info->speed_capa = ETH_LINK_SPEED_1G; - } else if (dpaa_intf->fif->mac_type == fman_mac_2_5g) { + } else if (fif->mac_type == fman_mac_2_5g) { dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G; - } else if (dpaa_intf->fif->mac_type == fman_mac_10g) { + } else if (fif->mac_type == fman_mac_10g) { dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_10G; } else { DPAA_PMD_ERR("invalid link_speed: %s, %d", - dpaa_intf->name, dpaa_intf->fif->mac_type); + dpaa_intf->name, fif->mac_type); return -EINVAL; } @@ -384,18 +383,19 @@ static int dpaa_eth_link_update(struct rte_eth_dev *dev, { struct dpaa_if *dpaa_intf = dev->data->dev_private; struct rte_eth_link *link = &dev->data->dev_link; + struct fman_if *fif = dev->process_private; PMD_INIT_FUNC_TRACE(); - if (dpaa_intf->fif->mac_type == fman_mac_1g) + if (fif->mac_type == fman_mac_1g) link->link_speed = ETH_SPEED_NUM_1G; - else if (dpaa_intf->fif->mac_type == fman_mac_2_5g) + else if (fif->mac_type == fman_mac_2_5g) link->link_speed = ETH_SPEED_NUM_2_5G; - else if (dpaa_intf->fif->mac_type == fman_mac_10g) + else if (fif->mac_type == fman_mac_10g) link->link_speed = ETH_SPEED_NUM_10G; else DPAA_PMD_ERR("invalid link_speed: %s, %d", - dpaa_intf->name, dpaa_intf->fif->mac_type); + dpaa_intf->name, fif->mac_type); link->link_status = dpaa_intf->valid; link->link_duplex = ETH_LINK_FULL_DUPLEX; @@ -406,21 +406,17 @@ static int dpaa_eth_link_update(struct rte_eth_dev *dev, static int dpaa_eth_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) { - struct dpaa_if *dpaa_intf = dev->data->dev_private; - PMD_INIT_FUNC_TRACE(); - fman_if_stats_get(dpaa_intf->fif, stats); + fman_if_stats_get(dev->process_private, stats); return 0; } static int dpaa_eth_stats_reset(struct rte_eth_dev *dev) { - struct dpaa_if *dpaa_intf = dev->data->dev_private; - PMD_INIT_FUNC_TRACE(); - fman_if_stats_reset(dpaa_intf->fif); + fman_if_stats_reset(dev->process_private); return 0; } @@ -429,7 +425,6 @@ static int dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, unsigned int n) { - struct dpaa_if *dpaa_intf = dev->data->dev_private; unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings); uint64_t values[sizeof(struct dpaa_if_stats) / 8]; @@ -439,7 +434,7 @@ dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, if (xstats == NULL) return 0; - fman_if_stats_get_all(dpaa_intf->fif, values, + fman_if_stats_get_all(dev->process_private, values, sizeof(struct dpaa_if_stats) / 8); for (i = 0; i < num; i++) { @@ -476,15 +471,13 @@ dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8]; if (!ids) { - struct dpaa_if *dpaa_intf = dev->data->dev_private; - if (n < stat_cnt) return stat_cnt; if (!values) return 0; - fman_if_stats_get_all(dpaa_intf->fif, values_copy, + fman_if_stats_get_all(dev->process_private, values_copy, sizeof(struct dpaa_if_stats) / 8); for (i = 0; i < stat_cnt; i++) @@ -533,44 +526,36 @@ dpaa_xstats_get_names_by_id( static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev) { - struct dpaa_if *dpaa_intf = dev->data->dev_private; - PMD_INIT_FUNC_TRACE(); - fman_if_promiscuous_enable(dpaa_intf->fif); + fman_if_promiscuous_enable(dev->process_private); return 0; } static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev) { - struct dpaa_if *dpaa_intf = dev->data->dev_private; - PMD_INIT_FUNC_TRACE(); - fman_if_promiscuous_disable(dpaa_intf->fif); + fman_if_promiscuous_disable(dev->process_private); return 0; } static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev) { - struct dpaa_if *dpaa_intf = dev->data->dev_private; - PMD_INIT_FUNC_TRACE(); - fman_if_set_mcast_filter_table(dpaa_intf->fif); + fman_if_set_mcast_filter_table(dev->process_private); return 0; } static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev) { - struct dpaa_if *dpaa_intf = dev->data->dev_private; - PMD_INIT_FUNC_TRACE(); - fman_if_reset_mcast_filter_table(dpaa_intf->fif); + fman_if_reset_mcast_filter_table(dev->process_private); return 0; } @@ -583,6 +568,7 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, struct rte_mempool *mp) { struct dpaa_if *dpaa_intf = dev->data->dev_private; + struct fman_if *fif = dev->process_private; struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx]; struct qm_mcc_initfq opts = {0}; u32 flags = 0; @@ -645,22 +631,22 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, icp.iciof = DEFAULT_ICIOF; icp.iceof = DEFAULT_RX_ICEOF; icp.icsz = DEFAULT_ICSZ; - fman_if_set_ic_params(dpaa_intf->fif, &icp); + fman_if_set_ic_params(fif, &icp); fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE; - fman_if_set_fdoff(dpaa_intf->fif, fd_offset); + fman_if_set_fdoff(fif, fd_offset); /* Buffer pool size should be equal to Dataroom Size*/ bp_size = rte_pktmbuf_data_room_size(mp); - fman_if_set_bp(dpaa_intf->fif, mp->size, + fman_if_set_bp(fif, mp->size, dpaa_intf->bp_info->bpid, bp_size); dpaa_intf->valid = 1; DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d", dpaa_intf->name, fd_offset, - fman_if_get_fdoff(dpaa_intf->fif)); + fman_if_get_fdoff(fif)); } DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name, - fman_if_get_sg_enable(dpaa_intf->fif), + fman_if_get_sg_enable(fif), dev->data->dev_conf.rxmode.max_rx_pkt_len); /* checking if push mode only, no error check for now */ if (!rxq->is_static && @@ -952,11 +938,12 @@ dpaa_flow_ctrl_set(struct rte_eth_dev *dev, return 0; } else if (fc_conf->mode == RTE_FC_TX_PAUSE || fc_conf->mode == RTE_FC_FULL) { - fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water, + fman_if_set_fc_threshold(dev->process_private, + fc_conf->high_water, fc_conf->low_water, - dpaa_intf->bp_info->bpid); + dpaa_intf->bp_info->bpid); if (fc_conf->pause_time) - fman_if_set_fc_quanta(dpaa_intf->fif, + fman_if_set_fc_quanta(dev->process_private, fc_conf->pause_time); } @@ -992,10 +979,11 @@ dpaa_flow_ctrl_get(struct rte_eth_dev *dev, fc_conf->autoneg = net_fc->autoneg; return 0; } - ret = fman_if_get_fc_threshold(dpaa_intf->fif); + ret = fman_if_get_fc_threshold(dev->process_private); if (ret) { fc_conf->mode = RTE_FC_TX_PAUSE; - fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif); + fc_conf->pause_time = + fman_if_get_fc_quanta(dev->process_private); } else { fc_conf->mode = RTE_FC_NONE; } @@ -1010,11 +998,11 @@ dpaa_dev_add_mac_addr(struct rte_eth_dev *dev, __rte_unused uint32_t pool) { int ret; - struct dpaa_if *dpaa_intf = dev->data->dev_private; PMD_INIT_FUNC_TRACE(); - ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index); + ret = fman_if_add_mac_addr(dev->process_private, + addr->addr_bytes, index); if (ret) RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:" @@ -1026,11 +1014,9 @@ static void dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) { - struct dpaa_if *dpaa_intf = dev->data->dev_private; - PMD_INIT_FUNC_TRACE(); - fman_if_clear_mac_addr(dpaa_intf->fif, index); + fman_if_clear_mac_addr(dev->process_private, index); } static int @@ -1038,11 +1024,10 @@ dpaa_dev_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) { int ret; - struct dpaa_if *dpaa_intf = dev->data->dev_private; PMD_INIT_FUNC_TRACE(); - ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0); + ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0); if (ret) RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret); @@ -1145,7 +1130,6 @@ int rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on) { struct rte_eth_dev *dev; - struct dpaa_if *dpaa_intf; RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); @@ -1154,17 +1138,16 @@ rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on) if (!is_dpaa_supported(dev)) return -ENOTSUP; - dpaa_intf = dev->data->dev_private; - if (on) - fman_if_loopback_enable(dpaa_intf->fif); + fman_if_loopback_enable(dev->process_private); else - fman_if_loopback_disable(dpaa_intf->fif); + fman_if_loopback_disable(dev->process_private); return 0; } -static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf) +static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf, + struct fman_if *fman_intf) { struct rte_eth_fc_conf *fc_conf; int ret; @@ -1180,10 +1163,10 @@ static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf) } } fc_conf = dpaa_intf->fc_conf; - ret = fman_if_get_fc_threshold(dpaa_intf->fif); + ret = fman_if_get_fc_threshold(fman_intf); if (ret) { fc_conf->mode = RTE_FC_TX_PAUSE; - fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif); + fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf); } else { fc_conf->mode = RTE_FC_NONE; } @@ -1345,6 +1328,39 @@ static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid) } #endif +/* Initialise a network interface */ +static int +dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev) +{ + struct rte_dpaa_device *dpaa_device; + struct fm_eth_port_cfg *cfg; + struct dpaa_if *dpaa_intf; + struct fman_if *fman_intf; + int dev_id; + + PMD_INIT_FUNC_TRACE(); + + dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); + dev_id = dpaa_device->id.dev_id; + cfg = &dpaa_netcfg->port_cfg[dev_id]; + fman_intf = cfg->fman_if; + eth_dev->process_private = fman_intf; + + /* Plugging of UCODE burst API not supported in Secondary */ + dpaa_intf = eth_dev->data->dev_private; + eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; + if (dpaa_intf->cgr_tx) + eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; + else + eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; +#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP + qman_set_fq_lookup_table( + dpaa_intf->rx_queues->qman_fq_lookup_table); +#endif + + return 0; +} + /* Initialise a network interface */ static int dpaa_dev_init(struct rte_eth_dev *eth_dev) @@ -1362,23 +1378,6 @@ dpaa_dev_init(struct rte_eth_dev *eth_dev) PMD_INIT_FUNC_TRACE(); - dpaa_intf = eth_dev->data->dev_private; - /* For secondary processes, the primary has done all the work */ - if (rte_eal_process_type() != RTE_PROC_PRIMARY) { - eth_dev->dev_ops = &dpaa_devops; - /* Plugging of UCODE burst API not supported in Secondary */ - eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; - if (dpaa_intf->cgr_tx) - eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; - else - eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; -#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP - qman_set_fq_lookup_table( - dpaa_intf->rx_queues->qman_fq_lookup_table); -#endif - return 0; - } - dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); dev_id = dpaa_device->id.dev_id; dpaa_intf = eth_dev->data->dev_private; @@ -1388,7 +1387,7 @@ dpaa_dev_init(struct rte_eth_dev *eth_dev) dpaa_intf->name = dpaa_device->name; /* save fman_if & cfg in the interface struture */ - dpaa_intf->fif = fman_intf; + eth_dev->process_private = fman_intf; dpaa_intf->ifid = dev_id; dpaa_intf->cfg = cfg; @@ -1457,7 +1456,7 @@ dpaa_dev_init(struct rte_eth_dev *eth_dev) if (default_q) fqid = cfg->rx_def; else - fqid = DPAA_PCD_FQID_START + dpaa_intf->fif->mac_idx * + fqid = DPAA_PCD_FQID_START + fman_intf->mac_idx * DPAA_PCD_FQID_MULTIPLIER + loop; if (dpaa_intf->cgr_rx) @@ -1529,7 +1528,7 @@ dpaa_dev_init(struct rte_eth_dev *eth_dev) DPAA_PMD_DEBUG("All frame queues created"); /* Get the initial configuration for flow control */ - dpaa_fc_set_default(dpaa_intf); + dpaa_fc_set_default(dpaa_intf, fman_intf); /* reset bpool list, initialize bpool dynamically */ list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) { @@ -1682,6 +1681,13 @@ rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused, return -ENOMEM; eth_dev->device = &dpaa_dev->device; eth_dev->dev_ops = &dpaa_devops; + + ret = dpaa_dev_init_secondary(eth_dev); + if (ret != 0) { + RTE_LOG(ERR, PMD, "secondary dev init failed\n"); + return ret; + } + rte_eth_dev_probing_finish(eth_dev); return 0; } @@ -1718,29 +1724,20 @@ rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused, } } - /* In case of secondary process, the device is already configured - * and no further action is required, except portal initialization - * and verifying secondary attachment to port name. - */ - if (rte_eal_process_type() != RTE_PROC_PRIMARY) { - eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); - if (!eth_dev) - return -ENOMEM; - } else { - eth_dev = rte_eth_dev_allocate(dpaa_dev->name); - if (eth_dev == NULL) - return -ENOMEM; + eth_dev = rte_eth_dev_allocate(dpaa_dev->name); + if (!eth_dev) + return -ENOMEM; - eth_dev->data->dev_private = rte_zmalloc( - "ethdev private structure", - sizeof(struct dpaa_if), - RTE_CACHE_LINE_SIZE); - if (!eth_dev->data->dev_private) { - DPAA_PMD_ERR("Cannot allocate memzone for port data"); - rte_eth_dev_release_port(eth_dev); - return -ENOMEM; - } + eth_dev->data->dev_private = rte_zmalloc( + "ethdev private structure", + sizeof(struct dpaa_if), + RTE_CACHE_LINE_SIZE); + if (!eth_dev->data->dev_private) { + DPAA_PMD_ERR("Cannot allocate memzone for port data"); + rte_eth_dev_release_port(eth_dev); + return -ENOMEM; } + eth_dev->device = &dpaa_dev->device; dpaa_dev->eth_dev = eth_dev; diff --git a/drivers/net/dpaa/dpaa_ethdev.h b/drivers/net/dpaa/dpaa_ethdev.h index 3eab029fd..72a9c5910 100644 --- a/drivers/net/dpaa/dpaa_ethdev.h +++ b/drivers/net/dpaa/dpaa_ethdev.h @@ -115,7 +115,6 @@ struct dpaa_if { uint16_t nb_rx_queues; uint16_t nb_tx_queues; uint32_t ifid; - struct fman_if *fif; struct dpaa_bp_info *bp_info; struct rte_eth_fc_conf *fc_conf; }; From patchwork Fri Mar 6 09:57:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 184250 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp7233645ile; Fri, 6 Mar 2020 02:02:05 -0800 (PST) X-Google-Smtp-Source: ADFU+vvJ0rnWyn79mQcvnJlh+0jnRN2pqQEl+jmxWdud0y2EDHTjTXahujxVvKkgFIn13cFK8oQJ X-Received: by 2002:a05:6402:94b:: with SMTP id h11mr2237382edz.339.1583488925480; Fri, 06 Mar 2020 02:02:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583488925; cv=none; d=google.com; s=arc-20160816; b=DyhVXMY3OnXXIYY415dbTeyTNBQ2iGwa8NLY0l8EuCXTvHDjP9zIVV7XBEtuosMNkv lWoowuZb5//LaTGfP0M+Sx2gPC3GRHdJzx/tPq+H6kRo+mF5IXJFqqtdXjqswNA/en7h u9Of2AKYMnjvBhsTKz/dGEaU+2H81O4PC/VBJhLTiHW8l6luCoJs7do0OEhBAHcSo8UQ gcNZ48R9y3rywaANr8E7U8ZauzHm/OeV78Wbyh+VesSgWppdoDYDRnuojbyo+C/x+zsT qK2+RIbVYRs6KGSw1eaetPPRUE3TNbd3NYbISVv5q8tlTsanF/GK23R9FyQHADyS3lEX 7MvQ== ARC-Message-Signature: i=1; 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[92.243.14.124]) by mx.google.com with ESMTP id q18si833086edg.337.2020.03.06.02.02.05; Fri, 06 Mar 2020 02:02:05 -0800 (PST) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 957811C0BE; Fri, 6 Mar 2020 11:00:08 +0100 (CET) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id 2023D1C000 for ; Fri, 6 Mar 2020 10:59:56 +0100 (CET) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 004221A0A62; Fri, 6 Mar 2020 10:59:56 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id A2DE41A0A80; Fri, 6 Mar 2020 10:59:53 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id C88A9402E2; Fri, 6 Mar 2020 17:59:50 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Rohit Raj Date: Fri, 6 Mar 2020 15:27:40 +0530 Message-Id: <20200306095742.18080-15-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200306095742.18080-1-hemant.agrawal@nxp.com> References: <20200302145829.27808-1-hemant.agrawal@nxp.com> <20200306095742.18080-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 14/16] bus/dpaa: enable link state interrupt X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Rohit Raj Enable/disable link state interrupt and get link state api is defined using IOCTL calls. Signed-off-by: Rohit Raj --- drivers/bus/dpaa/base/fman/fman.c | 4 +- drivers/bus/dpaa/base/qbman/process.c | 68 ++++++++++++++++++- drivers/bus/dpaa/dpaa_bus.c | 28 +++++++- drivers/bus/dpaa/include/fman.h | 2 + drivers/bus/dpaa/include/process.h | 20 ++++++ drivers/bus/dpaa/rte_bus_dpaa_version.map | 8 +++ drivers/bus/dpaa/rte_dpaa_bus.h | 6 +- drivers/common/dpaax/compat.h | 5 +- drivers/net/dpaa/dpaa_ethdev.c | 82 ++++++++++++++++++++++- 9 files changed, 217 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/drivers/bus/dpaa/base/fman/fman.c b/drivers/bus/dpaa/base/fman/fman.c index ae26041ca..33be9e5d7 100644 --- a/drivers/bus/dpaa/base/fman/fman.c +++ b/drivers/bus/dpaa/base/fman/fman.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2010-2016 Freescale Semiconductor Inc. - * Copyright 2017-2019 NXP + * Copyright 2017-2020 NXP * */ @@ -185,6 +185,8 @@ fman_if_init(const struct device_node *dpa_node) } memset(__if, 0, sizeof(*__if)); INIT_LIST_HEAD(&__if->__if.bpool_list); + strlcpy(__if->node_name, dpa_node->name, IF_NAME_MAX_LEN - 1); + __if->node_name[IF_NAME_MAX_LEN - 1] = '\0'; strlcpy(__if->node_path, dpa_node->full_name, PATH_MAX - 1); __if->node_path[PATH_MAX - 1] = '\0'; diff --git a/drivers/bus/dpaa/base/qbman/process.c b/drivers/bus/dpaa/base/qbman/process.c index 2c23c98df..598b10661 100644 --- a/drivers/bus/dpaa/base/qbman/process.c +++ b/drivers/bus/dpaa/base/qbman/process.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2011-2016 Freescale Semiconductor Inc. - * Copyright 2017 NXP + * Copyright 2017,2020 NXP * */ #include @@ -296,3 +296,69 @@ int bman_free_raw_portal(struct dpaa_raw_portal *portal) return process_portal_free(&input); } + +#define DPAA_IOCTL_ENABLE_LINK_STATUS_INTERRUPT \ + _IOW(DPAA_IOCTL_MAGIC, 0x0E, struct usdpaa_ioctl_link_status) + +#define DPAA_IOCTL_DISABLE_LINK_STATUS_INTERRUPT \ + _IOW(DPAA_IOCTL_MAGIC, 0x0F, char*) + +int rte_dpaa_intr_enable(char *if_name, int efd) +{ + struct usdpaa_ioctl_link_status args; + + int ret = check_fd(); + + if (ret) + return ret; + + args.efd = (uint32_t)efd; + strcpy(args.if_name, if_name); + + ret = ioctl(fd, DPAA_IOCTL_ENABLE_LINK_STATUS_INTERRUPT, &args); + if (ret) { + perror("Failed to enable interrupt\n"); + return ret; + } + + return 0; +} + +int rte_dpaa_intr_disable(char *if_name) +{ + int ret = check_fd(); + + if (ret) + return ret; + + ret = ioctl(fd, DPAA_IOCTL_DISABLE_LINK_STATUS_INTERRUPT, &if_name); + if (ret) { + perror("Failed to disable interrupt\n"); + return ret; + } + + return 0; +} + +#define DPAA_IOCTL_GET_LINK_STATUS \ + _IOWR(DPAA_IOCTL_MAGIC, 0x10, struct usdpaa_ioctl_link_status_args) + +int rte_dpaa_get_link_status(char *if_name) +{ + int ret = check_fd(); + struct usdpaa_ioctl_link_status_args args; + + if (ret) + return ret; + + strcpy(args.if_name, if_name); + args.link_status = 0; + + ret = ioctl(fd, DPAA_IOCTL_GET_LINK_STATUS, &args); + if (ret) { + perror("Failed to get link status\n"); + return ret; + } + + return args.link_status; +} diff --git a/drivers/bus/dpaa/dpaa_bus.c b/drivers/bus/dpaa/dpaa_bus.c index f27820db3..2dedb138d 100644 --- a/drivers/bus/dpaa/dpaa_bus.c +++ b/drivers/bus/dpaa/dpaa_bus.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: BSD-3-Clause * - * Copyright 2017-2019 NXP + * Copyright 2017-2020 NXP * */ /* System headers */ @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -545,6 +546,23 @@ rte_dpaa_bus_dev_build(void) return 0; } +static int rte_dpaa_setup_intr(struct rte_intr_handle *intr_handle) +{ + int fd; + + fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC); + if (fd < 0) { + DPAA_BUS_ERR("Cannot set up eventfd, error %i (%s)", + errno, strerror(errno)); + return errno; + } + + intr_handle->fd = fd; + intr_handle->type = RTE_INTR_HANDLE_EXT; + + return 0; +} + static int rte_dpaa_bus_probe(void) { @@ -592,6 +610,14 @@ rte_dpaa_bus_probe(void) fclose(svr_file); } + TAILQ_FOREACH(dev, &rte_dpaa_bus.device_list, next) { + if (dev->device_type == FSL_DPAA_ETH) { + ret = rte_dpaa_setup_intr(&dev->intr_handle); + if (ret) + DPAA_PMD_ERR("Error setting up interrupt.\n"); + } + } + /* And initialize the PA->VA translation table */ dpaax_iova_table_populate(); diff --git a/drivers/bus/dpaa/include/fman.h b/drivers/bus/dpaa/include/fman.h index 12e598b2d..d90f2f5fc 100644 --- a/drivers/bus/dpaa/include/fman.h +++ b/drivers/bus/dpaa/include/fman.h @@ -2,6 +2,7 @@ * * Copyright 2010-2012 Freescale Semiconductor, Inc. * All rights reserved. + * Copyright 2019-2020 NXP * */ @@ -361,6 +362,7 @@ struct fman_if_ic_params { */ struct __fman_if { struct fman_if __if; + char node_name[IF_NAME_MAX_LEN]; char node_path[PATH_MAX]; uint64_t regs_size; void *ccsr_map; diff --git a/drivers/bus/dpaa/include/process.h b/drivers/bus/dpaa/include/process.h index d9ec94ee2..312da1245 100644 --- a/drivers/bus/dpaa/include/process.h +++ b/drivers/bus/dpaa/include/process.h @@ -2,6 +2,7 @@ * * Copyright 2010-2011 Freescale Semiconductor, Inc. * All rights reserved. + * Copyright 2020 NXP * */ @@ -74,4 +75,23 @@ struct dpaa_ioctl_irq_map { int process_portal_irq_map(int fd, struct dpaa_ioctl_irq_map *irq); int process_portal_irq_unmap(int fd); +struct usdpaa_ioctl_link_status { + char if_name[IF_NAME_MAX_LEN]; + uint32_t efd; +}; + +__rte_experimental +int rte_dpaa_intr_enable(char *if_name, int efd); + +__rte_experimental +int rte_dpaa_intr_disable(char *if_name); + +struct usdpaa_ioctl_link_status_args { + /* network device node name */ + char if_name[IF_NAME_MAX_LEN]; + int link_status; +}; +__rte_experimental +int rte_dpaa_get_link_status(char *if_name); + #endif /* __PROCESS_H */ diff --git a/drivers/bus/dpaa/rte_bus_dpaa_version.map b/drivers/bus/dpaa/rte_bus_dpaa_version.map index ed319539c..bf70e6656 100644 --- a/drivers/bus/dpaa/rte_bus_dpaa_version.map +++ b/drivers/bus/dpaa/rte_bus_dpaa_version.map @@ -96,3 +96,11 @@ DPDK_20.0 { local: *; }; + +EXPERIMENTAL { + global: + + rte_dpaa_get_link_status; + rte_dpaa_intr_disable; + rte_dpaa_intr_enable; +}; diff --git a/drivers/bus/dpaa/rte_dpaa_bus.h b/drivers/bus/dpaa/rte_dpaa_bus.h index 373aca978..f385f6de8 100644 --- a/drivers/bus/dpaa/rte_dpaa_bus.h +++ b/drivers/bus/dpaa/rte_dpaa_bus.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: BSD-3-Clause * - * Copyright 2017-2019 NXP + * Copyright 2017-2020 NXP * */ #ifndef __RTE_DPAA_BUS_H__ @@ -30,6 +30,9 @@ #define SVR_LS1046A_FAMILY 0x87070000 #define SVR_MASK 0xffff0000 +/** Device driver supports link state interrupt */ +#define RTE_DPAA_DRV_INTR_LSC 0x0008 + #define RTE_DEV_TO_DPAA_CONST(ptr) \ container_of(ptr, const struct rte_dpaa_device, device) @@ -88,6 +91,7 @@ struct rte_dpaa_driver { TAILQ_ENTRY(rte_dpaa_driver) next; struct rte_driver driver; struct rte_dpaa_bus *dpaa_bus; + uint32_t drv_flags; /**< Flags for controlling device.*/ enum rte_dpaa_type drv_type; rte_dpaa_probe_t probe; rte_dpaa_remove_t remove; diff --git a/drivers/common/dpaax/compat.h b/drivers/common/dpaax/compat.h index 12c9d9917..78e16fa2f 100644 --- a/drivers/common/dpaax/compat.h +++ b/drivers/common/dpaax/compat.h @@ -2,7 +2,7 @@ * * Copyright 2011 Freescale Semiconductor, Inc. * All rights reserved. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP * */ @@ -390,4 +390,7 @@ static inline unsigned long get_zeroed_page(gfp_t __foo __rte_unused) #define atomic_dec_return(v) rte_atomic32_sub_return(v, 1) #define atomic_sub_and_test(i, v) (rte_atomic32_sub_return(v, i) == 0) +/* Interface name len*/ +#define IF_NAME_MAX_LEN 16 + #endif /* __COMPAT_H */ diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c index abe247acd..28c6b1c17 100644 --- a/drivers/net/dpaa/dpaa_ethdev.c +++ b/drivers/net/dpaa/dpaa_ethdev.c @@ -45,6 +45,7 @@ #include #include #include +#include /* Supported Rx offloads */ static uint64_t dev_rx_offloads_sup = @@ -131,6 +132,11 @@ static struct rte_dpaa_driver rte_dpaa_pmd; static int dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); +static int dpaa_eth_link_update(struct rte_eth_dev *dev, + int wait_to_complete __rte_unused); + +static void dpaa_interrupt_handler(void *param); + static inline void dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts) { @@ -195,9 +201,18 @@ dpaa_eth_dev_configure(struct rte_eth_dev *dev) struct rte_eth_conf *eth_conf = &dev->data->dev_conf; uint64_t rx_offloads = eth_conf->rxmode.offloads; uint64_t tx_offloads = eth_conf->txmode.offloads; + struct rte_device *rdev = dev->device; + struct rte_dpaa_device *dpaa_dev; + struct fman_if *fif = dev->process_private; + struct __fman_if *__fif; + struct rte_intr_handle *intr_handle; PMD_INIT_FUNC_TRACE(); + dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); + intr_handle = &dpaa_dev->intr_handle; + __fif = container_of(fif, struct __fman_if, __if); + /* Rx offloads which are enabled by default */ if (dev_rx_offloads_nodis & ~rx_offloads) { DPAA_PMD_INFO( @@ -241,6 +256,14 @@ dpaa_eth_dev_configure(struct rte_eth_dev *dev) dev->data->scattered_rx = 1; } + /* if the interrupts were configured on this devices*/ + if (intr_handle && intr_handle->fd && + dev->data->dev_conf.intr_conf.lsc != 0) + rte_intr_callback_register(intr_handle, dpaa_interrupt_handler, + (void *)dev); + + rte_dpaa_intr_enable(__fif->node_name, intr_handle->fd); + return 0; } @@ -269,6 +292,25 @@ dpaa_supported_ptypes_get(struct rte_eth_dev *dev) return NULL; } +static void dpaa_interrupt_handler(void *param) +{ + struct rte_eth_dev *dev = param; + struct rte_device *rdev = dev->device; + struct rte_dpaa_device *dpaa_dev; + struct rte_intr_handle *intr_handle; + uint64_t buf; + int bytes_read; + + dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); + intr_handle = &dpaa_dev->intr_handle; + + bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t)); + if (bytes_read < 0) + DPAA_PMD_ERR("Error reading eventfd\n"); + dpaa_eth_link_update(dev, 0); + _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); +} + static int dpaa_eth_dev_start(struct rte_eth_dev *dev) { struct dpaa_if *dpaa_intf = dev->data->dev_private; @@ -298,9 +340,27 @@ static void dpaa_eth_dev_stop(struct rte_eth_dev *dev) static void dpaa_eth_dev_close(struct rte_eth_dev *dev) { + struct fman_if *fif = dev->process_private; + struct __fman_if *__fif; + struct rte_device *rdev = dev->device; + struct rte_dpaa_device *dpaa_dev; + struct rte_intr_handle *intr_handle; + PMD_INIT_FUNC_TRACE(); + dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); + intr_handle = &dpaa_dev->intr_handle; + __fif = container_of(fif, struct __fman_if, __if); + dpaa_eth_dev_stop(dev); + + rte_dpaa_intr_disable(__fif->node_name); + + if (intr_handle && intr_handle->fd && + dev->data->dev_conf.intr_conf.lsc != 0) + rte_intr_callback_unregister(intr_handle, + dpaa_interrupt_handler, + (void *)dev); } static int @@ -384,6 +444,8 @@ static int dpaa_eth_link_update(struct rte_eth_dev *dev, struct dpaa_if *dpaa_intf = dev->data->dev_private; struct rte_eth_link *link = &dev->data->dev_link; struct fman_if *fif = dev->process_private; + struct __fman_if *__fif = container_of(fif, struct __fman_if, __if); + int ret; PMD_INIT_FUNC_TRACE(); @@ -397,9 +459,23 @@ static int dpaa_eth_link_update(struct rte_eth_dev *dev, DPAA_PMD_ERR("invalid link_speed: %s, %d", dpaa_intf->name, fif->mac_type); - link->link_status = dpaa_intf->valid; + ret = rte_dpaa_get_link_status(__fif->node_name); + if (ret < 0) { + if (ret == -EINVAL) { + DPAA_PMD_DEBUG("Using default link status-No Support"); + ret = 1; + } else { + DPAA_PMD_ERR("rte_dpaa_get_link_status %d", ret); + return ret; + } + } + + link->link_status = ret; link->link_duplex = ETH_LINK_FULL_DUPLEX; link->link_autoneg = ETH_LINK_AUTONEG; + + DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, + link->link_status ? "Up" : "Down"); return 0; } @@ -1743,6 +1819,9 @@ rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused, qman_ern_register_cb(dpaa_free_mbuf); + if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC) + eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; + /* Invoke PMD device initialization function */ diag = dpaa_dev_init(eth_dev); if (diag == 0) { @@ -1770,6 +1849,7 @@ rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev) } static struct rte_dpaa_driver rte_dpaa_pmd = { + .drv_flags = RTE_DPAA_DRV_INTR_LSC, .drv_type = FSL_DPAA_ETH, .probe = rte_dpaa_probe, .remove = rte_dpaa_remove, From patchwork Fri Mar 6 09:57:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 184251 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp7233821ile; Fri, 6 Mar 2020 02:02:15 -0800 (PST) X-Google-Smtp-Source: ADFU+vtITzvCAodAYXrODvOQUceyqj5PxbhH88wTWPy0ZNeTaTzJbluXMBjW9eW5515e8qfunBCM X-Received: by 2002:a17:906:f258:: with SMTP id gy24mr2245867ejb.120.1583488934689; Fri, 06 Mar 2020 02:02:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583488934; cv=none; d=google.com; s=arc-20160816; b=FHefyX9jDyZjmi2MunBrDU0hSB2yM9bgSYsvhrdHMubPw6LsucAz9VfnOE1gb7KHGm ufeDfZayq1bLKXy1rEkbz5cs2aKZCKHHfCD158tvNGQNMOvpf9HnQVsXGYIsGZW1cqr0 RFC/liQP7hBXWE3hosRe71fJHMgya/9G8MhGHP8rViNa3Jw8nLvJUyKpSAnFRMrYECVA QLMnBDr/R+R5K2fJos/c/hXtSi648JOyF26L9V/ThCU3ugBloCSneqB1E6/ech+kvSjg 3tF8rB/n/H3M6B3I4wvB0tFRAD4tJOAA7rZ1JBwLG5zKEvAwIaKjUG5B5+d6plt6B3ig JQjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=24AcGpA/42VRh2lY4d8MdSQJxmdZMP/SgBAzzYC61Hw=; b=yieC0zzgtDgbP9UngVrAHWvGKVAaZOhb2FCGyqFi1peGHk+KFpg7Ye/zqIBlmSfSZv hHHonphY3aSn4zYjSZ/HG0kXz3X/JmeJr/sPF8CW4KfYMjoCcYGIDDNUmUJrg6mxvNSK cluCSSq599EK0xtMCfYhNI8vxDfg8ATaECytOeQXPBu5demfBQFSAUj7KDQtbp9diyvl kYHp83HKyb1algxrCK9KCMMVxYQDdsGlJx9dRxmimnN/jYRHEjPzpfQkjtmKfFjewvpl IuA8BelkoxmLu5tqkeAZNPhGPmTuYQX7EiJhDY2oFoglDEu2VKmZCaZHuGoGaU4uIKpv gqdw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id o18si1457087edz.215.2020.03.06.02.02.14; Fri, 06 Mar 2020 02:02:14 -0800 (PST) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D9B761C0C3; Fri, 6 Mar 2020 11:00:09 +0100 (CET) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id 1300D1C038 for ; Fri, 6 Mar 2020 10:59:57 +0100 (CET) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id C09B71A0A80; Fri, 6 Mar 2020 10:59:56 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6BE931A0AA5; Fri, 6 Mar 2020 10:59:54 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id B7BE54029B; Fri, 6 Mar 2020 17:59:51 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Rohit Raj Date: Fri, 6 Mar 2020 15:27:41 +0530 Message-Id: <20200306095742.18080-16-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200306095742.18080-1-hemant.agrawal@nxp.com> References: <20200302145829.27808-1-hemant.agrawal@nxp.com> <20200306095742.18080-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 15/16] bus/dpaa: enable set link status X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Rohit Raj Enabled set link status API to start/stop phy device from application. Signed-off-by: Rohit Raj --- drivers/bus/dpaa/base/qbman/process.c | 35 ++++++++++++++++++++--- drivers/bus/dpaa/include/process.h | 3 ++ drivers/bus/dpaa/rte_bus_dpaa_version.map | 1 + drivers/net/dpaa/dpaa_ethdev.c | 14 +++++++-- 4 files changed, 47 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/drivers/bus/dpaa/base/qbman/process.c b/drivers/bus/dpaa/base/qbman/process.c index 598b10661..8ab57f105 100644 --- a/drivers/bus/dpaa/base/qbman/process.c +++ b/drivers/bus/dpaa/base/qbman/process.c @@ -317,7 +317,7 @@ int rte_dpaa_intr_enable(char *if_name, int efd) ret = ioctl(fd, DPAA_IOCTL_ENABLE_LINK_STATUS_INTERRUPT, &args); if (ret) { - perror("Failed to enable interrupt\n"); + printf("Failed to enable interrupt: Not Supported\n"); return ret; } @@ -333,7 +333,7 @@ int rte_dpaa_intr_disable(char *if_name) ret = ioctl(fd, DPAA_IOCTL_DISABLE_LINK_STATUS_INTERRUPT, &if_name); if (ret) { - perror("Failed to disable interrupt\n"); + printf("Failed to disable interrupt: Not Supported\n"); return ret; } @@ -356,9 +356,36 @@ int rte_dpaa_get_link_status(char *if_name) ret = ioctl(fd, DPAA_IOCTL_GET_LINK_STATUS, &args); if (ret) { - perror("Failed to get link status\n"); - return ret; + printf("Failed to get link status: Not Supported\n"); + return -errno; } return args.link_status; } + +#define DPAA_IOCTL_UPDATE_LINK_STATUS \ + _IOW(DPAA_IOCTL_MAGIC, 0x11, struct usdpaa_ioctl_link_status_args) + +int rte_dpaa_update_link_status(char *if_name, int link_status) +{ + struct usdpaa_ioctl_link_status_args args; + int ret; + + ret = check_fd(); + if (ret) + return ret; + + strcpy(args.if_name, if_name); + args.link_status = link_status; + + ret = ioctl(fd, DPAA_IOCTL_UPDATE_LINK_STATUS, &args); + if (ret) { + if (errno == EINVAL) + printf("Failed to set link status: Not Supported\n"); + else + perror("Failed to set link status"); + return ret; + } + + return 0; +} diff --git a/drivers/bus/dpaa/include/process.h b/drivers/bus/dpaa/include/process.h index 312da1245..9f8c85895 100644 --- a/drivers/bus/dpaa/include/process.h +++ b/drivers/bus/dpaa/include/process.h @@ -94,4 +94,7 @@ struct usdpaa_ioctl_link_status_args { __rte_experimental int rte_dpaa_get_link_status(char *if_name); +__rte_experimental +int rte_dpaa_update_link_status(char *if_name, int link_status); + #endif /* __PROCESS_H */ diff --git a/drivers/bus/dpaa/rte_bus_dpaa_version.map b/drivers/bus/dpaa/rte_bus_dpaa_version.map index bf70e6656..146f29556 100644 --- a/drivers/bus/dpaa/rte_bus_dpaa_version.map +++ b/drivers/bus/dpaa/rte_bus_dpaa_version.map @@ -103,4 +103,5 @@ EXPERIMENTAL { rte_dpaa_get_link_status; rte_dpaa_intr_disable; rte_dpaa_intr_enable; + rte_dpaa_update_link_status; }; diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c index 28c6b1c17..c0a96dd47 100644 --- a/drivers/net/dpaa/dpaa_ethdev.c +++ b/drivers/net/dpaa/dpaa_ethdev.c @@ -972,17 +972,27 @@ dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) static int dpaa_link_down(struct rte_eth_dev *dev) { + struct fman_if *fif = dev->process_private; + struct __fman_if *__fif; + PMD_INIT_FUNC_TRACE(); - dpaa_eth_dev_stop(dev); + __fif = container_of(fif, struct __fman_if, __if); + + rte_dpaa_update_link_status(__fif->node_name, ETH_LINK_DOWN); return 0; } static int dpaa_link_up(struct rte_eth_dev *dev) { + struct fman_if *fif = dev->process_private; + struct __fman_if *__fif; + PMD_INIT_FUNC_TRACE(); - dpaa_eth_dev_start(dev); + __fif = container_of(fif, struct __fman_if, __if); + + rte_dpaa_update_link_status(__fif->node_name, ETH_LINK_UP); return 0; } From patchwork Fri Mar 6 09:57:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 184252 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp7234026ile; Fri, 6 Mar 2020 02:02:27 -0800 (PST) X-Google-Smtp-Source: ADFU+vsxlgAU3eppxVy7tSh/Jg7V6Oh5LjYRPsWxh4+yfRL6UB9vrMf1u6uWPcD+M8F2072OJL2q X-Received: by 2002:a05:6402:2208:: with SMTP id cq8mr2362589edb.161.1583488947599; Fri, 06 Mar 2020 02:02:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583488947; cv=none; d=google.com; s=arc-20160816; b=M5yE7/mjrd/XW2+Owc9E1L0S+WEn0JzIseoPdKDffK+ASvYFFmu1OMQPLCVaQXOG0C tUibrv7kVBtvl4V1sMFQ1tXejj8fwrDIvuNcHWQgtKCjZ7MKe4JE/4oqChDrajYtp4V4 Bato7ncQW1QnvJ6RZ1uUJ8PXghXQrFf3i8jRlEDlF6eGeMYsFkZgp0iuNjSpeqnX7Jin zKg8sTyzyP4m8gKbdh+P+6LXAIIp0sXn0XVxe7R4YK2uGh+bDjn3AvAleFj6tUhglCD3 YHiSZhhShjMit2X0pZmLw8MPv7mCWH54N2w1yChpWumghrcjiQYhFW0eLfkRyYvmdFxR vZHw== ARC-Message-Signature: i=1; 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[92.243.14.124]) by mx.google.com with ESMTP id k22si1294237edq.183.2020.03.06.02.02.27; Fri, 06 Mar 2020 02:02:27 -0800 (PST) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 101931C0D2; Fri, 6 Mar 2020 11:00:12 +0100 (CET) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by dpdk.org (Postfix) with ESMTP id CC8E41C045 for ; Fri, 6 Mar 2020 10:59:57 +0100 (CET) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id B0373200217; Fri, 6 Mar 2020 10:59:57 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 572E8200AD8; Fri, 6 Mar 2020 10:59:55 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 846D5402D5; Fri, 6 Mar 2020 17:59:52 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Nipun Gupta Date: Fri, 6 Mar 2020 15:27:42 +0530 Message-Id: <20200306095742.18080-17-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200306095742.18080-1-hemant.agrawal@nxp.com> References: <20200302145829.27808-1-hemant.agrawal@nxp.com> <20200306095742.18080-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 16/16] net/dpaa2: do not prefetch annotaion for physical mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nipun Gupta When IOVA is physical address do not prefetch the annotation of the next frame, as there is a cost involved there to convert the physical address to virtual address. Signed-off-by: Nipun Gupta --- drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 6 ++-- drivers/net/dpaa2/dpaa2_rxtx.c | 40 +++++++++++++++---------- 2 files changed, 28 insertions(+), 18 deletions(-) -- 2.17.1 diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h index bde1441f4..6b07b628a 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. - * Copyright 2016-2019 NXP + * Copyright 2016-2020 NXP * */ @@ -403,8 +403,8 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) #else /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */ #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_addr) -#define DPAA2_VADDR_TO_IOVA(_vaddr) (_vaddr) -#define DPAA2_IOVA_TO_VADDR(_iova) (_iova) +#define DPAA2_VADDR_TO_IOVA(_vaddr) (phys_addr_t)(_vaddr) +#define DPAA2_IOVA_TO_VADDR(_iova) (void *)(_iova) #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) #endif /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */ diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c index d809e0f4b..4d024a85f 100644 --- a/drivers/net/dpaa2/dpaa2_rxtx.c +++ b/drivers/net/dpaa2/dpaa2_rxtx.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. - * Copyright 2016-2019 NXP + * Copyright 2016-2020 NXP * */ @@ -324,8 +324,8 @@ static inline struct rte_mbuf *__attribute__((hot)) eth_fd_to_mbuf(const struct qbman_fd *fd, int port_id) { - struct rte_mbuf *mbuf = DPAA2_INLINE_MBUF_FROM_BUF( - DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)), + void *iova_addr = DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)); + struct rte_mbuf *mbuf = DPAA2_INLINE_MBUF_FROM_BUF(iova_addr, rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size); /* need to repopulated some of the fields, @@ -350,8 +350,7 @@ eth_fd_to_mbuf(const struct qbman_fd *fd, dpaa2_dev_rx_parse_new(mbuf, fd); else mbuf->packet_type = dpaa2_dev_rx_parse(mbuf, - (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) - + DPAA2_FD_PTA_SIZE)); + (void *)((size_t)iova_addr + DPAA2_FD_PTA_SIZE)); DPAA2_PMD_DP_DEBUG("to mbuf - mbuf =%p, mbuf->buf_addr =%p, off = %d," "fd_off=%d fd =%" PRIx64 ", meta = %d bpid =%d, len=%d\n", @@ -518,7 +517,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) int ret, num_rx = 0, pull_size; uint8_t pending, status; struct qbman_swp *swp; - const struct qbman_fd *fd, *next_fd; + const struct qbman_fd *fd; struct qbman_pull_desc pulldesc; struct queue_storage_info_t *q_storage = dpaa2_q->q_storage; struct rte_eth_dev_data *eth_data = dpaa2_q->eth_data; @@ -617,12 +616,15 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) } fd = qbman_result_DQ_fd(dq_storage); +#ifndef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA if (dpaa2_svr_family != SVR_LX2160A) { - next_fd = qbman_result_DQ_fd(dq_storage + 1); + const struct qbman_fd *next_fd = + qbman_result_DQ_fd(dq_storage + 1); /* Prefetch Annotation address for the parse results */ - rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR( - next_fd) + DPAA2_FD_PTA_SIZE + 16)); + rte_prefetch0(DPAA2_IOVA_TO_VADDR((DPAA2_GET_FD_ADDR( + next_fd) + DPAA2_FD_PTA_SIZE + 16))); } +#endif if (unlikely(DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg)) bufs[num_rx] = eth_sg_fd_to_mbuf(fd, eth_data->port_id); @@ -753,7 +755,7 @@ dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) int ret, num_rx = 0, next_pull = nb_pkts, num_pulled; uint8_t pending, status; struct qbman_swp *swp; - const struct qbman_fd *fd, *next_fd; + const struct qbman_fd *fd; struct qbman_pull_desc pulldesc; struct rte_eth_dev_data *eth_data = dpaa2_q->eth_data; @@ -821,11 +823,19 @@ dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) } fd = qbman_result_DQ_fd(dq_storage); - next_fd = qbman_result_DQ_fd(dq_storage + 1); - /* Prefetch Annotation address for the parse results */ - rte_prefetch0( - (void *)(size_t)(DPAA2_GET_FD_ADDR(next_fd) - + DPAA2_FD_PTA_SIZE + 16)); +#ifndef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA + if (dpaa2_svr_family != SVR_LX2160A) { + const struct qbman_fd *next_fd = + qbman_result_DQ_fd(dq_storage + 1); + + /* Prefetch Annotation address for the parse + * results. + */ + rte_prefetch0((DPAA2_IOVA_TO_VADDR( + DPAA2_GET_FD_ADDR(next_fd) + + DPAA2_FD_PTA_SIZE + 16))); + } +#endif if (unlikely(DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg)) bufs[num_rx] = eth_sg_fd_to_mbuf(fd,