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Tue, 25 Feb 2025 10:46:29 -0800 (PST) Received: from draig.lan ([185.126.160.109]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390cd8e70c8sm3151125f8f.76.2025.02.25.10.46.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2025 10:46:29 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 844E95F9D0; Tue, 25 Feb 2025 18:46:28 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Igor Mammedov , Richard Henderson , Helge Deller , Paolo Bonzini , Nicholas Piggin , qemu-ppc@nongnu.org, Zhao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 1/4] target/ppc: drop ppc_tlb_invalidate_all from cpu_reset Date: Tue, 25 Feb 2025 18:46:25 +0000 Message-Id: <20250225184628.3590671-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250225184628.3590671-1-alex.bennee@linaro.org> References: <20250225184628.3590671-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The vCPU parent already triggers a tb_flush so this is un-needed: #0 tlb_flush_other_cpu (cpu=0x555556df8630) at ../../accel/tcg/cputlb.c:419 #1 0x0000555555ee38c9 in tcg_cpu_reset_hold (cpu=0x555556df8630) at ../../accel/tcg/tcg-accel-ops.c:88 #2 0x0000555555bc29e5 in cpu_exec_reset_hold (cpu=0x555556df8630) at ../../system/cpus.c:208 #3 0x00005555558932c3 in cpu_common_reset_hold (obj=0x555556df8630, type=RESET_TYPE_COLD) at ../../hw/core/cpu-common.c:139 #4 0x0000555555d480b1 in ppc_cpu_reset_hold (obj=0x555556df8630, type=RESET_TYPE_COLD) at ../../target/ppc/cpu_init.c:7200 #5 0x0000555555ef28f0 in resettable_phase_hold (obj=0x555556df8630, opaque=0x0, type=RESET_TYPE_COLD) at ../../hw/core/resettable.c:162 #6 0x0000555555ef24f4 in resettable_assert_reset (obj=0x555556df8630, type=RESET_TYPE_COLD) at ../../hw/core/resettable.c:58 #7 0x0000555555ef244c in resettable_reset (obj=0x555556df8630, type=RESET_TYPE_COLD) at ../../hw/core/resettable.c:45 #8 0x0000555555eef525 in device_cold_reset (dev=0x555556df8630) at ../../hw/core/qdev.c:239 #9 0x00005555558931ab in cpu_reset (cpu=0x555556df8630) at ../../hw/core/cpu-common.c:114 #10 0x0000555555d1ec6b in ppce500_cpu_reset (opaque=0x555556df8630) at ../../hw/ppc/e500.c:785 #11 0x000055555595c410 in legacy_reset_hold (obj=0x555556e6bbc0, type=RESET_TYPE_COLD) at ../../hw/core/reset.c:76 #12 0x0000555555ef28f0 in resettable_phase_hold (obj=0x555556e6bbc0, opaque=0x0, type=RESET_TYPE_COLD) at ../../hw/core/resettable.c:162 Signed-off-by: Alex Bennée --- target/ppc/cpu_init.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 062a6e85fb..f987b75c4f 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7242,9 +7242,6 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) if (tcg_enabled()) { cpu_breakpoint_remove_all(cs, BP_CPU); cpu_watchpoint_remove_all(cs, BP_CPU); - if (env->mmu_model != POWERPC_MMU_REAL) { - ppc_tlb_invalidate_all(env); - } pmu_mmcr01a_updated(env); } From patchwork Tue Feb 25 18:46:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 868174 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f56:0:b0:38f:210b:807b with SMTP id cm22csp451959wrb; Tue, 25 Feb 2025 10:47:51 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXLq3vQPf04JyCCuSp8/fOqYE8u9JLBGcqcHjJAwJxW1qlQuY0hq8e+6jKAHfKM+dR1/i2ijQ==@linaro.org X-Google-Smtp-Source: AGHT+IEmQqxCIaZqD+sKYyY14tzY8zjAViKKPtXo8oV4p4/17EhP5UF0ctrjAnk+0LWmJ66sGjSV X-Received: by 2002:a05:620a:258a:b0:7c0:b0eb:4fa9 with SMTP id af79cd13be357-7c247efc703mr72139685a.5.1740509271458; Tue, 25 Feb 2025 10:47:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1740509271; cv=none; d=google.com; s=arc-20240605; b=lEgglJP1BzO6JCvDx972bNroNOOvPPv8/vIWA3CMSB/QrcV1qaE02IF3cwAD7Jbqre W9tEbWd7WY/wqTjW3WekKAbaT8Sgcexni/MnkiugPiNdiJUR5bnaKKWvP+yhDqbcX8qt G0ZO8+q63WiX1WZIptfiFOzsTAtRyoHXA9iOeN8SWj1dKpkQvkXnvpzZZXneQnd5fhOt +MCSTJ5eQ8LHuQCMniDQMNQW4b5Ab7vwynA3ZBfMewfBdVZw7d9XYQX2+pBBNBY34yYu aCHNbaAzbT1bKvpNoJMMl93qI2uamYhnxsQCHJ5jV2X/6D5nTQoiAICMyzu0eiFhauhT uknw== ARC-Message-Signature: i=1; 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Tue, 25 Feb 2025 10:46:30 -0800 (PST) Received: from draig.lan ([185.126.160.109]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390cd8fc1f9sm3107205f8f.88.2025.02.25.10.46.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2025 10:46:29 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 990E85F9D3; Tue, 25 Feb 2025 18:46:28 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Igor Mammedov , Richard Henderson , Helge Deller , Paolo Bonzini , Nicholas Piggin , qemu-ppc@nongnu.org, Zhao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 2/4] target/hppa: defer hppa_ptlbe until CPU starts running Date: Tue, 25 Feb 2025 18:46:26 +0000 Message-Id: <20250225184628.3590671-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250225184628.3590671-1-alex.bennee@linaro.org> References: <20250225184628.3590671-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since 30933c4fb4 (tcg/cputlb: remove other-cpu capability from TLB flushing) we don't expect non-CPU callers to the tlb_flush() code. Normally I would drop the call anyway as the common cpu_reset() code will call tlb_flush anyway. However as the flush function does more than that, and is called from helpers instead defer it with an async_run_on_cpu. Signed-off-by: Alex Bennée --- target/hppa/cpu.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 5655677431..b631af381c 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -168,6 +168,14 @@ void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, cpu_loop_exit(cs); } + +static void hppa_clear_ptlbe(CPUState *cpu, run_on_cpu_data opaque) +{ + CPUHPPAState *env = (CPUHPPAState *) opaque.host_ptr; + hppa_ptlbe(env); +} + + #endif /* CONFIG_USER_ONLY */ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) @@ -191,7 +199,7 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hppa_cpu_alarm_timer, cpu); - hppa_ptlbe(&cpu->env); + async_run_on_cpu(cs, hppa_clear_ptlbe, RUN_ON_CPU_HOST_PTR(&cpu->env)); } #endif From patchwork Tue Feb 25 18:46:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 868171 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f56:0:b0:38f:210b:807b with SMTP id cm22csp451936wrb; Tue, 25 Feb 2025 10:47:50 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWA8KUIue/czleYhoR7IiSE5M7LeSaEkbNQEZJsO+vWOVpyvKFNHXiW4JpDVKjB176OMe5CnQ==@linaro.org X-Google-Smtp-Source: AGHT+IFstrfHTI5AvwujN1ctgEG1G74D5jK2A79j7iwX2E+YthYdByocbqQni6qZ6qvbnRTtRehO X-Received: by 2002:a05:620a:3184:b0:7c0:b0e5:96e with SMTP id af79cd13be357-7c247fd0f38mr61736885a.46.1740509269819; Tue, 25 Feb 2025 10:47:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1740509269; cv=none; d=google.com; s=arc-20240605; b=CXFLhG6HnBsldfo23VHVyGrN/MGu/hrnkonkAn9xcHI2fxu/c5hNl6psF6tMemH5qS PolQOH7BCOCxSk4sBzuTocRPRf7DWcayxanVfJAJet8FY+ndibbE8MfYhBqlVjXBmtBr pAjL8kL1r9oh3SKl27HbNU1sZmtNgQ5dPyHO0k5Quf+Ut5ZwvV2wvhOSGO/57JZykMo7 NONQX/Rm3ciFo5MLCQbhnPv+YGok7AgwrUWLK8Fk5b5rtLYnzYVMUD4twcLsNoN+jlDz w+5DjPx/2uj4XR/bu2c7xfybLBLOmuhADJMJhtPZ7GPrWT9dfhAPixxNn+vBPsDIjEAF YGNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jbTRpF5vcyxr/D6s1C7IEHtKwvLNoxEVjp74TTMjyRA=; fh=dFDpqKUIk5e4jJnU8vTV6qs+Qflv6j/ZkUgZdBt3wxc=; b=Km/Gb9tuFfzTWUkS/XMhh1JGAUxbsB6DUoShkjuNGVt2fX3BxSM5AF5WVbh+tq+5VL ddPI5WMHsWuy0byBJdTfHIC17LjNOyIlelQzhSaq1zWtFBVgt6cVqYktIRaGn0adKnNg FaQ84Z9mdJqsM+LCqEDUG89umn6j1vGh1N0HPN9LuGJTH12+DzqaJQkSkdYBAdVj5/ql i3fsqADarnDXYNWWYkvtH5jiWp91D/K1QZPd7Sx+PfIY0MvPb31p5rETJcOMgbPpsHdr hqMrEZq/SzL+gxa3Ur8iPPNb8b/sdj12V6Za0JAK8uT1rzjVgRTHZzzlc76Mjbj1HmC/ 5sdA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KSuLm6NC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 25 Feb 2025 10:46:32 -0800 (PST) Received: from draig.lan ([185.126.160.109]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ab155eb77sm37328515e9.32.2025.02.25.10.46.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2025 10:46:29 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id B2C1F5F9D7; Tue, 25 Feb 2025 18:46:28 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Igor Mammedov , Richard Henderson , Helge Deller , Paolo Bonzini , Nicholas Piggin , qemu-ppc@nongnu.org, Zhao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 3/4] cputlb: introduce tlb_flush_other_cpu for reset use Date: Tue, 25 Feb 2025 18:46:27 +0000 Message-Id: <20250225184628.3590671-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250225184628.3590671-1-alex.bennee@linaro.org> References: <20250225184628.3590671-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The commit 30933c4fb4 (tcg/cputlb: remove other-cpu capability from TLB flushing) introduced a regression that only shows up when --enable-debug-tcg is used. The main use case of tlb_flush outside of the current_cpu context is for handling reset and CPU creation. Rather than revert the commit introduce a new helper and tweak the documentation to make it clear where it should be used. Signed-off-by: Alex Bennée --- v2 - appraently reset can come from both cpu context and outside - add cpu_common_post_load fixes --- include/exec/exec-all.h | 20 ++++++++++++++++---- accel/tcg/cputlb.c | 11 +++++++++++ accel/tcg/tcg-accel-ops.c | 2 +- cpu-target.c | 2 +- target/i386/machine.c | 2 +- 5 files changed, 30 insertions(+), 7 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index d9045c9ac4..cf030001ca 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -64,12 +64,24 @@ void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr); * tlb_flush: * @cpu: CPU whose TLB should be flushed * - * Flush the entire TLB for the specified CPU. Most CPU architectures - * allow the implementation to drop entries from the TLB at any time - * so this is generally safe. If more selective flushing is required - * use one of the other functions for efficiency. + * Flush the entire TLB for the specified current CPU. + * + * Most CPU architectures allow the implementation to drop entries + * from the TLB at any time so this is generally safe. If more + * selective flushing is required use one of the other functions for + * efficiency. */ void tlb_flush(CPUState *cpu); +/** + * tlb_flush_other_cpu: + * @cpu: CPU whose TLB should be flushed + * + * Flush the entire TLB for a specified CPU. For cross vCPU flushes + * you shuld be using a more selective function. This is really only + * used for flushing CPUs being reset from outside their current + * context. + */ +void tlb_flush_other_cpu(CPUState *cpu); /** * tlb_flush_all_cpus_synced: * @cpu: src CPU of the flush diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ad158050a1..fc16a576f0 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -417,6 +417,17 @@ void tlb_flush(CPUState *cpu) tlb_flush_by_mmuidx(cpu, ALL_MMUIDX_BITS); } +void tlb_flush_other_cpu(CPUState *cpu) +{ + if (qemu_cpu_is_self(cpu)) { + tlb_flush(cpu); + } else { + async_run_on_cpu(cpu, + tlb_flush_by_mmuidx_async_work, + RUN_ON_CPU_HOST_INT(ALL_MMUIDX_BITS)); + } +} + void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *src_cpu, uint16_t idxmap) { const run_on_cpu_func fn = tlb_flush_by_mmuidx_async_work; diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 6e3f1fa92b..e85d317d34 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -85,7 +85,7 @@ static void tcg_cpu_reset_hold(CPUState *cpu) { tcg_flush_jmp_cache(cpu); - tlb_flush(cpu); + tlb_flush_other_cpu(cpu); } /* mask must never be zero, except for A20 change call */ diff --git a/cpu-target.c b/cpu-target.c index 667688332c..8eb1633c02 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -56,7 +56,7 @@ static int cpu_common_post_load(void *opaque, int version_id) /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the version_id is increased. */ cpu->interrupt_request &= ~0x01; - tlb_flush(cpu); + tlb_flush_other_cpu(cpu); /* loadvm has just updated the content of RAM, bypassing the * usual mechanisms that ensure we flush TBs for writes to diff --git a/target/i386/machine.c b/target/i386/machine.c index d9d4f25d1a..e66f46758a 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -401,7 +401,7 @@ static int cpu_post_load(void *opaque, int version_id) env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK); cpu_x86_update_dr7(env, dr7); } - tlb_flush(cs); + tlb_flush_other_cpu(cs); return 0; } From patchwork Tue Feb 25 18:46:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 868173 Delivered-To: patch@linaro.org Received: by 2002:a5d:5f56:0:b0:38f:210b:807b with SMTP id cm22csp451954wrb; Tue, 25 Feb 2025 10:47:51 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVtYgU4ttxuhthm5DGFVtnTPZPruOEDDNM7U5ydcFM2w8VigTXbcSCZzZdgOPKBIrkW2MJZRQ==@linaro.org X-Google-Smtp-Source: AGHT+IFzvM6WkpVKwIqSpuB1NnU05aMuT3HWGvRk9UYm8DGn8oPDURIDiF8MkzxADfIWuMjKu2U7 X-Received: by 2002:a05:6214:400c:b0:6d9:2e0c:56c4 with SMTP id 6a1803df08f44-6e88686e258mr4892786d6.1.1740509271322; Tue, 25 Feb 2025 10:47:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1740509271; cv=none; d=google.com; s=arc-20240605; b=Hh2JlyleYvQXsoPcjWnAcC1AmAMS84/ysVC9LdHMpPdPWdOE3hEV+pomuqB6t92M9v ztiK3Td7YOVtgX26GdCeFzDuExdPOywjTfizHU7rwSLQS6Q3qFBa01RSTeKAs+udJyvu 0DVfdzBtouq60xFyoYXPh4N4YigZjvYxthyqjwD26efi8X9YoMR2lq+Ddw9bSVTJQ+x3 C+JQWIC3qog3nbaWv6/Bat6kQtYmvCTb8LeIA4kVNVF/FVR0AE1wh8y/74ENWI/F00yX Idq5e2OE6ImMONPxAAOWDpbC1L0N6fmRBNt16/HlYKM0xCqMh3sG0ZEgbHYhAUwQDC11 s7KA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=FbQf2cPMJ6YImQV1+hw0Op2lVZ36B/VbRboWjVjmjAI=; fh=dFDpqKUIk5e4jJnU8vTV6qs+Qflv6j/ZkUgZdBt3wxc=; b=G18w0XFhmo/xBoy3vcaldv7jsnEtQthXXRCmLCeT70tTBtXBoi7vxvJZ5IlhQeywD+ BLKkC761WRkHFYlhVULJStMuDLZyVe7GlQbwlhpD4tIkyDKr0L8rUkAsSCpDHJjRkUny fcPM4Ue2l3p1MHmJZA/4XbEZEDo8/wiQj7FosMyHNFTaFfa6rffJEIXMV03zG8+9pxqR /MJK19OVFoi+kibxcTG3Xv/ROD+FcdrEtv299IRX1dSnQvA6M0t6xyRWpv+1EdxdngIV GTYpsDmHONfF/xH4T8pnmevkhOG+3wmz2x+fqDhHtzBvCnQHboV103COthtN0IctFT5e E9Cw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BDHQ1k4g; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 25 Feb 2025 10:46:31 -0800 (PST) Received: from draig.lan ([185.126.160.109]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b02d854csm149295355e9.15.2025.02.25.10.46.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2025 10:46:29 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id C83175FA34; Tue, 25 Feb 2025 18:46:28 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Igor Mammedov , Richard Henderson , Helge Deller , Paolo Bonzini , Nicholas Piggin , qemu-ppc@nongnu.org, Zhao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 4/4] tcg:tlb: use tcg_debug_assert() in assert_cpu_is_self() Date: Tue, 25 Feb 2025 18:46:28 +0000 Message-Id: <20250225184628.3590671-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250225184628.3590671-1-alex.bennee@linaro.org> References: <20250225184628.3590671-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Igor Mammedov that will enable assert_cpu_is_self when QEMU is configured with --enable-debug without need for manual patching DEBUG_TLB_GATE define. Need to manually path DEBUG_TLB_GATE define to enable assert, let regression caused by [1] creep in unnoticed. 1) 30933c4fb4f3d ("tcg/cputlb: remove other-cpu capability from TLB flushing") Signed-off-by: Igor Mammedov Suggested-by: Alex Bennée Message-Id: <20250207162048.1890669-5-imammedo@redhat.com> Signed-off-by: Alex Bennée --- accel/tcg/cputlb.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index fc16a576f0..65b04b1055 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -73,11 +73,8 @@ } \ } while (0) -#define assert_cpu_is_self(cpu) do { \ - if (DEBUG_TLB_GATE) { \ - g_assert(!(cpu)->created || qemu_cpu_is_self(cpu)); \ - } \ - } while (0) +#define assert_cpu_is_self(cpu) \ + tcg_debug_assert(!(cpu)->created || qemu_cpu_is_self(cpu)) /* run_on_cpu_data.target_ptr should always be big enough for a * vaddr even on 32 bit builds