From patchwork Sun Feb 23 12:22:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivaylo Ivanov X-Patchwork-Id: 867657 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D44C20409D; Sun, 23 Feb 2025 12:22:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740313356; cv=none; b=olemZkrAgqjYhZJJa1tTbfwOa28l2qjSJKaYkB2dDIIcVCfP7RQNxWIXdRR6YU0y665bAMdSqNDvjL6Tzx8Pbl6gC1rCokkZljSyb9pWw/R8PJ482LqTf2axAzUslzfAXE+dKOYXUdax17gwzRtI6BXeewlFTG4iRAmhw6Sd05o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740313356; c=relaxed/simple; bh=5kv+oUncvcmPyEDFirc9RwH6p4wXr6C2jOa6K8b8JPU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JvrwGn5/BozIM9LA7+8Zt6qO/AMP1Wi7EJ7+sjlMAZtepFC6E4laY8El9/+SJQmk+DYaICcLXgguLTKtPF7yBtD5dahug2+wB3L1IRAgH+/v0EoY4BM0Y9NTR3bNg4sKZYdkrKxUW3F0Or9i2HS08ngdyZ8pT+czQ7ra4lNbT34= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=SsJwR32R; arc=none smtp.client-ip=209.85.221.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SsJwR32R" Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-38f406e9f80so3293854f8f.2; Sun, 23 Feb 2025 04:22:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740313353; x=1740918153; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Imu1A98L2KP46AIXwK/kKuPHdfCAq0a74bOMQZLOfVI=; b=SsJwR32RnnO67tpWIQ0lJzdxCVs8QiECH/mnDhGDZjUb3Y9W7t0uJ9jvMYlExMy82Y +ekHC6pwoXTa39AfgofKE8c+hKQx5CC5uflrvARndayqn4bqlthOmF/rPc26y6r1m6gC 5vzpGv0YETqaR7WM7YBarxBOp92Z+TUD+KfjuMsVGxbygFXw9P1PZdQfcfoNEUP/m0Xh m7Pw2qdh8RmLoWJXF4Ftx2mpSZrEGieDuKQVinCjRMb3iVTFREqBnz8J2gZaGJhrXUJe Az0564SEzlr5fPiKLzAlK1tkGJ1ou+6g4R4O0bAO4nY+sfOQZyZSls/xfguC5dOuqVva 4xKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740313353; x=1740918153; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Imu1A98L2KP46AIXwK/kKuPHdfCAq0a74bOMQZLOfVI=; b=pMytzEXdk4UmV3maX6e3xfkKiTenlsp2P371NtiDaE7UfXiZOf+CTssHgenEySYnmq YGIHeIYBHqKeGNSeNJcGUDGWaCLX6AbOgvCi8ygFQ2erDUwz3Vk3o4PUtQeYs5qvYcNB TxQunzgC6adJSdgPxd2xsT7TGIDvM/LP1shTrWBYtEBx3pM7/HThgEEdkguOvR41NWVS rOu5zTtNuvIP73c50H4KlYlXnzy1gH7aUCIVk6hD1q70RjntSZ58L3/EER0heamB/kQt qvUpM6XY6OH5Br4TmZ5cKfWiOfseKq4oEBBvDme+tpcTF07moSeWwcGZH4l4eWs6T78E qN6w== X-Forwarded-Encrypted: i=1; AJvYcCVzNwXSLpfc/TDQ0yYKXRyDu/5q+9w3Ie18Nf9sK3ch+Gzb1j2RPf079d30UrnqH/odjKp5NMFK9vre7+N8iYOhon8=@vger.kernel.org, AJvYcCWG82i923arM838q7Qr1+0Ja+9NwzyhsAQVF4bzCIowYIPP9IExDI3dIK0avZAWCBoEIrAEpNS9VcROs5Tv@vger.kernel.org, AJvYcCXzUlxA4Yq89VC8Eu1nd3LI+iFZWzEljSGb/mV6Q2VvLBSyAUYhIpLubGXcZ8on83jDwVGbnBcNTdgG@vger.kernel.org X-Gm-Message-State: AOJu0YyHWYdmGhjeefLgyaDFQreSAEqpDQ5xTdbbT53Bud5D2DSAnn+/ KWeHlpgSyAtjoDgZhn9wF0agfshCL+90KSZ0nQolnyegAdiBIUYV X-Gm-Gg: ASbGncu8Xv9yvUPP9DK//2ZK2aklgdlchfZy3D30J7d8tjQgqFfJ9yZ8UgzJlWxxKMS kTQwplNcm6P4eLJpHloJLKbzxUGHTkCR/xzFElOSv0jJ7lq4HMOWKidWJukHOkUYWdTMRTLKYwH cSCeAmb7LUkzDGCZ1OGRO1GilYZkuvzAAgrOI+ExG5Ru9TNj3qA3Lp0g2mBpgYsenW1bNNchdwA BuTKmpVKR0HHesNlcNpWlYeOxDgimijBFRbb+2ZO8/u5wu3A62NxHCzGrAeYV97QOLvcnLn9QWd 5UR4xIhDYF0nCla8wMM4jA0XwsMo1LvtwqYJOYRp/kNeCBcNFovmjaFZnS3OhPZnWFiHtjiF46x jig== X-Google-Smtp-Source: AGHT+IHaUz0XhpP9SWkDpIHgSlmiijMV4PEbmK8V+w/DLEX2GzBOqorv8lkEfT706XJetrp/boI5lQ== X-Received: by 2002:a5d:5888:0:b0:38f:2efb:b829 with SMTP id ffacd0b85a97d-38f6f0d1d04mr7837154f8f.50.1740313351723; Sun, 23 Feb 2025 04:22:31 -0800 (PST) Received: from ivaylo-T580.. (91-139-201-119.stz.ddns.bulsat.com. [91.139.201.119]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f259f8602sm29611608f8f.94.2025.02.23.04.22.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Feb 2025 04:22:31 -0800 (PST) From: Ivaylo Ivanov To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Philipp Zabel , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/8] dt-bindings: phy: rename qcom,snps-eusb2-phy binding to snps,eusb2-phy Date: Sun, 23 Feb 2025 14:22:20 +0200 Message-ID: <20250223122227.725233-2-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250223122227.725233-1-ivo.ivanov.ivanov1@gmail.com> References: <20250223122227.725233-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 As Samsung has been using the same Synopsys eUSB2 IP in Exynos2200, albeit with a different register layout, rename qcom,snps-eusb2-phy to snps,eusb2-phy and drop mentions of it being only for Qualcomm SoCs in the binding description. Signed-off-by: Ivaylo Ivanov --- .../phy/{qcom,snps-eusb2-phy.yaml => snps,eusb2-phy.yaml} | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) rename Documentation/devicetree/bindings/phy/{qcom,snps-eusb2-phy.yaml => snps,eusb2-phy.yaml} (90%) diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/snps,eusb2-phy.yaml similarity index 90% rename from Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml rename to Documentation/devicetree/bindings/phy/snps,eusb2-phy.yaml index 142b3c883..22c77968f 100644 --- a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/snps,eusb2-phy.yaml @@ -1,16 +1,16 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-phy.yaml# +$id: http://devicetree.org/schemas/phy/snps,eusb2-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm SNPS eUSB2 phy controller +title: SNPS eUSB2 phy controller maintainers: - Abel Vesa description: - eUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. + eUSB2 controller supports LS/FS/HS usb connectivity. properties: compatible: From patchwork Sun Feb 23 12:22:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivaylo Ivanov X-Patchwork-Id: 867656 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CFC3206F16; Sun, 23 Feb 2025 12:22:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740313358; cv=none; b=lO9FrYKlho+38kesm+3rkNe8QvdPb8W+w+O+s7n1ZILdn1JGe2wtZyUHEv+sFJOuL4AZ8OtDT8c3ra0uSMYsZaCjAlxTbRcE0pDe4Q8Gn5o5qiPA3atmdj+BVn/dHAaF5yKjQ/a+9pbHTS0s5+sM0p7uVLrweZd67CNMmeXVRzU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740313358; c=relaxed/simple; bh=XpX6AEIeWqhI9NarS2+Jte5eYMQsoExH2SeFYA9z3jE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IRCwsO7xKnqTjle7yqtbE84nGPN0k7AkhgHGz+PbQib4w+Xr82bietvqdWZ5ePVbCPQXN2De2mLuLJ+6/qAIZkjyubh4eQOgMoErCVFjfBrVWJ6ikGX0dkr6h8seodIrWNqFWbMcVdWtWd72AZq6omGR0AXwRKjYYQwyoxA4yq0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=MrAxln4M; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MrAxln4M" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-38f2f391864so1944281f8f.3; Sun, 23 Feb 2025 04:22:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740313355; x=1740918155; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2TbGBzUDvgVe7DZmZtqsqC9SxMmEhDsYTwwUDb5o6oI=; b=MrAxln4MXNbdGhNpgPL8jvBczJx1Z1SsEuCcKbJ9ieZ6p4iC05ME9UcLlBEp830pOn UlG5M0pEgrRxiRhXBGSyLtZ+W7cqN+c9JWr5p2QpMoQf8xEf9BiLn95OZNN/azF61U31 OqzqUKD1+wGODZiwd2Z49AiuwS9s8zSnmZB99ivebpJlkZnMCFSfMvd4k11vkfv1mV05 ymBogDQwBoUa7XkWUeJOtwLZzKWrhM2+6iAJLnskVYvHfMFDJZb5Xffzy6sp1lbWvB3z Yf+U/7F6hqQTajLNtxGSjNE1Lqx7Rl6C/CxCki2FlJTUPSsVxGu8LuFPAch7DEM/5JuE Tgjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740313355; x=1740918155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2TbGBzUDvgVe7DZmZtqsqC9SxMmEhDsYTwwUDb5o6oI=; b=bosSQ6yxmI14csIJ8rCfxA6c7zKZ5Afvl0JMmG0okmlur4xJLujiEznzyDNj1QDMoe VIMK0KEhudNx9qrf6Z5L1Y4JPu8Xk3/Dk79YZ4FaP321xHtVn3Igg/+UJUXHXqKzSW8n DXcPhxAgp1Vuz59iFmOVsVcx52pLyRYDvjver2CihQOUWfvQ00bYtR+6lKgEPM8xE0dN 3Z3d3uvFICPX/8VyLqFGmy6BK87Pn6ZpWD+7NkL5rPtt9RAQbJp1MjBKwVtaco6ZbPgc 34N/ddOJJSZSwIs5robEnmqwbL3GiREY262iNpT09gvXtF+RdE769NyzrAk1sIfaZuGT mW8A== X-Forwarded-Encrypted: i=1; AJvYcCUEmQEGs04FTmEt61fmugK3OGU8/y0S2kYpHG4x/OfMh+iCTnKD//Dnd1ty8iTqStiER+wJCYdV/zEXMCpkQMGvLQQ=@vger.kernel.org, AJvYcCVXjQqjDHhiw8fkNur+ovw5bYhmVaOAl4t1hdLSQ9b8f6bac8ffkHt8d+7lTGm1wAxMkMaEtkrXjLzLHCts@vger.kernel.org, AJvYcCWEA1vir8NivoYVoazToDJ2ISLSvThzYKM1BIWPtpym5Lzf5Kk4O2u4tVr+hqEtE+trX56EJPuGq0lb@vger.kernel.org X-Gm-Message-State: AOJu0YxtmpH6FwO114P5Bq2efcRb7wTHtS89pQwYbW9hwVb+x9qS6Zqx JIRWecvCAYZySrIDmyGX4Ca3zoQQYFGZiBfDtYjNJ2ePJC/yWlTK X-Gm-Gg: ASbGncveL/o9dM+9Dnrt8Te4o752agwLJE7ndJmYpGpjaha6h7Bx/q5iiv0kSw34ORw wZU7ZvyQ77D08N9BK0lcXsNoEC3Q44DJIcCK9N561QNJMmyyGmqsBp2Ow/gDnZHRQIHZDXTjzSH r7diuefyvTQjpOUF9+D/nfeQ5vqcBJvm9yaoRlSGxgS3fdytbEbDiHS9J9jzodplAIfAe0WVs3M 5s17ztCx0AApgjqtDW4+paKn2qLIQFM6lzjTzBs2QKKVHYE4cLOnRICkpUXtq4k0eWnFaI89nj5 5kL4RZEbXPzOGYFxw0+bbAyi8Kzzl0ycd0TDh5mxyS94NfFAQsellUHsr+/KRAiCU0tqK7Z1JK7 Nqw== X-Google-Smtp-Source: AGHT+IFMMFEPDMQAE9igHIO1s4NQHd7QMje6bLzkA+Bu0OEI2dPAuclKIJlYvuVA53CK1jDPbgzvtA== X-Received: by 2002:a5d:584b:0:b0:38f:3b41:c952 with SMTP id ffacd0b85a97d-38f6e754b82mr7082161f8f.4.1740313354607; Sun, 23 Feb 2025 04:22:34 -0800 (PST) Received: from ivaylo-T580.. (91-139-201-119.stz.ddns.bulsat.com. [91.139.201.119]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f259f8602sm29611608f8f.94.2025.02.23.04.22.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Feb 2025 04:22:34 -0800 (PST) From: Ivaylo Ivanov To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Philipp Zabel , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/8] dt-bindings: phy: add samsung,exynos2200-usbcon-phy schema file Date: Sun, 23 Feb 2025 14:22:22 +0200 Message-ID: <20250223122227.725233-4-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250223122227.725233-1-ivo.ivanov.ivanov1@gmail.com> References: <20250223122227.725233-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Exynos2200 SoC has a USB controller PHY, which acts as an intermediary between a USB controller (typically DWC3) and other PHYs (UTMI, PIPE3). Add a dt-binding schema for it. Signed-off-by: Ivaylo Ivanov --- .../phy/samsung,exynos2200-usbcon-phy.yaml | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml new file mode 100644 index 000000000..7d879ec8b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/samsung,exynos2200-usbcon-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Exynos2200 USB controller PHY + +maintainers: + - Ivaylo Ivanov + +description: + Exynos2200 USB controller PHY is an intermediary between a USB controller + (typically DWC3) and other PHYs (UTMI, PIPE3). + +properties: + compatible: + enum: + - samsung,exynos2200-usbcon-phy + + reg: + maxItems: 1 + + clocks: + items: + - description: bus clock + + clock-names: + items: + - const: bus + + "#phy-cells": + const: 0 + + phys: + maxItems: 1 + description: + Phandle to eUSB2 PHY + + samsung,pmu-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + items: + minItems: 1 + items: + - description: phandle for PMU system controller interface, used to + control PMU registers bits for USBCON PHY + - description: offset of the pmu control register + description: + Should be phandle/offset pair. The phandle to System Register syscon node + and the offset for USBCON PHY. + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + - phys + - samsung,pmu-syscon + +additionalProperties: false + +examples: + - | + #include + + usb_con_phy: phy@10aa0000 { + compatible = "samsung,exynos2200-usbcon-phy"; + reg = <0x10aa0000 0x10000>; + clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>; + clock-names = "bus"; + #phy-cells = <0>; + phys = <&usb_hs_phy>; + samsung,pmu-syscon = <&pmu_system_controller 0x72c>; + }; From patchwork Sun Feb 23 12:22:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivaylo Ivanov X-Patchwork-Id: 867655 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22944207A20; Sun, 23 Feb 2025 12:22:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740313361; cv=none; b=X0OzkP55TH0pMwOmra4w8BzRCrE2j4QdF7JQXmoIK3AmXpIwdUN85zFjmmAt7CjmMpKShMWLU1/MP9sL1punR+pL5a+dWf3EJ4xvrlLBuXDXxrnaQctVTmpVHocdtsi/w9gg++5jnSxlUZuaMeqBzC3t4d7ksf198R1U9l/FHh0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740313361; c=relaxed/simple; bh=n9eA+aTBOKbIOiv4MRI4KMJsBryhl6JUd30Cu6T5CRg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oCOEmzWL99jbRAsZoVmqRsmhrk8L/Dxzhs8d3LxpFmRFYoTWJpPsa9x13S2L/mUK0Jm2zAAdyXwmlXV3gxXS58cmr05VON4WP1eb0mbfZnINb90W3dg1MjG7Y/rSEHECSKDgb2PalXbHXYb83SoJclfMjN6r8yCma0WB6gb6Fyg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=fLHdey8B; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fLHdey8B" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-4399a1eada3so30939715e9.2; Sun, 23 Feb 2025 04:22:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740313356; x=1740918156; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w5AqloAAA42MXmA8w7bAhHKGWmPLv+VF0Ofk4tbyqKU=; b=fLHdey8BwXwirtI+GGvQbNJix2eFYhimaIL41J7Z+OnUANBvUhNQjwSjwotECEO/qQ nWIkiK3GGM8zfyE6I9joCEiiRthU1LCn8myS3mf/e7iSOsmCTXbdlVT1aqBm8dNYqsGs O1XtaFJFzqQ5CtwGnw3VmAnFlLX+5qER9YXj4+jAihzouNQ6Sc9wge28XIvTXUtBqZh0 2R8Ch+YUzwz1L4wCjmrgVJql8Ta1YTeSC1WvXNxXWn4CEri9seo7LTu6o0wZbTfCFtJS ul4DSSYvREIV6CBeoKYvukSdJk4HA47M4L8VHifE1Gt7iF4o4vKmCOqL0/4Adnz0VztI yQww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740313356; x=1740918156; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w5AqloAAA42MXmA8w7bAhHKGWmPLv+VF0Ofk4tbyqKU=; b=oLnrI3SypvTJEcDG/TStNDBZFpDzFh/7bl1fRoC4NS9cIU13KiDcW2qPLUxDZtuOlO b1WlbFgOI4jKs1F5n7sntsWdgFCQh2j8GANbVx7QjoFQgnF1PlGD5QE2FoMkAPuuaew9 cx43H02RH/IAaaUGm9rYG/Iz5GU0u5IPFEaanBGBg08NfkNwOAI8kksuBdg2KAs/adwH AtEn9lnP3HfqPM0PSi69ZUDEDLcqZMOuTpBYlUbpE8iSxAAcoVd7k+3ZpFNfpDKH4F+4 3udMMnrjoKwrUgazFpxAxOP5MlZpEyV2GTGXBUnNcUsvNRqfbPhuMrEgfNJv1g2FHL3C YntQ== X-Forwarded-Encrypted: i=1; AJvYcCUwX5CkNxWZ4Iohx7NDa1L3TN5Pomjz2n1eeE1Vi+g3LUIrpohIxstGtIYd2BsGNThx67OBzfiGSX7qETR5BzN0q8U=@vger.kernel.org, AJvYcCVJWvpLCGmO/w7i0sJKXsjvJFH0AtY0Kh1JtYtlluuBnrC95n+wDaIjbpOtQ/H3lHjW4mEziLLaYm0I@vger.kernel.org, AJvYcCWd8y09nFJIKWvQnN20ZI7SWAM19+CWdQ6u0yp94bBGtVCvjOzlSFbQIMyIv3yYmsotH2rRaIOnY/+EKV2r@vger.kernel.org X-Gm-Message-State: AOJu0YzX7E9qW1EvjjisFoGUyOf02DwnChb3BylYpsoI0pyhpsvb6tme 6oOP9kOQLeikCcO5Pj4E4e+2IDEXwIX3uh3T4u2dz10LXVYKbfAm X-Gm-Gg: ASbGncu1MmNtmLsSap05n0fsCVSaTaPId0J07d5ALAXPO6orqEiLH2/d49AYua6+jAa abG6NpMFH1ojfHsH2xv5vA+c/e97iKmRk56VpjNbFHyt4Yxlsgjc9u+LZhuze+hAiZPz6UAv3hf KEkBKfRr2oTMD0AWb4muVB9eq7fm7MjQyWpEuGzQxqPvSuLqDkp5iwK4qDvBX0bYjasdeIoNFU+ PBbkvvTwgwJdunsze9kx4TVuk3Koqg0OLifgF/DWIlr1ED982/KzopeH8BK+yEicJvLzz5pnrxH 39GALB13CFlswsK8idKc6hqq74xRSvbaMkGDU2vfEOuBrmWi9MGZywHv1UsBX++xNkAi1sNfFHX xUQ== X-Google-Smtp-Source: AGHT+IHqP76iHfiYngmm0o31mQ9yL26b7/JkdUj5J77MLt+JVK4hCOloOw0no10cd3jakQMTipP2eA== X-Received: by 2002:a05:6000:184f:b0:38d:dffc:c144 with SMTP id ffacd0b85a97d-38f6f0c8e74mr7319751f8f.55.1740313356080; Sun, 23 Feb 2025 04:22:36 -0800 (PST) Received: from ivaylo-T580.. (91-139-201-119.stz.ddns.bulsat.com. [91.139.201.119]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f259f8602sm29611608f8f.94.2025.02.23.04.22.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Feb 2025 04:22:35 -0800 (PST) From: Ivaylo Ivanov To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Philipp Zabel , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/8] phy: move phy-qcom-snps-eusb2 out of its vendor sub-directory Date: Sun, 23 Feb 2025 14:22:23 +0200 Message-ID: <20250223122227.725233-5-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250223122227.725233-1-ivo.ivanov.ivanov1@gmail.com> References: <20250223122227.725233-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 As Samsung is using the same Synopsys eUSB2 IP in Exynos2200, albeit with a different register layout, it only makes sense to implement support for that in the existing eUSB2 driver. To make room for new non-qcom SoCs, do the following: 1. Move phy-qcom-snps-eusb2.c to phy-snps-eusb2.c 2. Rename all qcom_snps_eusb2 functions and structs to snps_eusb2_phy 3. Add a prefix to the qcom-specific register offset definitions 4. Make a generic phy_ops init that sets up power before the SoC-specific eUSB2 IP init 5. Introduce a driver data structure with init function and clocks Signed-off-by: Ivaylo Ivanov Suggested-by: Krzysztof Kozlowski --- drivers/phy/Kconfig | 8 + drivers/phy/Makefile | 1 + drivers/phy/phy-snps-eusb2.c | 505 +++++++++++++++++++++ drivers/phy/qualcomm/Kconfig | 9 - drivers/phy/qualcomm/Makefile | 1 - drivers/phy/qualcomm/phy-qcom-snps-eusb2.c | 442 ------------------ 6 files changed, 514 insertions(+), 452 deletions(-) create mode 100644 drivers/phy/phy-snps-eusb2.c delete mode 100644 drivers/phy/qualcomm/phy-qcom-snps-eusb2.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 8d58efe99..11c166204 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -43,6 +43,14 @@ config PHY_PISTACHIO_USB help Enable this to support the USB2.0 PHY on the IMG Pistachio SoC. +config PHY_SNPS_EUSB2 + tristate "SNPS eUSB2 PHY Driver" + depends on OF && (ARCH_QCOM || COMPILE_TEST) + select GENERIC_PHY + help + Enable support for the USB high-speed SNPS eUSB2 phy on select + SoCs. The PHY is usually paired with a Synopsys DWC3 USB controller. + config PHY_XGENE tristate "APM X-Gene 15Gbps PHY support" depends on HAS_IOMEM && OF && (ARCH_XGENE || COMPILE_TEST) diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index e281442ac..c670a8dac 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o obj-$(CONFIG_PHY_XGENE) += phy-xgene.o obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o +obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o diff --git a/drivers/phy/phy-snps-eusb2.c b/drivers/phy/phy-snps-eusb2.c new file mode 100644 index 000000000..4e5914a76 --- /dev/null +++ b/drivers/phy/phy-snps-eusb2.c @@ -0,0 +1,505 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define QCOM_USB_PHY_UTMI_CTRL0 (0x3c) +#define SLEEPM BIT(0) +#define OPMODE_MASK GENMASK(4, 3) +#define OPMODE_NONDRIVING BIT(3) + +#define QCOM_USB_PHY_UTMI_CTRL5 (0x50) +#define POR BIT(1) + +#define QCOM_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) +#define PHY_ENABLE BIT(0) +#define SIDDQ_SEL BIT(1) +#define SIDDQ BIT(2) +#define RETENABLEN BIT(3) +#define FSEL_MASK GENMASK(6, 4) +#define FSEL_19_2_MHZ_VAL (0x0) +#define FSEL_38_4_MHZ_VAL (0x4) + +#define QCOM_USB_PHY_CFG_CTRL_1 (0x58) +#define PHY_CFG_PLL_CPBIAS_CNTRL_MASK GENMASK(7, 1) + +#define QCOM_USB_PHY_CFG_CTRL_2 (0x5c) +#define PHY_CFG_PLL_FB_DIV_7_0_MASK GENMASK(7, 0) +#define DIV_7_0_19_2_MHZ_VAL (0x90) +#define DIV_7_0_38_4_MHZ_VAL (0xc8) + +#define QCOM_USB_PHY_CFG_CTRL_3 (0x60) +#define PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(3, 0) +#define DIV_11_8_19_2_MHZ_VAL (0x1) +#define DIV_11_8_38_4_MHZ_VAL (0x0) + +#define PHY_CFG_PLL_REF_DIV GENMASK(7, 4) +#define PLL_REF_DIV_VAL (0x0) + +#define QCOM_USB_PHY_HS_PHY_CTRL2 (0x64) +#define VBUSVLDEXT0 BIT(0) +#define USB2_SUSPEND_N BIT(2) +#define USB2_SUSPEND_N_SEL BIT(3) +#define VBUS_DET_EXT_SEL BIT(4) + +#define QCOM_USB_PHY_CFG_CTRL_4 (0x68) +#define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0) +#define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2) + +#define QCOM_USB_PHY_CFG_CTRL_5 (0x6c) +#define PHY_CFG_PLL_PROP_CNTRL_MASK GENMASK(4, 0) +#define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6) + +#define QCOM_USB_PHY_CFG_CTRL_6 (0x70) +#define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0) + +#define QCOM_USB_PHY_CFG_CTRL_7 (0x74) + +#define QCOM_USB_PHY_CFG_CTRL_8 (0x78) +#define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0) +#define PHY_CFG_TX_FSLS_VREG_BYPASS BIT(2) +#define PHY_CFG_TX_HS_VREF_TUNE_MASK GENMASK(5, 3) +#define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6) + +#define QCOM_USB_PHY_CFG_CTRL_9 (0x7c) +#define PHY_CFG_TX_PREEMP_TUNE_MASK GENMASK(2, 0) +#define PHY_CFG_TX_RES_TUNE_MASK GENMASK(4, 3) +#define PHY_CFG_TX_RISE_TUNE_MASK GENMASK(6, 5) +#define PHY_CFG_RCAL_BYPASS BIT(7) + +#define QCOM_USB_PHY_CFG_CTRL_10 (0x80) + +#define QCOM_USB_PHY_CFG0 (0x94) +#define DATAPATH_CTRL_OVERRIDE_EN BIT(0) +#define CMN_CTRL_OVERRIDE_EN BIT(1) + +#define QCOM_UTMI_PHY_CMN_CTRL0 (0x98) +#define TESTBURNIN BIT(6) + +#define QCOM_USB_PHY_FSEL_SEL (0xb8) +#define FSEL_SEL BIT(0) + +#define QCOM_USB_PHY_APB_ACCESS_CMD (0x130) +#define RW_ACCESS BIT(0) +#define APB_START_CMD BIT(1) +#define APB_LOGIC_RESET BIT(2) + +#define QCOM_USB_PHY_APB_ACCESS_STATUS (0x134) +#define ACCESS_DONE BIT(0) +#define TIMED_OUT BIT(1) +#define ACCESS_ERROR BIT(2) +#define ACCESS_IN_PROGRESS BIT(3) + +#define QCOM_USB_PHY_APB_ADDRESS (0x138) +#define APB_REG_ADDR_MASK GENMASK(7, 0) + +#define QCOM_USB_PHY_APB_WRDATA_LSB (0x13c) +#define APB_REG_WRDATA_7_0_MASK GENMASK(3, 0) + +#define QCOM_USB_PHY_APB_WRDATA_MSB (0x140) +#define APB_REG_WRDATA_15_8_MASK GENMASK(7, 4) + +#define QCOM_USB_PHY_APB_RDDATA_LSB (0x144) +#define APB_REG_RDDATA_7_0_MASK GENMASK(3, 0) + +#define QCOM_USB_PHY_APB_RDDATA_MSB (0x148) +#define APB_REG_RDDATA_15_8_MASK GENMASK(7, 4) + +static const char * const eusb2_hsphy_vreg_names[] = { + "vdd", "vdda12", +}; + +#define EUSB2_NUM_VREGS ARRAY_SIZE(eusb2_hsphy_vreg_names) + +struct snps_eusb2_phy_drvdata { + int (*phy_init)(struct phy *p); + const char * const *clk_names; + int num_clks; +}; + +struct snps_eusb2_hsphy { + struct phy *phy; + void __iomem *base; + + struct clk *ref_clk; + struct clk_bulk_data *clks; + + struct reset_control *phy_reset; + + struct regulator_bulk_data vregs[EUSB2_NUM_VREGS]; + + enum phy_mode mode; + + struct phy *repeater; + + const struct snps_eusb2_phy_drvdata *data; +}; + +static int snps_eusb2_hsphy_set_mode(struct phy *p, enum phy_mode mode, int submode) +{ + struct snps_eusb2_hsphy *phy = phy_get_drvdata(p); + + phy->mode = mode; + + return phy_set_mode_ext(phy->repeater, mode, submode); +} + +static void snps_eusb2_hsphy_write_mask(void __iomem *base, u32 offset, + u32 mask, u32 val) +{ + u32 reg; + + reg = readl_relaxed(base + offset); + reg &= ~mask; + reg |= val & mask; + writel_relaxed(reg, base + offset); + + /* Ensure above write is completed */ + readl_relaxed(base + offset); +} + +static void qcom_eusb2_default_parameters(struct snps_eusb2_hsphy *phy) +{ + /* default parameters: tx pre-emphasis */ + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_9, + PHY_CFG_TX_PREEMP_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0)); + + /* tx rise/fall time */ + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_9, + PHY_CFG_TX_RISE_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_RISE_TUNE_MASK, 0x2)); + + /* source impedance adjustment */ + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_9, + PHY_CFG_TX_RES_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_RES_TUNE_MASK, 0x1)); + + /* dc voltage level adjustement */ + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_8, + PHY_CFG_TX_HS_VREF_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_HS_VREF_TUNE_MASK, 0x3)); + + /* transmitter HS crossover adjustement */ + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_8, + PHY_CFG_TX_HS_XV_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0)); +} + +static int qcom_eusb2_ref_clk_init(struct snps_eusb2_hsphy *phy) +{ + unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); + + switch (ref_clk_freq) { + case 19200000: + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_HS_PHY_CTRL_COMMON0, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_2, + PHY_CFG_PLL_FB_DIV_7_0_MASK, + DIV_7_0_19_2_MHZ_VAL); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_3, + PHY_CFG_PLL_FB_DIV_11_8_MASK, + DIV_11_8_19_2_MHZ_VAL); + break; + + case 38400000: + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_HS_PHY_CTRL_COMMON0, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_38_4_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_2, + PHY_CFG_PLL_FB_DIV_7_0_MASK, + DIV_7_0_38_4_MHZ_VAL); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_3, + PHY_CFG_PLL_FB_DIV_11_8_MASK, + DIV_11_8_38_4_MHZ_VAL); + break; + + default: + dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq); + return -EINVAL; + } + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_3, + PHY_CFG_PLL_REF_DIV, PLL_REF_DIV_VAL); + + return 0; +} + +static int qcom_snps_eusb2_hsphy_init(struct phy *p) +{ + struct snps_eusb2_hsphy *phy = phy_get_drvdata(p); + int ret; + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG0, + CMN_CTRL_OVERRIDE_EN, CMN_CTRL_OVERRIDE_EN); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_UTMI_CTRL5, POR, POR); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_HS_PHY_CTRL_COMMON0, + PHY_ENABLE | RETENABLEN, PHY_ENABLE | RETENABLEN); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_APB_ACCESS_CMD, + APB_LOGIC_RESET, APB_LOGIC_RESET); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_UTMI_PHY_CMN_CTRL0, TESTBURNIN, 0); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_FSEL_SEL, + FSEL_SEL, FSEL_SEL); + + /* update ref_clk related registers */ + ret = qcom_eusb2_ref_clk_init(phy); + if (ret) + return ret; + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_1, + PHY_CFG_PLL_CPBIAS_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x1)); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_4, + PHY_CFG_PLL_INT_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_INT_CNTRL_MASK, 0x8)); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_4, + PHY_CFG_PLL_GMP_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_GMP_CNTRL_MASK, 0x1)); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_5, + PHY_CFG_PLL_PROP_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_PROP_CNTRL_MASK, 0x10)); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_6, + PHY_CFG_PLL_VCO_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_VCO_CNTRL_MASK, 0x0)); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_5, + PHY_CFG_PLL_VREF_TUNE_MASK, + FIELD_PREP(PHY_CFG_PLL_VREF_TUNE_MASK, 0x1)); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_HS_PHY_CTRL2, + VBUS_DET_EXT_SEL, VBUS_DET_EXT_SEL); + + /* set default parameters */ + qcom_eusb2_default_parameters(phy); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_HS_PHY_CTRL_COMMON0, + SIDDQ_SEL, SIDDQ_SEL); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_HS_PHY_CTRL_COMMON0, + SIDDQ, 0); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_UTMI_CTRL5, POR, 0); + + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL, 0); + + return 0; +} + +static const char * const qcom_eusb2_hsphy_clock_names[] = { + "ref", +}; + +static const struct snps_eusb2_phy_drvdata sm8550_snps_eusb2_phy = { + .phy_init = qcom_snps_eusb2_hsphy_init, + .clk_names = qcom_eusb2_hsphy_clock_names, + .num_clks = ARRAY_SIZE(qcom_eusb2_hsphy_clock_names), +}; + +static int snps_eusb2_hsphy_init(struct phy *p) +{ + struct snps_eusb2_hsphy *phy = phy_get_drvdata(p); + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(phy->vregs), phy->vregs); + if (ret) + return ret; + + ret = phy_init(phy->repeater); + if (ret) { + dev_err(&p->dev, "repeater init failed. %d\n", ret); + goto disable_vreg; + } + + ret = clk_prepare_enable(phy->ref_clk); + if (ret) { + dev_err(&p->dev, "failed to enable ref clock, %d\n", ret); + goto disable_vreg; + } + + ret = reset_control_assert(phy->phy_reset); + if (ret) { + dev_err(&p->dev, "failed to assert phy_reset, %d\n", ret); + goto disable_ref_clk; + } + + usleep_range(100, 150); + + ret = reset_control_deassert(phy->phy_reset); + if (ret) { + dev_err(&p->dev, "failed to de-assert phy_reset, %d\n", ret); + goto disable_ref_clk; + } + + ret = phy->data->phy_init(p); + if (ret) + goto disable_ref_clk; + + return 0; + +disable_ref_clk: + clk_disable_unprepare(phy->ref_clk); + +disable_vreg: + regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs); + + return ret; +} + +static int snps_eusb2_hsphy_exit(struct phy *p) +{ + struct snps_eusb2_hsphy *phy = phy_get_drvdata(p); + + clk_disable_unprepare(phy->ref_clk); + + regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs); + + phy_exit(phy->repeater); + + return 0; +} + +static const struct phy_ops snps_eusb2_hsphy_ops = { + .init = snps_eusb2_hsphy_init, + .exit = snps_eusb2_hsphy_exit, + .set_mode = snps_eusb2_hsphy_set_mode, + .owner = THIS_MODULE, +}; + +static int snps_eusb2_hsphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct snps_eusb2_hsphy *phy; + struct phy_provider *phy_provider; + struct phy *generic_phy; + const struct snps_eusb2_phy_drvdata *drv_data; + int ret, i; + int num; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + drv_data = of_device_get_match_data(dev); + if (!drv_data) + return -EINVAL; + phy->data = drv_data; + + phy->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(phy->base)) + return PTR_ERR(phy->base); + + phy->phy_reset = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(phy->phy_reset)) + return PTR_ERR(phy->phy_reset); + + phy->clks = devm_kcalloc(dev, + phy->data->num_clks, + sizeof(*phy->clks), + GFP_KERNEL); + if (!phy->clks) + return -ENOMEM; + + for (int i = 0; i < phy->data->num_clks; ++i) + phy->clks[i].id = phy->data->clk_names[i]; + + ret = devm_clk_bulk_get(dev, phy->data->num_clks, + phy->clks); + if (ret) + return dev_err_probe(dev, ret, + "failed to get phy clock(s)\n"); + + phy->ref_clk = NULL; + for (int i = 0; i < phy->data->num_clks; ++i) { + if (!strcmp(phy->clks[i].id, "ref")) { + phy->ref_clk = phy->clks[i].clk; + break; + } + } + + if (IS_ERR_OR_NULL(phy->ref_clk)) + return dev_err_probe(dev, PTR_ERR(phy->ref_clk), + "failed to get ref clk\n"); + + num = ARRAY_SIZE(phy->vregs); + for (i = 0; i < num; i++) + phy->vregs[i].supply = eusb2_hsphy_vreg_names[i]; + + ret = devm_regulator_bulk_get(dev, num, phy->vregs); + if (ret) + return dev_err_probe(dev, ret, + "failed to get regulator supplies\n"); + + phy->repeater = devm_of_phy_get_by_index(dev, np, 0); + if (IS_ERR(phy->repeater)) + return dev_err_probe(dev, PTR_ERR(phy->repeater), + "failed to get repeater\n"); + + generic_phy = devm_phy_create(dev, NULL, &snps_eusb2_hsphy_ops); + if (IS_ERR(generic_phy)) { + dev_err(dev, "failed to create phy %d\n", ret); + return PTR_ERR(generic_phy); + } + + dev_set_drvdata(dev, phy); + phy_set_drvdata(generic_phy, phy); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(phy_provider)) + return PTR_ERR(phy_provider); + + dev_info(dev, "Registered Snps-eUSB2 phy\n"); + + return 0; +} + +static const struct of_device_id snps_eusb2_hsphy_of_match_table[] = { + { + .compatible = "qcom,sm8550-snps-eusb2-phy", + .data = &sm8550_snps_eusb2_phy, + }, { }, +}; +MODULE_DEVICE_TABLE(of, snps_eusb2_hsphy_of_match_table); + +static struct platform_driver snps_eusb2_hsphy_driver = { + .probe = snps_eusb2_hsphy_probe, + .driver = { + .name = "snps-eusb2-hsphy", + .of_match_table = snps_eusb2_hsphy_of_match_table, + }, +}; + +module_platform_driver(snps_eusb2_hsphy_driver); +MODULE_DESCRIPTION("SNPS eUSB2 HS PHY driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 846f8c995..914547068 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -125,15 +125,6 @@ config PHY_QCOM_QUSB2 PHY which is usually paired with either the ChipIdea or Synopsys DWC3 USB IPs on MSM SOCs. -config PHY_QCOM_SNPS_EUSB2 - tristate "Qualcomm SNPS eUSB2 PHY Driver" - depends on OF && (ARCH_QCOM || COMPILE_TEST) - select GENERIC_PHY - help - Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm - chipsets. The PHY is paired with a Synopsys DWC3 USB controller - on Qualcomm SOCs. - config PHY_QCOM_EUSB2_REPEATER tristate "Qualcomm SNPS eUSB2 Repeater Driver" depends on OF && (ARCH_QCOM || COMPILE_TEST) diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index eb60e950a..2121e92df 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -15,7 +15,6 @@ obj-$(CONFIG_PHY_QCOM_QMP_USB) += phy-qcom-qmp-usb.o obj-$(CONFIG_PHY_QCOM_QMP_USB_LEGACY) += phy-qcom-qmp-usb-legacy.o obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o -obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o obj-$(CONFIG_PHY_QCOM_EUSB2_REPEATER) += phy-qcom-eusb2-repeater.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o diff --git a/drivers/phy/qualcomm/phy-qcom-snps-eusb2.c b/drivers/phy/qualcomm/phy-qcom-snps-eusb2.c deleted file mode 100644 index 1484691a4..000000000 --- a/drivers/phy/qualcomm/phy-qcom-snps-eusb2.c +++ /dev/null @@ -1,442 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023, Linaro Limited - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define USB_PHY_UTMI_CTRL0 (0x3c) -#define SLEEPM BIT(0) -#define OPMODE_MASK GENMASK(4, 3) -#define OPMODE_NONDRIVING BIT(3) - -#define USB_PHY_UTMI_CTRL5 (0x50) -#define POR BIT(1) - -#define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) -#define PHY_ENABLE BIT(0) -#define SIDDQ_SEL BIT(1) -#define SIDDQ BIT(2) -#define RETENABLEN BIT(3) -#define FSEL_MASK GENMASK(6, 4) -#define FSEL_19_2_MHZ_VAL (0x0) -#define FSEL_38_4_MHZ_VAL (0x4) - -#define USB_PHY_CFG_CTRL_1 (0x58) -#define PHY_CFG_PLL_CPBIAS_CNTRL_MASK GENMASK(7, 1) - -#define USB_PHY_CFG_CTRL_2 (0x5c) -#define PHY_CFG_PLL_FB_DIV_7_0_MASK GENMASK(7, 0) -#define DIV_7_0_19_2_MHZ_VAL (0x90) -#define DIV_7_0_38_4_MHZ_VAL (0xc8) - -#define USB_PHY_CFG_CTRL_3 (0x60) -#define PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(3, 0) -#define DIV_11_8_19_2_MHZ_VAL (0x1) -#define DIV_11_8_38_4_MHZ_VAL (0x0) - -#define PHY_CFG_PLL_REF_DIV GENMASK(7, 4) -#define PLL_REF_DIV_VAL (0x0) - -#define USB_PHY_HS_PHY_CTRL2 (0x64) -#define VBUSVLDEXT0 BIT(0) -#define USB2_SUSPEND_N BIT(2) -#define USB2_SUSPEND_N_SEL BIT(3) -#define VBUS_DET_EXT_SEL BIT(4) - -#define USB_PHY_CFG_CTRL_4 (0x68) -#define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0) -#define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2) - -#define USB_PHY_CFG_CTRL_5 (0x6c) -#define PHY_CFG_PLL_PROP_CNTRL_MASK GENMASK(4, 0) -#define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6) - -#define USB_PHY_CFG_CTRL_6 (0x70) -#define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0) - -#define USB_PHY_CFG_CTRL_7 (0x74) - -#define USB_PHY_CFG_CTRL_8 (0x78) -#define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0) -#define PHY_CFG_TX_FSLS_VREG_BYPASS BIT(2) -#define PHY_CFG_TX_HS_VREF_TUNE_MASK GENMASK(5, 3) -#define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6) - -#define USB_PHY_CFG_CTRL_9 (0x7c) -#define PHY_CFG_TX_PREEMP_TUNE_MASK GENMASK(2, 0) -#define PHY_CFG_TX_RES_TUNE_MASK GENMASK(4, 3) -#define PHY_CFG_TX_RISE_TUNE_MASK GENMASK(6, 5) -#define PHY_CFG_RCAL_BYPASS BIT(7) - -#define USB_PHY_CFG_CTRL_10 (0x80) - -#define USB_PHY_CFG0 (0x94) -#define DATAPATH_CTRL_OVERRIDE_EN BIT(0) -#define CMN_CTRL_OVERRIDE_EN BIT(1) - -#define UTMI_PHY_CMN_CTRL0 (0x98) -#define TESTBURNIN BIT(6) - -#define USB_PHY_FSEL_SEL (0xb8) -#define FSEL_SEL BIT(0) - -#define USB_PHY_APB_ACCESS_CMD (0x130) -#define RW_ACCESS BIT(0) -#define APB_START_CMD BIT(1) -#define APB_LOGIC_RESET BIT(2) - -#define USB_PHY_APB_ACCESS_STATUS (0x134) -#define ACCESS_DONE BIT(0) -#define TIMED_OUT BIT(1) -#define ACCESS_ERROR BIT(2) -#define ACCESS_IN_PROGRESS BIT(3) - -#define USB_PHY_APB_ADDRESS (0x138) -#define APB_REG_ADDR_MASK GENMASK(7, 0) - -#define USB_PHY_APB_WRDATA_LSB (0x13c) -#define APB_REG_WRDATA_7_0_MASK GENMASK(3, 0) - -#define USB_PHY_APB_WRDATA_MSB (0x140) -#define APB_REG_WRDATA_15_8_MASK GENMASK(7, 4) - -#define USB_PHY_APB_RDDATA_LSB (0x144) -#define APB_REG_RDDATA_7_0_MASK GENMASK(3, 0) - -#define USB_PHY_APB_RDDATA_MSB (0x148) -#define APB_REG_RDDATA_15_8_MASK GENMASK(7, 4) - -static const char * const eusb2_hsphy_vreg_names[] = { - "vdd", "vdda12", -}; - -#define EUSB2_NUM_VREGS ARRAY_SIZE(eusb2_hsphy_vreg_names) - -struct qcom_snps_eusb2_hsphy { - struct phy *phy; - void __iomem *base; - - struct clk *ref_clk; - struct reset_control *phy_reset; - - struct regulator_bulk_data vregs[EUSB2_NUM_VREGS]; - - enum phy_mode mode; - - struct phy *repeater; -}; - -static int qcom_snps_eusb2_hsphy_set_mode(struct phy *p, enum phy_mode mode, int submode) -{ - struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p); - - phy->mode = mode; - - return phy_set_mode_ext(phy->repeater, mode, submode); -} - -static void qcom_snps_eusb2_hsphy_write_mask(void __iomem *base, u32 offset, - u32 mask, u32 val) -{ - u32 reg; - - reg = readl_relaxed(base + offset); - reg &= ~mask; - reg |= val & mask; - writel_relaxed(reg, base + offset); - - /* Ensure above write is completed */ - readl_relaxed(base + offset); -} - -static void qcom_eusb2_default_parameters(struct qcom_snps_eusb2_hsphy *phy) -{ - /* default parameters: tx pre-emphasis */ - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9, - PHY_CFG_TX_PREEMP_TUNE_MASK, - FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0)); - - /* tx rise/fall time */ - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9, - PHY_CFG_TX_RISE_TUNE_MASK, - FIELD_PREP(PHY_CFG_TX_RISE_TUNE_MASK, 0x2)); - - /* source impedance adjustment */ - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9, - PHY_CFG_TX_RES_TUNE_MASK, - FIELD_PREP(PHY_CFG_TX_RES_TUNE_MASK, 0x1)); - - /* dc voltage level adjustement */ - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8, - PHY_CFG_TX_HS_VREF_TUNE_MASK, - FIELD_PREP(PHY_CFG_TX_HS_VREF_TUNE_MASK, 0x3)); - - /* transmitter HS crossover adjustement */ - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8, - PHY_CFG_TX_HS_XV_TUNE_MASK, - FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0)); -} - -static int qcom_eusb2_ref_clk_init(struct qcom_snps_eusb2_hsphy *phy) -{ - unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); - - switch (ref_clk_freq) { - case 19200000: - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, - FSEL_MASK, - FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL)); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2, - PHY_CFG_PLL_FB_DIV_7_0_MASK, - DIV_7_0_19_2_MHZ_VAL); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3, - PHY_CFG_PLL_FB_DIV_11_8_MASK, - DIV_11_8_19_2_MHZ_VAL); - break; - - case 38400000: - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, - FSEL_MASK, - FIELD_PREP(FSEL_MASK, FSEL_38_4_MHZ_VAL)); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2, - PHY_CFG_PLL_FB_DIV_7_0_MASK, - DIV_7_0_38_4_MHZ_VAL); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3, - PHY_CFG_PLL_FB_DIV_11_8_MASK, - DIV_11_8_38_4_MHZ_VAL); - break; - - default: - dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq); - return -EINVAL; - } - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3, - PHY_CFG_PLL_REF_DIV, PLL_REF_DIV_VAL); - - return 0; -} - -static int qcom_snps_eusb2_hsphy_init(struct phy *p) -{ - struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p); - int ret; - - ret = regulator_bulk_enable(ARRAY_SIZE(phy->vregs), phy->vregs); - if (ret) - return ret; - - ret = phy_init(phy->repeater); - if (ret) { - dev_err(&p->dev, "repeater init failed. %d\n", ret); - goto disable_vreg; - } - - ret = clk_prepare_enable(phy->ref_clk); - if (ret) { - dev_err(&p->dev, "failed to enable ref clock, %d\n", ret); - goto disable_vreg; - } - - ret = reset_control_assert(phy->phy_reset); - if (ret) { - dev_err(&p->dev, "failed to assert phy_reset, %d\n", ret); - goto disable_ref_clk; - } - - usleep_range(100, 150); - - ret = reset_control_deassert(phy->phy_reset); - if (ret) { - dev_err(&p->dev, "failed to de-assert phy_reset, %d\n", ret); - goto disable_ref_clk; - } - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG0, - CMN_CTRL_OVERRIDE_EN, CMN_CTRL_OVERRIDE_EN); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, POR); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, - PHY_ENABLE | RETENABLEN, PHY_ENABLE | RETENABLEN); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_APB_ACCESS_CMD, - APB_LOGIC_RESET, APB_LOGIC_RESET); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, UTMI_PHY_CMN_CTRL0, TESTBURNIN, 0); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_FSEL_SEL, - FSEL_SEL, FSEL_SEL); - - /* update ref_clk related registers */ - ret = qcom_eusb2_ref_clk_init(phy); - if (ret) - goto disable_ref_clk; - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_1, - PHY_CFG_PLL_CPBIAS_CNTRL_MASK, - FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x1)); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4, - PHY_CFG_PLL_INT_CNTRL_MASK, - FIELD_PREP(PHY_CFG_PLL_INT_CNTRL_MASK, 0x8)); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4, - PHY_CFG_PLL_GMP_CNTRL_MASK, - FIELD_PREP(PHY_CFG_PLL_GMP_CNTRL_MASK, 0x1)); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5, - PHY_CFG_PLL_PROP_CNTRL_MASK, - FIELD_PREP(PHY_CFG_PLL_PROP_CNTRL_MASK, 0x10)); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_6, - PHY_CFG_PLL_VCO_CNTRL_MASK, - FIELD_PREP(PHY_CFG_PLL_VCO_CNTRL_MASK, 0x0)); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5, - PHY_CFG_PLL_VREF_TUNE_MASK, - FIELD_PREP(PHY_CFG_PLL_VREF_TUNE_MASK, 0x1)); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2, - VBUS_DET_EXT_SEL, VBUS_DET_EXT_SEL); - - /* set default parameters */ - qcom_eusb2_default_parameters(phy); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2, - USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, - USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, - SIDDQ_SEL, SIDDQ_SEL); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, - SIDDQ, 0); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, 0); - - qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2, - USB2_SUSPEND_N_SEL, 0); - - return 0; - -disable_ref_clk: - clk_disable_unprepare(phy->ref_clk); - -disable_vreg: - regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs); - - return ret; -} - -static int qcom_snps_eusb2_hsphy_exit(struct phy *p) -{ - struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p); - - clk_disable_unprepare(phy->ref_clk); - - regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs); - - phy_exit(phy->repeater); - - return 0; -} - -static const struct phy_ops qcom_snps_eusb2_hsphy_ops = { - .init = qcom_snps_eusb2_hsphy_init, - .exit = qcom_snps_eusb2_hsphy_exit, - .set_mode = qcom_snps_eusb2_hsphy_set_mode, - .owner = THIS_MODULE, -}; - -static int qcom_snps_eusb2_hsphy_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; - struct qcom_snps_eusb2_hsphy *phy; - struct phy_provider *phy_provider; - struct phy *generic_phy; - int ret, i; - int num; - - phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); - if (!phy) - return -ENOMEM; - - phy->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(phy->base)) - return PTR_ERR(phy->base); - - phy->phy_reset = devm_reset_control_get_exclusive(dev, NULL); - if (IS_ERR(phy->phy_reset)) - return PTR_ERR(phy->phy_reset); - - phy->ref_clk = devm_clk_get(dev, "ref"); - if (IS_ERR(phy->ref_clk)) - return dev_err_probe(dev, PTR_ERR(phy->ref_clk), - "failed to get ref clk\n"); - - num = ARRAY_SIZE(phy->vregs); - for (i = 0; i < num; i++) - phy->vregs[i].supply = eusb2_hsphy_vreg_names[i]; - - ret = devm_regulator_bulk_get(dev, num, phy->vregs); - if (ret) - return dev_err_probe(dev, ret, - "failed to get regulator supplies\n"); - - phy->repeater = devm_of_phy_get_by_index(dev, np, 0); - if (IS_ERR(phy->repeater)) - return dev_err_probe(dev, PTR_ERR(phy->repeater), - "failed to get repeater\n"); - - generic_phy = devm_phy_create(dev, NULL, &qcom_snps_eusb2_hsphy_ops); - if (IS_ERR(generic_phy)) { - dev_err(dev, "failed to create phy %d\n", ret); - return PTR_ERR(generic_phy); - } - - dev_set_drvdata(dev, phy); - phy_set_drvdata(generic_phy, phy); - - phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - if (IS_ERR(phy_provider)) - return PTR_ERR(phy_provider); - - dev_info(dev, "Registered Qcom-eUSB2 phy\n"); - - return 0; -} - -static const struct of_device_id qcom_snps_eusb2_hsphy_of_match_table[] = { - { .compatible = "qcom,sm8550-snps-eusb2-phy", }, - { }, -}; -MODULE_DEVICE_TABLE(of, qcom_snps_eusb2_hsphy_of_match_table); - -static struct platform_driver qcom_snps_eusb2_hsphy_driver = { - .probe = qcom_snps_eusb2_hsphy_probe, - .driver = { - .name = "qcom-snps-eusb2-hsphy", - .of_match_table = qcom_snps_eusb2_hsphy_of_match_table, - }, -}; - -module_platform_driver(qcom_snps_eusb2_hsphy_driver); -MODULE_DESCRIPTION("Qualcomm SNPS eUSB2 HS PHY driver"); -MODULE_LICENSE("GPL"); From patchwork Sun Feb 23 12:22:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivaylo Ivanov X-Patchwork-Id: 867654 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D786E20B7EE; Sun, 23 Feb 2025 12:22:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740313363; cv=none; b=SvfuYOZsRzxhPx/CT0NfDh13IhKdxh9St9ygKgS5op8CoaUrnxPJ6goBCI6zrHiQvYksLAQB6MgSWhbZfVGEQYXPRMMyvJj+QqQjv+7DYVCn4bDBTpHm05HTlEE/SkEbIc5YKJXPQkVY2ZSk18uyQ+MwXnCW4zOxNWtX7QET5CI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740313363; c=relaxed/simple; bh=QNSa3aRW3WG2Wjc3QNhfE78/uzTq93FyGueo8wjMNeQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cKOGcHrWhdkk4IBPNoYtZif0Bgcw/HZRwnHkPU5nY5jwUWbD7eozvpQQ6vLTAYvEUzPYgmwPEFxNZXvvePkpfnwlOesUbO9A1CSs10QlYZKOWlRClR6DbcmdLMtOR6GhpeP+JotJQp9n5WDK9zKG3LnDKR7ugkpuh9AaV/ALouU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Cq9ZK5s6; arc=none smtp.client-ip=209.85.221.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Cq9ZK5s6" Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-38f325ddbc2so2634624f8f.1; Sun, 23 Feb 2025 04:22:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740313360; x=1740918160; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uX6OdJxwETGtTGGkJLPqG+9wSA4petjmxxTURrNfA8Q=; b=Cq9ZK5s6NFnm5wG7IA7podCjmftB15JckbF3FDHwTu5YKV6Oco6WDwmU81h1lt2oeO 9ZODI5CZcI+zca4oR7mBNlsvEERnNtz/6ny3i+UjqLejHpw1sjvpkYRxs1tOB2ONudZs 3n9lqE0VCiBFh2aP1PXdF1HtoXq7gViGcLlHqUFa2BcI1DNnIxzIAI7mNIwywr5K6skF cqA7r6S03vu6YBy/eIbj6npR5F15D+aHpqjtZsgQxiK74zdj7bFz84bYTori87NVf2TI AFZ25GrP9ZKs28kihVmNmR45vOXDMsQvadn7UwcZY5f5NiQRiht7sgkLzAGvpXxZOOmg KPyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740313360; x=1740918160; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uX6OdJxwETGtTGGkJLPqG+9wSA4petjmxxTURrNfA8Q=; b=bCkQuDqPVRpbZGcHDuq+wSU3ocPt8GIlnMn8hJOP/RD5GqwmCH6X2pI1NfvduR/I+0 viT6KGWScaqYidkWCkBvmk0Z3QYrlod4gxMntYaCgGcKaDXKtFo+xmch1ag73QkwjRvq D7ccDpNNNw6uJmR/DvQPd845G6wj9ue/n5pmhI/WykZ86RR5DkNXPElQGj1e9ycwJtaF Ee8/rlF3pMSxxpBJ+lbyCbr21aQ9Olhs0U8QqQD0nsH20u/LvtA0ZNxAw6WDt0J7tNuh NfBNfWl7UgB84CmZdimywewFUtcMw7tgrvJVgF7aqTAMg5jApxJZyDnF6FDhxzyR6q19 cffQ== X-Forwarded-Encrypted: i=1; AJvYcCUTOj1vNnvraHTLLQYWsE8AAav+cpPEJ1k0ye3AbXFiqAhik+3Fx2OBIy6yFySWpGGvJVxwk4akIClrNcXF@vger.kernel.org, AJvYcCWfDcpY24hn2y2Xou5iG7EqKxWqmQT22t6sE3GRQWIbPvjtfo8JccNS7VBr3Bk2WZIH/ito/RYxoCBdXcPRToUURXs=@vger.kernel.org, AJvYcCXlaoREcN6/uKWXt4BFBMZYD8pzJlqm2QMAbQjO5kpBU1XWzsFRpBLB5nord02FH7vQg0tLi3fE4s+j@vger.kernel.org X-Gm-Message-State: AOJu0YxO1Eu62DPullunz4lTl7Pn1MRDPLFy3R91NnghYrRp2SXkf+MM UNwMMfkm7YbS3MiJlqevpUdpy/wFcpVvD9/x6okZiKS63ADdag9Q X-Gm-Gg: ASbGncv22BMqiHvWYeKR6a5K8dG4qMMRQpTU6fgYNjC6WAXCqc1V9gAKSqOK319ZPuG TzDCZ2iA+/nuLRQLUt802nXQ0jcB2AnoyrlMfy5zpT8/0p1sGygSoOx3N6JjJMXjKCG6MogYrnS 2IvMaETDUZTkOcpGMTKjIa0sCgzYuc5+I8XfB4PcJoto3CRo6wFRYA9g0acb7mmgdGJ5dlnpYZW SLNPyAvcWKcXV9SODCj8y2dLTcSDXyXSTfSZVmVWz1qf4C/oDWfF3XAftAq9cFDiwNKnCu5B6RR yAPR11c7kfCKtQQPUTkDxj2L7sklkphF4cG25Ptg+X1FB4/vHNVFe9rJQBi1XDnBnMxdxy+JVDx Rpw== X-Google-Smtp-Source: AGHT+IGM38Zp+pP6TM93b+qjLZgJemULvP7cowReOHzSCfeBj9XGBP7OMOSTNANHlWJlZmr6UB7gYw== X-Received: by 2002:a05:6000:2a8:b0:38d:d69e:1326 with SMTP id ffacd0b85a97d-38f70783ad2mr7683466f8f.9.1740313360081; Sun, 23 Feb 2025 04:22:40 -0800 (PST) Received: from ivaylo-T580.. (91-139-201-119.stz.ddns.bulsat.com. [91.139.201.119]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f259f8602sm29611608f8f.94.2025.02.23.04.22.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Feb 2025 04:22:39 -0800 (PST) From: Ivaylo Ivanov To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Philipp Zabel , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/8] phy: phy-snps-eusb2: add support for exynos2200 Date: Sun, 23 Feb 2025 14:22:26 +0200 Message-ID: <20250223122227.725233-8-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250223122227.725233-1-ivo.ivanov.ivanov1@gmail.com> References: <20250223122227.725233-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Exynos2200 SoC reuses the Synopsis eUSB2 PHY IP, alongside an external repeater, for USB 2.0. Add support for it to the existing driver. Signed-off-by: Ivaylo Ivanov --- drivers/phy/Kconfig | 2 +- drivers/phy/phy-snps-eusb2.c | 172 +++++++++++++++++++++++++++++++++++ 2 files changed, 173 insertions(+), 1 deletion(-) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 11c166204..58c911e1b 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -45,7 +45,7 @@ config PHY_PISTACHIO_USB config PHY_SNPS_EUSB2 tristate "SNPS eUSB2 PHY Driver" - depends on OF && (ARCH_QCOM || COMPILE_TEST) + depends on OF && (ARCH_EXYNOS || ARCH_QCOM || COMPILE_TEST) select GENERIC_PHY help Enable support for the USB high-speed SNPS eUSB2 phy on select diff --git a/drivers/phy/phy-snps-eusb2.c b/drivers/phy/phy-snps-eusb2.c index 7a242fe32..67a19d671 100644 --- a/drivers/phy/phy-snps-eusb2.c +++ b/drivers/phy/phy-snps-eusb2.c @@ -13,6 +13,39 @@ #include #include +#define EXYNOS_USB_PHY_HS_PHY_CTRL_RST (0x0) +#define USB_PHY_RST_MASK GENMASK(1, 0) +#define UTMI_PORT_RST_MASK GENMASK(5, 4) + +#define EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON (0x4) +#define RPTR_MODE BIT(10) +#define FSEL_20_MHZ_VAL (0x1) +#define FSEL_24_MHZ_VAL (0x2) +#define FSEL_26_MHZ_VAL (0x3) +#define FSEL_48_MHZ_VAL (0x2) + +#define EXYNOS_USB_PHY_CFG_PLLCFG0 (0x8) +#define PHY_CFG_PLL_FB_DIV_19_8_MASK GENMASK(19, 8) +#define DIV_19_8_19_2_MHZ_VAL (0x170) +#define DIV_19_8_20_MHZ_VAL (0x160) +#define DIV_19_8_24_MHZ_VAL (0x120) +#define DIV_19_8_26_MHZ_VAL (0x107) +#define DIV_19_8_48_MHZ_VAL (0x120) + +#define EXYNOS_USB_PHY_CFG_PLLCFG1 (0xc) +#define EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(11, 8) +#define EXYNOS_DIV_11_8_19_2_MHZ_VAL (0x0) +#define EXYNOS_DIV_11_8_20_MHZ_VAL (0x0) +#define EXYNOS_DIV_11_8_24_MHZ_VAL (0x0) +#define EXYNOS_DIV_11_8_26_MHZ_VAL (0x0) +#define EXYNOS_DIV_11_8_48_MHZ_VAL (0x1) + +#define EXYNOS_PHY_CFG_TX (0x14) +#define EXYNOS_PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(2, 1) + +#define EXYNOS_USB_PHY_UTMI_TESTSE (0x20) +#define TEST_IDDQ BIT(6) + #define QCOM_USB_PHY_UTMI_CTRL0 (0x3c) #define SLEEPM BIT(0) #define OPMODE_MASK GENMASK(4, 3) @@ -196,6 +229,93 @@ static void qcom_eusb2_default_parameters(struct snps_eusb2_hsphy *phy) FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0)); } +static int exynos_eusb2_ref_clk_init(struct snps_eusb2_hsphy *phy) +{ + unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); + + switch (ref_clk_freq) { + case 19200000: + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG0, + PHY_CFG_PLL_FB_DIV_19_8_MASK, + FIELD_PREP(PHY_CFG_PLL_FB_DIV_19_8_MASK, + DIV_19_8_19_2_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG1, + EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK, + EXYNOS_DIV_11_8_19_2_MHZ_VAL); + break; + + case 20000000: + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_20_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG0, + PHY_CFG_PLL_FB_DIV_19_8_MASK, + FIELD_PREP(PHY_CFG_PLL_FB_DIV_19_8_MASK, + DIV_19_8_20_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG1, + EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK, + EXYNOS_DIV_11_8_20_MHZ_VAL); + break; + + case 24000000: + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_24_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG0, + PHY_CFG_PLL_FB_DIV_19_8_MASK, + FIELD_PREP(PHY_CFG_PLL_FB_DIV_19_8_MASK, + DIV_19_8_24_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG1, + EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK, + EXYNOS_DIV_11_8_24_MHZ_VAL); + break; + + case 26000000: + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_26_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG0, + PHY_CFG_PLL_FB_DIV_19_8_MASK, + FIELD_PREP(PHY_CFG_PLL_FB_DIV_19_8_MASK, + DIV_19_8_26_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG1, + EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK, + EXYNOS_DIV_11_8_26_MHZ_VAL); + break; + + case 48000000: + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_48_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG0, + PHY_CFG_PLL_FB_DIV_19_8_MASK, + FIELD_PREP(PHY_CFG_PLL_FB_DIV_19_8_MASK, + DIV_19_8_48_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG1, + EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK, + EXYNOS_DIV_11_8_48_MHZ_VAL); + break; + default: + dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq); + return -EINVAL; + } + + return 0; +} + static int qcom_eusb2_ref_clk_init(struct snps_eusb2_hsphy *phy) { unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); @@ -240,6 +360,55 @@ static int qcom_eusb2_ref_clk_init(struct snps_eusb2_hsphy *phy) return 0; } +static int exynos_snps_eusb2_hsphy_init(struct phy *p) +{ + struct snps_eusb2_hsphy *phy = phy_get_drvdata(p); + int ret; + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_RST, + USB_PHY_RST_MASK | UTMI_PORT_RST_MASK, + USB_PHY_RST_MASK | UTMI_PORT_RST_MASK); + fsleep(50); /* required after holding phy in reset */ + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, + RPTR_MODE, RPTR_MODE); + + /* update ref_clk related registers */ + ret = exynos_eusb2_ref_clk_init(phy); + if (ret) + return ret; + + /* default parameter: tx fsls-vref */ + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_PHY_CFG_TX, + EXYNOS_PHY_CFG_TX_FSLS_VREF_TUNE_MASK, + FIELD_PREP(EXYNOS_PHY_CFG_TX_FSLS_VREF_TUNE_MASK, 0x0)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_UTMI_TESTSE, + TEST_IDDQ, 0); + fsleep(10); /* required after releasing test_iddq */ + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_RST, + USB_PHY_RST_MASK, 0); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, + PHY_ENABLE, PHY_ENABLE); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_RST, + UTMI_PORT_RST_MASK, 0); + + return 0; +} + +static const char * const exynos_eusb2_hsphy_clock_names[] = { + "ref", "bus", "ctrl", +}; + +static const struct snps_eusb2_phy_drvdata exynos2200_snps_eusb2_phy = { + .phy_init = exynos_snps_eusb2_hsphy_init, + .clk_names = exynos_eusb2_hsphy_clock_names, + .num_clks = ARRAY_SIZE(exynos_eusb2_hsphy_clock_names), +}; + static int qcom_snps_eusb2_hsphy_init(struct phy *p) { struct snps_eusb2_hsphy *phy = phy_get_drvdata(p); @@ -488,6 +657,9 @@ static const struct of_device_id snps_eusb2_hsphy_of_match_table[] = { { .compatible = "qcom,sm8550-snps-eusb2-phy", .data = &sm8550_snps_eusb2_phy, + }, { + .compatible = "samsung,exynos2200-snps-eusb2-phy", + .data = &exynos2200_snps_eusb2_phy, }, { }, }; MODULE_DEVICE_TABLE(of, snps_eusb2_hsphy_of_match_table);