From patchwork Fri Feb 21 00:57:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 867351 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C76C12A1A4; Fri, 21 Feb 2025 01:00:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740099619; cv=none; b=gWFhB6AkRwW5HcGFBLca5Lj2bWJcVD2JefXn343xoOXN3lrQP9JFAPa3xVsp60ivESqB8WOf9REKdYwE9S4eFjeJxJGKeCH1+H+r4RbnurfT1aVBM7NsgtICdIE8yoHnhjVVi7txjuuFUAOd6PA1b5WNtZzAnmOhT12H9TaP2nQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740099619; c=relaxed/simple; bh=N3l8k06E2lTecUPOk6hqSheF+IUZ9RXQkUANLTLh9zI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W1lkIRO4wrxvSLQWGYHgUFt0UClN0s8qar9ISv3P7KtzXTWEqNG7lnOptdqbZ7FuQFgakkohb4T98bky9h6V0Hgns3hJoqR/pTCh4tMOwq6jHqNSbArFl5mmgR0PCwWBWiDPNZtN2uQUW47p4wyRg4DciwdF+mipPwZebTtavRg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 274B81C01; Thu, 20 Feb 2025 17:00:34 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BFAA53F59E; Thu, 20 Feb 2025 17:00:13 -0800 (PST) From: Andre Przywara To: Ulf Hansson , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: David Airlie , Simona Vetter , Boris Brezillon , Steven Price , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-pm@vger.kernel.org Subject: [PATCH 1/5] dt-bindings: power: Add Allwinner H6/H616 PRCM PPU Date: Fri, 21 Feb 2025 00:57:58 +0000 Message-ID: <20250221005802.11001-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250221005802.11001-1-andre.przywara@arm.com> References: <20250221005802.11001-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Allwinner H6 and some later SoCs contain some bits in the PRCM (Power Reset Clock Management) block that control some power domains. Those power domains include the one for the GPU, the PLLs and some analogue circuits. Signed-off-by: Andre Przywara --- .../power/allwinner,sun50i-h6-prcm-ppu.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml diff --git a/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml b/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml new file mode 100644 index 0000000000000..7eaff9baf7268 --- /dev/null +++ b/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/allwinner,sun50i-h6-prcm-ppu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner SoCs PRCM power domain controller + +maintainers: + - Andre Przywara + +description: + The Allwinner Power Reset Clock Management (PRCM) unit contains bits to + control a few power domains. + +properties: + compatible: + enum: + - allwinner,sun50i-h6-prcm-ppu + - allwinner,sun50i-h616-prcm-ppu + - allwinner,sun55i-a523-prcm-ppu + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + prcm_ppu: power-controller@7010210 { + compatible = "allwinner,sun50i-h616-prcm-ppu"; + reg = <0x07010250 0x10>; + #power-domain-cells = <1>; + }; From patchwork Fri Feb 21 00:58:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 867350 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E045A2557C; Fri, 21 Feb 2025 01:00:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740099623; cv=none; b=STbxJD2TNVVK18/sv4BvJpQlbTa6H/TxeY295zAVsYsBA91TGvNxIwZnk0xDcb1tsD52N/w1ITZr/tjczyfA6ibblepPpq2YaS5ADW+MgeBbZ4/YeBMsOjjlkkW4KbrKaS7kUaeuzBveGOh9JK9F/dGJq37KEuppVjrDlfg1Aak= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740099623; c=relaxed/simple; bh=xRUY4tvyULutpc6g2QiZnz2yzAXeXmCC6FV/Ag43M0c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gJ6LvsFtxAJov6WD41rSMKV1tM/CwBrzi27x2cbQ+WgfLdV+E5nI9kvN1rwnD9039sAtANSkD0biJ6sygljm+YB7FZdjloJB2ki9Z1i7hzpJUoFCpZ3L9NY9fJryJcKWSt+bu9gToTMmFKwe9RconVlCQHLCpDrbTE4D4I6SGc0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7A5821BA8; Thu, 20 Feb 2025 17:00:39 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 20D833F59E; Thu, 20 Feb 2025 17:00:19 -0800 (PST) From: Andre Przywara To: Ulf Hansson , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: David Airlie , Simona Vetter , Boris Brezillon , Steven Price , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-pm@vger.kernel.org Subject: [PATCH 3/5] dt-bindings: gpu: mali-bifrost: Add Allwinner H616 compatible Date: Fri, 21 Feb 2025 00:58:00 +0000 Message-ID: <20250221005802.11001-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250221005802.11001-1-andre.przywara@arm.com> References: <20250221005802.11001-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Allwinner H616 SoC has a Mali-G31 MP2 GPU, which is of the Mali Bifrost family. Add the SoC specific compatible string and pair it with the bifrost fallback compatible. Signed-off-by: Andre Przywara --- Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 735c7f06c24e6..439d5c59daa28 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -17,6 +17,7 @@ properties: oneOf: - items: - enum: + - allwinner,sun50i-h616-mali - amlogic,meson-g12a-mali - mediatek,mt8183-mali - mediatek,mt8183b-mali From patchwork Fri Feb 21 00:58:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 867349 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4A2612AD13; Fri, 21 Feb 2025 01:00:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740099629; cv=none; b=mmy5lUsfkiXQsVpUQxFdKSL0BapZct3A1pUkaPzos3GKVIUq2EBeh9pXblKypMuraIX/bWfhdUXi4rp+lI4Bdwr5TVBqBhC70wzrwjiug4RR+ASh5NiSaPQIDXILm4Ez6JZtdUNId4qKZSKLFG5ipSDgRh3nFmouCNiluSArj6Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740099629; c=relaxed/simple; bh=Z7YW0++AAqIo98z6DBnMerWXfId2k/29R1PiCFEj0uA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cjSY8+fDuW/04r7XLH1JXpeFqEnZYZft1ziCU2mu7p5s21bIM1Bxi+8Oe+RXNMoQ1yd8J8CTGbD+1BinnqVik+XZCvJRnY9mNUkVMTSMuhlgo0diouWJSntZBtGqg7opLCiJxv9gopFKEhsmjzoDmkafEjodiIH2+AKs2VuTn7E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D4DD31BA8; Thu, 20 Feb 2025 17:00:44 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 79BE83F59E; Thu, 20 Feb 2025 17:00:24 -0800 (PST) From: Andre Przywara To: Ulf Hansson , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: David Airlie , Simona Vetter , Boris Brezillon , Steven Price , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-pm@vger.kernel.org Subject: [PATCH 5/5] arm64: dts: allwinner: h616: enable Mali GPU for all boards Date: Fri, 21 Feb 2025 00:58:02 +0000 Message-ID: <20250221005802.11001-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250221005802.11001-1-andre.przywara@arm.com> References: <20250221005802.11001-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 All Allwinner H616/H618 SoCs contain a Mali G31 MP2 GPU. Enable the DT nodes for that GPU, and specify the regulator providing power to the VDD_GPU pins of the package. The rest of the DT node is set by the SoC, so is not board specific. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts | 5 +++++ .../boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi | 5 +++++ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi | 4 ++++ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 4 ++++ arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts | 5 +++++ .../boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi | 5 +++++ .../arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts | 5 +++++ arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts | 4 ++++ .../boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts | 5 +++++ .../boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts | 5 +++++ .../boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts | 5 +++++ 11 files changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts index 17e6aef67aaf9..7906b79c03898 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts @@ -79,6 +79,11 @@ &ehci0 { status = "okay"; }; +&gpu { + mali-supply = <®_dcdc1>; + status = "okay"; +}; + &ir { status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi index d12b01c5f41b6..bebfeb2a337a3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi @@ -67,6 +67,11 @@ &cpu0 { cpu-supply = <®_dcdc2>; }; +&gpu { + mali-supply = <®_dcdc1>; + status = "okay"; +}; + &mmc0 { vmmc-supply = <®_dldo1>; /* Card detection pin is not connected */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi index 908fa3b847a66..a8644fb52b04e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi @@ -77,6 +77,10 @@ &emac0 { status = "okay"; }; +&gpu { + status = "okay"; +}; + &mdio0 { ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts index a360d8567f955..f2e3300e078a9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts @@ -24,6 +24,10 @@ &emac0 { phy-supply = <®_dcdce>; }; +&gpu { + mali-supply = <®_dcdcc>; +}; + &mmc0 { vmmc-supply = <®_dcdce>; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts index 968960ebf1d18..085f3e4e8eaa8 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts @@ -50,6 +50,11 @@ &ehci2 { status = "okay"; }; +&gpu { + mali-supply = <®_dcdcc>; + status = "okay"; +}; + &ir { status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi index e92d150aaf1c1..3f416d129b727 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi @@ -10,6 +10,11 @@ &cpu0 { cpu-supply = <®_dcdc2>; }; +&gpu { + mali-supply = <®_dcdc1>; + status = "okay"; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts index a0fe7a9afb77c..b340bbcb710de 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts @@ -69,6 +69,11 @@ &ehci1 { /* USB 2 & 3 are on the FPC connector (or the exansion board) */ +&gpu { + mali-supply = <®_dcdc1>; + status = "okay"; +}; + &mmc0 { cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ bus-width = <4>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts index e1cd7572a14ce..c51d4d9120dee 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts @@ -27,6 +27,10 @@ &ext_rgmii_phy { motorcomm,clk-out-frequency-hz = <125000000>; }; +&gpu { + mali-supply = <®_dcdc1>; +}; + &mmc0 { /* * The schematic shows the card detect pin wired up to PF6, via an diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts index f828ca1ce51ef..efe0faa252f5e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts @@ -69,6 +69,11 @@ &ehci1 { status = "okay"; }; +&gpu { + mali-supply = <®_dcdc1>; + status = "okay"; +}; + &ir { status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts index 747242becbb6e..d6768455404ee 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts @@ -68,6 +68,11 @@ &ehci3 { status = "okay"; }; +&gpu { + mali-supply = <®_dcdc1>; + status = "okay"; +}; + &mmc0 { bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts index a231abf1684ad..4a7f382e0e722 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts @@ -191,6 +191,11 @@ &ehci0 { status = "okay"; }; +&gpu { + mali-supply = <®_dcdc2>; + status = "okay"; +}; + &mmc0 { vmmc-supply = <®_cldo3>; disable-wp;