From patchwork Sat Feb 8 12:57:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183220 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1944890ile; Sat, 8 Feb 2020 05:00:10 -0800 (PST) X-Google-Smtp-Source: APXvYqypAeFVnw1PH9zRQLrtKvpg9cqp8RRyiIwrOzfQ4paygTGI6FbmUkAd38sRZuUEXDEonhrj X-Received: by 2002:ac8:3602:: with SMTP id m2mr2682441qtb.356.1581166810472; Sat, 08 Feb 2020 05:00:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581166810; cv=none; d=google.com; s=arc-20160816; b=IkmHYr1XQy8RLIgIC/tmixKRsbe2SelzeTco3eUfGH/uxahqQ7vj1GEhdytyPVgP3p zo9zIdCSI/2o69QfA9fNNljIX3T63/P2O9xvTnkzJb4bCLzDE3k0BeF4HSAUHsjZavUZ YN2r4bE8uvMlmerg5AngLw8PuyoASmDaTlByjuV6a6rRXJXWmSQJft6SHwkD59XxTPjc 8kdAZpIlgtQX2vlOTqtLmjlpoxXan4pZUkJl10GFouVBgJEgpjYo7ECpOCOkzJ5BfJaY NlT+POP5uezmSqSIRAdf+k7Co3Pc8FpU4DuAxI+B1+WPeprbDx+tKSYcVIkK8IwJraf8 o18Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+p2s9N3zCo3UaOQi/uOXcF/XhbniIaFNMwB/Qn1Qo28=; b=jKoHYpsvGGjL37KVJBTUq5aJXO4KIbPZEzHHqAA7eqG3p6etFd9N8PAGnDGqfiTGph YNwgN4OnTpt6DlxDnWJCCepCB2Sip7obUK4eAfVkyuMMPFuO57wPohGl173sqhBedCMZ dPqxshuCMx+STleC7Ee08NtGHfWDjLWhaEUw5pLZ/iNwzorp3N1/pPS1wsqZ8M+S0E0m N7KQTyCB9Wy7vcvY8XPAeSNPxcOdC/VOV2jkZF+oljI5nfg8appLf2Px6E9Y5He//sH7 i9wtxvjDmAstr+awrCu4WNSs86WZ5nIo23kYDKwzXU2MGrO1E2CdAvKFkqHlwchvotwA zSeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WICaqGP6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q26si1447363qkc.306.2020.02.08.05.00.10 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:00:10 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WICaqGP6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40946 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0PiT-0003gF-Pu for patch@linaro.org; Sat, 08 Feb 2020 08:00:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41304) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgj-0000OC-On for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgi-0004XF-II for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:21 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:45983) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgi-0004UH-CU for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:20 -0500 Received: by mail-wr1-x441.google.com with SMTP id g3so962219wrs.12 for ; Sat, 08 Feb 2020 04:58:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+p2s9N3zCo3UaOQi/uOXcF/XhbniIaFNMwB/Qn1Qo28=; b=WICaqGP6mrzfkTePBo+m1JVOLT+bi80f8Zsj/fSTM6IiFyjvj4MsCflrTMFTA1ghhH AaMaMxSAITNg94g8T3aETiQOqyxBTlYqTmdtB2D2X7t8czpn8KyYkqEacpNVYFPAelUu t/UigsPrBN27GY4aZ/k8vXDv9/nrgMIuKmZwCil4hjqmge/wpKRVrmJyn3UjmAybDLuG UsDZGCbaQPNSm6DxkwvZ6FWDT9TpNvwmdrXXemkiSVtq+SAQ40/EuVXP2eY9fYQKT8F9 w9pjAg3C7/GViGgokNcbLUAhKHObeJuIpDkWBE2na9DYTsKBMHaOED7/M3FWTeCgBBAi hCOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+p2s9N3zCo3UaOQi/uOXcF/XhbniIaFNMwB/Qn1Qo28=; b=i5EqAPYVzgIqSxTRgFJJev/LuMphoJ+R99I46UDde63QRtUjDBSrEWLqfG7WgsvxUf 1LAb6INQbrtN8MvrP4C6zOv/ZBk2EgJpa0/aEdHpiblOPnJEMlfQIlpKru7LZtLy87Dl E1wccxMxoGV36njCJRdlrD9UUZOTNwMNavvnw2bghi9iVNc/JidpzVplWP1p3h+BXZJ2 DzOC+Fbu7LhhmVlLfVNuNWld7SAOeu0JBqhGlPBl3Kty8cBhs1fk/ngX6LO5lZb8fRVB B0a43NY8SlN28qigLIyz5VsGb40EBEbFh1LiXQ9ANwU40LO6m/MQLaFwSNsSDdqIC9jL MNEA== X-Gm-Message-State: APjAAAWD90+qdlwcg7P8ilaSzex5BdWuUmi6ukBzVDtTC+ViioBJBQ7v Hoguo0Y5aYGgECKe9Z3BU86HwQ6PpMFxnQ== X-Received: by 2002:adf:b193:: with SMTP id q19mr5362141wra.78.1581166699008; Sat, 08 Feb 2020 04:58:19 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/20] target/arm: Add arm_mmu_idx_is_stage1_of_2 Date: Sat, 8 Feb 2020 12:57:57 +0000 Message-Id: <20200208125816.14954-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use a common predicate for querying stage1-ness. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Rename from arm_mmu_idx_is_stage1 to arm_mmu_idx_is_stage1_of_2 --- target/arm/internals.h | 18 ++++++++++++++++++ target/arm/helper.c | 8 +++----- 2 files changed, 21 insertions(+), 5 deletions(-) -- 2.20.1 diff --git a/target/arm/internals.h b/target/arm/internals.h index 6d4a942bde..1f8ee5f573 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1034,6 +1034,24 @@ static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); #endif +/** + * arm_mmu_idx_is_stage1_of_2: + * @mmu_idx: The ARMMMUIdx to test + * + * Return true if @mmu_idx is a NOTLB mmu_idx that is the + * first stage of a two stage regime. + */ +static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + return true; + default: + return false; + } +} + /* * Parameters of a given virtual address, as extracted from the * translation control register (TCR) for a given regime. diff --git a/target/arm/helper.c b/target/arm/helper.c index 7d15d5c933..57dc7a307c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3261,8 +3261,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, bool take_exc = false; if (fi.s1ptw && current_el == 1 && !arm_is_secure(env) - && (mmu_idx == ARMMMUIdx_Stage1_E1 || - mmu_idx == ARMMMUIdx_Stage1_E0)) { + && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { /* * Synchronous stage 2 fault on an access made as part of the * translation table walk for AT S1E0* or AT S1E1* insn @@ -9285,8 +9284,7 @@ static inline bool regime_translation_disabled(CPUARMState *env, } } - if ((env->cp15.hcr_el2 & HCR_DC) && - (mmu_idx == ARMMMUIdx_Stage1_E0 || mmu_idx == ARMMMUIdx_Stage1_E1)) { + if ((env->cp15.hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { /* HCR.DC means SCTLR_EL1.M behaves as 0 */ return true; } @@ -9595,7 +9593,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr addr, MemTxAttrs txattrs, ARMMMUFaultInfo *fi) { - if ((mmu_idx == ARMMMUIdx_Stage1_E0 || mmu_idx == ARMMMUIdx_Stage1_E1) && + if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { target_ulong s2size; hwaddr s2pa; From patchwork Sat Feb 8 12:57:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183219 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1944744ile; Sat, 8 Feb 2020 04:59:59 -0800 (PST) X-Google-Smtp-Source: APXvYqxxfgnTMpthc6wulZ5riAXc8vreuzqFjmDraXYqj2mIs8Sjm/g1RpfsqFd5MulGCYyKWN4m X-Received: by 2002:ac8:2bcd:: with SMTP id n13mr2797182qtn.21.1581166798884; Sat, 08 Feb 2020 04:59:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581166798; cv=none; d=google.com; s=arc-20160816; b=Uf8TuDfP1pCRtrhjplJwO7BnZ80szu6Q7q5BE4kc3x8YxkfoHTgHvi1wvDl3szHMAD TDKQtAM0WxqRrjehhYrpojAX68mxgCxJLIjM0o5iRKz5rHpr5vA+1gAd2K7lh2apzRJ7 IHWG1aKSfzkjNnx+cjxB77fyk4FIWo/pI1i4zBnEzCj+xzlzkuATsiukRGjjxVg982dy eAOBkUCxTY2iMnZLCzDFyUQTE9GBOpcf4D1LzSA7Z62pWYlwRfCNYGZJyLD8csvxFZUR YcsZ5kW3XuQbtonWawid3l59E/8wAGNie6ERxqLpKwIlTOswtz1Xc5G7TiEMEBdxWkux kgww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BEqIPnPpK8WT34WIzblMKwve8clAu6Vf1J/OozrQddw=; b=QiGRU0xhl3z3Ve8PthR/THoeSMNZc77WF9tvcMWDCmfUQDBpAaMV/Xld7dsUkrI52x qzYp6Jey3LmwhJYVwlLGAPf2OuCYUpKG6yjaUtB4DXi2BA9wX09Q024nkrb9QAgjtHqS CXbOpj+kUk4hkPgNHNSnP4bYuqeC6tiyGwg35ZkLaDHO5gj/5A2kWGv6JVQ8ssSPmbE4 K4/oMXnjkJpuMdGKEhlF48hk50TT5fR3fIDho53dv9L6UOOomKMXvnYfOg81Iiz6Cjp1 HFvJQCySReG96xB51rRsEGFW2kNoa2jAiC1AfT4iyJKNcj5uN6OnsYwUBxPRQ/Nw3dVf VziA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p8BwdLdw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" To implement PAN, we will want to swap, for short periods of time, to a different privileged mmu_idx. In addition, we cannot do this with flushing alone, because the AT* instructions have both PAN and PAN-less versions. Add the ARMMMUIdx*_PAN constants where necessary next to the corresponding ARMMMUIdx* constant. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 33 ++++++++++++++------- target/arm/internals.h | 9 ++++++ target/arm/helper.c | 60 +++++++++++++++++++++++++++++++------- target/arm/translate-a64.c | 3 ++ target/arm/translate.c | 2 ++ 6 files changed, 87 insertions(+), 22 deletions(-) -- 2.20.1 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 18ac562346..d593b60b28 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -29,6 +29,6 @@ # define TARGET_PAGE_BITS_MIN 10 #endif -#define NB_MMU_MODES 9 +#define NB_MMU_MODES 12 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0b3036c484..c63bceaaa5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2751,20 +2751,24 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); * 5. we want to be able to use the TLB for accesses done as part of a * stage1 page table walk, rather than having to walk the stage2 page * table over and over. + * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access + * Never (PAN) bit within PSTATE. * * This gives us the following list of cases: * * NS EL0 EL1&0 stage 1+2 (aka NS PL0) * NS EL1 EL1&0 stage 1+2 (aka NS PL1) + * NS EL1 EL1&0 stage 1+2 +PAN * NS EL0 EL2&0 - * NS EL2 EL2&0 + * NS EL2 EL2&0 +PAN * NS EL2 (aka NS PL2) * S EL0 EL1&0 (aka S PL0) * S EL1 EL1&0 (not used if EL3 is 32 bit) + * S EL1 EL1&0 +PAN * S EL3 (aka S PL1) * NS EL1&0 stage 2 * - * for a total of 9 different mmu_idx. + * for a total of 12 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish NS EL0 and NS EL1 (and @@ -2819,19 +2823,22 @@ typedef enum ARMMMUIdx { /* * A-profile. */ - ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, - ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1_PAN = 3 | ARM_MMU_IDX_A, - ARMMMUIdx_E2 = 3 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_2 = 4 | ARM_MMU_IDX_A, + ARMMMUIdx_E2 = 4 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2 = 5 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2_PAN = 6 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_0 = 5 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_1 = 6 | ARM_MMU_IDX_A, - ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_0 = 7 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_1 = 8 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A, + ARMMMUIdx_SE3 = 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Stage2 = 8 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A, /* * These are not allocated TLBs and are used only for AT system @@ -2839,6 +2846,7 @@ typedef enum ARMMMUIdx { */ ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, /* * M-profile. @@ -2864,10 +2872,13 @@ typedef enum ARMMMUIdxBit { TO_CORE_BIT(E10_0), TO_CORE_BIT(E20_0), TO_CORE_BIT(E10_1), + TO_CORE_BIT(E10_1_PAN), TO_CORE_BIT(E2), TO_CORE_BIT(E20_2), + TO_CORE_BIT(E20_2_PAN), TO_CORE_BIT(SE10_0), TO_CORE_BIT(SE10_1), + TO_CORE_BIT(SE10_1_PAN), TO_CORE_BIT(SE3), TO_CORE_BIT(Stage2), diff --git a/target/arm/internals.h b/target/arm/internals.h index 1f8ee5f573..6be8b2d1a9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -843,12 +843,16 @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_SE10_0: case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: return true; default: return false; @@ -861,10 +865,13 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E2: case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: @@ -875,6 +882,7 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_SE3: case ARMMMUIdx_SE10_0: case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: @@ -1046,6 +1054,7 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: return true; default: return false; diff --git a/target/arm/helper.c b/target/arm/helper.c index 57dc7a307c..bfd6c0d04b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -671,6 +671,7 @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stage2); } @@ -682,6 +683,7 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stage2); } @@ -2700,6 +2702,7 @@ static int gt_phys_redir_timeridx(CPUARMState *env) switch (arm_mmu_idx(env)) { case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: return GTIMER_HYP; default: return GTIMER_PHYS; @@ -2711,6 +2714,7 @@ static int gt_virt_redir_timeridx(CPUARMState *env) switch (arm_mmu_idx(env)) { case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: return GTIMER_HYPVIRT; default: return GTIMER_VIRT; @@ -3337,7 +3341,9 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); if (arm_feature(env, ARM_FEATURE_EL2)) { - if (mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_E10_1) { + if (mmu_idx == ARMMMUIdx_E10_0 || + mmu_idx == ARMMMUIdx_E10_1 || + mmu_idx == ARMMMUIdx_E10_1_PAN) { format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); } else { format64 |= arm_current_el(env) == 2; @@ -3797,7 +3803,9 @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, if (extract64(raw_read(env, ri) ^ value, 48, 16) && (arm_hcr_el2_eff(env) & HCR_E2H)) { tlb_flush_by_mmuidx(env_cpu(env), - ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0); + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0); } raw_write(env, ri, value); } @@ -3815,6 +3823,7 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, if (raw_read(env, ri) != value) { tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stage2); raw_write(env, ri, value); @@ -4175,12 +4184,18 @@ static int vae1_tlbmask(CPUARMState *env) { /* Since we exclude secure first, we may read HCR_EL2 directly. */ if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0; + return ARMMMUIdxBit_SE10_1 | + ARMMMUIdxBit_SE10_1_PAN | + ARMMMUIdxBit_SE10_0; } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { - return ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0; + return ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0; } else { - return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0; + return ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0; } } @@ -4214,18 +4229,28 @@ static int alle1_tlbmask(CPUARMState *env) * stage 1 translations. */ if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0; + return ARMMMUIdxBit_SE10_1 | + ARMMMUIdxBit_SE10_1_PAN | + ARMMMUIdxBit_SE10_0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { - return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stage2; + return ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0 | + ARMMMUIdxBit_Stage2; } else { - return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0; + return ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0; } } static int e2_tlbmask(CPUARMState *env) { /* TODO: ARMv8.4-SecEL2 */ - return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E2; + return ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E2; } static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -9206,6 +9231,7 @@ static uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_Stage2: case ARMMMUIdx_E2: return 2; @@ -9214,10 +9240,13 @@ static uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_SE10_0: return arm_el_is_aa64(env, 3) ? 1 : 3; case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -9333,6 +9362,8 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) return ARMMMUIdx_Stage1_E0; case ARMMMUIdx_E10_1: return ARMMMUIdx_Stage1_E1; + case ARMMMUIdx_E10_1_PAN: + return ARMMMUIdx_Stage1_E1_PAN; default: return mmu_idx; } @@ -9379,6 +9410,7 @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) return false; case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: g_assert_not_reached(); } } @@ -11271,7 +11303,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { - if (mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_E10_1) { + if (mmu_idx == ARMMMUIdx_E10_0 || + mmu_idx == ARMMMUIdx_E10_1 || + mmu_idx == ARMMMUIdx_E10_1_PAN) { /* Call ourselves recursively to do the stage 1 and then stage 2 * translations. */ @@ -11798,10 +11832,13 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) case ARMMMUIdx_SE10_0: return 0; case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: return 1; case ARMMMUIdx_E2: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: return 2; case ARMMMUIdx_SE3: return 3; @@ -12018,11 +12055,14 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, /* TODO: ARMv8.2-UAO */ switch (mmu_idx) { case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: /* TODO: ARMv8.3-NV */ flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); break; case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: /* TODO: ARMv8.4-SecEL2 */ /* * Note that E20_2 is gated by HCR_EL2.E2H == 1, but E20_0 is diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6e82486884..49631c2340 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -124,12 +124,15 @@ static int get_a64_user_mem_index(DisasContext *s) */ switch (useridx) { case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: useridx = ARMMMUIdx_E10_0; break; case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: useridx = ARMMMUIdx_E20_0; break; case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: useridx = ARMMMUIdx_SE10_0; break; default: diff --git a/target/arm/translate.c b/target/arm/translate.c index e11a5871d0..d58c328e08 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -155,10 +155,12 @@ static inline int get_a32_user_mem_index(DisasContext *s) case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: return arm_to_core_mmu_idx(ARMMMUIdx_E10_0); case ARMMMUIdx_SE3: case ARMMMUIdx_SE10_0: case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0); case ARMMMUIdx_MUser: case ARMMMUIdx_MPriv: From patchwork Sat Feb 8 12:57:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183216 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1943780ile; Sat, 8 Feb 2020 04:58:38 -0800 (PST) X-Google-Smtp-Source: APXvYqzeiVBYVZTJlegJlugbXITD4TMXt3EaWYzcr16H6AwJ6C9A1t9hpAo4SsbXTIVhnfvqHA1r X-Received: by 2002:a05:620a:412:: with SMTP id 18mr3240914qkp.213.1581166718408; Sat, 08 Feb 2020 04:58:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581166718; cv=none; d=google.com; s=arc-20160816; b=DxHfGGDPvtdnhQpOnqR2mTnjDMVALwpOAvLRuv4D2cIFnymfH7G51W1lOlz6/uki5D KOjQRg18eZ98dPlEahVUlEotBdlwSMXOCq0wtpZEkcTSna6SEkHBnH+mje/O7hCe637G PaTZxtGFYu7Z2nDHRdk370Od0c/xcpbp7cvEZ7Cr3x2YnfsrsKNc9GipUyUvlJQwQph0 IaD1cRlMDk9p7HjAoMKPBHvDCnsGsH19cTP56rRVRk/ZAWJvGiTOAmtuLwnAiYixkpng oo/qrmdSpFg1XX4eUZIDk4JLkD8aeJeBRxzsRw4y+fEbh4ErhM0l5AR6FUTOJJrqJttd xN4w== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id r15si1487923qtn.171.2020.02.08.04.58.38 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 04:58:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="XP/JEWx4"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40834 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgz-0000Rx-SF for patch@linaro.org; Sat, 08 Feb 2020 07:58:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41333) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgl-0000OO-4p for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgk-0004b7-38 for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:23 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:45985) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgj-0004ZQ-TX for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:22 -0500 Received: by mail-wr1-x443.google.com with SMTP id g3so962279wrs.12 for ; Sat, 08 Feb 2020 04:58:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xtW+FSSefxatLNrrEmn+GvZA5uNXwjZFYEeWUyFoKGE=; b=XP/JEWx4NU6g4VtDbSBwPdjxevhfE2JL2asufRvsplPOeEpbiGmuF6hojoO++2faRP oCJtNxHVviTQ4hJA0l7a7Wz58hbQUrxQeH6TYFYJf7AiyGzys0DGA91zeD10+wtVf8po L3x0zFmcVmTiJJXhhwk8XILyyK9cmqbHPg/fYdtQiGV8WQ8ABcfoHa+wyflJq51Cuowl 9LiLVMJ0Gy8ap27qVy9pqFGydLaEuu3+/LhWtd98pZlHU1mtXr818qRikMNbp8EY/qAv mJchN/TTp7Q6V2yJFmVjlbN6hY/S+QotYuAe17TMI071ksRj0qM74F/QoWUee4A5PzR2 Hvrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xtW+FSSefxatLNrrEmn+GvZA5uNXwjZFYEeWUyFoKGE=; b=MI5Og65J8x+JOaAhEZFy707cRIBLBqzhXfSFOiEsje5pxvBwwzPchfhCT56OwOwSO1 sy/RBNyon1dG1tVqkYUfnKqLPAgY/ZmluOidYnlUWz3rTNutOqV5ym/dUzErBYn6KK5J g5nXtCBaFrj/l5Dn8eFI2oPrb5O/vdDoSCiDYSZ9f9iObvmBBGDP1AKMNUyDonGXSdga wGvMfSxjAbmSdOymI7DCbC9jdp549Ksi13Qj96qOJwqq12SJ6NPaFVrZDsVW5drbjh/Y Bji7xw25oQvY4M5MqHMRnA0CcVlwyZ+dbITjiaB0xWmXlW/jv5ca77AcHFv7YRXethk6 by5Q== X-Gm-Message-State: APjAAAXTPzB2+LERNOaoD6EAJCNeqlbcyeZdEHWAuaAAu/DJrQ/6qaiJ guYsYTT3sfwVAC+1rPn1yn++i7GKcCtyVw== X-Received: by 2002:adf:d850:: with SMTP id k16mr5284870wrl.216.1581166700754; Sat, 08 Feb 2020 04:58:20 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 03/20] target/arm: Add isar_feature tests for PAN + ATS1E1 Date: Sat, 8 Feb 2020 12:57:59 +0000 Message-Id: <20200208125816.14954-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Include definitions for all of the bits in ID_MMFR3. We already have a definition for ID_AA64MMFR1.PAN. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c63bceaaa5..08b2f5d73e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1727,6 +1727,15 @@ FIELD(ID_ISAR6, FHM, 8, 4) FIELD(ID_ISAR6, SB, 12, 4) FIELD(ID_ISAR6, SPECRES, 16, 4) +FIELD(ID_MMFR3, CMAINTVA, 0, 4) +FIELD(ID_MMFR3, CMAINTSW, 4, 4) +FIELD(ID_MMFR3, BPMAINT, 8, 4) +FIELD(ID_MMFR3, MAINTBCST, 12, 4) +FIELD(ID_MMFR3, PAN, 16, 4) +FIELD(ID_MMFR3, COHWALK, 20, 4) +FIELD(ID_MMFR3, CMEMSZ, 24, 4) +FIELD(ID_MMFR3, SUPERSEC, 28, 4) + FIELD(ID_MMFR4, SPECSEI, 0, 4) FIELD(ID_MMFR4, AC2, 4, 4) FIELD(ID_MMFR4, XNX, 8, 4) @@ -3443,6 +3452,16 @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4; } +static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0; +} + +static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2; +} + /* * 64-bit feature tests via id registers. */ @@ -3602,6 +3621,16 @@ static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; } +static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; +} + +static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; +} + static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; From patchwork Sat Feb 8 12:58:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183229 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1949295ile; Sat, 8 Feb 2020 05:04:17 -0800 (PST) X-Google-Smtp-Source: APXvYqyXgYMU5XsDOCJWAZv73H32FhLDQZu2SLVdEjvI5GhMYvuNUcHr81lqmkXJc31xVfhQHnH8 X-Received: by 2002:a05:620a:909:: with SMTP id v9mr3235479qkv.138.1581167057864; Sat, 08 Feb 2020 05:04:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581167057; cv=none; d=google.com; s=arc-20160816; b=EDs2IytlYd/hbMvaYATRBjjmWsHzpl2EEjI2InJg48ak0iNUtRZRyjsv6Nyilm3qzx IcAop6M4qC0Rm15etrAv63GvxSI18zK1njmZb1a9JZV0csDNsI2vtLw6MIeDFWXxYGJF dr53lZq1KWCwschxyi1bQtTzue/zt67U5YW/idJlEewFpV0z/v3E54gtxmeYnyT9ty5H zdRef6dWWo6BUG8R1Ssf0S/HHFXYftbUysXoJujqCGgRvbyfbYxpmTuUXloJoIpRVSZE tEvihuxJYBa4WB+yF4Ecv9+LNHdtkMYT4gV4cuMNm8AScYxojenV7Q2J+lTdfTiS4DcK kEhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Xngl1cCVNWBf5Cw2CDK8Z2YQwTs9m5X5G+obWGPZ0QA=; b=asP5ksG2r1Ky4wMgLxWj3LsOEsV6nzbqLvSelp/X9BBjZBeUgufk8X8h+Iz1Zv5ICR bjuod6lq/JN8b6q6pjqGCnjOYUscpDSlDs3jaLaa/LJFjdhFeIMGbXFrEP/2Bccg7rzc QWQgk1HhDchql4Bedrzt6vjyOQoWy/qO4bviuT56j6n5fW270TXx0/lEqQPf6EVy1ucM Lyz1pfBD1dI8ARdYqMhmGk/FDr2cDIgSB3al+g7LmGTmOGfe0TzBfnVaXXzo3TJSSmiX U/Mvo+1gc4w6pZbc4SmCVWMqZUCkZzg5S3yEVfRvfVN2SO9can3aJcBU63SBDSwAlFIx iSGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="LWk7/n+p"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For static const regdefs, file scope is preferred. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 57 +++++++++++++++++++++++---------------------- 1 file changed, 29 insertions(+), 28 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index bfd6c0d04b..e4f17c7e83 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6334,6 +6334,35 @@ static CPAccessResult access_lor_other(CPUARMState *env, return access_lor_ns(env); } +/* + * A trivial implementation of ARMv8.1-LOR leaves all of these + * registers fixed at 0, which indicates that there are zero + * supported Limited Ordering regions. + */ +static const ARMCPRegInfo lor_reginfo[] = { + { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, + .access = PL1_R, .accessfn = access_lorid, + .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + #ifdef TARGET_AARCH64 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -7568,34 +7597,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (cpu_isar_feature(aa64_lor, cpu)) { - /* - * A trivial implementation of ARMv8.1-LOR leaves all of these - * registers fixed at 0, which indicates that there are zero - * supported Limited Ordering regions. - */ - static const ARMCPRegInfo lor_reginfo[] = { - { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, - .access = PL1_RW, .accessfn = access_lor_other, - .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, - .access = PL1_RW, .accessfn = access_lor_other, - .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, - .access = PL1_RW, .accessfn = access_lor_other, - .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, - .access = PL1_RW, .accessfn = access_lor_other, - .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, - .access = PL1_R, .accessfn = access_lorid, - .type = ARM_CP_CONST, .resetvalue = 0 }, - REGINFO_SENTINEL - }; define_arm_cp_regs(cpu, lor_reginfo); } From patchwork Sat Feb 8 12:58:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183221 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1947107ile; Sat, 8 Feb 2020 05:02:15 -0800 (PST) X-Google-Smtp-Source: APXvYqzw11hmjaeirkuG4cNHWzbAJxH6mdf3aNofx5h/4PqihggZcYLxy10CBKvzXcUGD+X4bq5V X-Received: by 2002:a05:620a:1333:: with SMTP id p19mr3313703qkj.73.1581166935009; Sat, 08 Feb 2020 05:02:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581166935; cv=none; d=google.com; s=arc-20160816; b=hBN4YrlhziljBfVxZrbIohYMYgzdMScKI1YUY4jyfu5JIWfCBFa8a+4ECMr1zmgzdm VS84LEpj4KR5ak4skhRi/YwIMtmviyOpAhWNNg46zj6PtIL5/x3a8oxTXHne22zDyD5i 8wlpAAY24TZH+2YhCJgQjfNGlguCuGeJTXSTo2Q3b41ZN83JmH7NIh2SoqlNTt+KXtd2 tTPQKFmZNbGDKB/bneyOKZ4NDx882ejP+RBH1BHccR7hZ/IxxqX6TU3sXUAF9dPg6w6K uT82lixaTWyj5DjufVCDn/bAd9SQMnMDLYRd0Yzeq9a1Nw1ntqLIJAysexp1asBumgS3 CqIw== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id a188si1518156qke.248.2020.02.08.05.02.14 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:02:15 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q3x3wOZQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41024 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0PkT-0007XQ-DL for patch@linaro.org; Sat, 08 Feb 2020 08:02:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41377) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgn-0000PX-Bg for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgm-0004eM-7j for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:25 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:39683) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgm-0004cd-1X for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:24 -0500 Received: by mail-wr1-x444.google.com with SMTP id y11so2041590wrt.6 for ; Sat, 08 Feb 2020 04:58:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MWLtQ/ag+NbaBqsy4KxfJtC383rnR0ndbUAkAnWV62s=; b=q3x3wOZQvXuB4LPB4zbEIkoPpjRb6/jTBJMTTy1twEuLqqyWyH4TqLeFo0vNo+fu7m aIxA5obm0+l0DN/H7/iO/toOyWG+5rvNtgPzK1e7Yg0MClTJtIH6sWdlY6JUrdSv2eID ROxgrzlPunEemdY9ddnKyghpxTcrlb0l+XpA9BHlVKOTHdtgbCfUp+OFok+Q/sxFkqwT Bj3yN2JOa8uNsb4MRcg/OEOQEjBairL8BC+pTWOcdwOzBT9ykpJVQBI6Ym52merIimC8 BH2Sti/h9dJJi2OFf7gblPptrUbmtcq0DuXtKrNtC94bytgi1BLGmJM+EoHBVIj5edwx ywFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MWLtQ/ag+NbaBqsy4KxfJtC383rnR0ndbUAkAnWV62s=; b=bZ0rFw2OHzqONBnVu9i5p1iC0CweN9Dc8bvA9HWU6LBfBKDdoSJY5vd1l/rkfgmCfT +k/HdkKdE4qO//WvsDd4xRh9Y1JArs6tbI+c3QXvm2QMu8fuRRfUkvLchaNw5HFJvEqq PPQqKQuN7Suq/m4oXOCXWpW3a8KLtmq3MCobgnBuj7D4DFtcHVyoGwnF8OME3g2iaCby L7RvVIJTgFqIPzJmBIG2z4RjvwiqPGH9sz9+hjwjviWkocKsYci/FfGUXglY9zwpj/it dIQ1fUA4/6Ay1hyPtNTvyOIyIFokV0H4UTyKWwakoWUHfHGY46aixDSCP+rjh10XQw29 YUKw== X-Gm-Message-State: APjAAAXw5yIji6Crl41tnLvvfVDPHPGiswAX5JnfWyfx+jNzDPe5YnQE +xceApdsRO6zVh17ZrsvSXhVRdneR/SFLw== X-Received: by 2002:a5d:5273:: with SMTP id l19mr5608705wrc.175.1581166702843; Sat, 08 Feb 2020 04:58:22 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/20] target/arm: Split out aarch32_cpsr_valid_mask Date: Sat, 8 Feb 2020 12:58:01 +0000 Message-Id: <20200208125816.14954-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split this helper out of msr_mask in translate.c. At the same time, transform the negative reductive logic to positive accumulative logic. It will be usable along the exception paths. While touching msr_mask, fix up formatting. Signed-off-by: Richard Henderson --- v4: Keep CPSR_J unconditionally in this patch. Fix all formatting in msr_mask. --- target/arm/internals.h | 21 +++++++++++++++++++++ target/arm/translate.c | 40 +++++++++++++++++----------------------- 2 files changed, 38 insertions(+), 23 deletions(-) -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index 6be8b2d1a9..4d4896fcdc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1061,6 +1061,27 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) } } +static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, + const ARMISARegisters *id) +{ + uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV | CPSR_J; + + if ((features >> ARM_FEATURE_V4T) & 1) { + valid |= CPSR_T; + } + if ((features >> ARM_FEATURE_V5) & 1) { + valid |= CPSR_Q; /* V5TE in reality*/ + } + if ((features >> ARM_FEATURE_V6) & 1) { + valid |= CPSR_E | CPSR_GE; + } + if ((features >> ARM_FEATURE_THUMB2) & 1) { + valid |= CPSR_IT; + } + + return valid; +} + /* * Parameters of a given virtual address, as extracted from the * translation control register (TCR) for a given regime. diff --git a/target/arm/translate.c b/target/arm/translate.c index d58c328e08..20f89ace2f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2734,39 +2734,33 @@ static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y) /* Return the mask of PSR bits set by a MSR instruction. */ static uint32_t msr_mask(DisasContext *s, int flags, int spsr) { - uint32_t mask; + uint32_t mask = 0; - mask = 0; - if (flags & (1 << 0)) + if (flags & (1 << 0)) { mask |= 0xff; - if (flags & (1 << 1)) + } + if (flags & (1 << 1)) { mask |= 0xff00; - if (flags & (1 << 2)) + } + if (flags & (1 << 2)) { mask |= 0xff0000; - if (flags & (1 << 3)) + } + if (flags & (1 << 3)) { mask |= 0xff000000; + } - /* Mask out undefined bits. */ - mask &= ~CPSR_RESERVED; - if (!arm_dc_feature(s, ARM_FEATURE_V4T)) { - mask &= ~CPSR_T; - } - if (!arm_dc_feature(s, ARM_FEATURE_V5)) { - mask &= ~CPSR_Q; /* V5TE in reality*/ - } - if (!arm_dc_feature(s, ARM_FEATURE_V6)) { - mask &= ~(CPSR_E | CPSR_GE); - } - if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) { - mask &= ~CPSR_IT; - } - /* Mask out execution state and reserved bits. */ + /* Mask out undefined and reserved bits. */ + mask &= aarch32_cpsr_valid_mask(s->features, s->isar); + + /* Mask out execution state. */ if (!spsr) { - mask &= ~(CPSR_EXEC | CPSR_RESERVED); + mask &= ~CPSR_EXEC; } + /* Mask out privileged bits. */ - if (IS_USER(s)) + if (IS_USER(s)) { mask &= CPSR_USER; + } return mask; } From patchwork Sat Feb 8 12:58:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183217 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1943789ile; Sat, 8 Feb 2020 04:58:39 -0800 (PST) X-Google-Smtp-Source: APXvYqzfbrJoXXixJSOlhB6UPvY1OKee0hqLUVX+4ea0f+h5Crf0KIerAIT9Q3ntBgn3LMcjWoHF X-Received: by 2002:aed:3ee5:: with SMTP id o34mr2794087qtf.164.1581166719449; Sat, 08 Feb 2020 04:58:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581166719; cv=none; d=google.com; s=arc-20160816; b=s0I/rBgrZ5BVRXJFq1vEZn6fb0EigAzUwHMuVKMGHCQNb6sANdl69IYsDLO8O/wk2F XPSgG16SIqTdWDYs9cfdR4bo8kwhRfHjIQGjCs+beM9p5e7aM9+X3xf6ocp0kfLz06rX WhGsBaj9+jaFk3VjeAsiw57R8YX3EkAKoLu0tNkgqDsFOZcRb/8z0u726xqCI5cqPZn8 qhIGUGjrzz3oqnjomITHbFLIEYWJ8R0GOh0TVOdMTDbnfzyZO75OX60PmqJwXGdMevbO OognUsdqQb+SbffMkFhYyw8t80COI2dFXJYwH+AiG4VD4K9uKhpOyFwz2EmA2PvAN24P 7LBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vAUcjHBqsvT+BhxEKa5AU6R34xRpNG4GK3faR8zhdYE=; b=efxHSp/l2Gpy/qx5DZhBAPKmUMPY+L6/KbgC3R+mhBWZfvS5oCAxAodxr8Zra/wM5Z 9/bQxLIUf9kZu79AHAVWgWhQOneMuFWDJaUHEqx7sVGCsvYHOyUFEw36zmEHct/Ik0W4 AMYWFWhUBnn5VT5/r3KbtOo00qWvZ2CxyPJ+EysP1Okd+/tYHWn407/mP56Ub/0RC/ZP A6i88YhoYXZ8O2X1HKXGxnCnWYnXiEdZlZ+dK716Aky4qXuTu9zlo0hqBlkf4T2YqODY 2JOPBcXgN3waa9yHqqSyks6qYNcb46B1EpETVpm+4zSWRIZHayiRgs+Yq0j/f/nxqyY+ LAsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HAdebjwJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z24si1475487qtn.325.2020.02.08.04.58.39 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 04:58:39 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HAdebjwJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40846 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Ph0-0000V6-W6 for patch@linaro.org; Sat, 08 Feb 2020 07:58:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41387) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgn-0000Qe-U7 for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgm-0004fG-Vl for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:25 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:38252) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgm-0004eX-Pt for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:24 -0500 Received: by mail-wr1-x443.google.com with SMTP id y17so2042148wrh.5 for ; Sat, 08 Feb 2020 04:58:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vAUcjHBqsvT+BhxEKa5AU6R34xRpNG4GK3faR8zhdYE=; b=HAdebjwJYDJGDdwlquEmVGbZUyBdDD82fX9Rat/iA1lhOHwcKKoClsWtZooy9wBkdQ GdO0MzHIS0mTVMHOz3krZnnVkwGR7iRM/D41sO2F1QHZsL0tYTv5jrFH9D1xp6xknrW6 QSzYl51/y4VBGh8Uoy70zQV7nCFng/C/WfETZBOolq6yCBvuxBmBDe74BjDscDi211Dk PqOgnnndjd3WIWUT61BGzBseVntj254e0w+tDY7OPoeyEl6eQzJgM3ZVI92nYrG6P9PR DN0eZZiS9h0ipNSt0w7iWirep2nuZo79XP5SQ0b9aIYxWLfO0+UdUwjngIzpcgH4xnHr 1HXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vAUcjHBqsvT+BhxEKa5AU6R34xRpNG4GK3faR8zhdYE=; b=T/nDN9PDLmnzX9uvoq9mzTQWwHs0wgJz0AbcnO5XgDz5Kn5INHbysNEl9qbT0miZTk hVVq+O91NSV1df7sxilElSOW7Ko77YOw9NHEh7VJguOHeQ3gD7+MlX+5xmW6gjuCv/3H KYMH+fy/8ZfklgrgZ1iZBTvQISKfHahvBKJkVQDmzoh9hvpGv8WZZeNvDdEOdiz4oIW3 NcPoj6axv8Laasg6OC/7bVe5hzxc2Ms6DE0LN90DogHWt80KZ5E38ZUNGDmeJKwGQdqu K2KtLxlJQno7Wsh4AuuUrAow0Yr0aH+EAigpq42FDvLyK8WFTgJHIDZZ7pbGBiwkZg9l Na7g== X-Gm-Message-State: APjAAAXw/hsBXtH4jO3DzCIAVmEIVoSSz2/4Q4hrmWFMEvPoJcLVPOJt EFy2tJGFEomLOnj0x0yKtEKLme//jCWeMA== X-Received: by 2002:adf:fdc7:: with SMTP id i7mr5165273wrs.270.1581166703687; Sat, 08 Feb 2020 04:58:23 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 06/20] target/arm: Mask CPSR_J when Jazelle is not enabled Date: Sat, 8 Feb 2020 12:58:02 +0000 Message-Id: <20200208125816.14954-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The J bit signals Jazelle mode, and so of course is RES0 when the feature is not enabled. Signed-off-by: Richard Henderson --- v4: Split out from aarch32_cpsr_valid_mask creation in previous patch. --- target/arm/internals.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index 4d4896fcdc..0569c96fd9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1064,7 +1064,7 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, const ARMISARegisters *id) { - uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV | CPSR_J; + uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; if ((features >> ARM_FEATURE_V4T) & 1) { valid |= CPSR_T; @@ -1078,6 +1078,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, if ((features >> ARM_FEATURE_THUMB2) & 1) { valid |= CPSR_IT; } + if (isar_feature_jazelle(id)) { + valid |= CPSR_J; + } return valid; } From patchwork Sat Feb 8 12:58:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183222 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1947124ile; Sat, 8 Feb 2020 05:02:15 -0800 (PST) X-Google-Smtp-Source: APXvYqzO6kdzcRl5Q1oW/psGkfJzjueCnyF5dBJAQJOxfCTmuQmts/TP19gA0d64zdsvKP0xo5xe X-Received: by 2002:ac8:163c:: with SMTP id p57mr2816871qtj.106.1581166935793; Sat, 08 Feb 2020 05:02:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581166935; cv=none; d=google.com; s=arc-20160816; b=IvGR00l4nphI4QHJ/I2KQQ6G+/3HuaYaEBiQSiEzTM2N4awxOvrCL0vJhc4URQffL/ qh4KysoTLSICAZVyjX3TGE8DIbdB7uG4kycjsZvCq1QMuu0CZDeXSTilYPnmn0eAg7z8 eo/C+Xc6GV3pTTwaWo6gzkDp+WhQF7F4BPkdOVfTJP+E6s52bzZYIDNlpxM0FBv4W1tM KdVQZF3VtY1K/Dn3P+KbH1AFuj+bNXpajp+bv6mhNfLa+nl1FXw5nS5ZE7SLhg5nQ3AI 9ZG86fdfSGeOxkZU1B9Ecb0vLtkE8L+AFAcNrMg6AtXa3/yg3uAWu/qPLtECAciHeOit j2DA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tvJQ3fhZEDoIAjBPdFLswJao5LtCHZt/hd8CPib7dDo=; b=vp+YoY2ElYGCx60zf/X0ZQOjgr/TASI+Hi4AYCkVt/nqp92hDyBQWCwd8q582AVLmY xb8Y4jFsAwsy4mMbqNWons6v8TRX9DvaWSQaHyOGBlvk5lxjga1aQWWiNP/PdIxhLEFA K19kSIicybORGtYhfiIcg4/hPT6ZFKW9zPCjy6M+FQhEGRSoYnwXP9FkXcGYAdDI/1Ix zuR2NcKeF77bqtaU11UJtLjjDr4dvC73xfr8VQVDx98AuWIMUm6c5apwpIJ0hOYvQbaJ N9bkla5PtulmQ+352uYD13Gh0ARMI9vqGIeEAt9GjwBpr356KKsK0z5/1r+CdtSvvi57 xKVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tisg0nLu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k23si134271qkk.81.2020.02.08.05.02.15 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:02:15 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tisg0nLu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41028 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0PkV-0007YN-8H for patch@linaro.org; Sat, 08 Feb 2020 08:02:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41412) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgp-0000So-8T for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgo-0004ie-5b for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:27 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:50812) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgn-0004g7-Vw for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:26 -0500 Received: by mail-wm1-x343.google.com with SMTP id a5so5226679wmb.0 for ; Sat, 08 Feb 2020 04:58:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tvJQ3fhZEDoIAjBPdFLswJao5LtCHZt/hd8CPib7dDo=; b=tisg0nLuaHHslptN22cKKGj9BdulPfWBJNYsmnMp7rvOGOLPIptYW6HKdOCVVM9rT7 oZLsCiyD+C0UVBFlhST7eN8bj6l6Eb15cWHm3LjOVkyhLb1Y2nZU4IqOTkYk43DZ42vz QX5PNyseqm/g65N6fnU5nKjJO7N++okggK3h4AbBkiTSiWBoV1T/Cul+F1ShKlERsLb3 kK4VwpKjMnoKONfjB2CR8AcKh8lvdOriCEtghEBI7TBUDknFQr7QAgca1Ms31/AzdvdT 1vtIOeyEr2IFB2l2QquPuHA1cUCzaw4AdLypPkk61pH3bB/YofPplDFMspm9BcXhjur7 NT/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tvJQ3fhZEDoIAjBPdFLswJao5LtCHZt/hd8CPib7dDo=; b=PO984tcPZYhnYz53tPN/RUXHAI43WId2X7Ago5swuvehoW2xmL7KOO7FdBv1g3/TEg WqLghR9WfUoGmB1wFh3kcEUMQmEb07oCkmZFxk/Bee3wXHnyhUVwP+jT+oEWQgHX7xtl fDh3ELZzsj9wBGUrl04GWACihn730mqMuQJo2LD8CBxROst0NzvO72cwzWQlMU5nBZ/e cfrSs2OR17AGBrucxeMknVI814qqiH0EDiDOhKqKiBfv6yDBaxyNnTI/KUdVz7NR1BEG 5B+8cizyFKtlxhJH6bQ1pu+8tQpKMVpPu+PjnXG/CbzYwGzai9iToU27hJpZY/CAL2ne yIjA== X-Gm-Message-State: APjAAAX+Hl6s8k6SRKSgJHkjTNISXFLgqjPRn+4+P31gBX74R9ZXQn8L VhCn8nrF05R6juWd/NQ52AS1zTMj7OW5HQ== X-Received: by 2002:a05:600c:23ce:: with SMTP id p14mr4269683wmb.114.1581166704693; Sat, 08 Feb 2020 04:58:24 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/20] target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask Date: Sat, 8 Feb 2020 12:58:03 +0000 Message-Id: <20200208125816.14954-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" CPSR_ERET_MASK was a useless renaming of CPSR_RESERVED. The function also takes into account bits that the cpu does not support. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 -- target/arm/op_helper.c | 5 ++++- 2 files changed, 4 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 08b2f5d73e..694b074298 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1209,8 +1209,6 @@ void pmu_init(ARMCPU *cpu); #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) /* Execution state bits. MRS read as zero, MSR writes ignored. */ #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) -/* Mask of bits which may be set by exception return copying them from SPSR */ -#define CPSR_ERET_MASK (~CPSR_RESERVED) /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ #define XPSR_EXCP 0x1ffU diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 27d16ad9ad..acf1815ea3 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -400,11 +400,14 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) /* Write the CPSR for a 32-bit exception return */ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) { + uint32_t mask; + qemu_mutex_lock_iothread(); arm_call_pre_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); - cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn); + mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar); + cpsr_write(env, val, mask, CPSRWriteExceptionReturn); /* Generated code has already stored the new PC value, but * without masking out its low bits, because which bits need From patchwork Sat Feb 8 12:58:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183226 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1948804ile; Sat, 8 Feb 2020 05:03:50 -0800 (PST) X-Google-Smtp-Source: APXvYqw1W6b6eAPNtPduUhF+JVZeETCWX7o0I3xJ62n6TRzr+6N+Eue9hNWHouKfuZaDsWOkICLt X-Received: by 2002:aed:2643:: with SMTP id z61mr2803326qtc.49.1581167030020; Sat, 08 Feb 2020 05:03:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581167030; cv=none; d=google.com; s=arc-20160816; b=hnhvjIPRDNq2tOgno+aIxmmiDbJzy9itja3Rmy13eDPUc1+niUwEqLu5CSzAfdUf21 tHBeuCvOpIYzcKT3so4OyEcnfRJwwnEFWH1eOaKJUAbwTfuxb6hTJ9Cmz8Sd5PvH20m5 5K04Vpl3tSBw8hpmjguF4NTY0ksZuleYVCiTaHlJG7cc3vyndKecpWHl8OFpeBsmFn58 /8kRVuA2U20FzYH9hYtDGgZia+GqQO97AgW+3UZnJ9NWzhcXERovxzAf0++SDIgi45hI SSiPQpFf3sY7BIsCjlbi16ye21PTVapbfZUA0pwXnchKVm0lhJCgTDQwlZpNLQzaOv5m Fqeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JxCN9UgAkN2gvbQt24qXPYmKBF/541S9HRLtE/c4bb4=; b=ARskaFysZiZvMqedpsZxncLayjEXNDKqKvW9IOGv3TESh8jO1+QZFNPiYVAawgnI0p 6AON+Zb/OvecnAXZA6p2Wg3Ij4LKwGhxvudeg23WQIhb06Gyq1OwIHoaaZ59KBoN+IbZ AxnhLp6YgqeLkdlI5Go20ZGScde6StcwE9fXoD5qkFRor5OIHdJE+OSUWXhltJMv76O+ cki4h1So1dSxZX63uHr/i2tBeQ27nsEGX6pkK399nyqrgaInWfn2J5Xe3rO+fYIPBBvj Z0PDeXu2JjqB4IgCzTqJAFRTZsmmFGiKwAuWCEiS009OtPEK5iqp1dz0Aoyko7xYd6To L6hQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YpZry2ls; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d24si1523782qka.252.2020.02.08.05.03.49 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:03:50 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YpZry2ls; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41080 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pm1-0002Vo-CK for patch@linaro.org; Sat, 08 Feb 2020 08:03:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41423) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgp-0000Un-Va for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgp-0004ju-0y for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:27 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:54370) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgo-0004ij-Rc for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:26 -0500 Received: by mail-wm1-x342.google.com with SMTP id g1so5183183wmh.4 for ; Sat, 08 Feb 2020 04:58:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JxCN9UgAkN2gvbQt24qXPYmKBF/541S9HRLtE/c4bb4=; b=YpZry2lsVluWDjdTfDIfq/R+H4jEceTA9Ethab3i3dI/DRF1B4yaRKqV7qwnzDgtfP jC0EwEJMe9OoWZdct//0D+2dh/ey9+c37VBidLgsgyjKa6y5DdU8vEV9ll/OSmu8a3sE A2GVlymJVgzxFnpmPo7mGQDf7xbU2vQ5uVBY3YwhAe1kOXY0aEhyGalhaeB87gY2xO51 U9szEfbKzPWfGpYZL1Hx5zagjF5clX2bZwiDB6wuA0g8wmEc/fwBf10ZgoWcvaqB3cF3 VGPNymuD6Fo+Tb9krI7KqheWQZsn9tDKtgIodZsmyOO7RQPjPnjU+kVAiFqjG2Wpad02 OdLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JxCN9UgAkN2gvbQt24qXPYmKBF/541S9HRLtE/c4bb4=; b=NVtClWmOaRmE85O0MlpzYg4uw+WwpPP+obYmSssDFpdtS9doF7+lEK1sdhAH34I+eD W8kQk0xUYWKYR003hb4tSQb/pJ2qLjyhPh9D6etzAmhIH7mbIvisszMZHhicdZlihgKQ nZ2Pk2LzMu5D97ilB9iG9lScepKhS1vC/ffxmxsmVrRmXRoCqBs0ODeiKB1A3bT023Uy +/mCRrcHdu7AAN/vBI16Qkk25fW+A1yVScyAJBsixK0eEkV4zDeunb6n6HCxy+PTtPCE Nnv0lbXGCU1Lk1wmSEeh67G3E2CoVt8kXUL38tjub4cHipn7DbuSXNUxAP/9/y6PLDbz VZKA== X-Gm-Message-State: APjAAAUmlJxRfR59vb+9X5WvmP1K1w9GPSjsUaG2kP4DZn1zd8hRq8hh pq2/tnB4SSB7cECt4iXUCa22i6XlqTexcA== X-Received: by 2002:a1c:65d6:: with SMTP id z205mr4292384wmb.38.1581166705609; Sat, 08 Feb 2020 04:58:25 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 08/20] target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return Date: Sat, 8 Feb 2020 12:58:04 +0000 Message-Id: <20200208125816.14954-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Using ~0 as the mask on the aarch64->aarch32 exception return was not even as correct as the CPSR_ERET_MASK that we had used on the aarch32->aarch32 exception return. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index bf45f8a785..0c9feba392 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -959,7 +959,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) { int cur_el = arm_current_el(env); unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); - uint32_t spsr = env->banked_spsr[spsr_idx]; + uint32_t mask, spsr = env->banked_spsr[spsr_idx]; int new_el; bool return_to_aa64 = (spsr & PSTATE_nRW) == 0; @@ -1014,7 +1014,8 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) * will sort the register banks out for us, and we've already * caught all the bad-mode cases in el_from_spsr(). */ - cpsr_write(env, spsr, ~0, CPSRWriteRaw); + mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar); + cpsr_write(env, spsr, mask, CPSRWriteRaw); if (!arm_singlestep_active(env)) { env->uncached_cpsr &= ~PSTATE_SS; } From patchwork Sat Feb 8 12:58:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183228 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1949075ile; Sat, 8 Feb 2020 05:04:04 -0800 (PST) X-Google-Smtp-Source: APXvYqxK/K7l4MZxU+8vh7ZV5T41VamL6H9lg6VWqZPzC+fppiEff+vPA3bGWSj+Y7k3ZIM87xLj X-Received: by 2002:ae9:e210:: with SMTP id c16mr908728qkc.334.1581167044878; Sat, 08 Feb 2020 05:04:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581167044; cv=none; d=google.com; s=arc-20160816; b=xKJVn7bmzvuicJVJEQT9YP6gjVOIml5Nxx+Xn861wURM0T7YRigWmuc5gc6cy5vyh5 JODxO/OW1gK0oljaGO0C5afHfG6mn1nHMOve2j9SaC2lWGST1Lwjn5F/tnLn0mKm1bn8 BAlJsW8NSWwRya++HvE2fs/5HuPBx0URwnGjDklGLKtJQI+z6uKPl6mRsZ19z3FB8o/n pEEg6NRr6J0rbHO3I/wEgfQCsgazBEQbs6aMEqWAqaWt+n8C8TSAN0drAvAxxS0urOQi lS0a6w4kxHE9qDX03ITpt6rk8Yxw1PSywTMVg7Jt7CxC5fbxq98Vobu6RoX7nxG+N0cl /+4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ovq6zgHOTulKMgq/xQFAYxCo50RIglYC4qMYC5kDj6w=; b=DILStLh6MnBQ0F1UiO3KpH57xLkZR2pseYZuyKppw+m545T8Ye3tVufg+rASXDbPP0 MVltDRa/BebRZTP6uknYFc8WvLVEzAFfoUbs+4Z+xwMynC3xj65x0ioZKp1Sxw/rNJXB nYbwF98Yrdp+oHkEghgZ67mgOQAK5OK3fpdgvZZwq3VCvfJS62F0UF2ZLRTh853c1Gve S62GxLIRw/Y5LnN9Z6r3Sk5G1AM2mc7zWhOjbc79uGfqoNV1C36USDeFKashXT/k5zRA Nsl7C7hPhUd7mnc4bm400KgETBML9riEO8EM9CHwh2AwiOAJ3aCrRbR2zE03OwjS2rIQ vlMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wNSpIODd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e13si1739721qtw.142.2020.02.08.05.04.04 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:04:04 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wNSpIODd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41093 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0PmG-0002fS-AO for patch@linaro.org; Sat, 08 Feb 2020 08:04:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41437) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgr-0000Xr-1y for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgq-0004mw-0L for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:28 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:43668) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgp-0004kT-Qi for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:27 -0500 Received: by mail-wr1-x443.google.com with SMTP id z9so2005214wrs.10 for ; Sat, 08 Feb 2020 04:58:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ovq6zgHOTulKMgq/xQFAYxCo50RIglYC4qMYC5kDj6w=; b=wNSpIODde3vl4gV01F+TyZqhfEtZmnarHKukxP47IeFAbl4vXActWeUuJBMk86i7rT 1sGvexGBYJORTMwCnlEmIPnIUkxFLdAfgDZ1g66WMX0kIQE0ktKFrpfUYlYNieAilHXn 4xNGGXnv5col+ns2c50YwReQ+A6YzhuiScKo9U4acenMV3VzXVz9qC251/r+FjLjwp4d tgcra/tDgKYAWAfinbKCJiKLrN9KueEBmYSbBD5WfyQdOFMPO1S9Y1YGqRcVgenf3hDa vlk2MMZeKvM/c1Mc1Hb9RfSYyEgtHnDY+rZ4un14BYDPXKxY5PoB/sjG1HJb8CGREwTp 9dPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ovq6zgHOTulKMgq/xQFAYxCo50RIglYC4qMYC5kDj6w=; b=Zyj9LhUEFEzehpiPv0zva0DaQLZhNFGKH1gUs7FwWCYPfcZf6lH5kxN0wTKs6i4Qsy icOWFJuKRqog0KnUMqmZ8yfbaz3gsy1THMogGuJSDLI1cod5Bi/ppBko1Vt8c+g/xFdk NzVRxM6/lYvQLTviuRRUNpnUWybsg9m/gVUkK7ZqXfr1yObvWA4sbebJmzkB9oHBr6CJ 0kx3Xn8cTtSRTOG/UYyKXb6lOSMQemligWBnoJBQEhCB60npLBTi6N7YMMru9dtTZi1N A+va+BR9kAf9tHtPlcZ6OtvruBXBqorhb+OVLww+8lnX28Mk6aj9XN4ioFGtnwPgWBAK ONCQ== X-Gm-Message-State: APjAAAXCEZSa3Ha4oIV9hV8VmMM3o3+nxTuya0kXsMZFay5Kl/JA0pyX 1z228TgW6ctO1cV40dibdqdTQhya5EMvfA== X-Received: by 2002:adf:ea4a:: with SMTP id j10mr5202640wrn.119.1581166706692; Sat, 08 Feb 2020 04:58:26 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 09/20] target/arm: Remove CPSR_RESERVED Date: Sat, 8 Feb 2020 12:58:05 +0000 Message-Id: <20200208125816.14954-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The only remaining use was in op_helper.c. Use PSTATE_SS directly, and move the commentary so that it is more obvious what is going on. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 ------ target/arm/op_helper.c | 9 ++++++++- 2 files changed, 8 insertions(+), 7 deletions(-) -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 694b074298..c6dff1d55b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1186,12 +1186,6 @@ void pmu_init(ARMCPU *cpu); #define CPSR_IT_2_7 (0xfc00U) #define CPSR_GE (0xfU << 16) #define CPSR_IL (1U << 20) -/* Note that the RESERVED bits include bit 21, which is PSTATE_SS in - * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use - * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, - * where it is live state but not accessible to the AArch32 code. - */ -#define CPSR_RESERVED (0x7U << 21) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) #define CPSR_Q (1U << 27) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index acf1815ea3..af3020b78f 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -387,7 +387,14 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) uint32_t HELPER(cpsr_read)(CPUARMState *env) { - return cpsr_read(env) & ~(CPSR_EXEC | CPSR_RESERVED); + /* + * We store the ARMv8 PSTATE.SS bit in env->uncached_cpsr. + * This is convenient for populating SPSR_ELx, but must be + * hidden from aarch32 mode, where it is not visible. + * + * TODO: ARMv8.4-DIT -- need to move SS somewhere else. + */ + return cpsr_read(env) & ~(CPSR_EXEC | PSTATE_SS); } void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) From patchwork Sat Feb 8 12:58:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183230 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1949682ile; Sat, 8 Feb 2020 05:04:38 -0800 (PST) X-Google-Smtp-Source: APXvYqylDr8tKdXVOVDaS/+SmTkgWu6utKk33BL93Qj4g9knqqtaN2jcftMtdBMsY2O0mj5G/vk7 X-Received: by 2002:ac8:5448:: with SMTP id d8mr2683732qtq.205.1581167078101; Sat, 08 Feb 2020 05:04:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581167078; cv=none; d=google.com; s=arc-20160816; b=jveJ7KPDg3GTb3BTyVPHJraMtNlIhmIzcxN2KC+M8YIehfO5l6FPmaq6DxymofnWPg bI0Krg+eCvQmkYvN4swxZyUk4ZrOqVHwS29KYG02swGbFYHpZr0pchMMZxKUHKtHbbPF 9fOmIUzWbk0s3BlTGfRWyswogIdFDEmfCzwqTB172Dy7TJXSe7qa07yzOG0sr2CamJgb 1KFhB/cvZLhptTmfodJQecSUsLlF5hv8ga2B8fgCSCTWjVKc2qA8dRmwqGjCW7qf8Jj1 ftIgs5B7qQ8lkPabSxSUd7VE41cHpdpSHJp7dvsJfP3eww5TiabEkcW/DjS5steV8U4Z zE0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wslv7CYEufFwFJCvr0YawYhKrjC9XNcJ2ZwEcRCjRWY=; b=pzqaXqCAUxISCulmIn6wnS/pmfQB7+ULiqGwhZtLiWSm9gAgufwzl6R3H/+xS45fmR itjAZMv4lCvrHqJFNQI4vW8q9HI06ws5jAyJWZAjTWWVD4Kr2coUBPyfM9wE51dKfxQW 5u+1DJHVWvPbrm7nKvgEtSt7OgJU2v7QFanHQbTdbqXoqOaDB94OOJVzkCuXd89JDEy9 Xag/wZXxkrZAZAxlguLoJelAfLfb09IROnyvHUkLqfRlLH1qBsYpshPcgyytN1JKIjvw Zpbf4g45DWQKrywzHijvmemztJO8jniYi2hQiX0+AGh8Ro2/9yP1V8oUIkJK7b4kNTne gcOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pDrjfa2N; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 3si1519750qtg.196.2020.02.08.05.04.38 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:04:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pDrjfa2N; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41126 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pmn-0003lI-KQ for patch@linaro.org; Sat, 08 Feb 2020 08:04:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41449) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgr-0000as-W0 for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgq-0004s1-To for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:29 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:54370) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgq-0004ni-NT for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:28 -0500 Received: by mail-wm1-x341.google.com with SMTP id g1so5183231wmh.4 for ; Sat, 08 Feb 2020 04:58:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wslv7CYEufFwFJCvr0YawYhKrjC9XNcJ2ZwEcRCjRWY=; b=pDrjfa2N7354imQpFehVJRZrkGS7Ke2bk8VJBnXpuBMGsWBXiJSu0l6SbGH9VZED/v hHwMZAY8Oe9GqVEUOal6hvSgc7E/lHQ0wQkfC/eJhNU3mjsn+VU8CT49t7EiQvqXDOV4 pc7BfbpdZar3nwFiVn38fIfZLvNPZ8d/RFnoGLuu44+oDXN3u0eSGqrmP0KrkDDRt63W QSiykQFzqpqxFsWR6sBt8OFyeQqxT6pyE+19JISgJS7l7jwFJKR0vvEk3QMi/vMNk+xK Wefq3spBy10J+teZwFPNQvt5mJI02Mj6MX0qI96y4+rhfAMoXSSHd2f+esqRgxma+kRN 4YIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wslv7CYEufFwFJCvr0YawYhKrjC9XNcJ2ZwEcRCjRWY=; b=OPh1l6nXNHWNGfI4I9xHDvma6Yoq+GimHHJDC6/9jD5p1w8HUreJuLOMo4a3mO+lVB 8/ZC4rf9NCXI0Gt01cB6I4ki23B+tQ5E+MjdHmQ7RKL7TRqehC2+VJSP2rplRbxuI7Cu BaqbD43pGK7Bl2MYfR8OsxXuwBg8bzAAlkyuuiUaoOTgwWljVupI0iRt45cMF33H3zCC nC+8RV1KjRloHEIcliUGxDUVV27bu/4fXqXhKCnKQahCJDLYSgBDMrNJSU9LEmyUdl+C 9La14hDfgnO95BFG9+ZavIFfVafWhU6D4BaxC43Zzt+xkLD96iYniZzXsAB4cU8Sxnfr cNtg== X-Gm-Message-State: APjAAAXYckTSPaiihjr4u1cKHV0X6dYyR3fO1Kd8+RwIn4rF8Oiaw9Qw JnBjSfCAYev+XMPbRcGn1LsVN5/6jcd66A== X-Received: by 2002:a05:600c:2301:: with SMTP id 1mr4433546wmo.147.1581166707530; Sat, 08 Feb 2020 04:58:27 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 10/20] target/arm: Introduce aarch64_pstate_valid_mask Date: Sat, 8 Feb 2020 12:58:06 +0000 Message-Id: <20200208125816.14954-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use this along the exception return path, where we previously accepted any values. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 12 ++++++++++++ target/arm/helper-a64.c | 1 + 2 files changed, 13 insertions(+) -- 2.20.1 diff --git a/target/arm/internals.h b/target/arm/internals.h index 0569c96fd9..034d98ad53 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1085,6 +1085,18 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, return valid; } +static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) +{ + uint32_t valid; + + valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV; + if (isar_feature_aa64_bti(id)) { + valid |= PSTATE_BTYPE; + } + + return valid; +} + /* * Parameters of a given virtual address, as extracted from the * translation control register (TCR) for a given regime. diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 0c9feba392..509ae93069 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1032,6 +1032,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) cur_el, new_el, env->regs[15]); } else { env->aarch64 = 1; + spsr &= aarch64_pstate_valid_mask(&env_archcpu(env)->isar); pstate_write(env, spsr); if (!arm_singlestep_active(env)) { env->pstate &= ~PSTATE_SS; From patchwork Sat Feb 8 12:58:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183223 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1947140ile; Sat, 8 Feb 2020 05:02:16 -0800 (PST) X-Google-Smtp-Source: APXvYqzCLA743iuA+CGENH0zi2cMEaXAebVEKxinUpxi8ojguB5l+JDoqgfs2CoI2bySlZ0NOex4 X-Received: by 2002:a05:6214:1389:: with SMTP id g9mr2732129qvz.40.1581166936558; Sat, 08 Feb 2020 05:02:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581166936; cv=none; d=google.com; s=arc-20160816; b=JZUTh8hyct8U/kzKRp1so63XGJkrn5fFMnoNTz0/2l28VdPsHn3lbby6AWGd2fJeXO a39hbvcuIsVdz+P5wNFgkLd1KcCFgGocI/EB/Z0syXAq1CKU7aVEd5pHNhaGjoXZWB3r D77sxjELtshMQkZyngQ4r+JCwIMTC9pV7mq505TyMEgcLnOo8MQ4FlQybTqbeQki3Pk3 OLTSd9jJiubK67y3e4DJS0xrHmW7Lgl3eHR1gh8cRRU1HY0sxpFI2xKDpgA8czsAl7h1 1Lu28U4sn0C7Tus3oJB/gJFdh686G8X1Xs7AbOeahSVljnIzfmaKZKQbkGeLZjSrME0E Ipmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ffmGYNu7uQNDZ2hXeKd5mhG9+9eYvjRJF/DWhIeGdyE=; b=Bjx/imEWTYOwbC0NzQ1yKg10behjjcaYRbFA1d9OFRGYlk5/tAQ5CaDwx3kw9oMt1z 01xN3G9zFa2ZmKrHzw2z2RscRB/MUVOsSqzQ96mcbeV+CQ3e/dsBmsdK78GZTa59Gft7 ju27oMy50AkkEdOrQGeeOkA/w0PPd1bg0MGHj/CuW7uIMpgjeBnrrUmx3hSTOzd/P77O 2791m+CwHgsFQT3EREo2zTRrbjAMzuKcAMCQTTG/rT246QKMEYXOvajUAB6+dzHzffrS Nlf1VrzhcWtk+bW6ui66vgFrnhVkGwGMGwr/4B+xndK/Z2nlXAxFPawGZigfOKkPqCN9 h/uA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="bqc/suh0"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 22si1572239qkk.69.2020.02.08.05.02.16 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:02:16 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="bqc/suh0"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41032 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0PkW-0007aM-1R for patch@linaro.org; Sat, 08 Feb 2020 08:02:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41463) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgt-0000f0-9w for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgr-0004v4-Us for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:31 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:50812) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgr-0004t9-O2 for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:29 -0500 Received: by mail-wm1-x341.google.com with SMTP id a5so5226838wmb.0 for ; Sat, 08 Feb 2020 04:58:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ffmGYNu7uQNDZ2hXeKd5mhG9+9eYvjRJF/DWhIeGdyE=; b=bqc/suh07UkZaHOWJTB3WR1DJjkk9Dj2nl2tPZWLdeYLtUDIZcNxLPxZrPsDmiPSWw u7RmwzJEII7t1JIw5n0StyroM/05OjZ3c1WFVgqQKkB5Bw+H33JG9JdPUx8v+VCtjCCK KKtj3t011CCZkMHf/W/YMdUvWXzcXVkaFADF8JEcqVegwsUkVg3FHvdUPSGJTLarHKGC AP1sxc5bYEsbVzZ3KtlBRX6ustIR5y+b2mEUEWy4ynYqhlBu1SDHmSKXsiPOuBNcoNfx 9XemfJPhLO/ggnnImsxeHq2Ovaimb2S82JPoObjwZwFAyOHzMD/BMoAYWoW22i0fAGff gIeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ffmGYNu7uQNDZ2hXeKd5mhG9+9eYvjRJF/DWhIeGdyE=; b=YcjDT0IscQEMYeXpKgdjIwyFASEqInfqxR9mpjoR/h19wL8k7VwojB8B8X0T7AZJZS 3v1hGc83Owx0jxIdPR4QzJLHqh814CXCYVQro+nr2WoBojkMfJA79A3lvdENgFVBCkLc nSrgmJIhmvUUEmxSeEwKbJHSpiQlWKT5+IZMSgn1LUMgiMLJxKDICx5CTmG4TxN9GLAk XfnjREALm/cDCwSxp6kxtFFKpCXL717pQuxN9fUhHvsFumS3cm/7aHHOggDzFQLxz3fd RqAfVK1J8rOlJJBs7JOTdquKNMJXKW8ShvxnHUFw6VLUuZzhSbgSH19tFMxZ9zmYaM3t yysw== X-Gm-Message-State: APjAAAXGljzKmOvGx9HDGkyfb9ZGxp2d/ZcXG/4XtJ7d9x2XuVDBqH0j cbv8HrZLAj+BgckpBKXIeZrSSvcSathkpQ== X-Received: by 2002:a05:600c:10d2:: with SMTP id l18mr4334225wmd.122.1581166708502; Sat, 08 Feb 2020 04:58:28 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 11/20] target/arm: Update MSR access for PAN Date: Sat, 8 Feb 2020 12:58:07 +0000 Message-Id: <20200208125816.14954-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For aarch64, there's a dedicated msr (imm, reg) insn. For aarch32, this is done via msr to cpsr. Writes from el0 are ignored, which is already handled by the CPSR_USER mask. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Move regdef to file scope; merge patch for CPSR_RESERVED: do not remove CPSR_SSBS from CPSR_RESERVED yet, mask PAN from CPSR if feature not enabled (pmm). v3: Update for cpsr_valid_mask etc. --- target/arm/cpu.h | 2 ++ target/arm/internals.h | 6 ++++++ target/arm/helper.c | 21 +++++++++++++++++++++ target/arm/translate-a64.c | 14 ++++++++++++++ 4 files changed, 43 insertions(+) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6dff1d55b..65a0ef8cd6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1186,6 +1186,7 @@ void pmu_init(ARMCPU *cpu); #define CPSR_IT_2_7 (0xfc00U) #define CPSR_GE (0xfU << 16) #define CPSR_IL (1U << 20) +#define CPSR_PAN (1U << 22) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) #define CPSR_Q (1U << 27) @@ -1250,6 +1251,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) +#define PSTATE_PAN (1U << 22) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) diff --git a/target/arm/internals.h b/target/arm/internals.h index 034d98ad53..f6709a2b08 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1081,6 +1081,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, if (isar_feature_jazelle(id)) { valid |= CPSR_J; } + if (isar_feature_aa32_pan(id)) { + valid |= CPSR_PAN; + } return valid; } @@ -1093,6 +1096,9 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) if (isar_feature_aa64_bti(id)) { valid |= PSTATE_BTYPE; } + if (isar_feature_aa64_pan(id)) { + valid |= PSTATE_PAN; + } return valid; } diff --git a/target/arm/helper.c b/target/arm/helper.c index e4f17c7e83..058fb23959 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4163,6 +4163,24 @@ static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, env->daif = value & PSTATE_DAIF; } +static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_PAN; +} + +static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); +} + +static const ARMCPRegInfo pan_reginfo = { + .name = "PAN", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3, + .type = ARM_CP_NO_RAW, .access = PL1_RW, + .readfn = aa64_pan_read, .writefn = aa64_pan_write +}; + static CPAccessResult aa64_cacheop_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -7599,6 +7617,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_lor, cpu)) { define_arm_cp_regs(cpu, lor_reginfo); } + if (cpu_isar_feature(aa64_pan, cpu)) { + define_one_arm_cp_reg(cpu, &pan_reginfo); + } if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { define_arm_cp_regs(cpu, vhe_reginfo); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 49631c2340..d8ba240a15 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1602,6 +1602,20 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, s->base.is_jmp = DISAS_NEXT; break; + case 0x04: /* PAN */ + if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_PAN); + } else { + clear_pstate_bits(PSTATE_PAN); + } + t1 = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, t1); + tcg_temp_free_i32(t1); + break; + case 0x05: /* SPSel */ if (s->current_el == 0) { goto do_unallocated; From patchwork Sat Feb 8 12:58:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183231 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1950788ile; Sat, 8 Feb 2020 05:05:40 -0800 (PST) X-Google-Smtp-Source: APXvYqwKgvNrrS3arYm4T3O1gaOYj4TRJLUSHAsmWUtbz6PmRufQpAXGlUHZpy2Y4JLS1nJyjyjT X-Received: by 2002:aed:3b14:: with SMTP id p20mr2814404qte.176.1581167140005; Sat, 08 Feb 2020 05:05:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581167140; cv=none; d=google.com; s=arc-20160816; b=IpnlZwxZMEtFqOX8BaiqXp+/O67rbJ+s2yYAwPIC68o9t1euMrAkquv/VkIlvCbuY3 qNzR5yC2LkJ3AtJRXI+g7oqb9JGA6TxUIjQmfIfPNIzn/+cD8SaoNAj3C33RMlc9Yddt 10PzIKWzsSuM+SqFlSzWKxwj11lb2QGOxUpWURCxuIBL/HC3KQ8vBWvgibcJodqG77M9 7NkiGMd4LNYpNgzmMYqIXzN3VBKnAH6U/xdIfsjfe2Ww/y01gONGfiJgynXWu0kwTLrT f4a3sY8dCFrJLJO/bkNpfGVBsUEiOOhzHVinVhKgsMSogP6hVd9H8Wap/BT19Yj0p6Pa WRnA== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id i11si1338516qvt.120.2020.02.08.05.05.39 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:05:39 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="wW4/AfO4"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41158 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pnn-0006QI-8T for patch@linaro.org; Sat, 08 Feb 2020 08:05:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41468) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgt-0000gh-RU for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgs-0004zd-UE for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:31 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:40479) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgs-0004wH-Nr for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:30 -0500 Received: by mail-wm1-x343.google.com with SMTP id t14so5596560wmi.5 for ; Sat, 08 Feb 2020 04:58:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8y0KNL/AFSS9j7gNmLDE5wRNKMVyyA8vBmve9VVvdXg=; b=wW4/AfO4fxkE82GLltPce2B5qr9vNeQ1eorHc95qNkTgs1YiTdlIrWpSD+u4KSXeSM AYzO6Wx3uYsFcgBiv05o3beK1GlbD/FiWe9Z0zyLAS5quQStgUk40nuhEIMEVfZisZzl xMcY/6jxMdvmHhgYczlM8hN3UfQB9owqmLoW5UHH5n+3JipV0Kmy18d5H3I8Hw06XzwC A0VI3PZKbyUg04rGromLt7Mmj2Vb0urwosVnpAyt6ibw9vAZdyUEzhAAD0crbJC/kaoN LWHQl6+40+DUlXQb11l93oaTE/ZhhUrg2izyBRfZ0ohRxIP4O7sAY18yLOX97dqUWU0B 4Pbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8y0KNL/AFSS9j7gNmLDE5wRNKMVyyA8vBmve9VVvdXg=; b=BPKT2gDIyLnIZC9YAdb34avQNjkhNI1IxLMQPP8oRU17kXGY0rJVjRSDNc2gQrSGdu +CNLFLXmAMaxp7+Ukd8lX029s3lLNVAxyLrexb6/vBYTWYU9hXK1q2pX1XcE/KFAOveW u42uxCVSrDP4hLS/zqEIh7ZDIuvlxl6UdRcRTBRitO/cLVHfPmWK8EECdeZP32/TarLs MFNWngf4njRGyQa1H7mvXNpIQf/mJPyF8fQ1bk+EgGhr36cotsXoTLGWMgzI8zko4qxE wGnol9Q45yhU1ORE8LBToDlwBkVdrezbjASE+vOKzqEbN5JVXEhGJJGKR1xtuqcPtVgC Zg+A== X-Gm-Message-State: APjAAAUdR3vPv8vIfMkJ1YUhJ/3zY6LFOEZX//kovZYneb96PC8dNa8Q cfg0CKKQhBsuEq9z5zHKg1OhY/0pujqTkA== X-Received: by 2002:a7b:c7d2:: with SMTP id z18mr4396895wmk.160.1581166709590; Sat, 08 Feb 2020 04:58:29 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/20] target/arm: Update arm_mmu_idx_el for PAN Date: Sat, 8 Feb 2020 12:58:08 +0000 Message-Id: <20200208125816.14954-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Examine the PAN bit for EL1, EL2, and Secure EL1 to determine if it applies. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 058fb23959..f6a600aa00 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11895,13 +11895,22 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) return ARMMMUIdx_E10_0; case 1: if (arm_is_secure_below_el3(env)) { + if (env->pstate & PSTATE_PAN) { + return ARMMMUIdx_SE10_1_PAN; + } return ARMMMUIdx_SE10_1; } + if (env->pstate & PSTATE_PAN) { + return ARMMMUIdx_E10_1_PAN; + } return ARMMMUIdx_E10_1; case 2: /* TODO: ARMv8.4-SecEL2 */ /* Note that TGE does not apply at EL2. */ if ((env->cp15.hcr_el2 & HCR_E2H) && arm_el_is_aa64(env, 2)) { + if (env->pstate & PSTATE_PAN) { + return ARMMMUIdx_E20_2_PAN; + } return ARMMMUIdx_E20_2; } return ARMMMUIdx_E2; From patchwork Sat Feb 8 12:58:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183225 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1948773ile; Sat, 8 Feb 2020 05:03:48 -0800 (PST) X-Google-Smtp-Source: APXvYqwN9Dn1DVVqg8Ugl/0q9GjWVj25Bgba1IkMWGbIfuM3mey9uiMnYMjSNbt6baJNth0UeIcw X-Received: by 2002:ad4:40cb:: with SMTP id x11mr2728521qvp.167.1581167028525; Sat, 08 Feb 2020 05:03:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581167028; cv=none; d=google.com; s=arc-20160816; b=pd/CVFpnOlyerCsjFwKeCmh+cMhbDbQk39jkkr9bkFnEpD6FAsHlHvKh5O+gtraSsc gUHjrZtSlW4WUmJVY0sPiR7vI5oQ4BkWYsk9oMLgNjMT0pLkeKgLA8ZnT+B+67LjqvQw 1xFxx2y7CYKbFp5Rwy9ExQU7uFL4Nr5tL9qFjAT0MPg9ARyUQ4Pu2DzXU/9I2a5I/Ywo HiZS1jL7riV3Au+qVMOtAjNbAdOOyml/b5S+ir/6wkfl5FSlhsZdrjSheCkk3GZSosss jFA4N/e9siJrHu0udlznfo7Ec1tIxFzf8upiVUlkUQDNcZJs09S9qU5OwSO5hS3dibo7 M1Mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ENQgvGHJlgOvyNIKuMG2rnxdNRZFYiYT8ZYfYWz3WUI=; b=lQF2n6pBe3be89zGI2uADiRXoZcQIY25ZDI1yy1PFNrAI0nCn2HDjuvF7ALcQ73ONF 28cRMtalOIbD2a6XSZOFJXePONEOcc5mOjCiFSqMOMgT2L0yebytUdgDANZdGE+6vzuF GCGb03qUty7kwO34+TtkCBei/DsMGCT1k2kgpsBPWhj+PvMzdDg/bgWfvU1rT/dquwPx LdRXOEcEWXuVFmBAog1Yc4HW/7YbLXBnlJUfo+flsZxbyrqhaobyvTSYbvYi3jz8WJm4 Hi63mbNRoNenZqla/lT7jvHbrAAVtp/JgeJGy5sYIamgev+LGDVnWMK40TgbFtJRRsuQ 3m/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WYEPhxPx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r187si1435942qkb.359.2020.02.08.05.03.48 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:03:48 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WYEPhxPx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41076 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pm0-0002S6-0V for patch@linaro.org; Sat, 08 Feb 2020 08:03:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41485) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgv-0000kc-6l for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgu-00056p-6t for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:33 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:35365) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgu-00052a-0g for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:32 -0500 Received: by mail-wr1-x441.google.com with SMTP id w12so2064816wrt.2 for ; Sat, 08 Feb 2020 04:58:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ENQgvGHJlgOvyNIKuMG2rnxdNRZFYiYT8ZYfYWz3WUI=; b=WYEPhxPx5xLyyzO+9sogxoawsKbGdaU29SDxiv8YD/0yNxy7tcy7888GBhbxBbyXH9 6Df3SX3WSjocUDZILpCWM5K4Pn5lWL4TuX+nWeM45Pkt7vwW5NkmQoUIHg7dzFvjWRju lKYN6MzaT82FlMdeWuklLSXwZxYXKmLy/bbQ/Xkdu6qNZKjXMTy2Dj50CrfqLUdx25Ho EzcS8RGfNbbQrIO6U4jEPSMuYPluJRiJW35svSzx8vyWWFeJIdAhA5+5UKfPYXBu4AGQ tvanrEnVI8RXpyElleywz0cicQr/IchA6Mys1n2CtspBDf3LSI9036guP2LMDucUcovf 25lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ENQgvGHJlgOvyNIKuMG2rnxdNRZFYiYT8ZYfYWz3WUI=; b=ON03Orq3P+n6e09sEx0NYtbVELcwvzAXA4V1Mbu9ExGbgyNYQ797rN+T1BlG/Oh876 lOEZVFb16mpgyby10nn1Pc7Wu49Bm2EU1QwVDPGF0z91EUXr+wH2TDZK1RPhgmzdgXEF vL5wscP5PuCyANQJ1Iv7k6HFwPLjTaiODp0B3WGkymFbi6sRxZmvM9UGqXnfi2yPvbyx 54F5RHpDGtZACXA/Me9os/DZfYw7OtznunbaUtDntrOPp8ok/eL9dSST2mCFvZ853OHO DXzjFmc8eL4TEGbhKdD19eepk9EpdwhY5bwsoLBejAvo2Gxs3Q7nHJE74MymhejHFbK2 nxeg== X-Gm-Message-State: APjAAAUbkbHQjuAAunI1ndmFIhxAD1W8UF95xtfB3VAkafa7ySkZO2QS PSY+xJ3GONBnRZ/vjYOGR+FhlNtnX2651Q== X-Received: by 2002:a5d:538e:: with SMTP id d14mr5581291wrv.358.1581166710819; Sat, 08 Feb 2020 04:58:30 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 13/20] target/arm: Enforce PAN semantics in get_S1prot Date: Sat, 8 Feb 2020 12:58:09 +0000 Message-Id: <20200208125816.14954-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" If we have a PAN-enforcing mmu_idx, set prot == 0 if user_rw != 0. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 13 +++++++++++++ target/arm/helper.c | 3 +++ 2 files changed, 16 insertions(+) -- 2.20.1 diff --git a/target/arm/internals.h b/target/arm/internals.h index f6709a2b08..4a139644b5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -893,6 +893,19 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) } } +static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_E10_1_PAN: + case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_SE10_1_PAN: + return true; + default: + return false; + } +} + /* Return the FSR value for a debug exception (watchpoint, hardware * breakpoint or BKPT insn) targeting the specified exception level. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index f6a600aa00..178757d271 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9569,6 +9569,9 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, if (is_user) { prot_rw = user_rw; } else { + if (user_rw && regime_is_pan(env, mmu_idx)) { + return 0; + } prot_rw = simple_ap_to_rw_prot_is_user(ap, false); } From patchwork Sat Feb 8 12:58:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183227 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1949035ile; Sat, 8 Feb 2020 05:04:03 -0800 (PST) X-Google-Smtp-Source: APXvYqyItcD3xRyK3hFDU9d477fD8L2hZqI3KQL/Nc63ci4HV58rKm6eO52fX5iY48ntZ4AqF9eA X-Received: by 2002:a37:91c2:: with SMTP id t185mr3030472qkd.284.1581167043302; Sat, 08 Feb 2020 05:04:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581167043; cv=none; d=google.com; s=arc-20160816; b=YW7WBxID6b3Lh9jTQOjeLCZWRKqGy0mmT3U63PXKHSVOPgJunqTW+2IlSek4wJU0Hj tf6FifpDq1qyi90x80Y+bW5a8G135q1/J+K1Oi+os3FIImb1Duy7IMxc3RnJEM24k+e6 e8uFbDiUNaXNS3RihJFRGF3uSMcnKqQJX9WTbNZrVyYFcNxc1Tq7CnZV2JHwS7wVIxRN usLfvgPeuuA/XkQDhCC3uPAFaT4OLImpR28YE8Fe2kugpVJDudwCopdO9/K0oaBzXLI6 +tT6En/BeAq+yWgs5VCcrp6/tVeEqm8CRuCTwNlAYBgxU3gZ5Gu1v+a/mXnW1TFvUDcU mr+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5rep4zmfN+I/zzXm7mpLZvAoU6SaVw4L5kdUpJxxpog=; b=0VPhxAj0L5kCBM60F2pv2qnSzreVqhBN+o3XLpxnnG6+xsSWX8NnrTH+R3SyTR2JX6 xB8fVUZpFrAfYt8pijsVpcMCwdvluyOFNaoGVXalcxCg0PgMsRD+exBO94VUdt+Tkb6I 7ov7bJI7S/n5KPxRBKFhyjIrb4yyi2Ow7N970gZKI9R3dB2gK8SNdB8KsC8jtwMWUQ2j 0+TskyOulnT9V3zXUd9lHIjbScSLmGIXCTx6oAghZuyKxOyYnXmg9BIK7sgGPhtwnMzX jhxZocka6X+va4YrzSNXGJYLvynzeBrZ4a5xR4gB1jPyxJrm5J23Ibkry/dFDY3mTNv2 J9Ng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PNBFx+gu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g11si1469575qkm.233.2020.02.08.05.04.03 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:04:03 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PNBFx+gu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41088 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0PmE-0002b5-Rl for patch@linaro.org; Sat, 08 Feb 2020 08:04:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41501) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgw-0000oV-Jr for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgv-0005BB-BV for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:34 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:40568) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgv-00058b-51 for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:33 -0500 Received: by mail-wr1-x442.google.com with SMTP id t3so2034453wru.7 for ; Sat, 08 Feb 2020 04:58:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5rep4zmfN+I/zzXm7mpLZvAoU6SaVw4L5kdUpJxxpog=; b=PNBFx+gu5l69Qc/iAOvWkB5jdyGzCHQT7O9KdZz7fU440YzNlOT3AzLJrpmwMpCquc iWw5LlOWhQf7Gp9sP6Y/UHBgto86e8+5EpVvUHZ4yGIdJaPIm/QLCWEuznZuXdxpE/nO YF2IkTedwtgv6nU7vgqSe1wglUJ0mY6gZiEhFZagLj7GzZ4TEoXP1rZiYWjbTZC2VdnQ +YFg2brZJMAANuBLVUpE6KHQ+1Groyz1lJ6dy51fqXIxKL1EtDt5W08LivwRDfxmt+T/ GtGmKU+C5Hvz9sCpYEnukb2sD5vD1sPJwzsE2ooeg3fMZhb/tsgTkMJtHrrBc/a+2TeM Y/hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5rep4zmfN+I/zzXm7mpLZvAoU6SaVw4L5kdUpJxxpog=; b=fAaM2N4J1ZpwZCnQhdl5nlkd3yUcEUG4ciIzU3+MTO21R5sg2iK4L2prPK0suRzP9b 4o4IcBWIjb+I3IoqZn+mTGfzrR8qKyBuTJPEKD7hJDIObtXhquMbcbisyKztO7viTSUL P4pTiNMP+L1NAq+7eLALdo1fQeYnTmSqMS3EFWAaKNHEfRTifFCrTfv1MOMIfyt0H34h 3cvqP741/p3K7i7I53Mb9A1QYirUCLriI0wTIjC0OTpRFZPyypRMbpAqWrjaJPNGmfIl LN7dbVj/0et8jowp2blwrYpbF0BjKNgkwJdRi3uO0+nHVsocTE5t9YitCNyjFU7u0Fxx EcnA== X-Gm-Message-State: APjAAAVX0Mc3F4le/LSScODVCF1rzyVr6rRbS3cseSGuBAiMAPzfSmJl zyUF/eeNXmT17LZ59gBtnsruHEK3EyxwoQ== X-Received: by 2002:adf:ecc6:: with SMTP id s6mr5451347wro.345.1581166711877; Sat, 08 Feb 2020 04:58:31 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 14/20] target/arm: Set PAN bit as required on exception entry Date: Sat, 8 Feb 2020 12:58:10 +0000 Message-Id: <20200208125816.14954-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The PAN bit is preserved, or set as per SCTLR_ELx.SPAN, plus several other conditions listed in the ARM ARM. Signed-off-by: Richard Henderson --- v2: Tidy preservation of CPSR_PAN in take_aarch32_exception (pmm). v4: Fix exception entry to EL3. --- target/arm/helper.c | 53 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 3 deletions(-) -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/target/arm/helper.c b/target/arm/helper.c index 178757d271..de16ce79ad 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8763,8 +8763,12 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, uint32_t mask, uint32_t offset, uint32_t newpc) { + int new_el; + /* Change the CPU state so as to actually take the exception. */ switch_mode(env, new_mode); + new_el = arm_current_el(env); + /* * For exceptions taken to AArch32 we must clear the SS bit in both * PSTATE and in the old-state value we save to SPSR_, so zero it now. @@ -8777,7 +8781,7 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; /* Set new mode endianness */ env->uncached_cpsr &= ~CPSR_E; - if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { + if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { env->uncached_cpsr |= CPSR_E; } /* J and IL must always be cleared for exception entry */ @@ -8788,6 +8792,25 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; env->elr_el[2] = env->regs[15]; } else { + /* CPSR.PAN is normally preserved preserved unless... */ + if (cpu_isar_feature(aa64_pan, env_archcpu(env))) { + switch (new_el) { + case 3: + if (!arm_is_secure_below_el3(env)) { + /* ... the target is EL3, from non-secure state. */ + env->uncached_cpsr &= ~CPSR_PAN; + break; + } + /* ... the target is EL3, from secure state ... */ + /* fall through */ + case 1: + /* ... the target is EL1 and SCTLR.SPAN is 0. */ + if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { + env->uncached_cpsr |= CPSR_PAN; + } + break; + } + } /* * this is a lie, as there was no c1_sys on V4T/V5, but who cares * and we should just guard the thumb mode on V4 @@ -9050,6 +9073,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) unsigned int new_el = env->exception.target_el; target_ulong addr = env->cp15.vbar_el[new_el]; unsigned int new_mode = aarch64_pstate_mode(new_el, true); + unsigned int old_mode; unsigned int cur_el = arm_current_el(env); /* @@ -9129,20 +9153,43 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) } if (is_a64(env)) { - env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); + old_mode = pstate_read(env); aarch64_save_sp(env, arm_current_el(env)); env->elr_el[new_el] = env->pc; } else { - env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); + old_mode = cpsr_read(env); env->elr_el[new_el] = env->regs[15]; aarch64_sync_32_to_64(env); env->condexec_bits = 0; } + env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode; + qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", env->elr_el[new_el]); + if (cpu_isar_feature(aa64_pan, cpu)) { + /* The value of PSTATE.PAN is normally preserved, except when ... */ + new_mode |= old_mode & PSTATE_PAN; + switch (new_el) { + case 2: + /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */ + if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) + != (HCR_E2H | HCR_TGE)) { + break; + } + /* fall through */ + case 1: + /* ... the target is EL1 ... */ + /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */ + if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) { + new_mode |= PSTATE_PAN; + } + break; + } + } + pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = 1; aarch64_restore_sp(env, new_el); From patchwork Sat Feb 8 12:58:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183234 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1953883ile; Sat, 8 Feb 2020 05:08:48 -0800 (PST) X-Google-Smtp-Source: APXvYqy6nWM/l+LydzlaTVkzDZy3EfE2PWVkbgCo5Kgt/aJuZA9LvNlQltmvV8RVTztc91houf6O X-Received: by 2002:ac8:6759:: with SMTP id n25mr2857648qtp.226.1581167328760; Sat, 08 Feb 2020 05:08:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581167328; cv=none; d=google.com; s=arc-20160816; b=DVGDKXP6miZZxdXg2UnxdEFVU/3yWU2tNk8XzQ6Kqu6BrgY3DUek1lxb4LCkU7bWJm fd3MYHQsMCa3ziTu+C4ppPqBkEPRQO7YD++GfkhkefyoPvNFIuRoO8g/1ALxUonCqdYa gHk8xL5jWUdVhJMOfx2kJmYNUDVR5ZEUKoWqjM8HPNCRW+hKQT2l9d53F6l44KrsjIY2 ffeFwZf1qZcEEY4xWaEziaNllR7JwHgS2nygpc7cq8Pn7Hk0Q+iaCUElrcLQXN5xpxDu rhykR2e00oaFZpiJFNbR8cHRnpwu9jHGQby9YO5ce8+HxFVmbxWeyDuIB+wy5ogkz1Oz y0Mw== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id w54si1492554qtj.372.2020.02.08.05.08.48 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:08:48 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y6gd0Ky3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41318 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pqq-0004C8-6Y for patch@linaro.org; Sat, 08 Feb 2020 08:08:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41512) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgx-0000ql-Dz for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgw-0005CL-81 for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:35 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:37469) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgw-0005Be-1o for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:34 -0500 Received: by mail-wm1-x343.google.com with SMTP id f129so5631367wmf.2 for ; Sat, 08 Feb 2020 04:58:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m4T2G+2BVRE0tpK6F0FDHxQ98vwNbb8dIt/PD3r4gkg=; b=y6gd0Ky3n40UiSJHg7tyPyzONl/LEN7FFq+MWh9yQVBU47K3ruqXkTJ/DkW6ABSpnN L4QyLFDt7qyqhwAO3Ook/7jhUpFDybrOZ0dYKiCqhkYr/9GQvsBqmn9Sxo5giCGrMvPs 5C5yYbLfkN7QDHFxO+5ZZoRwT7e7SVqWdlx0/vNSqQ/8GeOUD19KKTJ0Rmv3kOr72X1l 5oS8XbbwMg4rgxwD6+1KgsHS4Q6epAfYjvUDCPYs18RYnTYtavhfwvq+Xa231DrjqlLm h27AWWHmDiasDZjOAO8TaQYNp++Ix0ONcwqxa2WmbZm1nvLIxjGVLdCm09Ial+qYogeY FI1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m4T2G+2BVRE0tpK6F0FDHxQ98vwNbb8dIt/PD3r4gkg=; b=Iv7mLqzAYKxch+/COtvcqBx1f0MG5Lck08P8C1pHKNfAiAIiWPpfNtB++FnFJ1y9gw kGNLEskfOxfHgvXm5rpZOBz+V5sNj1SJzWuLbeieZgGESJeR3TYIWBq5IAUdyfte9Tvh vLmUX6A39CZU1iuvcrvxNhaLgAymaESy41tEZ6ZTbNVm4vDvoIa8vhyFmyVan7XytDF4 piIxoCVnJ0RIwwaqPbpF9mFodv4gJlT9N3VelbY60Ny0cd18w+evq56WEWQFAcwzPDOT MMprBAQxj+XP/nIPwibsg84pMgghwDWSqKVznlAejDMIiuReFy3LZNLNH0y60tivUgLb HYEw== X-Gm-Message-State: APjAAAWfkO7uXbxy6Jb3KqOEYDWRe4eVlJECr7Y0/Y7f0K7fY6cR4vqe CeMSWFTyMhzewiihTkLy60apHGnEaNwAlA== X-Received: by 2002:a1c:3d46:: with SMTP id k67mr4508928wma.171.1581166712854; Sat, 08 Feb 2020 04:58:32 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 15/20] target/arm: Implement ATS1E1 system registers Date: Sat, 8 Feb 2020 12:58:11 +0000 Message-Id: <20200208125816.14954-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a minor enhancement over ARMv8.1-PAN. The *_PAN mmu_idx are used with the existing do_ats_write. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Move regdefs to file scope (pmm). --- target/arm/helper.c | 56 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 50 insertions(+), 6 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index de16ce79ad..d99661d4ea 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3409,16 +3409,21 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) switch (ri->opc2 & 6) { case 0: - /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ + /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */ switch (el) { case 3: mmu_idx = ARMMMUIdx_SE3; break; case 2: - mmu_idx = ARMMMUIdx_Stage1_E1; - break; + g_assert(!secure); /* TODO: ARMv8.4-SecEL2 */ + /* fall through */ case 1: - mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; + if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { + mmu_idx = (secure ? ARMMMUIdx_SE10_1_PAN + : ARMMMUIdx_Stage1_E1_PAN); + } else { + mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; + } break; default: g_assert_not_reached(); @@ -3487,8 +3492,13 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, switch (ri->opc2 & 6) { case 0: switch (ri->opc1) { - case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; + case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ + if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) { + mmu_idx = (secure ? ARMMMUIdx_SE10_1_PAN + : ARMMMUIdx_Stage1_E1_PAN); + } else { + mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; + } break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx = ARMMMUIdx_E2; @@ -6683,6 +6693,32 @@ static const ARMCPRegInfo vhe_reginfo[] = { REGINFO_SENTINEL }; +#ifndef CONFIG_USER_ONLY +static const ARMCPRegInfo ats1e1_reginfo[] = { + { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, + { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo ats1cp_reginfo[] = { + { .name = "ATS1CPRP", + .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write }, + { .name = "ATS1CPWP", + .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write }, + REGINFO_SENTINEL +}; +#endif + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -7620,6 +7656,14 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pan, cpu)) { define_one_arm_cp_reg(cpu, &pan_reginfo); } +#ifndef CONFIG_USER_ONLY + if (cpu_isar_feature(aa64_ats1e1, cpu)) { + define_arm_cp_regs(cpu, ats1e1_reginfo); + } + if (cpu_isar_feature(aa32_ats1e1, cpu)) { + define_arm_cp_regs(cpu, ats1cp_reginfo); + } +#endif if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { define_arm_cp_regs(cpu, vhe_reginfo); From patchwork Sat Feb 8 12:58:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183232 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1951955ile; Sat, 8 Feb 2020 05:06:50 -0800 (PST) X-Google-Smtp-Source: APXvYqzVhHzhTz/cgyFD1kk5W11WNdT1/IGJ/siN+egPRXYRbx5jdLz+GM686WLTEaGOoGi8A2YC X-Received: by 2002:a05:620a:126f:: with SMTP id b15mr3269631qkl.145.1581167210461; Sat, 08 Feb 2020 05:06:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581167210; cv=none; d=google.com; s=arc-20160816; b=HoGL0Ra317Kr8bc7VtPuAt64jzfHCg8Dw/0Yzh0EP29hQJfr4a+XGjSHMcsuWI2afN UrWHCBLbiqmGJZx9Doz0s3Q1ntldffF2zx/g3MJpzgYVh7fv5NPw73HCU++ICol7VwGm xoJnw7ML87kA33WCFxCyHiHjyrLrjesvIMDV4EJsIQoDjfI5M/XH3+mp1NmO/aRHNmn8 JaHktJktVYQw49QkclBmsGOJzkPOtAEQppzY1MvdD16V/i2NAeKCIdoPBdy+QVm2fb1a LG1Vi2GfHcr8Si4gVkdEz0iLQ0S8AbrS2grnYdxsLGpTCJq6HTJjqsqfHduede0jDh4R aGlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pbTFZCO7ADOXNmgFtzr7ygDnLBWMHSNndfGhWIzZQwI=; b=foOmRPB5pDXI1cTkBnDwLEl8ghkmxA5ROzh9wtQFo08ebko0nnaeljA2kZB+H6i+SV WTb2CjapePLDiay+akWjPAUVDQILHSIZ1GdjyHaafN2fN+wc05p6CQiZdR1K8TavDD8q Ds+wFTaPvpxGLzDWbpLZPoVRFxNBKYitMJfP7sHPshKWg2xrXmWogLQZRG1UMsTYZrrF hNAuenYygH85aHJmm7ynFyq/tBcad0KSCGJxLKcuFu94UXEg4BUBMRyZ8S9c0NOthQNs Ub1pXpYdoWVWk+ci8fRWuspY4gljRXNb83bfU+YQ/h/hrGUUW38E4JEX4wR/U+kCqMLd FLSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="vZd9KFp/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This includes enablement of ARMv8.1-PAN. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 4 ++++ target/arm/cpu64.c | 5 +++++ 2 files changed, 9 insertions(+) -- 2.20.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b0762a76c4..de733aceeb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2709,6 +2709,10 @@ static void arm_max_initfn(Object *obj) t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ cpu->isar.mvfr2 = t; + t = cpu->id_mmfr3; + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->id_mmfr3 = t; + t = cpu->id_mmfr4; t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ cpu->id_mmfr4 = t; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c80fb5fd43..57fbc5eade 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -673,6 +673,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); + t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ cpu->isar.id_aa64mmfr1 = t; /* Replicate the same data to the 32-bit id registers. */ @@ -693,6 +694,10 @@ static void aarch64_max_initfn(Object *obj) u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 = u; + u = cpu->id_mmfr3; + u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->id_mmfr3 = u; + /* * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet, * so do not set MVFR1.FPHP. Strictly speaking this is not legal, From patchwork Sat Feb 8 12:58:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183224 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1947409ile; Sat, 8 Feb 2020 05:02:31 -0800 (PST) X-Google-Smtp-Source: APXvYqwaPQMfR7URCamDmuEIYV2JJgWWQvMgkd3Px9BgZGs1qSVieSpWC8qWpvSqcI3lYYe1e4jj X-Received: by 2002:a05:620a:999:: with SMTP id x25mr3190618qkx.87.1581166951609; Sat, 08 Feb 2020 05:02:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581166951; cv=none; d=google.com; s=arc-20160816; b=E3AiZuDQSuXpnYEx9PeN6KymUVJpnKBMiULd/lPU5ZeAbsXCIFhoHkHjv0b8OxghUm GEsxd+gtJZH21RiI20MvM329aNhlYu9W3pMPUjixAp/dPSHkm62j7d0EMNeXDv5+PPrD O7WLpoQ7OUM/EJTPjSsBUEMbDLSfuwXT6KShoBHVbHCdKNFu0voXjPkwXMaVYAyq97Es MFrOzVhlOABkDnDlGINFyqVpzywsWOVJEbYD1XKwUh4ry1IhhcU5tyGHFr4inVeg9Ytw wVpcUDkbffSh5d/AdNPS99ebxqbuZpfxNA/b+1WzSrR58YjabwY1uohbbkXNOF79lhla /29g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=k/k5v7TYVkBZgnpFZntRFjxp8rADwUlaXt3p2gBQVc4=; b=Hic94RGZCqDMhTniXM5hqgq2aGIZhupMx0cepl2NSw7UrSeV6Vy+E3FjjsBrMI/jcm 6+fRFs1PO4QO4xq0V4I4KBEV+sz478i0d77uit29FdIRPsli18+iVKhzuBvIyYdc0jjv NbIR4sz/kqw5aD/UsJp6g01qB1t7jLgLU5Tv6jOCxSnOnKiImloIe+H9fyTBJsdXKwP9 jyoft105wQh88Tq6++ItHsnJOdFil+WgUxBz7rZvltkDZ1jWb/MKNawI/XIE7wJnISw1 5t2Jfi5CYufB5ruBtS3PIYU+teZkRAqXZwz8LGRrgMmi61RCqHf07CSML7fERi1lzzrE so/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AZZPNasi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k4si1683137qke.112.2020.02.08.05.02.31 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:02:31 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AZZPNasi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41044 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pkl-0007lJ-3s for patch@linaro.org; Sat, 08 Feb 2020 08:02:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41541) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgz-0000w3-9l for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgy-0005DF-7G for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:37 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:46542) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgy-0005Cv-0q for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:36 -0500 Received: by mail-wr1-x441.google.com with SMTP id z7so1983559wrl.13 for ; Sat, 08 Feb 2020 04:58:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=k/k5v7TYVkBZgnpFZntRFjxp8rADwUlaXt3p2gBQVc4=; b=AZZPNasiCTisHChLRWnP7pA6o7XQ05Oip72av1GxrImGkxwr4I4dmHK4EWmyv9Mnbt 9UpuX26bmxrEPN5UUKdUvEgft/CyGe10e3Tuk/xuD0rjaB4MzZS1CXuGba/nfVQG1K6H Jnm3dMcI7tzVBD5ndtE80GYgzRelSSTjzxbDMFX1xLrOMtdX2QICyBs9qz+BFEs/CkOi lShBM7TqdZMrDVtXtyRouN52HkejgdzmeVJh2BqjGIkakv079z59DWyTo7LHXEPcGfKF sdWRkXhrYjlM4RkKTxrDn+lM54wJMse5zN67oh6ne+Cu/hhJACaKKYLJSEzqDnYWrwsm sVRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k/k5v7TYVkBZgnpFZntRFjxp8rADwUlaXt3p2gBQVc4=; b=K7/OdksxWG1c3MV/EiRzxN+dhPZ1bAV04I9JppGfF9aWMV/QB4DU/XEy0x8o18EU6C njStPaPOR09cJcHWVO9HhtTaElVYqo6k2EfjBBv7JHeecyDQ92XlmBzVmpZJ8CXcg4H2 75zRQsGtpBMF6antt6qc1y5NQkBDn/MjAGPhQmiYJhqJ8CbSZ0AMFyBhAxcGJO79+D6Z PW4CeN6N2RM5JI7j0XLcmS5fsGetCpN9Qt2hmE/T2XpmBwgd3faYWPlByJPSxUwGdWjT dSgdqMBh8OFWGRF5z9VUVoZwglNJ1WEvzm1XS0JpT6pz3J50O8qRdfmvHpm9+NikjVIF NMOw== X-Gm-Message-State: APjAAAWHvWMN85BM5qZ+ypAOp3wER5SYZ0xWqW1Hi3t28MgEj6dLroii D1CFnldstwcq0V1anCPceEKKcti41p8iaw== X-Received: by 2002:adf:dc8d:: with SMTP id r13mr5571560wrj.357.1581166714886; Sat, 08 Feb 2020 04:58:34 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 17/20] target/arm: Add ID_AA64MMFR2_EL1 Date: Sat, 8 Feb 2020 12:58:13 +0000 Message-Id: <20200208125816.14954-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add definitions for all of the fields, up to ARMv8.5. Convert the existing RESERVED register to a full register. Query KVM for the value of the register for the host. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 17 +++++++++++++++++ target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 2 ++ 3 files changed, 21 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 65a0ef8cd6..71879393c2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -871,6 +871,7 @@ struct ARMCPU { uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; + uint64_t id_aa64mmfr2; } isar; uint32_t midr; uint32_t revidr; @@ -1803,6 +1804,22 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4) FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) FIELD(ID_AA64MMFR1, XNX, 28, 4) +FIELD(ID_AA64MMFR2, CNP, 0, 4) +FIELD(ID_AA64MMFR2, UAO, 4, 4) +FIELD(ID_AA64MMFR2, LSM, 8, 4) +FIELD(ID_AA64MMFR2, IESB, 12, 4) +FIELD(ID_AA64MMFR2, VARANGE, 16, 4) +FIELD(ID_AA64MMFR2, CCIDX, 20, 4) +FIELD(ID_AA64MMFR2, NV, 24, 4) +FIELD(ID_AA64MMFR2, ST, 28, 4) +FIELD(ID_AA64MMFR2, AT, 32, 4) +FIELD(ID_AA64MMFR2, IDS, 36, 4) +FIELD(ID_AA64MMFR2, FWB, 40, 4) +FIELD(ID_AA64MMFR2, TTL, 48, 4) +FIELD(ID_AA64MMFR2, BBM, 52, 4) +FIELD(ID_AA64MMFR2, EVT, 56, 4) +FIELD(ID_AA64MMFR2, E0PD, 60, 4) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) diff --git a/target/arm/helper.c b/target/arm/helper.c index d99661d4ea..d29722d8ac 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7073,11 +7073,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, .resetvalue = cpu->isar.id_aa64mmfr1 }, - { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_aa64mmfr2 }, { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index fb21ab9e73..3bae9e4a66 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -549,6 +549,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ARM64_SYS_REG(3, 0, 0, 7, 0)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, ARM64_SYS_REG(3, 0, 0, 7, 1)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, + ARM64_SYS_REG(3, 0, 0, 7, 2)); /* * Note that if AArch32 support is not present in the host, From patchwork Sat Feb 8 12:58:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183235 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1955211ile; Sat, 8 Feb 2020 05:10:13 -0800 (PST) X-Google-Smtp-Source: APXvYqwNhutO8Odbw4sRMwz6zV/6xW5cLV3wCZS36Zt5A3Wtjec/t5qq7ic87Kb+EOYPmQZqyt1I X-Received: by 2002:a05:6214:1149:: with SMTP id b9mr2669653qvt.227.1581167413455; Sat, 08 Feb 2020 05:10:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581167413; cv=none; d=google.com; s=arc-20160816; b=Q7huVOiIJEyJrVxM7P5Tu6tvDJ0jFDJZKfDnFAUsxreAdXsMx2ayPJpR5X9qrDmREp jew2Q0XcijMJp1BfNmV1BXBFmhdfrMQTyx4/ESKFZvonphqFmcoejiDtR0+7PTAhXMro ixHQmsGB0dBXKGRUJurDPNe1rzA2P+vDZX2B51xyho5sEFnz48Yqmg0kkUArhF1h2BdN FLYE1ELHn2E7R57CiZcepSqJxk1BMC1zRxJ++pYaIbjqYzzPYkofu7AL15TS1TCn4+20 sOHrxW5b0y0koP3UJ4B7TbP7LM6PVgBUYxjF4esy1qFBKizW3Dj5ZHUQGRXc5Iw69FML czEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Mdjhvy7wmcGZ9rsKN0Hq6HG9JnMWN4n96rrfZwt5buc=; b=pYXQqeQOjAhLfGpW1VekAWEzVO5s9NB/brbG3oKuQxUUnAhD/XGAoK6re0IXUMVdkm OmNznov39yUsWAhjCslhaCdWs9gStmh4fCQzBJlXIbN7zoGtPopbdnYcmmftfhng8bJk oL70hZAjDFIjmiBAzAr/Psi4qBPrZbaYpovCnOtcmcv0vV5kHTMEgdqYlygJ+hN4aVNn Yygx0ZFjHNbZ0iysOzPXzAgKDj+wP2MHjZsZ6anhCJUf93Ak+JBmA3j1ALwPI69Varl3 ikTIBn6LP15q358lEL3v6kj1ffh7AjkepoHbSSiEh//Bvl8CCI0ArWEY1xGjlPEWvO1a NU+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Sf0oRc15; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i7si1497336qkh.186.2020.02.08.05.10.13 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:10:13 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Sf0oRc15; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41378 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0PsD-0006qH-1g for patch@linaro.org; Sat, 08 Feb 2020 08:10:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41555) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Ph0-0000z8-Do for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgz-0005Ee-5M for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:38 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:43669) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgy-0005DM-V4 for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:37 -0500 Received: by mail-wr1-x441.google.com with SMTP id z9so2005541wrs.10 for ; Sat, 08 Feb 2020 04:58:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Mdjhvy7wmcGZ9rsKN0Hq6HG9JnMWN4n96rrfZwt5buc=; b=Sf0oRc159rjudaRbfeqDtkUK6waFsMmyxGRLd9H2DZUSGOMbfqhT3cvL6yKH/Wj7nm zpvbbUAPoqnfiDgWJp4/B27tQ77Oe4oj9hdwAkLDSlraLuWii+7OA0oj8z6TjgjGgxD+ hFfpLzwWzVkvBaEteaA44I8QJGrk6hWU2IrAySHUI06YWepPDjOQHFU3hkCMZ5jj89gp l51PRKLFlxA0V3EtcsSelJL4gJWM4+Qm+pLi6IMs6dF8v0ikvq+xwGjqltOYRVohsS4b tTh8tKWueG8k0G1kOiUrSIi+g9MmLhjgOI/Zyv7iLZXazNtCH2blYWg6MD9o6LM6MDt6 ZRNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Mdjhvy7wmcGZ9rsKN0Hq6HG9JnMWN4n96rrfZwt5buc=; b=gSJoBE/WtMhxVEteN2G5t8cXG1hWOnA0DqJ6Pknw1r0i96F7wxEJzcSu+eRusqw48Q dZdfnhTAn5HGmxw83jFKIySPzs5yMZauPy1O8Q4NBAIECjEI9tixT68qrKHXb1RLj3Nf GtjxNwltb1dCZEOts/VrvHlWEjCZQ7CA31IV9lbhy9BsboU5Ds5z8STpCCvyMveNIXS9 eWTDGSIQYZxhZxWMRy/dN2qE2/nPhr+sZ7MwQkfpqNkQ9ymdhdydqUIEzBZCV+/V6UNt gSt0yxKsvhCNb+GiLBquAnq3ZWxfId1C8YQR/0yBybcNlIZwIk/VQs0etmoXZIdHDvJC rjiQ== X-Gm-Message-State: APjAAAWg6j7jKXDFFqN7JlvvfxeZfLwg/dWueUPazdktI9Zk+asfceh2 LqAvTKlNSWwze4ViWf+CFCZJqz+uMItDXA== X-Received: by 2002:adf:dd46:: with SMTP id u6mr5140608wrm.13.1581166715726; Sat, 08 Feb 2020 04:58:35 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 18/20] target/arm: Update MSR access to UAO Date: Sat, 8 Feb 2020 12:58:14 +0000 Message-Id: <20200208125816.14954-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Move reginfo to file scope; avoid setting uao from spsr when the feature is not enabled (pmm). v3: Update for aarch64_pstate_valid_mask --- target/arm/cpu.h | 6 ++++++ target/arm/internals.h | 3 +++ target/arm/helper.c | 21 +++++++++++++++++++++ target/arm/translate-a64.c | 14 ++++++++++++++ 4 files changed, 44 insertions(+) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 71879393c2..e943ffe8a9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1253,6 +1253,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) #define PSTATE_PAN (1U << 22) +#define PSTATE_UAO (1U << 23) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) @@ -3642,6 +3643,11 @@ static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; } +static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; +} + static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; diff --git a/target/arm/internals.h b/target/arm/internals.h index 4a139644b5..58c4d707c5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1112,6 +1112,9 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) if (isar_feature_aa64_pan(id)) { valid |= PSTATE_PAN; } + if (isar_feature_aa64_uao(id)) { + valid |= PSTATE_UAO; + } return valid; } diff --git a/target/arm/helper.c b/target/arm/helper.c index d29722d8ac..11a5f0be52 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4191,6 +4191,24 @@ static const ARMCPRegInfo pan_reginfo = { .readfn = aa64_pan_read, .writefn = aa64_pan_write }; +static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_UAO; +} + +static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); +} + +static const ARMCPRegInfo uao_reginfo = { + .name = "UAO", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4, + .type = ARM_CP_NO_RAW, .access = PL1_RW, + .readfn = aa64_uao_read, .writefn = aa64_uao_write +}; + static CPAccessResult aa64_cacheop_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -7664,6 +7682,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, ats1cp_reginfo); } #endif + if (cpu_isar_feature(aa64_uao, cpu)) { + define_one_arm_cp_reg(cpu, &uao_reginfo); + } if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { define_arm_cp_regs(cpu, vhe_reginfo); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d8ba240a15..7c26c3bfeb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1602,6 +1602,20 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, s->base.is_jmp = DISAS_NEXT; break; + case 0x03: /* UAO */ + if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_UAO); + } else { + clear_pstate_bits(PSTATE_UAO); + } + t1 = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, t1); + tcg_temp_free_i32(t1); + break; + case 0x04: /* PAN */ if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) { goto do_unallocated; From patchwork Sat Feb 8 12:58:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183233 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1952587ile; Sat, 8 Feb 2020 05:07:29 -0800 (PST) X-Google-Smtp-Source: APXvYqxVkCBnJhABB8hxlJ/VxsPsvhHI3Gq1QX86wuEmWhzq1+ksnXM9oW7BlZcjcOriGxNjGoDg X-Received: by 2002:a0c:c542:: with SMTP id y2mr2682500qvi.225.1581167249357; Sat, 08 Feb 2020 05:07:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; 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[209.51.188.17]) by mx.google.com with ESMTPS id t37si1473252qth.239.2020.02.08.05.07.29 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:07:29 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Hq2l7CnX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41210 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0PpY-0001Ye-Tp for patch@linaro.org; Sat, 08 Feb 2020 08:07:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41565) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Ph1-00011R-6m for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Ph0-0005Gq-6Z for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:39 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:33984) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgz-0005FV-Vz for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:38 -0500 Received: by mail-wr1-x441.google.com with SMTP id t2so2072875wrr.1 for ; Sat, 08 Feb 2020 04:58:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6QhxeX6zK49ooY7+NT0s0wBH571TqTaLG1uXkEqzD/o=; b=Hq2l7CnX356ZC7G1PTAnahBVSZo3OvL/OYoSzyHE/WdonV+n1MvYaqFAaiy2XWAzmM thh1CJrEgwoAQdewaE1jheTaJgVhz2Y/7Y7X2DdT+bzmG2RBX4A75UFr7tR6hLy0wkGg 3yOUmLd7bxDrPk2QU6y7UlVh95Q0kRvY/L+lngPLZybdQ5peV+tWMlr/Ic4UZ5+veTwA sLYrH1RRAv/Wcj/yAcrg0xwESGkEOd4EIvc0t/yxqBRXNuuG0NH/S1XnUlggY8csy7YN fAcENAE5wHwkYFKD6ygVAEmwvEjyZfrbUJCMKUVQcqFQIC0EOnQPthUaMpSslaSfvyZt +mfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6QhxeX6zK49ooY7+NT0s0wBH571TqTaLG1uXkEqzD/o=; b=tZI/TbX4XPcJ+oX+aLgt1WEVoNM90n2WraZq4Q3y26qRmJf6jmN8ZWTe8uA/o8rJ2U arFEQubO4cZy/YtYMyYiJNZkGrXmy8iWjTLPiZW6cvBoTfLsYNhj/YhTkvZPV1vxSNep mQN1iHEb5Dng1y42lJ63HPUjSqMIF0gNO3ROeWjvGTugqiA1otiLRnVvQRc2Ga8xqzqY 2uA501KytPuWh8pcGEOH93HqT+ELneVBG7ZGk6P8bljzj1Qy/7KQM6RXT2mxb9k6OlBN 4faqQKSyn9uDIuXT5189V34QnAcUVQaO+8UtGrLO8+O1aPdkSQ2SU6dXgRpLZkEvGO3u GlCw== X-Gm-Message-State: APjAAAVUM8J4VEWjrB29JqQ/AqVzY43SzCVNxvVS0NNKaGnaIRNcaMk3 CfbF66TEIFk/V1OizXxB0JGN9QQ6BPezeA== X-Received: by 2002:a05:6000:50:: with SMTP id k16mr5105725wrx.145.1581166716838; Sat, 08 Feb 2020 04:58:36 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 19/20] target/arm: Implement UAO semantics Date: Sat, 8 Feb 2020 12:58:15 +0000 Message-Id: <20200208125816.14954-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We need only override the current condition under which TBFLAG_A64.UNPRIV is set. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 41 +++++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 20 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 11a5f0be52..366dbcf460 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12198,28 +12198,29 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, } /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ - /* TODO: ARMv8.2-UAO */ - switch (mmu_idx) { - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - /* TODO: ARMv8.3-NV */ - flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); - break; - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - /* TODO: ARMv8.4-SecEL2 */ - /* - * Note that E20_2 is gated by HCR_EL2.E2H == 1, but E20_0 is - * gated by HCR_EL2. == '11', and so is LDTR. - */ - if (env->cp15.hcr_el2 & HCR_TGE) { + if (!(env->pstate & PSTATE_UAO)) { + switch (mmu_idx) { + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: + /* TODO: ARMv8.3-NV */ flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + break; + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + /* TODO: ARMv8.4-SecEL2 */ + /* + * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is + * gated by HCR_EL2. == '11', and so is LDTR. + */ + if (env->cp15.hcr_el2 & HCR_TGE) { + flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + } + break; + default: + break; } - break; - default: - break; } return rebuild_hflags_common(env, fp_el, mmu_idx, flags); From patchwork Sat Feb 8 12:58:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183236 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1955380ile; Sat, 8 Feb 2020 05:10:24 -0800 (PST) X-Google-Smtp-Source: APXvYqz7cxPIZc/O1qwppVET4VmVwIJ+oTIJDCxPIW2EtR/EKNxVKlDWIn/q/wUfGx2rw3uHKM51 X-Received: by 2002:a0c:f910:: with SMTP id v16mr2853673qvn.108.1581167423930; Sat, 08 Feb 2020 05:10:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581167423; cv=none; d=google.com; s=arc-20160816; b=zqeOmrxg8/oHgtvzMV79wR7Jf6Xhxvuj5KWilghxwey9nasWcWnmBSaTViFxKsiTxo PwLllBynXHLtgoM/z58flMbo4hL/njogdPclgjYt+3f4L29N+B+8Qy/4AMA+ezYFUoxA jYTaeNdIqC+qv4j79B4u97FXKpBEw3jRPpsOcAv9DljkrdXp5hAvrawxUexIn/vY8MnC KwB29jOcxe5D9qQEx9nT38h9zfIc36ss7ZJdfLpUu74drT+RE/g/kd8jRMHqA5wMPBsz BbVgztUPdD8M0stdObt2rpRypYpW6k6cKs8gTODf+cLJ3WwNtW7+BWUZ8VC/gieYYuEm Cx/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=n25wa1lNKzA3qMHXUq9DJlF06TNEvhgokWarr1Y211Q=; b=d0MWif73hPg/Fg4bCfYcKaL37nnqfyo4nf8zzf0uIcbkhR/mXiNpxEUN+I9a19h3NL /EVSsA68NOpD7T3to1CrHhcOgVpJhYsXyiN2k7eC63OcYKFdKgGw3O0kIBI+L+yKrULD 5BdVK/8EVhcDq0IXzwLuZmxPD0tyYiDxp0+rJz7gCG5of9GZfBWc5RKtWdUQHZT83bTJ PYKOQU/DcV0CXzk/SAmvdA236IyEmkeVSl2FkGjw0Qtzj74mXh3WokSYQdc+bSEt6bhE cuv/ZIsCk1SFqSZiLQ3OMz1kB5kp8U0atTHifzjQF+reTtTNJag/mDvevgYpAEhOUFxk u6MA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=psKcGHON; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t1si1559779qtq.174.2020.02.08.05.10.23 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:10:23 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=psKcGHON; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41382 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0PsN-0006uD-Ec for patch@linaro.org; Sat, 08 Feb 2020 08:10:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41578) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Ph2-00013t-38 for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Ph1-0005JO-0n for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:40 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:35127) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Ph0-0005HA-Qo for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:38 -0500 Received: by mail-wm1-x341.google.com with SMTP id b17so5669232wmb.0 for ; Sat, 08 Feb 2020 04:58:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n25wa1lNKzA3qMHXUq9DJlF06TNEvhgokWarr1Y211Q=; b=psKcGHONxPbVPczSPJVjt80mj8pHOVWa1UuZ9t0rLSlscGs6ASfahIYU6ZuhYSQJiN FprqaBdkdJG4A8BD6Z58ELF8rYPLvVUyAWKdvowbrW9p+Ydq7SUu1iMqKOSN+M/NVNdQ nJR/Tw+1kXNYgBg6q3vOoZAdsANhWI5lGOOI0yxXAftwzwNnQJbsCMuF+emrV7UDvl+q Nm7hGZ+n1P9UO4+CC49m0oQSWLpBXxX5gbcfFjGK1mn38RVqv+NmHjjmgZpMR91PngHQ frYXexwnlN9KaxyM/jhaIqijYx3uiTSPVeq1hFRfFWDDx5zHl8XVbyn6chTHrbLS/LBh 1LoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n25wa1lNKzA3qMHXUq9DJlF06TNEvhgokWarr1Y211Q=; b=YIlV3GHgYT9z+bkWBOnZ6g69mkRuZCd4AqGiH1YLPqJZN+xzzo3neT/rEIoj/2HU+4 vN+t6R15o1t/qsNAiEN8p3MHRO5f5wzmDMq/e9X2l6o8zYGexkEVytjuWWc/HsSUHCvB GEQdlUkmL5hP9Gvcct+x7aIgPCavEh7rwbA/RJqUjMfC1oQTFMoQNIMMJ3wdRzPziBGE PJZ+/9X0NpvkIrcdh6qNXucvQ1NVcFRjhZ+5CKa6qhf1f/7JwXTnsT4qEs1TtzL3wZDY YcYrFkN4snS4iCZMKyh5Yy/ku0R5GBC8+gcuNwl2j8N0VvQY5Ermn30HU/7LeG37GN/v 4DFQ== X-Gm-Message-State: APjAAAWAFLrCfPS/4Oe6X+XzsIXeY6c2kSjwI9xCrFjHMvuI6x8GwogN kFRfG5bXmnxXxh8EpL/Iv8IGBM36v2GD5Q== X-Received: by 2002:a7b:cb42:: with SMTP id v2mr4459485wmj.170.1581166717682; Sat, 08 Feb 2020 04:58:37 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 20/20] target/arm: Enable ARMv8.2-UAO in -cpu max Date: Sat, 8 Feb 2020 12:58:16 +0000 Message-Id: <20200208125816.14954-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.20.1 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 57fbc5eade..1359564c55 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -676,6 +676,10 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ cpu->isar.id_aa64mmfr1 = t; + t = cpu->isar.id_aa64mmfr2; + t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); + cpu->isar.id_aa64mmfr2 = t; + /* Replicate the same data to the 32-bit id registers. */ u = cpu->isar.id_isar5; u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */