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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f9e1d60b57sm33888a91.9.2025.02.04.13.54.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 13:54:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 01/12] meson: Drop tcg as a module Date: Tue, 4 Feb 2025 13:53:48 -0800 Message-ID: <20250204215359.1238808-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250204215359.1238808-1-richard.henderson@linaro.org> References: <20250204215359.1238808-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This reverts commit dae0ec159f9 ("accel: build tcg modular"). The attempt was only enabled for x86, only modularized a small portion of tcg, and in more than 3 years there have been no follow-ups to improve the situation. Reviewed-by: Thomas Huth Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/meson.build | 11 ++++------- meson.build | 18 +----------------- 2 files changed, 5 insertions(+), 24 deletions(-) diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index aef80de967..69f4808ac4 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -21,16 +21,13 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', 'watchpoint.c', + 'tcg-accel-ops.c', + 'tcg-accel-ops-mttcg.c', + 'tcg-accel-ops-icount.c', + 'tcg-accel-ops-rr.c', )) system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'icount-common.c', 'monitor.c', )) - -tcg_module_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( - 'tcg-accel-ops.c', - 'tcg-accel-ops-mttcg.c', - 'tcg-accel-ops-icount.c', - 'tcg-accel-ops-rr.c', -)) diff --git a/meson.build b/meson.build index 2c9ac9cfe1..b72114819b 100644 --- a/meson.build +++ b/meson.build @@ -322,12 +322,6 @@ if cpu in ['x86', 'x86_64'] } endif -modular_tcg = [] -# Darwin does not support references to thread-local variables in modules -if host_os != 'darwin' - modular_tcg = ['i386-softmmu', 'x86_64-softmmu'] -endif - ################## # Compiler flags # ################## @@ -3279,11 +3273,6 @@ foreach target : target_dirs if sym == 'CONFIG_TCG' or target in accelerator_targets.get(sym, []) config_target += { sym: 'y' } config_all_accel += { sym: 'y' } - if target in modular_tcg - config_target += { 'CONFIG_TCG_MODULAR': 'y' } - else - config_target += { 'CONFIG_TCG_BUILTIN': 'y' } - endif target_kconfig += [ sym + '=y' ] endif endforeach @@ -3642,7 +3631,6 @@ util_ss = ss.source_set() # accel modules qtest_module_ss = ss.source_set() -tcg_module_ss = ss.source_set() modules = {} target_modules = {} @@ -3803,11 +3791,7 @@ subdir('tests/qtest/libqos') subdir('tests/qtest/fuzz') # accel modules -tcg_real_module_ss = ss.source_set() -tcg_real_module_ss.add_all(when: 'CONFIG_TCG_MODULAR', if_true: tcg_module_ss) -specific_ss.add_all(when: 'CONFIG_TCG_BUILTIN', if_true: tcg_module_ss) -target_modules += { 'accel' : { 'qtest': qtest_module_ss, - 'tcg': tcg_real_module_ss }} +target_modules += { 'accel' : { 'qtest': qtest_module_ss }} ############################################## # Internal static_libraries and dependencies # From patchwork Tue Feb 4 21:53:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861848 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:11cb:b0:385:e875:8a9e with SMTP id i11csp525504wrx; Tue, 4 Feb 2025 13:54:51 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVmcZ5Z6EkcgHgpjhxNCZtFdqTfvMWZZ49QmcYLPT/Z3MLj1rQd+dBiPWLK3uSVsu+Q8XtpZA==@linaro.org X-Google-Smtp-Source: AGHT+IFsgYYlgUXI1Ug8ENLZGR6Ux5idGNIBy2f0aGo2Ovf2RP+vqAObpfkojQHnojos2AcX9VPb X-Received: by 2002:ad4:4ee8:0:b0:6e2:485d:fde6 with SMTP id 6a1803df08f44-6e42fbb1c73mr4957466d6.15.1738706091737; Tue, 04 Feb 2025 13:54:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738706091; cv=none; d=google.com; s=arc-20240605; b=R69hd9beaxaPXjSZWjss403gb2/cfYEFIshS0VL/kNXEwZvTqY5NXj11KAzJEb7zsM /TGkqLd7sLpbyemA3dNKocAeilFvXIuALk017cr00uXH+MQdVLokiPRvgMFYq5P5OJnd 9QED0jDbF30Uam8ZgeD1+EAtt5wCtJLGXgFlGbwaJuap5MFpStgYWNPxFHIrf7rhruCx 08Q0fBhhd5y0uUdanFzIPC/4uRHNbCjSTSdJkq8ajunXxPuZXwqDCFhsAG+CNr3H24u9 kVnZtla9dYIzJaxHFdvsAziSevzmDiBYSdjJbvuKnz7/wlUKnY3IMCpcnRnM9JzhZXAQ oySg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=b0+vQ/EpH+1Ge24XXY5IBMPR1lS4eEvzXBLIAsOfJmA=; fh=WBfWBA4xhLBT7XcACU9php1VkQFXD3CDPq61lYOQNqc=; b=RcCtAOPOaQQGahoFZEEuAX88fC/BuyLM1eKOTtP08JeJ583RhRwgCmd2FAMQ+oeEvd 6X7d5Evea69F4NEKjEx3hh3ZkdZ3JfglR+q0t6f0q9dLQ324o+LFWpvyeG7MkF1BYdqL QW7kTqaZwR5ffqU2Ch0m9IDwlrf+TM4y0uKq78vJ2ZpwPFWMbAqiZTL+wmPpLj1nBCYO c65Vr1Uj3VhoKC3iiDa716HcbjXKX3uQFQvPfE83bXyykT5GEsOcZ5bu6Tf0azFGPoN1 ziv/9glsunKc1nVW2g8wZtuH02plYMSYqvXh8rEJZGDqY6eAGFQaujwtJ/f0voiQFmXV nL3w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LTvYNsQR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f9e1d60b57sm33888a91.9.2025.02.04.13.54.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 13:54:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 02/12] tcg: Move stubs in tcg/perf.h to tcg/perf-stubs.c Date: Tue, 4 Feb 2025 13:53:49 -0800 Message-ID: <20250204215359.1238808-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250204215359.1238808-1-richard.henderson@linaro.org> References: <20250204215359.1238808-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org These are not called so frequently as to be performance sensitive. Reviewed-by: Thomas Huth Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/tcg/perf.h | 23 ----------------------- tcg/perf-stubs.c | 26 ++++++++++++++++++++++++++ tcg/meson.build | 2 ++ 3 files changed, 28 insertions(+), 23 deletions(-) create mode 100644 tcg/perf-stubs.c diff --git a/include/tcg/perf.h b/include/tcg/perf.h index c96b5920a3..050ba855ab 100644 --- a/include/tcg/perf.h +++ b/include/tcg/perf.h @@ -7,7 +7,6 @@ #ifndef TCG_PERF_H #define TCG_PERF_H -#if defined(CONFIG_TCG) && defined(CONFIG_LINUX) /* Start writing perf-.map. */ void perf_enable_perfmap(void); @@ -23,27 +22,5 @@ void perf_report_code(uint64_t guest_pc, TranslationBlock *tb, /* Stop writing perf-.map and/or jit-.dump. */ void perf_exit(void); -#else -static inline void perf_enable_perfmap(void) -{ -} - -static inline void perf_enable_jitdump(void) -{ -} - -static inline void perf_report_prologue(const void *start, size_t size) -{ -} - -static inline void perf_report_code(uint64_t guest_pc, TranslationBlock *tb, - const void *start) -{ -} - -static inline void perf_exit(void) -{ -} -#endif #endif diff --git a/tcg/perf-stubs.c b/tcg/perf-stubs.c new file mode 100644 index 0000000000..ce2dd1a4b7 --- /dev/null +++ b/tcg/perf-stubs.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* TCG perf stubs */ + +#include "qemu/osdep.h" +#include "tcg/perf.h" + +void perf_enable_perfmap(void) +{ +} + +void perf_enable_jitdump(void) +{ +} + +void perf_report_prologue(const void *start, size_t size) +{ +} + +void perf_report_code(uint64_t guest_pc, TranslationBlock *tb, + const void *start) +{ +} + +void perf_exit(void) +{ +} diff --git a/tcg/meson.build b/tcg/meson.build index 69ebb4908a..2977df5862 100644 --- a/tcg/meson.build +++ b/tcg/meson.build @@ -25,6 +25,8 @@ endif tcg_ss.add(when: libdw, if_true: files('debuginfo.c')) if host_os == 'linux' tcg_ss.add(files('perf.c')) +else + tcg_ss.add(files('perf-stubs.c')) endif tcg_ss = tcg_ss.apply({}) From patchwork Tue Feb 4 21:53:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861847 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:11cb:b0:385:e875:8a9e with SMTP id i11csp525500wrx; Tue, 4 Feb 2025 13:54:51 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWWIEJpt1FdRnGNH6Mv+0sdJo7ZAf/2fpBdA/2olcU10MSj+Yl2m4y47ahCWnaXZLmdT6UlCQ==@linaro.org X-Google-Smtp-Source: AGHT+IEq8annBTYz9SVjpxNkoCZTrot/OZ6Hn9/UO9DI+YBglNPWh8f32vYq8gc6nFslN2mb+x3j X-Received: by 2002:a05:622a:1b13:b0:46f:d6c3:2dc7 with SMTP id d75a77b69052e-470281ced17mr5588581cf.23.1738706091454; Tue, 04 Feb 2025 13:54:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738706091; cv=none; d=google.com; s=arc-20240605; b=IecSzbD3rI8Zc+AAwBx3Djl+gxCUUnJpaO4M7tqxuqHVoX0/GmskH3ZeRxChh6c9Tu hd8kufphMEYySWZLa1CV22C44R1f8/UlNwSoyTpIPQ1DgNZ34JHWjSY1515TfcjXViPT WNIT51ilVRwRUVv8SsjyCeTPW1e1JcMsB6pcWbzpvzP3oh5e2+7ic3ypqICtBZcZKs2d 4QqVLVG7ydAK86Eb4FgYuNxzpQl9F+2qVkuByKhJTbZYM2KPFBJ/btJngkuIGXOPxgc/ HEmCrLQTX6cL2KP1CW430T0uxAFvZxXw9LnQdR7T1TXYhetuB7eulo8nMaNjCFz52lLx nWvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=AKQNLi/LAdrzzrDV1L5+9YwVJWRO7OgsuSiBwshaaYQ=; fh=WBfWBA4xhLBT7XcACU9php1VkQFXD3CDPq61lYOQNqc=; b=OV/pTLiga6W0UMcZjUhdwy8mVdnSvX0UdqQ2B8F+s8vxXnZ+4UDj4W0EjQIoWS03EF jiJsHTtnrrylSRP3EXffZyCk9+myHK0ZzXAcET0i1veRJOcPIzSOWX/8SsjLOi6aOQoQ lUUBwKHQZJ2oTBVSErGsPHyf/oDH+9Pi1uKP8RTZYSF+aU8mmrpUE3wXxU/ELy7rpx+2 t8HxKaB+8eHYtr2TwsbfaqDhKCHREk2Vy7u/TOTfOhti3GLpPEYxsLUzqzHK3dJVbW3e X2H8Wks861o9l2gjtnwlSxqFu2ButVtoZO34RpIiIRg0R6gZLAgCOcOd+l+crwZhjOiB w2hw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZTxUwRMM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f9e1d60b57sm33888a91.9.2025.02.04.13.54.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 13:54:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 03/12] plugins: Uninline qemu_plugin_add_opts Date: Tue, 4 Feb 2025 13:53:50 -0800 Message-ID: <20250204215359.1238808-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250204215359.1238808-1-richard.henderson@linaro.org> References: <20250204215359.1238808-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org No need to expand this function inline. Unexport qemu_plugin_opts to match. Reviewed-by: Thomas Huth Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/qemu/plugin.h | 9 +-------- plugins/loader.c | 7 ++++++- 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h index 9726a9ebf3..3efded6a3e 100644 --- a/include/qemu/plugin.h +++ b/include/qemu/plugin.h @@ -11,7 +11,6 @@ #include "qemu/qemu-plugin.h" #include "qemu/error-report.h" #include "qemu/queue.h" -#include "qemu/option.h" #include "qemu/plugin-event.h" #include "qemu/bitmap.h" #include "exec/memopidx.h" @@ -44,13 +43,7 @@ get_plugin_meminfo_rw(qemu_plugin_meminfo_t i) } #ifdef CONFIG_PLUGIN -extern QemuOptsList qemu_plugin_opts; - -static inline void qemu_plugin_add_opts(void) -{ - qemu_add_opts(&qemu_plugin_opts); -} - +void qemu_plugin_add_opts(void); void qemu_plugin_opt_parse(const char *optstr, QemuPluginList *head); int qemu_plugin_load_list(QemuPluginList *head, Error **errp); diff --git a/plugins/loader.c b/plugins/loader.c index ebc01da9c6..35680bfc13 100644 --- a/plugins/loader.c +++ b/plugins/loader.c @@ -55,7 +55,7 @@ struct qemu_plugin_parse_arg { struct qemu_plugin_desc *curr; }; -QemuOptsList qemu_plugin_opts = { +static QemuOptsList qemu_plugin_opts = { .name = "plugin", .implied_opt_name = "file", .head = QTAILQ_HEAD_INITIALIZER(qemu_plugin_opts.head), @@ -65,6 +65,11 @@ QemuOptsList qemu_plugin_opts = { }, }; +void qemu_plugin_add_opts(void) +{ + qemu_add_opts(&qemu_plugin_opts); +} + typedef int (*qemu_plugin_install_func_t)(qemu_plugin_id_t, const qemu_info_t *, int, char **); extern struct qemu_plugin_state plugin; From patchwork Tue Feb 4 21:53:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861856 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:11cb:b0:385:e875:8a9e with SMTP id i11csp525891wrx; Tue, 4 Feb 2025 13:56:07 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXpuA4g3q50xBilCUMSy96JRa33XDaAnNOBj6k+9CwLeZRsHI/wWcf4DPSMZXQX73+HBvU4+g==@linaro.org X-Google-Smtp-Source: AGHT+IElPkmMIm1xcuXXugTRic85ZASZEWNjhLCz8ePHd8ceooriysJmJffToZRCLx52P6hp5Eoo X-Received: by 2002:a05:620a:240a:b0:7a9:afef:33e6 with SMTP id af79cd13be357-7c039fbfb6bmr52506985a.34.1738706167671; Tue, 04 Feb 2025 13:56:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738706167; cv=none; d=google.com; s=arc-20240605; b=MkT00fTwUcFQ5/4T0d/eurvYQ+CvqYnzGP/NcLqvmK2/TORTczsylRNyJseXAYD6CM aZT9Nakn0RImmPRqSVJMzwguGx2fkRFtHh8bDDgqqOeecBK3P3InV4Z3XCTzUIkArnKO 01vwrTkeTi+F1raDJpQ3jM5kXsTnWVmk/Na/5WhLdmfc+YDiVSsoNvdN4NW21iivebAQ q81A0wEPjfjUlvj0J3kE3tl+OeYrdBmdFlc2q/hMZHjuS65SrViroC0YWehJSFT7n5WP okqmusPil8bx+db8byxc7U5yHpkqnjZIikl8gNhxy7CVOF/cZ4lDw15HfOAG6JUxCG6d jrmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4SBoep/xPxJrFv8mDouvokBTO/0tkAwIyQsgJPv3zeU=; fh=kJMCMx+0ERv7a3rbsYoH9j+lG6+DeyggCoQTi5fJs3w=; b=jdZNcWe/gwG14sthg6055oLLq2hsxTO7lYldQ9Qzt982A7h2v4DEO5Gj9SaFD68KfE 3u/2MGCP7/BH/OlYnzbmwmVWmSm9MJZqS5KQtraRgFctpulTZ6qz+CY6xqZnX4/zFBtk mNKjAuYBYL1qXTsGys0SrGfX1PtnNccHPpCZr4PJct6+DwGTQ+6f4IfmcAl1DZNNMs4x cAokUilYsIRqamJOkIcQXMZ1FaYBsVvpSRSd4EvUGIWCCxM6ppp2Z/VMqduu6fPqkEvu BkebaO9qyDit9EK+NsMJ99CAGaUaeTPLNPqW9rUQOaHRZ6NIFvcTPiKx+QiYocyq5amc +Cjg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TtSo2SOZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f9e1d60b57sm33888a91.9.2025.02.04.13.54.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 13:54:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v3 04/12] meson: Disallow 64-bit on 32-bit KVM emulation Date: Tue, 4 Feb 2025 13:53:51 -0800 Message-ID: <20250204215359.1238808-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250204215359.1238808-1-richard.henderson@linaro.org> References: <20250204215359.1238808-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Require a 64-bit host binary to spawn a 64-bit guest. Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé --- meson.build | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/meson.build b/meson.build index b72114819b..5a40a2a629 100644 --- a/meson.build +++ b/meson.build @@ -277,21 +277,27 @@ else host_arch = cpu endif -if cpu in ['x86', 'x86_64'] +if cpu == 'x86' + kvm_targets = ['i386-softmmu'] +elif cpu == 'x86_64' kvm_targets = ['i386-softmmu', 'x86_64-softmmu'] elif cpu == 'aarch64' kvm_targets = ['aarch64-softmmu'] elif cpu == 's390x' kvm_targets = ['s390x-softmmu'] -elif cpu in ['ppc', 'ppc64'] +elif cpu == 'ppc' + kvm_targets = ['ppc-softmmu'] +elif cpu == 'ppc64' kvm_targets = ['ppc-softmmu', 'ppc64-softmmu'] -elif cpu in ['mips', 'mips64'] +elif cpu == 'mips' + kvm_targets = ['mips-softmmu', 'mipsel-softmmu'] +elif cpu == 'mips64' kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu'] -elif cpu in ['riscv32'] +elif cpu == 'riscv32' kvm_targets = ['riscv32-softmmu'] -elif cpu in ['riscv64'] +elif cpu == 'riscv64' kvm_targets = ['riscv64-softmmu'] -elif cpu in ['loongarch64'] +elif cpu == 'loongarch64' kvm_targets = ['loongarch64-softmmu'] else kvm_targets = [] From patchwork Tue Feb 4 21:53:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861854 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:11cb:b0:385:e875:8a9e with SMTP id i11csp525828wrx; Tue, 4 Feb 2025 13:55:53 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU3A+qGESl58S3B5XoxVO/+WTeS9UD6On+wXyLCYfG3R6BPq9jjJECNXIJrPIKkwegHvc+VCg==@linaro.org X-Google-Smtp-Source: AGHT+IGbsRE02598LYjZ/B9hHSZk+myUbLQ5MV69bQcE0xAc73j5wkTI/rmCfuhpPBqPHbKuHZhP X-Received: by 2002:a05:622a:4a07:b0:463:6bc4:2a23 with SMTP id d75a77b69052e-47027ff316dmr4819751cf.0.1738706153753; Tue, 04 Feb 2025 13:55:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738706153; cv=none; d=google.com; s=arc-20240605; b=UwTEzaVraz47eo6kWB6y57oG4rr6NKof11JGBGQUPp9cXI0CHlOB33uI1HUsDHuWJf 0tqbsaNyUmdmK0V5SEFoUwLrZG1k25BtddRz7rWLk3Az+/TtwDwyER3aqjlKZeUrlXvf Mna9BA/cUJLxSXPZX+UdNvC+lQ/SNbr0yWO9IQGM7vNde7kkdzpD1q90hrN6aiCAU3Cw vKxeGHnWikJ5efv20Mf8V50JnP/WF3mKa07ADTf1wA0nXXXbvZrJs5HKud8o08fJFQF7 NBpIlNklJYxR5YM3A1IdhA1NloX5CvoJVeGEaY6erolTdRebvPhY8UpppQyOSx1a62Vp 3PSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KlDbZXrgGBhVV0MB00OdW/jeiXnekdaairr3vgBziX4=; fh=kJMCMx+0ERv7a3rbsYoH9j+lG6+DeyggCoQTi5fJs3w=; b=GZL+/rzOfUwVHP5I4ncAj28tq/jVGs5flqsDAL7kQ8B4+zSbn9A7BwCA2BKAg/QGoF S6b/AIZW5JzdwMXqvXXCh031SwPPIuxrYJDBPOzpkUeAIPX6gvnG+GBLlE9+DB07it8Z m1USvQVoQLpnAGivn9nU+Z0KbdKJSPu2l+NazC/Bsy6I7L1pGgnnjTZHZFbo5WRWgpfw FT+V7HdZ2mI4HiN9+E1f3kYaxyOOFMpojvckZOAJidBHIcENUO4xLBpkBO6HKiflLqM1 s0XkIObTFsAsoy4F/i/Mk56++BsAK8WYMpK+dFIX0556Y4MLdthraWnvI9CBrRZrqBhp iWew==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z5GeLEU5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f9e1d60b57sm33888a91.9.2025.02.04.13.54.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 13:54:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v3 05/12] meson: Disallow 64-bit on 32-bit Xen emulation Date: Tue, 4 Feb 2025 13:53:52 -0800 Message-ID: <20250204215359.1238808-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250204215359.1238808-1-richard.henderson@linaro.org> References: <20250204215359.1238808-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Require a 64-bit host binary to spawn a 64-bit guest. Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth --- meson.build | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/meson.build b/meson.build index 5a40a2a629..0ca83135e2 100644 --- a/meson.build +++ b/meson.build @@ -304,9 +304,14 @@ else endif accelerator_targets = { 'CONFIG_KVM': kvm_targets } -if cpu in ['x86', 'x86_64'] +if cpu == 'x86' + xen_targets = ['i386-softmmu'] +elif cpu == 'x86_64' xen_targets = ['i386-softmmu', 'x86_64-softmmu'] -elif cpu in ['arm', 'aarch64'] +elif cpu == 'arm' + # i386 emulator provides xenpv machine type for multiple architectures + xen_targets = ['i386-softmmu'] +elif cpu == 'aarch64' # i386 emulator provides xenpv machine type for multiple architectures xen_targets = ['i386-softmmu', 'x86_64-softmmu', 'aarch64-softmmu'] else From patchwork Tue Feb 4 21:53:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861853 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:11cb:b0:385:e875:8a9e with SMTP id i11csp525692wrx; Tue, 4 Feb 2025 13:55:27 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVzpuiyWzZoNjqMC1OsETzpuQ4hNBYxbgrP9pxCRtHmVHOoVN3I64bjjqG9Qe+XAngkl26llQ==@linaro.org X-Google-Smtp-Source: AGHT+IGy1qbBCbERGRWkMX7J83oyda9e5teS8Y0JDptEoGMpxB3c1Ym/BvTzbPhZherbMrHIHSc9 X-Received: by 2002:a05:6214:4507:b0:6d8:aa52:74a3 with SMTP id 6a1803df08f44-6e42fc2083amr6815256d6.28.1738706127237; Tue, 04 Feb 2025 13:55:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738706127; cv=none; d=google.com; s=arc-20240605; b=M1lq8B1D8o9FCcRQAag389W6wYuNSptC5arDa2M5nd/zL857CkWIF8fkxl1w956RoY G/bUU8A2hr8ly8h2FPmmh6qykh7x8nE4Hm953HHu1hvbUji+Mj07w/oF71fxSXvS2wjG iwyyKl9upySxhPYy674vOCbBXp/Rx5AEY6I3rmolazdGHqJsHvmUPzt1TFvKvvd751HT Ko6n5ii+5pDH3I5P5Em82kO/pgKJdyUUj8nBDpHxQBd31ORpHUk961eyYblbqpTKIdWv 4FNR1wRwH3z+4raJrP97pxbxYb+Fpv+VXAVsmYlw/wDivbOchV1b2vh92vHfvnHQFY7S 9E3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=kKWqfZr/ly3gmQRbhv9ZVAtml+TTp731tjlwJ2lULuY=; fh=kJMCMx+0ERv7a3rbsYoH9j+lG6+DeyggCoQTi5fJs3w=; b=B3PNvCtnZ7AC6z9xz1LUzWdPDiAEm+S7LQAJdQbaN78KiywOy2blj4UZ2UFi0zelnD twKuzqy+0aA5FFNRutrKaof0FfNJue5xei/weiFi8yjpQt+wMV2HixA000WVvhBtiAqi 8U80fgjJLXVyGk3CAU4KwlSOLo1qyE4r9dC/6qKKWnt8CWn4CKyWxQFva3rvtPE4hDV2 DhBIZOnS8aykmWaYmSu8Lp+gK85EocsB1VrdBvxyEb5XpEaN1vbsdFUk9HQloenxAKri OeeJIwgUmR3G2lTzcvpFRlckWdsm9pa++f5KZf0TP1I+eZTU28VKegvdkYcCM6PK8/3Q 1z9g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eomqP4u+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f9e1d60b57sm33888a91.9.2025.02.04.13.54.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 13:54:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v3 06/12] meson: Disallow 64-bit on 32-bit HVF/NVMM/WHPX emulation Date: Tue, 4 Feb 2025 13:53:53 -0800 Message-ID: <20250204215359.1238808-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250204215359.1238808-1-richard.henderson@linaro.org> References: <20250204215359.1238808-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Require a 64-bit host binary to spawn a 64-bit guest. For HVF this is trivially true because macOS 11 dropped support for 32-bit applications entirely. Signed-off-by: Richard Henderson --- meson.build | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/meson.build b/meson.build index 0ca83135e2..c80382befd 100644 --- a/meson.build +++ b/meson.build @@ -319,13 +319,16 @@ else endif accelerator_targets += { 'CONFIG_XEN': xen_targets } -if cpu in ['aarch64'] +if cpu == 'aarch64' accelerator_targets += { 'CONFIG_HVF': ['aarch64-softmmu'] } -endif - -if cpu in ['x86', 'x86_64'] +elif cpu == 'x86' + accelerator_targets += { + 'CONFIG_NVMM': ['i386-softmmu'], + 'CONFIG_WHPX': ['i386-softmmu'], + } +elif cpu == 'x86_64' accelerator_targets += { 'CONFIG_HVF': ['x86_64-softmmu'], 'CONFIG_NVMM': ['i386-softmmu', 'x86_64-softmmu'], From patchwork Tue Feb 4 21:53:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861855 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:11cb:b0:385:e875:8a9e with SMTP id i11csp525849wrx; Tue, 4 Feb 2025 13:55:59 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWQ6FFjKa/H1JAzhOp0Fd/G2eIpK3QHrpIhSeaNqC/pGWzZMClhc6c/lzHGbPWqd1axBn3+4g==@linaro.org X-Google-Smtp-Source: AGHT+IGhfkZ5w1KP0LM9MAgkNOVg2bnBask1tmGYDuvvv9CUuThegWb9g3H02K92rBHZG6FIDoWW X-Received: by 2002:a05:6214:e86:b0:6d4:215d:91b5 with SMTP id 6a1803df08f44-6e42fb4c8femr5084946d6.11.1738706159481; Tue, 04 Feb 2025 13:55:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738706159; cv=none; d=google.com; s=arc-20240605; b=TYWPZSTgzOwekIMMdXJFUwc3GPQJuZSDyN99drMDQlzHkU5b/ONc95it0u4inpq5cA xvrLiRlJBLkJmQRREhFtQDMgzKFYs8+cch3nac8Jxjz6DuWAlBF+cwXl3WJ83S+aOLhW 1N9jeZr4C6uFXN5W6cM8dT7O/kWVd1a6p6v8mL6cPT+B74kcELoqcVgZV+t05PqRsD4r eVRCWuXKPqZOfocNscraht9ZF1gPOw/xkKNh1FXlYf6mrz4mPoeYi4Mm38rSnVGwaTco 2sAQ4d0UKMRaBw1k2iXK4V0yRes2fPuGqNpFpMJlGaOThyf4r2A1JzXDPXD3eQVAuwel kumg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=j2FzoHSuAoX+1zQ7RA2/urh/hio8OfZSmlzrSvDG4W4=; fh=WBfWBA4xhLBT7XcACU9php1VkQFXD3CDPq61lYOQNqc=; b=LztWNTk3vAWDDUHT+L2sVnKc3mMyM65G+Ge97gp6lA3JtLHxCw4MjeK3mUOg7u543r L4WL5wxYm5CTvWXBLTrR01B/CsFzor854+1waOi1X+9r47CRaycbW8UUmB+SRUGnGLEZ PI3QoeGByySfjRmmKhiUtu1sHqWoR/PsOt/VMK7sg15rs0IvXuzrng9nn9RMMyGPtn7v v9KurIg08S/KHYjGCxb3zv3O8VTLX+Pe+6YF//AMG/UT2vASU5zBBODvqHqmnyQuijXT sBn0/t/UilBy/LaVJrXwY/49q9+IredtNZ3+gx4vV/mghT+oREVZKL0wAlk+eCdFUEHZ xcaQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PAOvao2p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f9e1d60b57sm33888a91.9.2025.02.04.13.54.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 13:54:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 07/12] gitlab-ci: Replace aarch64 with arm in cross-i686-tci build Date: Tue, 4 Feb 2025 13:53:54 -0800 Message-ID: <20250204215359.1238808-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250204215359.1238808-1-richard.henderson@linaro.org> References: <20250204215359.1238808-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Configuration of 64-bit host on 32-bit guest will shortly be denied. Use a 32-bit guest instead. Reviewed-by: Thomas Huth Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- .gitlab-ci.d/crossbuilds.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index 95dfc39224..7ae0f966f1 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -61,7 +61,7 @@ cross-i686-tci: variables: IMAGE: debian-i686-cross ACCEL: tcg-interpreter - EXTRA_CONFIGURE_OPTS: --target-list=i386-softmmu,i386-linux-user,aarch64-softmmu,aarch64-linux-user,ppc-softmmu,ppc-linux-user --disable-plugins --disable-kvm + EXTRA_CONFIGURE_OPTS: --target-list=i386-softmmu,i386-linux-user,arm-softmmu,arm-linux-user,ppc-softmmu,ppc-linux-user --disable-plugins --disable-kvm # Force tests to run with reduced parallelism, to see whether this # reduces the flakiness of this CI job. The CI # environment by default shows us 8 CPUs and so we From patchwork Tue Feb 4 21:53:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861858 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:11cb:b0:385:e875:8a9e with SMTP id i11csp525940wrx; Tue, 4 Feb 2025 13:56:17 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVYcziVZbOQxeHUnifysYNwkw9e1vDV0duc30UttnKbjPC/sAa7CN0ZtJN27B9h1Zlb44NktQ==@linaro.org X-Google-Smtp-Source: AGHT+IE91r8zbv0n86gciHVPYGxq4oFvIeaevXIJUvzP5zdlcLeYDfyxCio52edPFh6WyoP8PkoQ X-Received: by 2002:a05:622a:250a:b0:467:603d:1cd5 with SMTP id d75a77b69052e-470278f7e7cmr10619761cf.26.1738706177592; Tue, 04 Feb 2025 13:56:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738706177; cv=none; d=google.com; s=arc-20240605; b=QFNz9tNPSBJcEDss+LM0mKnf+D27zfgCrOo6qyEqE+q4VsL5Le6OMe2/Jhvsi89YdG X3l5sxn3VS3zNv1b19QwEC3uOr0L66B2w1q5zs9p9BLDTuRAdlCR7tsa1szy/Adnoxp+ 8psF2h9cdPQFvcrdlOUgn69y8XdaVXh6Ft3eKSLtwIGsZ9/W5Bt2DNkN+UBM9mNdY8rk yUQtUMKb2VN/ORprWQ0OaP4XwEZAKCFvXh4pSaIrd8p69cSLwyFIB71WBlRTb4CDGCBC iheAaa/ZR+pSxyqT7VclYNaO7dXZtQeMgwqpzkLI/TmNow/pAtM5DvwNoxcaqBAUvv5k ZGZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3ig5mIixAd1D8GX2WLlPtXqEvEbM1IN99JeDTCSsEl4=; fh=kJMCMx+0ERv7a3rbsYoH9j+lG6+DeyggCoQTi5fJs3w=; b=Xo1wn67VaoHj608ot7xluexlM98FVre8LXOrbpoCEg8CJkf9oAdvfMjz/Al15TtD0I w4kx7bg9eWLnQlHtI/+AGDPpRS33WLCLxvQUxDyICqRScFBkhFn/w+dWENLzFJPydlQ2 xrqtGBgp4pG0++EnQAAEV8lRu7hnB1tr8XvWnbjmTHUQSjpc63ehLtXUqOg7eDoe4N71 cnqbSU+AxZBJJAC1PHA3iFmSCxPoAA9+NxZjMFD/l0giDvn/6o4UQDf36LuwiH1g8R/i LWIvOlKDqFptMGZd1fvBsDa1IfOG2ubstMpUvIX96UECPmhiDem6IXl+FO8JzJPP07z3 teRA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qsry4gnW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f9e1d60b57sm33888a91.9.2025.02.04.13.54.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 13:54:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v3 08/12] configure: Define TARGET_LONG_BITS in configs/targets/*.mak Date: Tue, 4 Feb 2025 13:53:55 -0800 Message-ID: <20250204215359.1238808-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250204215359.1238808-1-richard.henderson@linaro.org> References: <20250204215359.1238808-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Define TARGET_LONG_BITS in each target's configure fragment. Do this without removing the define in target/*/cpu-param.h so that errors are caught like so: In file included from .../src/include/exec/cpu-defs.h:26, from ../src/target/hppa/cpu.h:24, from ../src/linux-user/qemu.h:4, from ../src/linux-user/hppa/cpu_loop.c:21: ../src/target/hppa/cpu-param.h:11: error: "TARGET_LONG_BITS" redefined [-Werror] 11 | #define TARGET_LONG_BITS 64 | In file included from .../src/include/qemu/osdep.h:36, from ../src/linux-user/hppa/cpu_loop.c:20: ./hppa-linux-user-config-target.h:32: note: this is the location of the previous definition 32 | #define TARGET_LONG_BITS 32 | cc1: all warnings being treated as errors Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- configs/targets/aarch64-bsd-user.mak | 1 + configs/targets/aarch64-linux-user.mak | 1 + configs/targets/aarch64-softmmu.mak | 1 + configs/targets/aarch64_be-linux-user.mak | 1 + configs/targets/alpha-linux-user.mak | 1 + configs/targets/alpha-softmmu.mak | 1 + configs/targets/arm-bsd-user.mak | 1 + configs/targets/arm-linux-user.mak | 1 + configs/targets/arm-softmmu.mak | 1 + configs/targets/armeb-linux-user.mak | 1 + configs/targets/avr-softmmu.mak | 1 + configs/targets/hexagon-linux-user.mak | 1 + configs/targets/hppa-linux-user.mak | 2 ++ configs/targets/hppa-softmmu.mak | 1 + configs/targets/i386-bsd-user.mak | 1 + configs/targets/i386-linux-user.mak | 1 + configs/targets/i386-softmmu.mak | 1 + configs/targets/loongarch64-linux-user.mak | 1 + configs/targets/loongarch64-softmmu.mak | 1 + configs/targets/m68k-linux-user.mak | 1 + configs/targets/m68k-softmmu.mak | 1 + configs/targets/microblaze-linux-user.mak | 1 + configs/targets/microblaze-softmmu.mak | 3 +++ configs/targets/microblazeel-linux-user.mak | 1 + configs/targets/microblazeel-softmmu.mak | 3 +++ configs/targets/mips-linux-user.mak | 1 + configs/targets/mips-softmmu.mak | 1 + configs/targets/mips64-linux-user.mak | 1 + configs/targets/mips64-softmmu.mak | 1 + configs/targets/mips64el-linux-user.mak | 1 + configs/targets/mips64el-softmmu.mak | 1 + configs/targets/mipsel-linux-user.mak | 1 + configs/targets/mipsel-softmmu.mak | 1 + configs/targets/mipsn32-linux-user.mak | 1 + configs/targets/mipsn32el-linux-user.mak | 1 + configs/targets/or1k-linux-user.mak | 1 + configs/targets/or1k-softmmu.mak | 1 + configs/targets/ppc-linux-user.mak | 1 + configs/targets/ppc-softmmu.mak | 1 + configs/targets/ppc64-linux-user.mak | 1 + configs/targets/ppc64-softmmu.mak | 1 + configs/targets/ppc64le-linux-user.mak | 1 + configs/targets/riscv32-linux-user.mak | 1 + configs/targets/riscv32-softmmu.mak | 1 + configs/targets/riscv64-bsd-user.mak | 1 + configs/targets/riscv64-linux-user.mak | 1 + configs/targets/riscv64-softmmu.mak | 1 + configs/targets/rx-softmmu.mak | 1 + configs/targets/s390x-linux-user.mak | 1 + configs/targets/s390x-softmmu.mak | 1 + configs/targets/sh4-linux-user.mak | 1 + configs/targets/sh4-softmmu.mak | 1 + configs/targets/sh4eb-linux-user.mak | 1 + configs/targets/sh4eb-softmmu.mak | 1 + configs/targets/sparc-linux-user.mak | 1 + configs/targets/sparc-softmmu.mak | 1 + configs/targets/sparc32plus-linux-user.mak | 1 + configs/targets/sparc64-linux-user.mak | 1 + configs/targets/sparc64-softmmu.mak | 1 + configs/targets/tricore-softmmu.mak | 1 + configs/targets/x86_64-bsd-user.mak | 1 + configs/targets/x86_64-linux-user.mak | 1 + configs/targets/x86_64-softmmu.mak | 1 + configs/targets/xtensa-linux-user.mak | 1 + configs/targets/xtensa-softmmu.mak | 1 + configs/targets/xtensaeb-linux-user.mak | 1 + configs/targets/xtensaeb-softmmu.mak | 1 + 67 files changed, 72 insertions(+) diff --git a/configs/targets/aarch64-bsd-user.mak b/configs/targets/aarch64-bsd-user.mak index 8aaa5d8c80..f99c73377a 100644 --- a/configs/targets/aarch64-bsd-user.mak +++ b/configs/targets/aarch64-bsd-user.mak @@ -1,3 +1,4 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak index 4c6570f56a..b779ac3b4a 100644 --- a/configs/targets/aarch64-linux-user.mak +++ b/configs/targets/aarch64-linux-user.mak @@ -6,3 +6,4 @@ CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y TARGET_SYSTBL_ABI=common,64,renameat,rlimit,memfd_secret TARGET_SYSTBL=syscall_64.tbl +TARGET_LONG_BITS=64 diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak index 84cb32dc2f..82cb72cb83 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -5,3 +5,4 @@ TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml # needed by boot.c TARGET_NEED_FDT=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak index dcef597a80..ef9be02290 100644 --- a/configs/targets/aarch64_be-linux-user.mak +++ b/configs/targets/aarch64_be-linux-user.mak @@ -7,3 +7,4 @@ CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y TARGET_SYSTBL_ABI=common,64,renameat,rlimit,memfd_secret TARGET_SYSTBL=syscall_64.tbl +TARGET_LONG_BITS=64 diff --git a/configs/targets/alpha-linux-user.mak b/configs/targets/alpha-linux-user.mak index f7d3fb4afa..ef8e365b09 100644 --- a/configs/targets/alpha-linux-user.mak +++ b/configs/targets/alpha-linux-user.mak @@ -1,3 +1,4 @@ TARGET_ARCH=alpha TARGET_SYSTBL_ABI=common TARGET_SYSTBL=syscall.tbl +TARGET_LONG_BITS=64 diff --git a/configs/targets/alpha-softmmu.mak b/configs/targets/alpha-softmmu.mak index 9dbe160740..89f3517aca 100644 --- a/configs/targets/alpha-softmmu.mak +++ b/configs/targets/alpha-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=alpha TARGET_SUPPORTS_MTTCG=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/arm-bsd-user.mak b/configs/targets/arm-bsd-user.mak index cb143e6426..472a4f9fb1 100644 --- a/configs/targets/arm-bsd-user.mak +++ b/configs/targets/arm-bsd-user.mak @@ -1,2 +1,3 @@ TARGET_ARCH=arm TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/arm-linux-user.mak b/configs/targets/arm-linux-user.mak index 7f5d65794c..bf35ded7fe 100644 --- a/configs/targets/arm-linux-user.mak +++ b/configs/targets/arm-linux-user.mak @@ -5,3 +5,4 @@ TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml TARGET_HAS_BFLT=y CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.mak index bf390b7a8d..afc64f5927 100644 --- a/configs/targets/arm-softmmu.mak +++ b/configs/targets/arm-softmmu.mak @@ -3,3 +3,4 @@ TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml # needed by boot.c TARGET_NEED_FDT=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/armeb-linux-user.mak b/configs/targets/armeb-linux-user.mak index 943d0d87bf..35fa4d91b3 100644 --- a/configs/targets/armeb-linux-user.mak +++ b/configs/targets/armeb-linux-user.mak @@ -6,3 +6,4 @@ TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml TARGET_HAS_BFLT=y CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/avr-softmmu.mak b/configs/targets/avr-softmmu.mak index e3f921c019..b6157fc465 100644 --- a/configs/targets/avr-softmmu.mak +++ b/configs/targets/avr-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=avr TARGET_XML_FILES= gdb-xml/avr-cpu.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/hexagon-linux-user.mak b/configs/targets/hexagon-linux-user.mak index b912045bd3..aec1a04d1b 100644 --- a/configs/targets/hexagon-linux-user.mak +++ b/configs/targets/hexagon-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=hexagon TARGET_XML_FILES=gdb-xml/hexagon-core.xml gdb-xml/hexagon-hvx.xml TARGET_SYSTBL=syscall.tbl TARGET_SYSTBL_ABI=common,32,hexagon,time32,stat64,rlimit,renameat +TARGET_LONG_BITS=32 diff --git a/configs/targets/hppa-linux-user.mak b/configs/targets/hppa-linux-user.mak index 8e0a80492f..59190f6335 100644 --- a/configs/targets/hppa-linux-user.mak +++ b/configs/targets/hppa-linux-user.mak @@ -3,3 +3,5 @@ TARGET_ABI32=y TARGET_SYSTBL_ABI=common,32 TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y +# Compromise to ease maintenance vs system mode +TARGET_LONG_BITS=64 diff --git a/configs/targets/hppa-softmmu.mak b/configs/targets/hppa-softmmu.mak index a41662aa99..63ca74ed5e 100644 --- a/configs/targets/hppa-softmmu.mak +++ b/configs/targets/hppa-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=hppa TARGET_BIG_ENDIAN=y TARGET_SUPPORTS_MTTCG=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/i386-bsd-user.mak b/configs/targets/i386-bsd-user.mak index 0283bb62a0..70e098da49 100644 --- a/configs/targets/i386-bsd-user.mak +++ b/configs/targets/i386-bsd-user.mak @@ -1,2 +1,3 @@ TARGET_ARCH=i386 TARGET_XML_FILES= gdb-xml/i386-32bit.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/i386-linux-user.mak b/configs/targets/i386-linux-user.mak index b72a156473..ea68a266fc 100644 --- a/configs/targets/i386-linux-user.mak +++ b/configs/targets/i386-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=i386 TARGET_SYSTBL_ABI=i386 TARGET_SYSTBL=syscall_32.tbl TARGET_XML_FILES= gdb-xml/i386-32bit.xml gdb-xml/i386-32bit-linux.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmmu.mak index 2eb0e86250..5dd8921756 100644 --- a/configs/targets/i386-softmmu.mak +++ b/configs/targets/i386-softmmu.mak @@ -3,3 +3,4 @@ TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_KVM_HAVE_RESET_PARKED_VCPU=y TARGET_XML_FILES= gdb-xml/i386-32bit.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/loongarch64-linux-user.mak b/configs/targets/loongarch64-linux-user.mak index dfded79dfa..249a26a798 100644 --- a/configs/targets/loongarch64-linux-user.mak +++ b/configs/targets/loongarch64-linux-user.mak @@ -4,3 +4,4 @@ TARGET_BASE_ARCH=loongarch TARGET_XML_FILES=gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-lasx.xml TARGET_SYSTBL=syscall.tbl TARGET_SYSTBL_ABI=common,64 +TARGET_LONG_BITS=64 diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak index ce19ab6a16..351341132f 100644 --- a/configs/targets/loongarch64-softmmu.mak +++ b/configs/targets/loongarch64-softmmu.mak @@ -5,3 +5,4 @@ TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-lasx.xml # all boards require libfdt TARGET_NEED_FDT=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/m68k-linux-user.mak b/configs/targets/m68k-linux-user.mak index 579b5d299c..2d9bae2270 100644 --- a/configs/targets/m68k-linux-user.mak +++ b/configs/targets/m68k-linux-user.mak @@ -4,3 +4,4 @@ TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y TARGET_XML_FILES= gdb-xml/cf-core.xml gdb-xml/cf-fp.xml gdb-xml/m68k-core.xml gdb-xml/m68k-fp.xml TARGET_HAS_BFLT=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/m68k-softmmu.mak b/configs/targets/m68k-softmmu.mak index bbcd0bada6..bacc52e96a 100644 --- a/configs/targets/m68k-softmmu.mak +++ b/configs/targets/m68k-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=m68k TARGET_BIG_ENDIAN=y TARGET_XML_FILES= gdb-xml/cf-core.xml gdb-xml/cf-fp.xml gdb-xml/m68k-core.xml gdb-xml/m68k-fp.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/microblaze-linux-user.mak b/configs/targets/microblaze-linux-user.mak index 0a2322c249..3772779769 100644 --- a/configs/targets/microblaze-linux-user.mak +++ b/configs/targets/microblaze-linux-user.mak @@ -4,3 +4,4 @@ TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y TARGET_HAS_BFLT=y TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/microblaze-softmmu.mak b/configs/targets/microblaze-softmmu.mak index eea266d4f3..99a33ed44a 100644 --- a/configs/targets/microblaze-softmmu.mak +++ b/configs/targets/microblaze-softmmu.mak @@ -4,3 +4,6 @@ TARGET_SUPPORTS_MTTCG=y # needed by boot.c TARGET_NEED_FDT=y TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml +# System mode can address up to 64 bits via lea/sea instructions. +# TODO: These bypass the mmu, so we could emulate these differently. +TARGET_LONG_BITS=64 diff --git a/configs/targets/microblazeel-linux-user.mak b/configs/targets/microblazeel-linux-user.mak index 270743156a..a51a05488d 100644 --- a/configs/targets/microblazeel-linux-user.mak +++ b/configs/targets/microblazeel-linux-user.mak @@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=common TARGET_SYSTBL=syscall.tbl TARGET_HAS_BFLT=y TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/microblazeel-softmmu.mak b/configs/targets/microblazeel-softmmu.mak index 77b968acad..52cdeae1a2 100644 --- a/configs/targets/microblazeel-softmmu.mak +++ b/configs/targets/microblazeel-softmmu.mak @@ -3,3 +3,6 @@ TARGET_SUPPORTS_MTTCG=y # needed by boot.c TARGET_NEED_FDT=y TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml +# System mode can address up to 64 bits via lea/sea instructions. +# TODO: These bypass the mmu, so we could emulate these differently. +TARGET_LONG_BITS=64 diff --git a/configs/targets/mips-linux-user.mak b/configs/targets/mips-linux-user.mak index b4569a9893..69bdc459b6 100644 --- a/configs/targets/mips-linux-user.mak +++ b/configs/targets/mips-linux-user.mak @@ -3,3 +3,4 @@ TARGET_ABI_MIPSO32=y TARGET_SYSTBL_ABI=o32 TARGET_SYSTBL=syscall_o32.tbl TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/mips-softmmu.mak b/configs/targets/mips-softmmu.mak index d34b4083fc..b62a088249 100644 --- a/configs/targets/mips-softmmu.mak +++ b/configs/targets/mips-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=mips TARGET_BIG_ENDIAN=y TARGET_SUPPORTS_MTTCG=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/mips64-linux-user.mak b/configs/targets/mips64-linux-user.mak index d2ff509a11..04e82b3ab1 100644 --- a/configs/targets/mips64-linux-user.mak +++ b/configs/targets/mips64-linux-user.mak @@ -4,3 +4,4 @@ TARGET_BASE_ARCH=mips TARGET_SYSTBL_ABI=n64 TARGET_SYSTBL=syscall_n64.tbl TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/mips64-softmmu.mak b/configs/targets/mips64-softmmu.mak index 12d9483bf0..7202655fca 100644 --- a/configs/targets/mips64-softmmu.mak +++ b/configs/targets/mips64-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=mips64 TARGET_BASE_ARCH=mips TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/mips64el-linux-user.mak b/configs/targets/mips64el-linux-user.mak index f9efeec8ea..27f4169426 100644 --- a/configs/targets/mips64el-linux-user.mak +++ b/configs/targets/mips64el-linux-user.mak @@ -3,3 +3,4 @@ TARGET_ABI_MIPSN64=y TARGET_BASE_ARCH=mips TARGET_SYSTBL_ABI=n64 TARGET_SYSTBL=syscall_n64.tbl +TARGET_LONG_BITS=64 diff --git a/configs/targets/mips64el-softmmu.mak b/configs/targets/mips64el-softmmu.mak index 3864daa736..3ebeadb29e 100644 --- a/configs/targets/mips64el-softmmu.mak +++ b/configs/targets/mips64el-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=mips64 TARGET_BASE_ARCH=mips +TARGET_LONG_BITS=64 diff --git a/configs/targets/mipsel-linux-user.mak b/configs/targets/mipsel-linux-user.mak index e8d7241d31..8b7e86ab28 100644 --- a/configs/targets/mipsel-linux-user.mak +++ b/configs/targets/mipsel-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=mips TARGET_ABI_MIPSO32=y TARGET_SYSTBL_ABI=o32 TARGET_SYSTBL=syscall_o32.tbl +TARGET_LONG_BITS=32 diff --git a/configs/targets/mipsel-softmmu.mak b/configs/targets/mipsel-softmmu.mak index 0829659fc2..620ec68178 100644 --- a/configs/targets/mipsel-softmmu.mak +++ b/configs/targets/mipsel-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=mips TARGET_SUPPORTS_MTTCG=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/mipsn32-linux-user.mak b/configs/targets/mipsn32-linux-user.mak index 206095da64..39ae214633 100644 --- a/configs/targets/mipsn32-linux-user.mak +++ b/configs/targets/mipsn32-linux-user.mak @@ -5,3 +5,4 @@ TARGET_BASE_ARCH=mips TARGET_SYSTBL_ABI=n32 TARGET_SYSTBL=syscall_n32.tbl TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/mipsn32el-linux-user.mak b/configs/targets/mipsn32el-linux-user.mak index ca2a3ed753..d9b61d6990 100644 --- a/configs/targets/mipsn32el-linux-user.mak +++ b/configs/targets/mipsn32el-linux-user.mak @@ -4,3 +4,4 @@ TARGET_ABI32=y TARGET_BASE_ARCH=mips TARGET_SYSTBL_ABI=n32 TARGET_SYSTBL=syscall_n32.tbl +TARGET_LONG_BITS=64 diff --git a/configs/targets/or1k-linux-user.mak b/configs/targets/or1k-linux-user.mak index eecb1e2241..810567a98f 100644 --- a/configs/targets/or1k-linux-user.mak +++ b/configs/targets/or1k-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=openrisc TARGET_BIG_ENDIAN=y TARGET_SYSTBL_ABI=common,32,or1k,time32,stat64,rlimit,renameat TARGET_SYSTBL=syscall.tbl +TARGET_LONG_BITS=32 diff --git a/configs/targets/or1k-softmmu.mak b/configs/targets/or1k-softmmu.mak index 0341cb2a6b..adfddb1a8a 100644 --- a/configs/targets/or1k-softmmu.mak +++ b/configs/targets/or1k-softmmu.mak @@ -3,3 +3,4 @@ TARGET_SUPPORTS_MTTCG=y TARGET_BIG_ENDIAN=y # needed by boot.c and all boards TARGET_NEED_FDT=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/ppc-linux-user.mak b/configs/targets/ppc-linux-user.mak index cc0439a528..970d04a5ba 100644 --- a/configs/targets/ppc-linux-user.mak +++ b/configs/targets/ppc-linux-user.mak @@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=common,nospu,32 TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y TARGET_XML_FILES= gdb-xml/power-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/ppc-softmmu.mak b/configs/targets/ppc-softmmu.mak index 53120dab41..9bfa7df6c3 100644 --- a/configs/targets/ppc-softmmu.mak +++ b/configs/targets/ppc-softmmu.mak @@ -2,3 +2,4 @@ TARGET_ARCH=ppc TARGET_BIG_ENDIAN=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/power-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml +TARGET_LONG_BITS=32 diff --git a/configs/targets/ppc64-linux-user.mak b/configs/targets/ppc64-linux-user.mak index 4d81969f4a..461f1c67d1 100644 --- a/configs/targets/ppc64-linux-user.mak +++ b/configs/targets/ppc64-linux-user.mak @@ -5,3 +5,4 @@ TARGET_SYSTBL_ABI=common,nospu,64 TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y TARGET_XML_FILES= gdb-xml/power64-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml gdb-xml/power-vsx.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/ppc64-softmmu.mak b/configs/targets/ppc64-softmmu.mak index 40881d9396..7cee0e97f4 100644 --- a/configs/targets/ppc64-softmmu.mak +++ b/configs/targets/ppc64-softmmu.mak @@ -6,3 +6,4 @@ TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/power64-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml gdb-xml/power-vsx.xml # all boards require libfdt TARGET_NEED_FDT=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/ppc64le-linux-user.mak b/configs/targets/ppc64le-linux-user.mak index 426d5a28d6..cf9d8a400d 100644 --- a/configs/targets/ppc64le-linux-user.mak +++ b/configs/targets/ppc64le-linux-user.mak @@ -4,3 +4,4 @@ TARGET_ABI_DIR=ppc TARGET_SYSTBL_ABI=common,nospu,64 TARGET_SYSTBL=syscall.tbl TARGET_XML_FILES= gdb-xml/power64-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml gdb-xml/power-vsx.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/riscv32-linux-user.mak b/configs/targets/riscv32-linux-user.mak index 0dbaf5210a..a0ef03c0c3 100644 --- a/configs/targets/riscv32-linux-user.mak +++ b/configs/targets/riscv32-linux-user.mak @@ -7,3 +7,4 @@ CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y TARGET_SYSTBL_ABI=32 TARGET_SYSTBL_ABI=common,32,riscv,memfd_secret TARGET_SYSTBL=syscall.tbl +TARGET_LONG_BITS=32 diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-softmmu.mak index 338182d5b8..c828066ce6 100644 --- a/configs/targets/riscv32-softmmu.mak +++ b/configs/targets/riscv32-softmmu.mak @@ -4,3 +4,4 @@ TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c TARGET_NEED_FDT=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/riscv64-bsd-user.mak b/configs/targets/riscv64-bsd-user.mak index 191c2c483f..c6348a7962 100644 --- a/configs/targets/riscv64-bsd-user.mak +++ b/configs/targets/riscv64-bsd-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/riscv64-linux-user.mak b/configs/targets/riscv64-linux-user.mak index 477cd4523e..aac7568305 100644 --- a/configs/targets/riscv64-linux-user.mak +++ b/configs/targets/riscv64-linux-user.mak @@ -7,3 +7,4 @@ CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y TARGET_SYSTBL_ABI=64 TARGET_SYSTBL_ABI=common,64,riscv,rlimit,memfd_secret TARGET_SYSTBL=syscall.tbl +TARGET_LONG_BITS=64 diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak index 6c5de72e03..09f613d24a 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -5,3 +5,4 @@ TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c TARGET_NEED_FDT=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/rx-softmmu.mak b/configs/targets/rx-softmmu.mak index 706bbe6062..1c250a6450 100644 --- a/configs/targets/rx-softmmu.mak +++ b/configs/targets/rx-softmmu.mak @@ -2,3 +2,4 @@ TARGET_ARCH=rx TARGET_XML_FILES= gdb-xml/rx-core.xml # all boards require libfdt TARGET_NEED_FDT=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/s390x-linux-user.mak b/configs/targets/s390x-linux-user.mak index 24c04c8589..68c2f28872 100644 --- a/configs/targets/s390x-linux-user.mak +++ b/configs/targets/s390x-linux-user.mak @@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=common,64 TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/s390x-softmmu.mak b/configs/targets/s390x-softmmu.mak index b22218aacc..5242ebe7c2 100644 --- a/configs/targets/s390x-softmmu.mak +++ b/configs/targets/s390x-softmmu.mak @@ -3,3 +3,4 @@ TARGET_BIG_ENDIAN=y TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/sh4-linux-user.mak b/configs/targets/sh4-linux-user.mak index 9908887566..d58c5471b7 100644 --- a/configs/targets/sh4-linux-user.mak +++ b/configs/targets/sh4-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=sh4 TARGET_SYSTBL_ABI=common TARGET_SYSTBL=syscall.tbl TARGET_HAS_BFLT=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/sh4-softmmu.mak b/configs/targets/sh4-softmmu.mak index f9d62d91e4..787d349b50 100644 --- a/configs/targets/sh4-softmmu.mak +++ b/configs/targets/sh4-softmmu.mak @@ -1 +1,2 @@ TARGET_ARCH=sh4 +TARGET_LONG_BITS=32 diff --git a/configs/targets/sh4eb-linux-user.mak b/configs/targets/sh4eb-linux-user.mak index 9db6b3609c..99007f0f2d 100644 --- a/configs/targets/sh4eb-linux-user.mak +++ b/configs/targets/sh4eb-linux-user.mak @@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=common TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y TARGET_HAS_BFLT=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/sh4eb-softmmu.mak b/configs/targets/sh4eb-softmmu.mak index 226b1fc698..cdea2c61c5 100644 --- a/configs/targets/sh4eb-softmmu.mak +++ b/configs/targets/sh4eb-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=sh4 TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/sparc-linux-user.mak b/configs/targets/sparc-linux-user.mak index abcfb8fc62..4ff4b7287d 100644 --- a/configs/targets/sparc-linux-user.mak +++ b/configs/targets/sparc-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=sparc TARGET_SYSTBL_ABI=common,32 TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak index a5d9200382..78c2e25bd1 100644 --- a/configs/targets/sparc-softmmu.mak +++ b/configs/targets/sparc-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=sparc TARGET_BIG_ENDIAN=y TARGET_SUPPORTS_MTTCG=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/sparc32plus-linux-user.mak b/configs/targets/sparc32plus-linux-user.mak index 6cc8fa516b..7a16934fd1 100644 --- a/configs/targets/sparc32plus-linux-user.mak +++ b/configs/targets/sparc32plus-linux-user.mak @@ -5,3 +5,4 @@ TARGET_ABI_DIR=sparc TARGET_SYSTBL_ABI=common,32 TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/sparc64-linux-user.mak b/configs/targets/sparc64-linux-user.mak index 52f05ec000..64ea04e3e2 100644 --- a/configs/targets/sparc64-linux-user.mak +++ b/configs/targets/sparc64-linux-user.mak @@ -4,3 +4,4 @@ TARGET_ABI_DIR=sparc TARGET_SYSTBL_ABI=common,64 TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak index 36ca64ec41..f7bab97a00 100644 --- a/configs/targets/sparc64-softmmu.mak +++ b/configs/targets/sparc64-softmmu.mak @@ -2,3 +2,4 @@ TARGET_ARCH=sparc64 TARGET_BASE_ARCH=sparc TARGET_BIG_ENDIAN=y TARGET_SUPPORTS_MTTCG=y +TARGET_LONG_BITS=64 diff --git a/configs/targets/tricore-softmmu.mak b/configs/targets/tricore-softmmu.mak index 96b10af853..781ce49a62 100644 --- a/configs/targets/tricore-softmmu.mak +++ b/configs/targets/tricore-softmmu.mak @@ -1 +1,2 @@ TARGET_ARCH=tricore +TARGET_LONG_BITS=32 diff --git a/configs/targets/x86_64-bsd-user.mak b/configs/targets/x86_64-bsd-user.mak index 799cd4acd4..d62d656f2c 100644 --- a/configs/targets/x86_64-bsd-user.mak +++ b/configs/targets/x86_64-bsd-user.mak @@ -1,3 +1,4 @@ TARGET_ARCH=x86_64 TARGET_BASE_ARCH=i386 TARGET_XML_FILES= gdb-xml/i386-64bit.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/x86_64-linux-user.mak b/configs/targets/x86_64-linux-user.mak index 86042814d3..b093ab5a16 100644 --- a/configs/targets/x86_64-linux-user.mak +++ b/configs/targets/x86_64-linux-user.mak @@ -3,3 +3,4 @@ TARGET_BASE_ARCH=i386 TARGET_SYSTBL_ABI=common,64 TARGET_SYSTBL=syscall_64.tbl TARGET_XML_FILES= gdb-xml/i386-64bit.xml gdb-xml/i386-64bit-linux.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-softmmu.mak index 920e9a4200..1ceefde131 100644 --- a/configs/targets/x86_64-softmmu.mak +++ b/configs/targets/x86_64-softmmu.mak @@ -4,3 +4,4 @@ TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_KVM_HAVE_RESET_PARKED_VCPU=y TARGET_XML_FILES= gdb-xml/i386-64bit.xml +TARGET_LONG_BITS=64 diff --git a/configs/targets/xtensa-linux-user.mak b/configs/targets/xtensa-linux-user.mak index 420b30a68d..cbec6e368a 100644 --- a/configs/targets/xtensa-linux-user.mak +++ b/configs/targets/xtensa-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=xtensa TARGET_SYSTBL_ABI=common TARGET_SYSTBL=syscall.tbl TARGET_HAS_BFLT=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/xtensa-softmmu.mak b/configs/targets/xtensa-softmmu.mak index f075557bfa..65845df4ff 100644 --- a/configs/targets/xtensa-softmmu.mak +++ b/configs/targets/xtensa-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=xtensa TARGET_SUPPORTS_MTTCG=y +TARGET_LONG_BITS=32 diff --git a/configs/targets/xtensaeb-linux-user.mak b/configs/targets/xtensaeb-linux-user.mak index bce2d1d65d..f455b1c780 100644 --- a/configs/targets/xtensaeb-linux-user.mak +++ b/configs/targets/xtensaeb-linux-user.mak @@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=common TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f9e1d60b57sm33888a91.9.2025.02.04.13.54.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 13:54:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 09/12] target/*: Remove TARGET_LONG_BITS from cpu-param.h Date: Tue, 4 Feb 2025 13:53:56 -0800 Message-ID: <20250204215359.1238808-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250204215359.1238808-1-richard.henderson@linaro.org> References: <20250204215359.1238808-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is now handled by the configs/targets/*.mak fragment. Reviewed-by: Thomas Huth Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/cpu-param.h | 2 -- target/arm/cpu-param.h | 2 -- target/avr/cpu-param.h | 1 - target/hexagon/cpu-param.h | 1 - target/hppa/cpu-param.h | 2 -- target/i386/cpu-param.h | 2 -- target/loongarch/cpu-param.h | 1 - target/m68k/cpu-param.h | 1 - target/microblaze/cpu-param.h | 2 -- target/mips/cpu-param.h | 5 ----- target/openrisc/cpu-param.h | 1 - target/ppc/cpu-param.h | 2 -- target/riscv/cpu-param.h | 2 -- target/rx/cpu-param.h | 1 - target/s390x/cpu-param.h | 1 - target/sh4/cpu-param.h | 1 - target/sparc/cpu-param.h | 2 -- target/tricore/cpu-param.h | 1 - target/xtensa/cpu-param.h | 1 - 19 files changed, 31 deletions(-) diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index c21ddf1afd..ff06e41497 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -8,8 +8,6 @@ #ifndef ALPHA_CPU_PARAM_H #define ALPHA_CPU_PARAM_H -#define TARGET_LONG_BITS 64 - /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */ #define TARGET_PHYS_ADDR_SPACE_BITS 44 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index bed29613c8..896b35bd6d 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -9,11 +9,9 @@ #define ARM_CPU_PARAM_H #ifdef TARGET_AARCH64 -# define TARGET_LONG_BITS 64 # define TARGET_PHYS_ADDR_SPACE_BITS 52 # define TARGET_VIRT_ADDR_SPACE_BITS 52 #else -# define TARGET_LONG_BITS 32 # define TARGET_PHYS_ADDR_SPACE_BITS 40 # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 93c2f470d0..81f3f49ee1 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -21,7 +21,6 @@ #ifndef AVR_CPU_PARAM_H #define AVR_CPU_PARAM_H -#define TARGET_LONG_BITS 32 /* * TARGET_PAGE_BITS cannot be more than 8 bits because * 1. all IO registers occupy [0x0000 .. 0x00ff] address range, and they diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 71b4a9b83e..45ee7b4640 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -19,7 +19,6 @@ #define HEXAGON_CPU_PARAM_H #define TARGET_PAGE_BITS 16 /* 64K pages */ -#define TARGET_LONG_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 36 #define TARGET_VIRT_ADDR_SPACE_BITS 32 diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index ef3200f0f3..7ed6b5741e 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -8,8 +8,6 @@ #ifndef HPPA_CPU_PARAM_H #define HPPA_CPU_PARAM_H -#define TARGET_LONG_BITS 64 - #if defined(CONFIG_USER_ONLY) && defined(TARGET_ABI32) # define TARGET_PHYS_ADDR_SPACE_BITS 32 # define TARGET_VIRT_ADDR_SPACE_BITS 32 diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index 8c75abe141..b0e884c5d7 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -9,7 +9,6 @@ #define I386_CPU_PARAM_H #ifdef TARGET_X86_64 -# define TARGET_LONG_BITS 64 # define TARGET_PHYS_ADDR_SPACE_BITS 52 /* * ??? This is really 48 bits, sign-extended, but the only thing @@ -18,7 +17,6 @@ */ # define TARGET_VIRT_ADDR_SPACE_BITS 47 #else -# define TARGET_LONG_BITS 32 # define TARGET_PHYS_ADDR_SPACE_BITS 36 # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index db5ad1c69f..52437946e5 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -8,7 +8,6 @@ #ifndef LOONGARCH_CPU_PARAM_H #define LOONGARCH_CPU_PARAM_H -#define TARGET_LONG_BITS 64 #define TARGET_PHYS_ADDR_SPACE_BITS 48 #define TARGET_VIRT_ADDR_SPACE_BITS 48 diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 5bbe623ba7..7afbf6d302 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -8,7 +8,6 @@ #ifndef M68K_CPU_PARAM_H #define M68K_CPU_PARAM_H -#define TARGET_LONG_BITS 32 /* * Coldfire Linux uses 8k pages * and m68k linux uses 4k pages diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 00efb509e3..c866ec6c14 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -17,11 +17,9 @@ * of address space. */ #ifdef CONFIG_USER_ONLY -#define TARGET_LONG_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 #else -#define TARGET_LONG_BITS 64 #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 #endif diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index f3a37e2dbe..11b3ac0ac6 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -7,11 +7,6 @@ #ifndef MIPS_CPU_PARAM_H #define MIPS_CPU_PARAM_H -#ifdef TARGET_MIPS64 -# define TARGET_LONG_BITS 64 -#else -# define TARGET_LONG_BITS 32 -#endif #ifdef TARGET_ABI_MIPSN64 #define TARGET_PHYS_ADDR_SPACE_BITS 48 #define TARGET_VIRT_ADDR_SPACE_BITS 48 diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h index 6169ed9f55..37627f2c39 100644 --- a/target/openrisc/cpu-param.h +++ b/target/openrisc/cpu-param.h @@ -8,7 +8,6 @@ #ifndef OPENRISC_CPU_PARAM_H #define OPENRISC_CPU_PARAM_H -#define TARGET_LONG_BITS 32 #define TARGET_PAGE_BITS 13 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index 9c481b9f6c..6c4525fdf3 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -9,7 +9,6 @@ #define PPC_CPU_PARAM_H #ifdef TARGET_PPC64 -# define TARGET_LONG_BITS 64 /* * Note that the official physical address space bits is 62-M where M * is implementation dependent. I've not looked up M for the set of @@ -27,7 +26,6 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 64 # endif #else -# define TARGET_LONG_BITS 32 # define TARGET_PHYS_ADDR_SPACE_BITS 36 # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index 25686192c0..fba30e966a 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -9,11 +9,9 @@ #define RISCV_CPU_PARAM_H #if defined(TARGET_RISCV64) -# define TARGET_LONG_BITS 64 # define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ # define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ #elif defined(TARGET_RISCV32) -# define TARGET_LONG_BITS 32 # define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ #endif diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index 521d669bdf..ef1970a09e 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -19,7 +19,6 @@ #ifndef RX_CPU_PARAM_H #define RX_CPU_PARAM_H -#define TARGET_LONG_BITS 32 #define TARGET_PAGE_BITS 12 #define TARGET_PHYS_ADDR_SPACE_BITS 32 diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index a05ffcf78d..5c331ec424 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -8,7 +8,6 @@ #ifndef S390_CPU_PARAM_H #define S390_CPU_PARAM_H -#define TARGET_LONG_BITS 64 #define TARGET_PAGE_BITS 12 #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index a30ba992b3..2b6e11dd0a 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -8,7 +8,6 @@ #ifndef SH4_CPU_PARAM_H #define SH4_CPU_PARAM_H -#define TARGET_LONG_BITS 32 #define TARGET_PAGE_BITS 12 /* 4k */ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #ifdef CONFIG_USER_ONLY diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index 14105dc18b..6952ee2b82 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -8,7 +8,6 @@ #define SPARC_CPU_PARAM_H #ifdef TARGET_SPARC64 -# define TARGET_LONG_BITS 64 # define TARGET_PAGE_BITS 13 /* 8k */ # define TARGET_PHYS_ADDR_SPACE_BITS 41 # ifdef TARGET_ABI32 @@ -17,7 +16,6 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 44 # endif #else -# define TARGET_LONG_BITS 32 # define TARGET_PAGE_BITS 12 /* 4k */ # define TARGET_PHYS_ADDR_SPACE_BITS 36 # define TARGET_VIRT_ADDR_SPACE_BITS 32 diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index e29d551dd6..790242ef3d 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -8,7 +8,6 @@ #ifndef TRICORE_CPU_PARAM_H #define TRICORE_CPU_PARAM_H -#define TARGET_LONG_BITS 32 #define TARGET_PAGE_BITS 14 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index 0000725f2f..5e4848ad05 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -8,7 +8,6 @@ #ifndef XTENSA_CPU_PARAM_H #define XTENSA_CPU_PARAM_H -#define TARGET_LONG_BITS 32 #define TARGET_PAGE_BITS 12 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #ifdef CONFIG_USER_ONLY From patchwork Tue Feb 4 21:53:57 2025 Content-Type: text/plain; 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f9e1d60b57sm33888a91.9.2025.02.04.13.54.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 13:54:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com Subject: [PATCH v3 10/12] meson: Disallow 64-bit on 32-bit emulation Date: Tue, 4 Feb 2025 13:53:57 -0800 Message-ID: <20250204215359.1238808-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250204215359.1238808-1-richard.henderson@linaro.org> References: <20250204215359.1238808-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For system mode, we can rarely support the amount of RAM that the guest requires. TCG emulation is restricted to round-robin mode, which solves many of the atomicity issues, but not those associated with virtio. In any case, round-robin does nothing to help the speed of emulation. For user mode, most emulation does not succeed at all. Most of the time we cannot even load 64-bit non-PIE binaries due to lack of a 64-bit address space. Threads are run in parallel, not round-robin, which means that atomicity is not handled. Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth --- meson.build | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/meson.build b/meson.build index c80382befd..aa1ca8355d 100644 --- a/meson.build +++ b/meson.build @@ -3190,6 +3190,9 @@ if host_os == 'windows' endif endif +# Detect host pointer size for the target configuration loop. +host_long_bits = cc.sizeof('void *') * 8 + ######################## # Target configuration # ######################## @@ -3282,8 +3285,14 @@ foreach target : target_dirs } endif + config_target += keyval.load('configs/targets' / target + '.mak') + target_kconfig = [] foreach sym: accelerators + # Disallow 64-bit on 32-bit emulation and virtualization + if host_long_bits < config_target['TARGET_LONG_BITS'].to_int() + continue + endif if sym == 'CONFIG_TCG' or target in accelerator_targets.get(sym, []) config_target += { sym: 'y' } config_all_accel += { sym: 'y' } @@ -3297,9 +3306,6 @@ foreach target : target_dirs error('No accelerator available for target @0@'.format(target)) endif - config_target += keyval.load('configs/targets' / target + '.mak') - config_target += { 'TARGET_' + config_target['TARGET_ARCH'].to_upper(): 'y' } - if 'TARGET_NEED_FDT' in config_target and not fdt.found() if default_targets warning('Disabling ' + target + ' due to missing libfdt') @@ -3312,6 +3318,7 @@ foreach target : target_dirs actual_target_dirs += target # Add default keys + config_target += { 'TARGET_' + config_target['TARGET_ARCH'].to_upper(): 'y' } if 'TARGET_BASE_ARCH' not in config_target config_target += {'TARGET_BASE_ARCH': config_target['TARGET_ARCH']} endif From patchwork Tue Feb 4 21:53:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861851 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:11cb:b0:385:e875:8a9e with SMTP id i11csp525575wrx; Tue, 4 Feb 2025 13:55:03 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXcBOK9Y3a+Ah7vPzYoUjFBdx46KTRddlyg2ZS96d7MSKnBmLVl6CVc/FmiV/DV5/whibzQHA==@linaro.org X-Google-Smtp-Source: AGHT+IEjw2npfV6ZAhQaRSDL2QCqzCWtnqRM0+iK0y1uC9WmmzFAW+WvMYQOGt4qU0qxpxVQ4aID X-Received: by 2002:a05:622a:2:b0:467:6b96:dc5a with SMTP id d75a77b69052e-47028301d3dmr4800431cf.47.1738706103099; Tue, 04 Feb 2025 13:55:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738706103; cv=none; d=google.com; s=arc-20240605; b=AbOoooIii/8SOkjTt/5+J/5n+gTuKL/ng9E8QxF2CcPdPCAe0jr1nFwA+V2cCHnLsu AQNy2LFICy/stNtVxfiuy2nbThDDIlael2k3d4GnvmvBdhndg8mmWyAz+ST9A164rrrq AwtOasEmEXX4se83gMeaMLtSwUwUuFZbU4wqwPf2b8l46dTlBeb1w+cm2JHIM7umOwlL bjAMu+R30BjTHcYD9v91nUziSOArmHEglGc9WNr7TN5ycIB++Nl6FgiLCMIc05Fy3mAW Ms29lKWy0min3WvjoaBMUGZn7W07YdwHgfiHbsiwKftMSVSxCXmtmMgFkfVqCKu5MCGt N5zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=POW93gVR6h/M8xFYSXewi98308xEJBX+M2a2KNFKUmQ=; fh=WBfWBA4xhLBT7XcACU9php1VkQFXD3CDPq61lYOQNqc=; b=OcgPRCFsV1OHTx8bkg26k6Sr/98oALm0NoiELNEOmuy5fmPsEH1xhX5nnrOhHLZr4r NHsZ6LZ5vA6KVsgICbVsjC+mF+1hBfxQDnv7raNg48HSHd1RgdMPIRnjRQ06h/rLWAd3 VmLdkNrmiRw4FdZaaVl/GKG6JUs4zB3xPnXe8mHwRRCL/HmF5xbWl1L69an5SS7vBkCR hrOEMvQimIuiwVa6TrT4EcDiv/ZZItF6x9vfG3whuO9ePRP5fuxu3NSvYkmKFuMsPwe1 lu8cvAbwaLgQ2gkCPWPoQv6TeBLDoms7DzKjYBdSi0isrtxkP5w6HUKE1zxF/732YSqn F8Eg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="JNsg/Ypf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f9e1d60b57sm33888a91.9.2025.02.04.13.54.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 13:54:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 11/12] meson: Deprecate 32-bit host support Date: Tue, 4 Feb 2025 13:53:58 -0800 Message-ID: <20250204215359.1238808-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250204215359.1238808-1-richard.henderson@linaro.org> References: <20250204215359.1238808-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We deprecated i686 system mode support for qemu 8.0. However, to make real cleanups to TCG we need to deprecate all 32-bit hosts. Reviewed-by: Thomas Huth Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- docs/about/deprecated.rst | 7 +++++++ meson.build | 8 +++----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 4a3c302962..7c61d0ba16 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -204,6 +204,13 @@ is going to be so much slower it wouldn't make sense for any serious instrumentation. Due to implementation differences there will also be anomalies in things like memory instrumentation. +32-bit host operating systems (since 10.0) +'''''''''''''''''''''''''''''''''''''''''' + +Keeping 32-bit host support alive is a substantial burden for the +QEMU project. Thus QEMU will in future drop the support for all +32-bit host systems. + System emulator CPUs -------------------- diff --git a/meson.build b/meson.build index aa1ca8355d..3347b0a553 100644 --- a/meson.build +++ b/meson.build @@ -4843,14 +4843,12 @@ if host_arch == 'unknown' message('configure has succeeded and you can continue to build, but') message('QEMU will use a slow interpreter to emulate the target CPU.') endif -elif host_arch == 'mips' +elif host_long_bits < 64 message() warning('DEPRECATED HOST CPU') message() - message('Support for CPU host architecture ' + cpu + ' is going to be') - message('dropped as soon as the QEMU project stops supporting Debian 12') - message('("Bookworm"). Going forward, the QEMU project will not guarantee') - message('that QEMU will compile or work on this host CPU.') + message('Support for 32-bit CPU host architecture ' + cpu + ' is going') + message('to be dropped in a future QEMU release.') endif if not supported_oses.contains(host_os) From patchwork Tue Feb 4 21:53:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 861849 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:11cb:b0:385:e875:8a9e with SMTP id i11csp525503wrx; Tue, 4 Feb 2025 13:54:51 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVP7kgc58Jlsic4O1SAAurknxKnCmv/RvKcrOcKYH1SiSui4ZfsMEDzKICJUqjJxqGWK8GJqw==@linaro.org X-Google-Smtp-Source: AGHT+IHI6NYe42Tqg/wT1G4SEDx8CCERbn9PLFXBTmTUCafTP2F2RzW3SglGOk9dMU1vodOFX4ho X-Received: by 2002:a05:620a:4542:b0:7b6:c695:fb7c with SMTP id af79cd13be357-7c039fcf5c8mr56857085a.33.1738706091559; Tue, 04 Feb 2025 13:54:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738706091; cv=none; d=google.com; s=arc-20240605; b=I3oUdYNkhDclrV8/cRDb5TCvDACk1nuDwYZ18HWQ96QePEZv+Jl63XzFCi53hJc9C2 lYIVR70ZiJrFW7sNqwMZrNhKe82mnEYzm7Ljoh5tBxG5s26xLjLaBZBD6oPD4Nlg7RHf JqklNN/S7qosM0ZPLVz5V1a51dbN3gqMWECl2ujDdNBrBuwBQ4dO19QSYjpMFqQ8NlkR lkSImYS7YImHMYsGpFPlNFlEjGHxlts3G5k84hD82UCW84Fq1xOQTa1xOHUS8SVQIbCs EpfBBx/zoD9nawNM/BEFTEj19LtcBSCU20TZ+R5JICE1uh4BVamTJPt5Rauixshr4qrC QnbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0D+qkdUAnGyLEvzj5WsailDQ6IwrMLobTEZGdeMA0tw=; fh=WBfWBA4xhLBT7XcACU9php1VkQFXD3CDPq61lYOQNqc=; b=eutq3eQg6yB9OHq57G++oBrD629USTSsIzbupXRdYokzC0JL2PNeb1vzdA6dRfb3Ip XNXWbRhNJdP+U/a+d+R7AkV97RTm0/eOkCOTn2rCCF/CXu0BE6Vr5OkiiPT8lgi2ElE/ 1co4HRPaeSIkzbcdmpJOT46wdcLyKwi8PvdvgrgaHxpBL6ph2XbmxD99A47SoC/yEl7A 9w+Ryt3wuKIS8UiFyWPOYNWxSPi0up/lqSfkKNYwAU5tP0AM8/4QoGH5SvXIps/sY9lo TGJx+5ZRoHvNqhUX5VmQCb3AIKFH67PxBanrRQXT10Le34MAFJ12Bu8dMcL2hMMwvQDK 2+cg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Kx+Myume; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f9e1d60b57sm33888a91.9.2025.02.04.13.54.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 13:54:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, berrange@redhat.com, philmd@linaro.org, thuth@redhat.com, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 12/12] tcg: Remove TCG_OVERSIZED_GUEST Date: Tue, 4 Feb 2025 13:53:59 -0800 Message-ID: <20250204215359.1238808-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250204215359.1238808-1-richard.henderson@linaro.org> References: <20250204215359.1238808-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is now prohibited in configuration. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/qemu/atomic.h | 18 +++-------------- include/tcg/oversized-guest.h | 23 ---------------------- accel/tcg/cputlb.c | 7 ------- accel/tcg/tcg-all.c | 9 ++++----- target/arm/ptw.c | 34 --------------------------------- target/riscv/cpu_helper.c | 13 +------------ docs/devel/multi-thread-tcg.rst | 1 - 7 files changed, 8 insertions(+), 97 deletions(-) delete mode 100644 include/tcg/oversized-guest.h diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index 7a3f2e6576..f80cba24cf 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -56,25 +56,13 @@ */ #define signal_barrier() __atomic_signal_fence(__ATOMIC_SEQ_CST) -/* Sanity check that the size of an atomic operation isn't "overly large". +/* + * Sanity check that the size of an atomic operation isn't "overly large". * Despite the fact that e.g. i686 has 64-bit atomic operations, we do not * want to use them because we ought not need them, and this lets us do a * bit of sanity checking that other 32-bit hosts might build. - * - * That said, we have a problem on 64-bit ILP32 hosts in that in order to - * sync with TCG_OVERSIZED_GUEST, this must match TCG_TARGET_REG_BITS. - * We'd prefer not want to pull in everything else TCG related, so handle - * those few cases by hand. - * - * Note that x32 is fully detected with __x86_64__ + _ILP32, and that for - * Sparc we always force the use of sparcv9 in configure. MIPS n32 (ILP32) & - * n64 (LP64) ABIs are both detected using __mips64. */ -#if defined(__x86_64__) || defined(__sparc__) || defined(__mips64) -# define ATOMIC_REG_SIZE 8 -#else -# define ATOMIC_REG_SIZE sizeof(void *) -#endif +#define ATOMIC_REG_SIZE sizeof(void *) /* Weak atomic operations prevent the compiler moving other * loads/stores past the atomic operation load/store. However there is diff --git a/include/tcg/oversized-guest.h b/include/tcg/oversized-guest.h deleted file mode 100644 index 641b9749ff..0000000000 --- a/include/tcg/oversized-guest.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Define TCG_OVERSIZED_GUEST - * Copyright (c) 2008 Fabrice Bellard - */ - -#ifndef EXEC_TCG_OVERSIZED_GUEST_H -#define EXEC_TCG_OVERSIZED_GUEST_H - -#include "tcg-target-reg-bits.h" -#include "cpu-param.h" - -/* - * Oversized TCG guests make things like MTTCG hard - * as we can't use atomics for cputlb updates. - */ -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS -#define TCG_OVERSIZED_GUEST 1 -#else -#define TCG_OVERSIZED_GUEST 0 -#endif - -#endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b4ccf0cdcb..17e2251695 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -47,7 +47,6 @@ #include "qemu/plugin-memory.h" #endif #include "tcg/tcg-ldst.h" -#include "tcg/oversized-guest.h" /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ @@ -118,12 +117,8 @@ static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry, return qatomic_read(ptr); #else const uint64_t *ptr = &entry->addr_idx[access_type]; -# if TCG_OVERSIZED_GUEST - return *ptr; -# else /* ofs might correspond to .addr_write, so use qatomic_read */ return qatomic_read(ptr); -# endif #endif } @@ -908,8 +903,6 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry, uint32_t *ptr_write = (uint32_t *)&tlb_entry->addr_write; ptr_write += HOST_BIG_ENDIAN; qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY); -#elif TCG_OVERSIZED_GUEST - tlb_entry->addr_write |= TLB_NOTDIRTY; #else qatomic_set(&tlb_entry->addr_write, tlb_entry->addr_write | TLB_NOTDIRTY); diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 95adaacee8..c1a30b0121 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -28,7 +28,6 @@ #include "exec/replay-core.h" #include "system/cpu-timers.h" #include "tcg/startup.h" -#include "tcg/oversized-guest.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/accel.h" @@ -41,6 +40,8 @@ #include "hw/boards.h" #endif #include "internal-common.h" +#include "cpu-param.h" + struct TCGState { AccelState parent_obj; @@ -72,7 +73,7 @@ DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE, static bool default_mttcg_enabled(void) { - if (icount_enabled() || TCG_OVERSIZED_GUEST) { + if (icount_enabled()) { return false; } #ifdef TARGET_SUPPORTS_MTTCG @@ -145,9 +146,7 @@ static void tcg_set_thread(Object *obj, const char *value, Error **errp) TCGState *s = TCG_STATE(obj); if (strcmp(value, "multi") == 0) { - if (TCG_OVERSIZED_GUEST) { - error_setg(errp, "No MTTCG when guest word size > hosts"); - } else if (icount_enabled()) { + if (icount_enabled()) { error_setg(errp, "No MTTCG when icount is enabled"); } else { #ifndef TARGET_SUPPORTS_MTTCG diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 64bb6878a4..4330900348 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -16,9 +16,6 @@ #include "internals.h" #include "cpu-features.h" #include "idau.h" -#ifdef CONFIG_TCG -# include "tcg/oversized-guest.h" -#endif typedef struct S1Translate { /* @@ -840,7 +837,6 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, ptw->out_rw = true; } -#ifdef CONFIG_ATOMIC64 if (ptw->out_be) { old_val = cpu_to_be64(old_val); new_val = cpu_to_be64(new_val); @@ -852,36 +848,6 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, cur_val = qatomic_cmpxchg__nocheck((uint64_t *)host, old_val, new_val); cur_val = le64_to_cpu(cur_val); } -#else - /* - * We can't support the full 64-bit atomic cmpxchg on the host. - * Because this is only used for FEAT_HAFDBS, which is only for AA64, - * we know that TCG_OVERSIZED_GUEST is set, which means that we are - * running in round-robin mode and could only race with dma i/o. - */ -#if !TCG_OVERSIZED_GUEST -# error "Unexpected configuration" -#endif - bool locked = bql_locked(); - if (!locked) { - bql_lock(); - } - if (ptw->out_be) { - cur_val = ldq_be_p(host); - if (cur_val == old_val) { - stq_be_p(host, new_val); - } - } else { - cur_val = ldq_le_p(host); - if (cur_val == old_val) { - stq_le_p(host, new_val); - } - } - if (!locked) { - bql_unlock(); - } -#endif - return cur_val; #else /* AArch32 does not have FEAT_HADFS; non-TCG guests only use debug-mode. */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e1dfc4ecbf..8ff6d900f2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -32,7 +32,6 @@ #include "system/cpu-timers.h" #include "cpu_bits.h" #include "debug.h" -#include "tcg/oversized-guest.h" #include "pmp.h" int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) @@ -1167,9 +1166,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, hwaddr pte_addr; int i; -#if !TCG_OVERSIZED_GUEST -restart: -#endif + restart: for (i = 0; i < levels; i++, ptshift -= ptidxbits) { target_ulong idx; if (i == 0) { @@ -1388,13 +1385,6 @@ restart: false, MEMTXATTRS_UNSPECIFIED); if (memory_region_is_ram(mr)) { target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1); -#if TCG_OVERSIZED_GUEST - /* - * MTTCG is not enabled on oversized TCG guests so - * page table updates do not need to be atomic - */ - *pte_pa = pte = updated_pte; -#else target_ulong old_pte; if (riscv_cpu_sxl(env) == MXL_RV32) { old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, pte, updated_pte); @@ -1405,7 +1395,6 @@ restart: goto restart; } pte = updated_pte; -#endif } else { /* * Misconfigured PTE in ROM (AD bits are not preset) or diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.rst index 7fd0a07633..b0f473961d 100644 --- a/docs/devel/multi-thread-tcg.rst +++ b/docs/devel/multi-thread-tcg.rst @@ -37,7 +37,6 @@ if: * forced by --accel tcg,thread=single * enabling --icount mode -* 64 bit guests on 32 bit hosts (TCG_OVERSIZED_GUEST) In the general case of running translated code there should be no inter-vCPU dependencies and all vCPUs should be able to run at full