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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c13a0efsm2733042f8f.60.2025.01.30.10.25.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Jan 2025 10:25:29 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 1/8] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition Date: Thu, 30 Jan 2025 19:24:34 +0100 Message-ID: <20250130182441.40480-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250130182441.40480-1-philmd@linaro.org> References: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The 32 IRQ lines skipped are the GIC internal ones. Use the GIC_INTERNAL definition for clarity. No logical change. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/exynos4210.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index dd0edc81d5c..99b05a175d6 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -393,8 +393,9 @@ static void exynos4210_init_board_irqs(Exynos4210State *s) } } if (irq_id) { + irq_id -= GIC_INTERNAL; qdev_connect_gpio_out(splitter, splitin, - qdev_get_gpio_in(extgicdev, irq_id - 32)); + qdev_get_gpio_in(extgicdev, irq_id)); } } for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { @@ -413,6 +414,7 @@ static void exynos4210_init_board_irqs(Exynos4210State *s) } if (irq_id) { + irq_id -= GIC_INTERNAL; assert(splitcount < EXYNOS4210_NUM_SPLITTERS); splitter = DEVICE(&s->splitter[splitcount]); qdev_prop_set_uint16(splitter, "num-lines", 2); @@ -421,7 +423,7 @@ static void exynos4210_init_board_irqs(Exynos4210State *s) s->irq_table[n] = qdev_get_gpio_in(splitter, 0); qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n)); qdev_connect_gpio_out(splitter, 1, - qdev_get_gpio_in(extgicdev, irq_id - 32)); + qdev_get_gpio_in(extgicdev, irq_id)); } else { s->irq_table[n] = qdev_get_gpio_in(intcdev, n); } From patchwork Thu Jan 30 18:24:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 860891 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp329696wrr; Thu, 30 Jan 2025 10:27:55 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXSM4YufJalMoxqZpuuLsGqfzmERgJE7HKhqkvfklNC2y0G8tJoy7VYLGam/3+ifmIn8Msz2A==@linaro.org X-Google-Smtp-Source: AGHT+IFypsfZwt64iHkxMsun8HnKG9r7ojGm/wv4hnPKurkaE70p8r1xeBXePntx4FrLvQgHbrzK X-Received: by 2002:a05:620a:191c:b0:7be:82e5:5693 with SMTP id af79cd13be357-7bffcce96bemr1101428685a.20.1738261675039; Thu, 30 Jan 2025 10:27:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738261675; cv=none; d=google.com; s=arc-20240605; b=JXekuah4NNb4G7A2LUEU/asUGdttufIiIREsWS+AZWaQBdyhR0u6qH5LekNr14cE+E uliHg061DAwn06L3jH+lBQoY9ClDQwSiY5gsRDbmuBK1OLvYhDVHol7iB6x7LUBnOPQs 4yLWe1YwMTG20g4OGtQVs3cbNK2nXjWZum7zdhTCALwg54IfuINFuQhiy1n64WKK2Adn zH84uv4wvMTjM2cYoEg0ZdYAw/tbW3ca80CtAEOEwxhDuvMiSYQ62fZDzcXnwYeKAKS8 vdm5lwXEsdZAa6KoAUg/D0UVKY0vgvHV+j5Uj/zxk3/pAZGWMex85d2+11PRdFoW1NfO 8JSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vZk0oTGxDURxLqCpPV0Zd69bGvF/XaBnOTd5i1RlcsU=; fh=SthhPtpqdehNGJNgy7ndeFIc3MS4iW7BmkhpFgvGJVQ=; b=iLO/K+CFvDxvEKJfKKRSAGfv4RtSxbfS+U+DqUXS0tB1CRvnLCWxajZ+DDe/fJ8+Or /D0bXXdGz400zP4/RXdTwRvyd3oW+qitebMOwScn+C1bc+Bmoh64AxmKvGRc285wnx+m 4pmANEUUeRj9WYlxRjcznAELig0eVAxKJQwqCBeS55XGHxJMg62EpWtBD6EbhWSxWD7F eh1tGhfRCp8+btk3faiwK4hIgukzZH6vbnbTs3f3YPo8NtQSLo+XcsRjBo9hHFd4JIhA oZ9CZmMXuO9nsyKYsTnYO+BcDQh7rRzaEyAfjE4lDWYUHE/lgJQRzWSnD0Bkl4KdaC7e NNEA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D2ttSnEm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c1b5780sm2721855f8f.67.2025.01.30.10.25.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Jan 2025 10:25:40 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 2/8] hw/arm/exynos4210: Explicit number of GIC external IRQs Date: Thu, 30 Jan 2025 19:24:35 +0100 Message-ID: <20250130182441.40480-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250130182441.40480-1-philmd@linaro.org> References: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When not specified, Cortex-A9MP configures its GIC with 64 external IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/exynos4210.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 99b05a175d6..75d6e4d1ab9 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -103,6 +103,14 @@ #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 +/* + * The Cortex-A9MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 64+32, which + * is the number provided by the Cortex-A9MP test chip in the + * Realview PBX-A9 and Versatile Express A9 development boards. + */ +#define GIC_EXT_IRQS 64 + enum ExtGicId { EXT_GIC_ID_MDMA_LCD0 = 66, EXT_GIC_ID_PDMA0, @@ -588,6 +596,8 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) /* Private memory region and Internal GIC */ qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS); + qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-irq", + GIC_EXT_IRQS + GIC_INTERNAL); busdev = SYS_BUS_DEVICE(&s->a9mpcore); sysbus_realize(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); From patchwork Thu Jan 30 18:24:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 860884 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp329058wrr; Thu, 30 Jan 2025 10:26:50 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWZqkXcip2nVjcBEZL56La3GJ9+DOB06x1hkAQTBekyhUB6VtswE574XsF6g6v2uWN0ocY1tg==@linaro.org X-Google-Smtp-Source: AGHT+IHdh/cTVjXBWyoOA9hDwPZY4JNumw+hSNPv1xFW5TVhmSik7NWt6GQCBNilWdYkFkGubcUZ X-Received: by 2002:a05:6214:487:b0:6d4:25c4:e772 with SMTP id 6a1803df08f44-6e243ca765amr155119196d6.36.1738261609975; Thu, 30 Jan 2025 10:26:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738261609; cv=none; d=google.com; s=arc-20240605; b=ikYOLlaRWwXKYxEyGuivLOUhxaJChb2PTzNDWXSyebVbB7tej2nKvXOrSboTxO6Emy uMSqltlaYtzW+7ewr2AZV6OGMlc9BAuhxvuGa+U/EmFr7orpL3vjQgTRjolmLCNVJCxS flDgosbw38ebDoJIkWjMWYX9z2R0Qb9o+eJ1IcEjQXJbBcM8a6+Dem69VblH8/020DoN BTXvovv1/6NSfqm/YTO+TFmogTGoJn+9gt33nS4hNKWfLUyMAScbV5/HVRp7NiXAFJoZ Hwa4kFT6CIyxeFkdEM/4QzLDhT4Af6vbMkjgMmVKDy1AeNoQK4dGeSeUdvC+prAkiDwN PA7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9Z3aEZJL4Zoy5jUwLn3/iNglhcvTDiQUnyONCdVRxkU=; fh=SthhPtpqdehNGJNgy7ndeFIc3MS4iW7BmkhpFgvGJVQ=; b=IQ/wYxTdRqH+eMkpP3FtkVsDjlWLzF7MLC7CdiyULK9kOmphSGsx2EjX7L33BDZD+8 OUvqPOXBuS4mGQDqPAjAm2iYBsqHe+Cx2DTy4mHSMMt2rlDMc9lh5ko2pubsvDIAW1s4 R/crLsBseAeqZ1+svwdGWAA98IzPCXo3diqpY3K4a5iCfNbV5Vk9ByZT1vmz8hdIS3L2 va7o/pgYrqgNMKOvesVimguIipO5YmyKUJHgVfnu98MX8GQ0M0EGncbNimi2JwvgqJmy iG1JuddlOz/3howYZRkhAQha6D1TF+AJd9lNrd/O+xVqDxTRWvGVd/ocRu3rGBe2a8dU qvCg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=asK31Kya; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438dcc2f17dsm66550335e9.23.2025.01.30.10.25.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Jan 2025 10:25:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 3/8] hw/arm/realview: Explicit number of GIC external IRQs Date: Thu, 30 Jan 2025 19:24:36 +0100 Message-ID: <20250130182441.40480-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250130182441.40480-1-philmd@linaro.org> References: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When not specified, Cortex-A9MP configures its GIC with 64 external IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/realview.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 9900a98f3b8..4a62c83506b 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -35,6 +35,14 @@ #define SMP_BOOT_ADDR 0xe0000000 #define SMP_BOOTREG_ADDR 0x10000030 +/* + * The Cortex-A9MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 64+32, which + * is the number provided by the Cortex-A9MP test chip in the + * Realview PBX-A9 and Versatile Express A9 development boards. + */ +#define GIC_EXT_IRQS 64 + /* Board init. */ static struct arm_boot_info realview_binfo = { @@ -185,7 +193,12 @@ static void realview_init(MachineState *machine, sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); if (is_mpcore) { - dev = qdev_new(is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore"); + if (is_pb) { + dev = qdev_new(TYPE_A9MPCORE_PRIV); + qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); + } else { + dev = qdev_new("realview_mpcore"); + } qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); @@ -201,7 +214,7 @@ static void realview_init(MachineState *machine, /* For now just create the nIRQ GIC, and ignore the others. */ dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]); } - for (n = 0; n < 64; n++) { + for (n = 0; n < GIC_EXT_IRQS; n++) { pic[n] = qdev_get_gpio_in(dev, n); } From patchwork Thu Jan 30 18:24:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 860893 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp329973wrr; Thu, 30 Jan 2025 10:28:29 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXvsXJ9j4afLyZkYAerBEuTGBqe+l4ClnC628CzXGizMESpoB0mGmJKikfRM+6jfKmLAcANKQ==@linaro.org X-Google-Smtp-Source: AGHT+IE9IwFcva5CBsfiXiDtiXvrR3YFuqZQ/59p+0rWXhYVHwTAIje+Yrw41lh6d/AIOiTWjHDK X-Received: by 2002:a05:622a:1aaa:b0:462:e827:c11a with SMTP id d75a77b69052e-46fd0aa2018mr135948911cf.19.1738261709632; Thu, 30 Jan 2025 10:28:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738261709; cv=none; d=google.com; s=arc-20240605; b=C6FvrHCP5P0y6JbIP8GzZRMXzn7uKzqp0+BIYBzhvOH0w3bD1H+bcmvu0B2utRXW6w 430M/rQT+r/RxXE5eJal8O5VMwX/P6KzrDdkt1Fpxtm4jfWT1aNWGiBnDK/y97Kku+If Boj9C6FakIDsxMnXypmCYPmm7jL6+y1u956MRf7twJ+tKtlCremrMnTb7DkBfnlzCiJQ +Yu+YSlFrmGnVD7vjoS86fLHPMTKpZXJFvN9sBTVBfqw/t0VDfhWRiupzCZizJAQ15P7 RIUIQSyrSkI5xx4HT3eBH8UBM13a8/T5PX/DGY0tLaToJ26f5CmTdSgso24uAdNJlYP1 DB3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Ffy+7tyS7lEIAtYpG0ijLba+piKy+IqvYcNHx83E6nQ=; fh=SthhPtpqdehNGJNgy7ndeFIc3MS4iW7BmkhpFgvGJVQ=; b=BDinx4dytGtaS9tlKmbz8nqylGa8DiqykFOQ6EkdNK5DO3tuaqYaeeCIoTbEgZntGP C58fmeR+vL6CK/zHIH9GLWnxObWgeAw1huwwnqwg788vhOaFWJ8iKUO8fqS749PKxVSM Ry0iXvRjqZQ4I99uatpvidxnNaurkMMkFnjmAY9JUA/LVer7WQ7m6eX/66AY1Pbqavmy /KKDoT01XO9hf8eIzWDQub8z7Art2Q/JvkOXKhxM/Pz8H6Ur6NQ75GcIQp7tL347E36l zydXEwMNpr4s2Vgzxj0uXLV2/h4WUBk2T1AnKKfgUygge5jD6hLjGFOJO/8Sd7HK/HzO apnQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FgWrhkx7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438e23e6bf8sm31108925e9.23.2025.01.30.10.26.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Jan 2025 10:26:02 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 4/8] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL Date: Thu, 30 Jan 2025 19:24:37 +0100 Message-ID: <20250130182441.40480-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250130182441.40480-1-philmd@linaro.org> References: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We already have a definition to distinct GIC internal IRQs versus external ones, use it. No logical changes. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/xilinx_zynq.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 8477b828745..18051458945 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -54,8 +54,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) #define FLASH_SIZE (64 * 1024 * 1024) #define FLASH_SECTOR_SIZE (128 * 1024) -#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ - #define MPCORE_PERIPHBASE 0xF8F00000 #define ZYNQ_BOARD_MIDR 0x413FC090 @@ -281,12 +279,12 @@ static void zynq_init(MachineState *machine) pic[n] = qdev_get_gpio_in(dev, n); } - n = zynq_init_spi_flashes(0xE0006000, pic[58 - IRQ_OFFSET], false, 0); - n = zynq_init_spi_flashes(0xE0007000, pic[81 - IRQ_OFFSET], false, n); - n = zynq_init_spi_flashes(0xE000D000, pic[51 - IRQ_OFFSET], true, n); + n = zynq_init_spi_flashes(0xE0006000, pic[58 - GIC_INTERNAL], false, 0); + n = zynq_init_spi_flashes(0xE0007000, pic[81 - GIC_INTERNAL], false, n); + n = zynq_init_spi_flashes(0xE000D000, pic[51 - GIC_INTERNAL], true, n); - sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); - sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]); + sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - GIC_INTERNAL]); + sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - GIC_INTERNAL]); dev = qdev_new(TYPE_CADENCE_UART); busdev = SYS_BUS_DEVICE(dev); @@ -295,7 +293,7 @@ static void zynq_init(MachineState *machine) qdev_get_clock_out(slcr, "uart0_ref_clk")); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, 0xE0000000); - sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]); + sysbus_connect_irq(busdev, 0, pic[59 - GIC_INTERNAL]); dev = qdev_new(TYPE_CADENCE_UART); busdev = SYS_BUS_DEVICE(dev); qdev_prop_set_chr(dev, "chardev", serial_hd(1)); @@ -303,15 +301,15 @@ static void zynq_init(MachineState *machine) qdev_get_clock_out(slcr, "uart1_ref_clk")); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, 0xE0001000); - sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]); + sysbus_connect_irq(busdev, 0, pic[82 - GIC_INTERNAL]); sysbus_create_varargs("cadence_ttc", 0xF8001000, - pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); + pic[42-GIC_INTERNAL], pic[43-GIC_INTERNAL], pic[44-GIC_INTERNAL], NULL); sysbus_create_varargs("cadence_ttc", 0xF8002000, - pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); + pic[69-GIC_INTERNAL], pic[70-GIC_INTERNAL], pic[71-GIC_INTERNAL], NULL); - gem_init(0xE000B000, pic[54 - IRQ_OFFSET]); - gem_init(0xE000C000, pic[77 - IRQ_OFFSET]); + gem_init(0xE000B000, pic[54 - GIC_INTERNAL]); + gem_init(0xE000C000, pic[77 - GIC_INTERNAL]); for (n = 0; n < 2; n++) { int hci_irq = n ? 79 : 56; @@ -330,7 +328,7 @@ static void zynq_init(MachineState *machine) qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - GIC_INTERNAL]); di = drive_get(IF_SD, 0, n); blk = di ? blk_by_legacy_dinfo(di) : NULL; @@ -343,7 +341,7 @@ static void zynq_init(MachineState *machine) dev = qdev_new(TYPE_ZYNQ_XADC); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-GIC_INTERNAL]); dev = qdev_new("pl330"); object_property_set_link(OBJECT(dev), "memory", @@ -363,15 +361,15 @@ static void zynq_init(MachineState *machine) busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, 0xF8003000); - sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ + sysbus_connect_irq(busdev, 0, pic[45-GIC_INTERNAL]); /* abort irq line */ for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */ - sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); + sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - GIC_INTERNAL]); } dev = qdev_new("xlnx.ps7-dev-cfg"); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); - sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); + sysbus_connect_irq(busdev, 0, pic[40 - GIC_INTERNAL]); sysbus_mmio_map(busdev, 0, 0xF8007000); /* From patchwork Thu Jan 30 18:24:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 860888 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp329417wrr; Thu, 30 Jan 2025 10:27:24 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVL3fYMb6odoQFsuAViaGtpSnYAfiCj3Y2Uzv0McVGOQZK1Ea1fEaNVr/sEemIDxRQU289nHg==@linaro.org X-Google-Smtp-Source: AGHT+IG9VPN4d9o5ewRNRfnHvp00FzAs6euKLMO3vYsOVMgui6O3tvXq5qdVtdLc9KSzHUMIeAhL X-Received: by 2002:a05:620a:4247:b0:7b6:d393:c213 with SMTP id af79cd13be357-7bffcccaf39mr1252023485a.8.1738261644642; Thu, 30 Jan 2025 10:27:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738261644; cv=none; d=google.com; s=arc-20240605; b=ZPaB4bWO4FLuPyDUmpu7Pcto2mxBh4rjGIhOCeR+kk5SqG+NXXnmrBgwCmPLet8mFV PFgLuLG41bHAO+BX8eRSM1AbkjzYiXe+t0dIY9yizi775i4u5nUcCaW4BB8tW36x2t7Y fOQ5W+vrWluMWvGw1K1uURWBvPKdur2MV3ErM9BB2uxDSEgEesPcvTWhqPh+EEQ80zl9 W3aJmy41CRw98bsj9R0JojERfaGHm/zbwxbc3sMrN6YNGQ/HoWygpwkMZ0+FP0IGhZE4 bQYlgDbYkoyoztxB7CaPJbg1uqcK4CpDnI1W9zPcvke8Pow98SH/Vo4JHNxElcC//VrR AgMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=94QBa4qt+xo//a/TAZxbNnQCwPiwQSuLzPc2Zl2fPdo=; fh=SthhPtpqdehNGJNgy7ndeFIc3MS4iW7BmkhpFgvGJVQ=; b=jqLkDpkPfMJOoJ1NOj633t+psUyfiPBFiPdqIwWcybc2IIypBiW77NwoIKwGf/O5c7 /TU2ED4iJe2WgS/RVmuHlSEXWalQI4S/oUwjqDyzESGKtlnKnrd/cz0tvQbimWkRsZPg vlGhi/MIiSdMaaw/f+h07c4/OrAPCuxH57DLLRaKQVlNzKEjuivpJiV/VwMLEyHDhvOJ W7tS4Nb8rEfsnmTJENciHC06EOjZ+GQupsa/efh9gLDoVjViMG5u+y7XAOMdP0AxrdNj wZslk4Bdr7Y6l9UZVOsSKLtQHH+KtIWqAuSyveuEuB2MbdbG3+YhBOWmSj3FXW1vaIil FPrQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XBtH51ix; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438dcc2ede0sm67053955e9.21.2025.01.30.10.26.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Jan 2025 10:26:18 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 5/8] hw/arm/xilinx_zynq: Explicit number of GIC external IRQs Date: Thu, 30 Jan 2025 19:24:38 +0100 Message-ID: <20250130182441.40480-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250130182441.40480-1-philmd@linaro.org> References: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When not specified, Cortex-A9MP configures its GIC with 64 external IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/xilinx_zynq.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 18051458945..dbb003e906a 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -57,6 +57,14 @@ OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) #define MPCORE_PERIPHBASE 0xF8F00000 #define ZYNQ_BOARD_MIDR 0x413FC090 +/* + * The Cortex-A9MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 64+32, which + * is the number provided by the Cortex-A9MP test chip in the + * Realview PBX-A9 and Versatile Express A9 development boards. + */ +#define GIC_EXT_IRQS 64 + static const int dma_irqs[8] = { 46, 47, 48, 49, 72, 73, 74, 75 }; @@ -205,7 +213,7 @@ static void zynq_init(MachineState *machine) MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); DeviceState *dev, *slcr; SysBusDevice *busdev; - qemu_irq pic[64]; + qemu_irq pic[GIC_EXT_IRQS]; int n; unsigned int smp_cpus = machine->smp.cpus; @@ -261,6 +269,7 @@ static void zynq_init(MachineState *machine) dev = qdev_new(TYPE_A9MPCORE_PRIV); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); + qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); @@ -275,7 +284,7 @@ static void zynq_init(MachineState *machine) qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); } - for (n = 0; n < 64; n++) { + for (n = 0; n < GIC_EXT_IRQS; n++) { pic[n] = qdev_get_gpio_in(dev, n); } From patchwork Thu Jan 30 18:24:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 860890 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp329683wrr; Thu, 30 Jan 2025 10:27:53 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUq71PLiFuTURfy36MS/ErOcTIfj/kIkurDftNQCeZ9LMajLdg0/jfh4v4wegBd1UHMJ5TCjw==@linaro.org X-Google-Smtp-Source: AGHT+IHe/yswdzlrxype5kD+rVVxxAL9E9A7h+MGiU+6++DhBgsF6Cl1bFTmf0WWahF5/C7xlvxV X-Received: by 2002:ac8:5f8f:0:b0:467:672a:abb6 with SMTP id d75a77b69052e-46fd0acbcebmr122141771cf.23.1738261673010; Thu, 30 Jan 2025 10:27:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738261673; cv=none; d=google.com; s=arc-20240605; b=Ci/lzZ/jS7NKVS1RCUWdJsaweLkvdulw/1fUgKHy2B1RKx/ywWQpEa1sqjJbG7WOse xohzdRe5r3G6eUcIN2OSiaHjr81GaGQ4smVgsx3E1estKZT0UkBJT3TxZuHPgVvlbM8G WTaFRNGUKvD/U8/cz1vCvBGOT2pfMmmQtn3E3mboxNgcva0zWyqzeqlt3jv4Melji0i2 DCmOSIBHKiYGG2d+UMV63eMQT/acz9q5lb+QJQV8qhhz/+vebTgKRZ4DY50cUmsCF1Ff J8CmE/u7heEhtCm1YUhzaUHOYEKs3dmjxwHSIz5Xv/nz04QCylFs4ZqwHf4UVdbJkXHI 1x4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=riA4zmJH/fUcpHKgfppzYaaXrF+oAl0RGRsil+s6hSg=; fh=SthhPtpqdehNGJNgy7ndeFIc3MS4iW7BmkhpFgvGJVQ=; b=JSkVGE+K2dd6Cn59I67H2W820npdtv9OxuTBB30+39ECFrSMhNWahvIFqjibxcP+aj iJJK4Wk5yDihQujGL0qOMozVcIzkLwUQS8eTJjWkEBTOFx9mNIDFU+zSruXP32fQv/bI 6dNxFUsG5vpydbL8G8kmlUv9bAbDks+nJg1t0Yic8ZhzwIgG9rnZ/5DioAdRa550a6Lc jyy3qhqNFXvq1M7H9M17RCQCGR05InnqvL3w2hgsbF2SA8ahsO0TOgxq1f6u0OMYD9vu yW3R17hxdEFalr5i6+1uHzJM1feh4I4rhXa/g7PwkqSy0Ub6Y7/4DZFzHoN2lC1FYryF Budw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R0WXohcB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438dcc26d05sm66624965e9.12.2025.01.30.10.26.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Jan 2025 10:26:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 6/8] hw/arm/vexpress: Explicit number of GIC external IRQs Date: Thu, 30 Jan 2025 19:24:39 +0100 Message-ID: <20250130182441.40480-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250130182441.40480-1-philmd@linaro.org> References: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When not specified, Cortex-A9MP configures its GIC with 64 external IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"), and Cortex-15MP to 128 (see commit 528622421eb "hw/cpu/a15mpcore: Correct default value for num-irq"). The Versatile Express board however expects a fixed set of 64 interrupts (see the fixed IRQ length when this board was added in commit 2055283bcc8 ("hw/vexpress: Add model of ARM Versatile Express board"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/vexpress.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 42c67034061..8e801aa79cb 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -51,6 +51,14 @@ #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) +/* + * The Cortex-A9MP/A15MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 64+32, which + * is the number provided by the Cortex-A9MP test chip in the + * Realview PBX-A9 and Versatile Express A9 development boards. + */ +#define GIC_EXT_IRQS 64 + /* Number of virtio transports to create (0..8; limited by * number of available IRQ lines). */ @@ -241,6 +249,7 @@ static void init_cpus(MachineState *ms, const char *cpu_type, */ dev = qdev_new(privdev); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); + qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, periphbase); @@ -251,7 +260,7 @@ static void init_cpus(MachineState *ms, const char *cpu_type, * external interrupts starting from 32 (because there * are internal interrupts 0..31). */ - for (n = 0; n < 64; n++) { + for (n = 0; n < GIC_EXT_IRQS; n++) { pic[n] = qdev_get_gpio_in(dev, n); } @@ -543,7 +552,7 @@ static void vexpress_common_init(MachineState *machine) VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); VEDBoardInfo *daughterboard = vmc->daughterboard; DeviceState *dev, *sysctl, *pl041; - qemu_irq pic[64]; + qemu_irq pic[GIC_EXT_IRQS]; uint32_t sys_id; DriveInfo *dinfo; PFlashCFI01 *pflash0; From patchwork Thu Jan 30 18:24:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 860889 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp329442wrr; Thu, 30 Jan 2025 10:27:26 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUXyhpJB7xnvqxozGO33LGHqLfMD88XvdaragFuj1M7FEcJx77jiYu+QFau+ny0im2cxXACSw==@linaro.org X-Google-Smtp-Source: AGHT+IEyTvAZ71kCi2NIaujwvfFRtrf5qj7NknzuERzVjkU640Pemv/kSkLxaA3LlVp7tGBsmqTD X-Received: by 2002:a05:620a:bc5:b0:7b1:4a2a:9ae0 with SMTP id af79cd13be357-7c011da6371mr81561785a.9.1738261646321; Thu, 30 Jan 2025 10:27:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738261646; cv=none; d=google.com; s=arc-20240605; b=GjBRaI/qleAJwAeTPgh5WZLq9R2ZVl2tEVI2rs9b4xpx1xM54j8ATUPf5QEh+9wZB4 BMuWWzryxoEoAfZKRmf6rJpvaQdncme+wIO59wnZ4+IwE9qy2BwrNNuyxkSU4KXBMx58 RIS+2N/6+h8nKOwlxfZKOjswuP5vNNLCuFQVNkz5kYpPquhjSUtjprBirfQzye5QN15F w2jUsFTF5kTgvbQTYuyqFA7CLMfCh91xUmPxmjGQMIB1PtWui/cfa8Epz8PBI+ghD5pG DAqPG9dbokZtObdwmEbVRfvYHZMSlpBvRB9shiMF8WeoerhH22N8usIFesiCclqwp2U2 Pptw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DSiba+A4z/eFTmtOIndcY8wTtwzH+kBQH69a+P0DCPY=; fh=SthhPtpqdehNGJNgy7ndeFIc3MS4iW7BmkhpFgvGJVQ=; b=fumZpFZgkUswHypAbi3Juzyq+wly22CIQdP0Wg2qXazDekIuqk1wj1PW/qii+BdHI9 SymK6xR+Sp2DN4j/7XdU8SKbsLpJ9JUysIniNll1qRQilcBwTIuYG0NY4Nl3sT4/LJg8 G/OpvDmApxUUo8/J/+D/73giEdjSzh+8r2oVVWdOkHJKGoXEOK/No2s72/Dnibvu372A nx9YkhmRrMzBE7pM4MH0kTLbXC8h+YH4tqd8YR6VaN3yuMNXFmg+5v4ZKKt7eFx2rbtZ IsjWsTolKazNW8QFv3rNJpQmInOZ97O3iAC7T+zcebNzsPQlVO5ZSbwtNwb2X6HpAYqa rDlw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Is6RaXYm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c122539sm2730881f8f.46.2025.01.30.10.26.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Jan 2025 10:26:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 7/8] hw/arm/highbank: Explicit number of GIC external IRQs Date: Thu, 30 Jan 2025 19:24:40 +0100 Message-ID: <20250130182441.40480-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250130182441.40480-1-philmd@linaro.org> References: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When not specified, Cortex-A9MP configures its GIC with 64 external IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"), and Cortex-15MP to 128 (see commit 528622421eb "hw/cpu/a15mpcore: Correct default value for num-irq"). The Caldexa Highbank board however expects a fixed set of 128 interrupts (see the fixed IRQ length when this board was added in commit 2488514cef2 ("arm: SoC model for Calxeda Highbank"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/highbank.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 495704d9726..d59f20b88e0 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -45,7 +45,14 @@ #define MVBAR_ADDR 0x200 #define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t)) -#define NIRQ_GIC 160 +/* + * The Cortex-A9MP/A15MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 128+32, which + * is the number provided by the Cortex-A15MP test chip in the + * Versatile Express A15 development board. + * Other boards may differ and should set this property appropriately. + */ +#define GIC_EXT_IRQS 128 /* Board init. */ @@ -180,7 +187,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) { DeviceState *dev = NULL; SysBusDevice *busdev; - qemu_irq pic[128]; + qemu_irq pic[GIC_EXT_IRQS]; int n; unsigned int smp_cpus = machine->smp.cpus; qemu_irq cpu_irq[4]; @@ -260,7 +267,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) break; } qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); - qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); + qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); @@ -271,7 +278,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]); } - for (n = 0; n < 128; n++) { + for (n = 0; n < GIC_EXT_IRQS; n++) { pic[n] = qdev_get_gpio_in(dev, n); } From patchwork Thu Jan 30 18:24:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 860892 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp329794wrr; Thu, 30 Jan 2025 10:28:08 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVGXbC7R6gm+zSOZUmhM9wMsZLgu1jaLufoH/f5Mfeg8DKu6e8kmDVSbngaxPXP84y5CKsqDQ==@linaro.org X-Google-Smtp-Source: AGHT+IFbC9Z6+6m5JsFMeMhPbnd2t6aa5N7OfY8iwtGgdNxpCbf19q4xwgHOtdtGWYcxFEHYUa5C X-Received: by 2002:ac8:7dd0:0:b0:467:59f6:3e56 with SMTP id d75a77b69052e-46fd0b68df0mr109522791cf.36.1738261687888; Thu, 30 Jan 2025 10:28:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738261687; cv=none; d=google.com; s=arc-20240605; b=aagd8jBIbsbEbguD5YcFSGl7pGS5r9PADTX7hG16Yitc2jG9PqA/wsn1xn43tAQlov 8CtuGhk6P7uTV/CcmpdGAVaa3ihGq+op9YpyGapOVcqrgVsnL/kVo/RDVBZV5v0lvMg3 w5KLK0wOJGQtXvmg51XHZvT9tgC+uFkSYcJ4Y5QZQ6zW3C+IWQGBrejh8MfT5lKPXhs3 oWF2YvyEXJTQwP0hbxCTZTPhSqzWIOFcAxhUDo9X+lZQt5d/kc46PHqdXjRTsBasLLqp SCFjKzPJZhYIfTVmyvBe85go12odiSqW051nDpDNzyGsQbeSFh3zoiKeJTMZ5vevFbn4 Uiig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XQNs/MO88QA6DkNCjxkxynlmOBFAmoCxktVishKIMrs=; fh=SthhPtpqdehNGJNgy7ndeFIc3MS4iW7BmkhpFgvGJVQ=; b=j/301YGPO35GC2oBsL/p/DHACYGtfpnZYyeYUv5jux7JGUmO17uZOJvN9Fm15zJyLN 23FS0om6C1SuXu6fO2PObXRkEWitACb5GykpuzqWINfoH3tgZWVVEOoMPDNjEQmwtv+f v9LFkVnmdqprFDsNC33pCMiP2NxudY3vBwHYxiU4+Pd/w5ZUDQoOFQWSnCBCf5TWQOy1 jJ30jAROA8JU+t6IxTKC8+wZChT6TlfS7eBrjFhahVEM47dY3Y+Dh5dBHahD/4W6uEyf 9bgXJA2iCHSOU7HVlBTosLrjehodl7nmkNkIFu1q8zBa9zR5ZqPSPtLEZBBgGWYWr9NF n+rw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uMkq8ODr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438e23de2d6sm30922185e9.11.2025.01.30.10.27.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Jan 2025 10:27:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 8/8] hw/cpu/arm_mpcore: Remove default values for GIC external IRQs Date: Thu, 30 Jan 2025 19:24:41 +0100 Message-ID: <20250130182441.40480-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250130182441.40480-1-philmd@linaro.org> References: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Implicit default values are often hard to figure out, better be explicit. Now that all boards explicitly set the number of GIC external IRQs, remove the default values (displaying an error message if it is not set). Signed-off-by: Philippe Mathieu-Daudé --- hw/cpu/a15mpcore.c | 13 ++++++------- hw/cpu/a9mpcore.c | 14 +++++++------- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 3b0897e54ee..372b615178f 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -58,6 +58,11 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) bool has_el2 = false; Object *cpuobj; + if (!s->num_irq) { + error_setg(errp, "Property 'num-irq' not set"); + return; + } + gicdev = DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); @@ -146,13 +151,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) static const Property a15mp_priv_properties[] = { DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), - /* The Cortex-A15MP may have anything from 0 to 224 external interrupt - * IRQ lines (with another 32 internal). We default to 128+32, which - * is the number provided by the Cortex-A15MP test chip in the - * Versatile Express A15 development board. - * Other boards may differ and should set this property appropriately. - */ - DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160), + DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 0), }; static void a15mp_priv_class_init(ObjectClass *klass, void *data) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 9671585b5f9..c522f8d4b05 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -56,6 +56,12 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) CPUState *cpu0; Object *cpuobj; + + if (!s->num_irq) { + error_setg(errp, "Property 'num-irq' not set"); + return; + } + cpu0 = qemu_get_cpu(0); cpuobj = OBJECT(cpu0); if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9"))) { @@ -160,13 +166,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) static const Property a9mp_priv_properties[] = { DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), - /* The Cortex-A9MP may have anything from 0 to 224 external interrupt - * IRQ lines (with another 32 internal). We default to 64+32, which - * is the number provided by the Cortex-A9MP test chip in the - * Realview PBX-A9 and Versatile Express A9 development boards. - * Other boards may differ and should set this property appropriately. - */ - DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), + DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 0), }; static void a9mp_priv_class_init(ObjectClass *klass, void *data)