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[176.92.181.30]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438dcc6df2asm48076345e9.29.2025.01.29.23.21.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 23:21:14 -0800 (PST) From: Ilias Apalodimas To: maz@kernel.org, trini@konsulko.com, CFSworks@gmail.com Cc: Ilias Apalodimas , Caleb Connolly , Neil Armstrong , Sumit Garg , Heinrich Schuchardt , Simon Glass , Marek Vasut , Peter Robinson , =?utf-8?q?Pierre-Cl=C3=A9ment_Tosi?= , Sam Protsenko , Sughosh Ganu , Peng Fan , Richard Henderson , Andre Przywara , Peter Hoyes , Patrick Rudolph , Sam Day , Evgeny Bachinin , Jerome Forissier , Michal Simek , Christian Marangi , u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [RFC PATCH 1/4] meminfo: add memory details for armv8 Date: Thu, 30 Jan 2025 09:20:26 +0200 Message-ID: <20250130072100.27297-2-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250130072100.27297-1-ilias.apalodimas@linaro.org> References: <20250130072100.27297-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Upcoming patches are mapping memory with RO, RW^X etc permsissions. Fix the meminfo command to display them properly Signed-off-by: Ilias Apalodimas Acked-by: Jerome Forissier --- arch/arm/cpu/armv8/cache_v8.c | 18 +++++++++++++++++- arch/arm/include/asm/armv8/mmu.h | 2 ++ cmd/meminfo.c | 5 +++++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 5d6953ffedd1..a4ca56c8ed42 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -421,7 +421,7 @@ static int count_ranges(void) return count; } -#define ALL_ATTRS (3 << 8 | PMD_ATTRINDX_MASK) +#define ALL_ATTRS (3 << 8 | PMD_ATTRMASK) #define PTE_IS_TABLE(pte, level) (pte_type(&(pte)) == PTE_TYPE_TABLE && (level) < 3) enum walker_state { @@ -568,6 +568,17 @@ static void pretty_print_table_attrs(u64 pte) static void pretty_print_block_attrs(u64 pte) { u64 attrs = pte & PMD_ATTRINDX_MASK; + u64 perm_attrs = pte & PMD_ATTRMASK; + + if ((perm_attrs & PTE_BLOCK_PXN) && (perm_attrs & PTE_BLOCK_UXN) && + perm_attrs & PTE_BLOCK_RO) + printf("%-5s", " | RO"); + else if ((perm_attrs & PTE_BLOCK_PXN) && (perm_attrs & PTE_BLOCK_UXN)) + printf("%-5s", " | RW"); + else if (perm_attrs & PTE_BLOCK_RO) + printf("%-5s", " | RX"); + else + printf("%-5s", " | RWX"); switch (attrs) { case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE): @@ -1112,3 +1123,8 @@ void __weak enable_caches(void) icache_enable(); dcache_enable(); } + +void arch_dump_mem_attrs(void) +{ + dump_pagetable(gd->arch.tlb_addr, get_tcr(NULL, NULL)); +} diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 0ab681c893d3..6af8cd111a44 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -66,6 +66,7 @@ #define PTE_BLOCK_NG (1 << 11) #define PTE_BLOCK_PXN (UL(1) << 53) #define PTE_BLOCK_UXN (UL(1) << 54) +#define PTE_BLOCK_RO (UL(1) << 7) /* * AttrIndx[2:0] @@ -75,6 +76,7 @@ #define PMD_ATTRMASK (PTE_BLOCK_PXN | \ PTE_BLOCK_UXN | \ PMD_ATTRINDX_MASK | \ + PTE_BLOCK_RO | \ PTE_TYPE_VALID) /* diff --git a/cmd/meminfo.c b/cmd/meminfo.c index 5e83d61c2dd3..3915e2bbb268 100644 --- a/cmd/meminfo.c +++ b/cmd/meminfo.c @@ -15,6 +15,10 @@ DECLARE_GLOBAL_DATA_PTR; +void __weak arch_dump_mem_attrs(void) +{ +} + static void print_region(const char *name, ulong base, ulong size, ulong *uptop) { ulong end = base + size; @@ -54,6 +58,7 @@ static int do_meminfo(struct cmd_tbl *cmdtp, int flag, int argc, puts("DRAM: "); print_size(gd->ram_size, "\n"); + arch_dump_mem_attrs(); if (!IS_ENABLED(CONFIG_CMD_MEMINFO_MAP)) return 0; From patchwork Thu Jan 30 07:20:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilias Apalodimas X-Patchwork-Id: 860843 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp17876wrr; Wed, 29 Jan 2025 23:21:29 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUSRBelvAfjk5Dlz8JelZHl1F+CdGUKlj+5D/9vjb70baib+keJVLZbSuYd4i6mNheV0dHq/A==@linaro.org X-Google-Smtp-Source: AGHT+IEy2+TzlEByHippGG6LEni2GsmYpK29R8JyULh6vq9cMmeiWZymduVvDFsO2I5MGklhOMVQ X-Received: by 2002:a05:6402:40c9:b0:5dc:100c:1569 with SMTP id 4fb4d7f45d1cf-5dc5efc4db7mr6002448a12.13.1738221688835; Wed, 29 Jan 2025 23:21:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738221688; cv=none; d=google.com; s=arc-20240605; b=JqkNgaPoMqdq3zIyRk2aqOL/OUNmIea0A16zKdXs2j6pxs/YEb1GMFhDzdBt7zuMGQ +Ec3q8osUFfxyDHeIzAtzW/iqwVaU9fYaTGhZTTWWnkMWUaZN4IuIMKTGHLdft+CZNtY 7ed+Iwk38imuD2Aoacbp9/rLVSMkTqBxFlZmJE6dm61m2rPCGzVry6f4YUuc5rovotyY Jop0RPYOAH9eRuMUM/ngSUsg+mjZ4znc5P8vPTBogej4fyn4bGNvy7T5Qai4WtDqIcnS EpGQ+HU20fezRqAL+b4mXFOSRzYkDEXEFO85nl6x/LC+nHC2xRzCb7qKpSJvJPnPK2NF 1SCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2gAXk5khHCJHZMkLiO2G7OIe/TkpJcjCDBqHXbwPC9U=; fh=JPrP+VswdRef0rwTnkcHgZJh1MXsAwfMcZHZX02g+T0=; b=h9YlOBFYvOCYgffgoi4VXnLmrXOGJP64hZwD+gFgdVjZp90nPIIxq2XXNDo69dAXun UYBrJ/eXn76oq8zjuRn5mRa0esnJ/gc9JsHlYpNI0dUnriBjTWpoCi7ywwiHrdB+vsSj lC0ogJzTpFoKUuiPW65utTmay1MdlV76thF22NqmMllzfwGB0yz2rRjz4SIHVytvE8Np Xr/nM26aiUVt8Y5jgGT2gTJsdmRs/dIa4KZQ6ITpLaU7KmvwAmXW9j6vzahD/b2/C/5+ /5k4CuL3Y2kqtRt/o1/LYIRACodzdO7P42tiibZPMYpckwU/kGVVdisq76QXVSSjV9Uw rcZQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SJNNSPB2; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[176.92.181.30]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438dcc6df2asm48076345e9.29.2025.01.29.23.21.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 23:21:22 -0800 (PST) From: Ilias Apalodimas To: maz@kernel.org, trini@konsulko.com, CFSworks@gmail.com Cc: Ilias Apalodimas , Caleb Connolly , Neil Armstrong , Sumit Garg , Heinrich Schuchardt , Simon Glass , Marek Vasut , Sam Protsenko , =?utf-8?q?Pierre-Cl=C3=A9ment_T?= =?utf-8?q?osi?= , Sughosh Ganu , Peng Fan , Richard Henderson , Peter Hoyes , Andre Przywara , Patrick Rudolph , Sam Day , Evgeny Bachinin , Michal Simek , Jerome Forissier , Christian Marangi , u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [RFC PATCH 2/4] arm: Prepare linker scripts for memory permissions Date: Thu, 30 Jan 2025 09:20:27 +0200 Message-ID: <20250130072100.27297-3-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250130072100.27297-1-ilias.apalodimas@linaro.org> References: <20250130072100.27297-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Upcoming patches are switching the memory mappings to RW, RO, RW^X page permissions after the U-Boot binary and its data are relocated. Add annotations in the linker scripts to and mark text, data, rodata etc sections and align them to a page boundary Signed-off-by: Ilias Apalodimas Acked-by: Jerome Forissier --- Makefile | 15 +++++++++------ arch/arm/cpu/armv8/u-boot.lds | 32 +++++++++++++++++++------------- include/asm-generic/sections.h | 2 ++ lib/efi_loader/efi_runtime.c | 2 ++ 4 files changed, 32 insertions(+), 19 deletions(-) diff --git a/Makefile b/Makefile index 33bb86343c5b..8d7c062ec830 100644 --- a/Makefile +++ b/Makefile @@ -2176,13 +2176,16 @@ System.map: u-boot # ARM relocations should all be R_ARM_RELATIVE (32-bit) or # R_AARCH64_RELATIVE (64-bit). checkarmreloc: u-boot - @RELOC="`$(CROSS_COMPILE)readelf -r -W $< | cut -d ' ' -f 4 | \ + @RELOCS="`$(CROSS_COMPILE)readelf -r -W $< | cut -d ' ' -f 4 | \ grep R_A | sort -u`"; \ - if test "$$RELOC" != "R_ARM_RELATIVE" -a \ - "$$RELOC" != "R_AARCH64_RELATIVE"; then \ - echo "$< contains unexpected relocations: $$RELOC"; \ - false; \ - fi + for reloc in $$RELOCS; do \ + if [ "$$reloc" != "R_ARM_RELATIVE" -a \ + "$$reloc" != "R_AARCH64_RELATIVE" -a \ + "$$reloc" != "R_AARCH64_NONE" ]; then \ + echo "$< contains unexpected relocations: $$reloc"; \ + false; \ + fi; \ + done tools/version.h: include/version.h $(Q)mkdir -p $(dir $@) diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds index 857f44412e07..18e168e27135 100644 --- a/arch/arm/cpu/armv8/u-boot.lds +++ b/arch/arm/cpu/armv8/u-boot.lds @@ -22,7 +22,7 @@ SECTIONS . = ALIGN(8); __image_copy_start = ADDR(.text); - .text : + .text ALIGN(4096): { CPUDIR/start.o (.text*) } @@ -36,9 +36,12 @@ SECTIONS __efi_runtime_stop = .; } - .text_rest : + .text_rest ALIGN(4096) : { + __text_start = .; *(.text*) + . = ALIGN(4096); + __text_end = .; } #ifdef CONFIG_ARMV8_PSCI @@ -98,27 +101,30 @@ SECTIONS } #endif - . = ALIGN(8); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + .rodata ALIGN(4096): { + __start_rodata = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + . = ALIGN(4096); + __end_rodata = .; + } - . = ALIGN(8); - .data : { + .data ALIGN(4096) : { + __start_data = .; *(.data*) + . = ALIGN(4096); + __end_data = .; } - . = ALIGN(8); - - . = .; - . = ALIGN(8); __u_boot_list : { KEEP(*(SORT(__u_boot_list*))); } - .efi_runtime_rel : { + .efi_runtime_rel ALIGN(4096) : { __efi_runtime_rel_start = .; *(.rel*.efi_runtime) *(.rel*.efi_runtime.*) + . = ALIGN(4096); __efi_runtime_rel_stop = .; } @@ -136,10 +142,10 @@ SECTIONS /* * arch/arm/lib/crt0_64.S assumes __bss_start - __bss_end % 8 == 0 */ - .bss ALIGN(8) : { + .bss ALIGN(4096) : { __bss_start = .; *(.bss*) - . = ALIGN(8); + . = ALIGN(4096); __bss_end = .; } diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index b6bca53db10d..5626df796f33 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -23,6 +23,7 @@ extern char __kprobes_text_start[], __kprobes_text_end[]; extern char __entry_text_start[], __entry_text_end[]; extern char __initdata_begin[], __initdata_end[]; extern char __start_rodata[], __end_rodata[]; +extern char __start_data[], __end_data[]; extern char __efi_helloworld_begin[]; extern char __efi_helloworld_end[]; extern char __efi_var_file_begin[]; @@ -63,6 +64,7 @@ static inline int arch_is_kernel_data(unsigned long addr) /* Start of U-Boot text region */ extern char __text_start[]; +extern char __text_end[]; /* This marks the text region which must be relocated */ extern char __image_copy_start[], __image_copy_end[]; diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c index 35eb6a777665..c10a79301a92 100644 --- a/lib/efi_loader/efi_runtime.c +++ b/lib/efi_loader/efi_runtime.c @@ -742,6 +742,8 @@ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map) rel->info, *p, rel->offset); switch (rel->info & R_MASK) { + case 0: + break; case R_RELATIVE: #ifdef IS_RELA newaddr = rel->addend + offset - CONFIG_TEXT_BASE; From patchwork Thu Jan 30 07:20:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilias Apalodimas X-Patchwork-Id: 860844 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp17910wrr; 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[176.92.181.30]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438dcc6df2asm48076345e9.29.2025.01.29.23.21.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 23:21:30 -0800 (PST) From: Ilias Apalodimas To: maz@kernel.org, trini@konsulko.com, CFSworks@gmail.com Cc: Ilias Apalodimas , Caleb Connolly , Neil Armstrong , Sumit Garg , Heinrich Schuchardt , Simon Glass , Marek Vasut , Peter Robinson , =?utf-8?q?Pierre-Cl=C3=A9ment_Tosi?= , Sam Protsenko , Sughosh Ganu , Peng Fan , Richard Henderson , Andre Przywara , Peter Hoyes , Patrick Rudolph , Sam Day , Evgeny Bachinin , Christian Marangi , Michal Simek , Jerome Forissier , u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [RFC PATCH 3/4] arm64: mmu_change_region_attr() add an option not to break PTEs Date: Thu, 30 Jan 2025 09:20:28 +0200 Message-ID: <20250130072100.27297-4-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250130072100.27297-1-ilias.apalodimas@linaro.org> References: <20250130072100.27297-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The ARM ARM on section 8.17.1 describes the cases where break-before-make is required when changing live page tables. Since we can use this function to tweak block and page permssions, where BBM is not required add an extra argument to the function. While at it add a function we can use to change the attributes of normal memory without breaking the pages tables first Signed-off-by: Ilias Apalodimas --- arch/arm/cpu/armv8/cache_v8.c | 27 ++++++++++++++++++++++++- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 10 ++++----- arch/arm/include/asm/system.h | 3 ++- arch/arm/mach-snapdragon/board.c | 2 +- 4 files changed, 34 insertions(+), 8 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index a4ca56c8ed42..60d0870013e8 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -968,11 +968,14 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, * The procecess is break-before-make. The target region will be marked as * invalid during the process of changing. */ -void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) +void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs, bool bbm) { int level; u64 r, size, start; + if (!bbm) + goto skip_bbm; + start = addr; size = siz; /* @@ -997,6 +1000,7 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) gd->arch.tlb_addr + gd->arch.tlb_size); __asm_invalidate_tlb_all(); +skip_bbm: /* * Loop through the address range until we find a page granule that fits * our alignment constraints, then set it to the new cache attributes @@ -1020,6 +1024,27 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) __asm_invalidate_tlb_all(); } +void mmu_set_attrs(phys_addr_t addr, size_t size, int type) +{ + u64 attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE | PTE_TYPE_VALID; + + switch (type) { + case 1: + /* RO */ + attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_RO; + break; + case 2: + /* RX */ + attrs |= PTE_BLOCK_RO; + break; + case 3: + /* RW */ + attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN; + } + + mmu_change_region_attr(addr, size, attrs, false); +} + #else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ /* diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d2d3e346a36f..caf1dab05936 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1573,7 +1573,7 @@ void update_early_mmu_table(void) PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | - PTE_TYPE_VALID); + PTE_TYPE_VALID, true); } else { mmu_change_region_attr( CFG_SYS_SDRAM_BASE, @@ -1581,7 +1581,7 @@ void update_early_mmu_table(void) PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | - PTE_TYPE_VALID); + PTE_TYPE_VALID, true); #ifdef CONFIG_SYS_DDR_BLOCK3_BASE #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE" @@ -1594,7 +1594,7 @@ void update_early_mmu_table(void) PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | - PTE_TYPE_VALID); + PTE_TYPE_VALID, true); mmu_change_region_attr( CONFIG_SYS_DDR_BLOCK3_BASE, gd->ram_size - @@ -1603,7 +1603,7 @@ void update_early_mmu_table(void) PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | - PTE_TYPE_VALID); + PTE_TYPE_VALID, true); } else #endif { @@ -1614,7 +1614,7 @@ void update_early_mmu_table(void) PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | - PTE_TYPE_VALID); + PTE_TYPE_VALID, true); } } } diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index dbf9ab43e280..0a8ca19e45e9 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -287,8 +287,9 @@ void flush_l3_cache(void); * @emerg: Also map the region in the emergency table */ void mmu_map_region(phys_addr_t start, u64 size, bool emerg); -void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs); +void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs, bool bbm); +void mmu_set_attrs(phys_addr_t addr, size_t size, int type); /* * smc_call() - issue a secure monitor call * diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 2ef936aab757..13f4e8e640ef 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -577,7 +577,7 @@ static void carve_out_reserved_memory(void) if (i == count || start + size < res[i].start - SZ_2M) { debug(" 0x%016llx - 0x%016llx: reserved\n", start, start + size); - mmu_change_region_attr(start, size, PTE_TYPE_FAULT); + mmu_change_region_attr(start, size, PTE_TYPE_FAULT, true); /* If this is the final region then quit here before we index * out of bounds... */ From patchwork Thu Jan 30 07:20:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilias Apalodimas X-Patchwork-Id: 860845 Delivered-To: patch@linaro.org Received: by 2002:adf:fb05:0:b0:385:e875:8a9e with SMTP id c5csp17948wrr; Wed, 29 Jan 2025 23:21:46 -0800 (PST) X-Forwarded-Encrypted: i=2; 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[176.92.181.30]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438dcc6df2asm48076345e9.29.2025.01.29.23.21.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 23:21:38 -0800 (PST) From: Ilias Apalodimas To: maz@kernel.org, trini@konsulko.com, CFSworks@gmail.com Cc: Ilias Apalodimas , Caleb Connolly , Neil Armstrong , Sumit Garg , Heinrich Schuchardt , Simon Glass , Marek Vasut , =?utf-8?q?Pierre-Cl=C3=A9men?= =?utf-8?q?t_Tosi?= , Sam Protsenko , Sughosh Ganu , Peng Fan , Richard Henderson , Peter Hoyes , Andre Przywara , Patrick Rudolph , Sam Day , Evgeny Bachinin , Michal Simek , Jerome Forissier , Christian Marangi , Rasmus Villemoes , u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [RFC PATCH 4/4] arm64: Change mapping for data/rodata/text Date: Thu, 30 Jan 2025 09:20:29 +0200 Message-ID: <20250130072100.27297-5-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250130072100.27297-1-ilias.apalodimas@linaro.org> References: <20250130072100.27297-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Now that we have everything in place switch the page permissions for .rodata, .text and .data just after we relocate everything in top of the RAM. Signed-off-by: Ilias Apalodimas --- common/board_r.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/common/board_r.c b/common/board_r.c index 179259b00de8..38944f600fd6 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -170,6 +170,13 @@ static int initr_reloc_global_data(void) efi_save_gd(); efi_runtime_relocate(gd->relocaddr, NULL); + +#if (IS_ENABLED(CONFIG_ARM64)) + mmu_set_attrs((u64)(__start_rodata), (u64)(__end_rodata - __start_rodata), 1); + mmu_set_attrs((u64)(__start_data), (u64)(__end_data - __start_data), 3); + mmu_set_attrs((u64)(__text_start), (u64)(__text_end - __text_start), 2); +#endif + #endif return 0;