From patchwork Fri Jan 24 13:49:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hao Chang X-Patchwork-Id: 859888 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CFCE4120B; Fri, 24 Jan 2025 13:49:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737726597; cv=none; b=QYk6Ow6JE3xXwXbmyMqgemq+gvTiPF0LIWDmhad4wqnedwTtNej3sPQQLtJFoSPawjZXso8P6hk2obmEJ7bg2nVyRSLf8YJb08SJhCXFQT3thIqJPKiYGJTEU2kn968iCkqf0M6BLUvnP4FqEm91HaQUhdwICoSDZVcfPsZfuqw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737726597; c=relaxed/simple; bh=dLonNhI7NkQyBIyIgOCDzUB+e6joMkqam4L7soGDxUM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZYkQX6D0k3kLpVsYq4F7lNMg5j5vJ0ZgMFd3KCwMSowseGiHe72fwDaEbJwnQh14daTtWW2LaZrTP7Imi2uRTPzwl8UEUnH92K5nh/js/gZylPA2XxEnDF1tnb5qNI717jT5NySckfCGUi6JT/Z71wJ4QaHqShlRPMvB0zVeS4U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=lfbW/1io; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="lfbW/1io" X-UUID: 1447c504da5a11ef99858b75a2457dd9-20250124 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=mxd6y8xWCXx2qwD35/Qus8yO+IDrLVV1lvVQaT0RaxQ=; b=lfbW/1iokKiUSNHRjiBO4bhUFKT7SpKNoPiGtaL8hU0Imtsgf3Ljnoc3fBTxMv/mYa69p7BAdPD6UuczLhhkVOuFPtN7DYYoZpeBNfO3rJKJv0VvTtw4ovSUvAL8T9MmtmsGlqartZ0HHRl7R91ITtn7AMzkOFoU8hZHf1R+DjM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.46, REQID:37d37300-96a1-4624-bf52-d9d806a23f99, IP:0, U RL:0,TC:0,Content:0,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:60aa074, CLOUDID:0bcdab7e-427a-4311-9df4-bfaeeacd8532, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:1, IP:nil,URL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0, AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 1447c504da5a11ef99858b75a2457dd9-20250124 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 442198939; Fri, 24 Jan 2025 21:49:49 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Fri, 24 Jan 2025 21:49:48 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Fri, 24 Jan 2025 21:49:47 +0800 From: Hao Chang To: Sean Wang , Linus Walleij , Matthias Brugger , AngeloGioacchino Del Regno CC: Wenbin Mei , Axe Yang , Qingliang Li , Hanks Chen , Chunhui Li , , , , , "Hao Chang" Subject: [PATCH v3 1/2] pinctrl: mediatek: update EINT base retrieval method Date: Fri, 24 Jan 2025 21:49:05 +0800 Message-ID: <20250124134918.2779-2-ot_chhao.chang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250124134918.2779-1-ot_chhao.chang@mediatek.com> References: <20250124134918.2779-1-ot_chhao.chang@mediatek.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Change the method of obtaining the EINT base from a single value to multiple values. Modify the EINT base and add nbase for counting. Change-Id: I708f2eaa4c57b5705201025c252a7122914c4a40 Signed-off-by: Hao Chang Signed-off-by: Qingliang Li --- .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 50 +++++++++++++------ 1 file changed, 35 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index 6411c10cb637..e74fc68f631d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -368,7 +368,7 @@ static const struct mtk_eint_xt mtk_eint_xt = { int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; - unsigned int i, j, count_reg_names; + int ret, i, j, count_reg_names; if (!IS_ENABLED(CONFIG_EINT_MTK)) return 0; @@ -377,7 +377,7 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) return -ENODEV; count_reg_names = of_property_count_strings(np, "reg-names"); - if (count_reg_names < 0 || count_reg_names < hw->soc->nbase_names) + if (count_reg_names < hw->soc->nbase_names) return -EINVAL; hw->eint = devm_kmalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL); @@ -385,33 +385,53 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) return -ENOMEM; hw->eint->nbase = count_reg_names - hw->soc->nbase_names; - hw->eint->base = devm_kmalloc_array(&pdev->dev, hw->eint->nbase, + hw->eint->base = devm_kmalloc_array(hw->dev, hw->eint->nbase, sizeof(*hw->eint->base), GFP_KERNEL); - if (!hw->eint->base) - return -ENOMEM; + if (!hw->eint->base) { + ret = -ENOMEM; + goto err_free_eint; + } for (i = hw->soc->nbase_names, j = 0; i < count_reg_names; i++, j++) { hw->eint->base[j] = of_iomap(np, i); - if (IS_ERR(hw->eint->base[j])) - return PTR_ERR(hw->eint->base[j]); + if (IS_ERR(hw->eint->base[j])) { + ret = PTR_ERR(hw->eint->base[j]); + goto err_free_eint; + } } - if (!of_property_read_bool(np, "interrupt-controller")) - return -ENODEV; + if (!of_property_read_bool(np, "interrupt-controller")) { + ret = -ENODEV; + goto err_free_eint; + } hw->eint->irq = irq_of_parse_and_map(np, 0); - if (!hw->eint->irq) - return -EINVAL; - - if (hw->soc->eint_pin) - hw->eint->pins = hw->soc->eint_pin; + if (!hw->eint->irq) { + ret = -EINVAL; + goto err_free_eint; + } hw->eint->dev = &pdev->dev; hw->eint->hw = hw->soc->eint_hw; hw->eint->pctl = hw; hw->eint->gpio_xlate = &mtk_eint_xt; - return mtk_eint_do_init(hw->eint); + ret = mtk_eint_do_init(hw->eint); + if (ret) + goto err_free_eint; + + return 0; + +err_free_eint: + for (j = 0; j < hw->eint->nbase; j++) { + if (hw->eint->base[j]) + iounmap(hw->eint->base[j]); + } + if (hw->eint->base) + devm_kfree(hw->dev, hw->eint->base); + devm_kfree(hw->dev, hw->eint); + hw->eint = NULL; + return ret; } EXPORT_SYMBOL_GPL(mtk_build_eint); From patchwork Fri Jan 24 13:40:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hao Chang X-Patchwork-Id: 859889 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E636612B169; 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Fri, 24 Jan 2025 21:41:05 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Fri, 24 Jan 2025 21:41:03 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Fri, 24 Jan 2025 21:41:03 +0800 From: Hao Chang To: Sean Wang , Linus Walleij , Matthias Brugger , AngeloGioacchino Del Regno CC: Wenbin Mei , Axe Yang , Qingliang Li , Hanks Chen , Chunhui Li , , , , , Hao Chang Subject: [PATCH v3 2/2] pinctrl: mediatek: adapt to multi-base design Date: Fri, 24 Jan 2025 21:40:14 +0800 Message-ID: <20250124134025.2666-3-ot_chhao.chang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250124134025.2666-1-ot_chhao.chang@mediatek.com> References: <20250124134025.2666-1-ot_chhao.chang@mediatek.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The eint num will obtain the operation address through pins. Change the traversal method of irq handle from traversing a set of registers to traversing one by one. Change-Id: I3962b78042d32501a73153201cddf52c6b62a695 Signed-off-by: Hao Chang Signed-off-by: Qingliang Li --- drivers/pinctrl/mediatek/mtk-eint.c | 38 +++++++++++++++++++---------- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c index 540245c3128d..949a20196f74 100644 --- a/drivers/pinctrl/mediatek/mtk-eint.c +++ b/drivers/pinctrl/mediatek/mtk-eint.c @@ -513,6 +513,7 @@ EXPORT_SYMBOL_GPL(mtk_eint_find_irq); int mtk_eint_do_init(struct mtk_eint *eint) { unsigned int size, i, port; + struct mtk_pinctrl *hw = (struct mtk_pinctrl *)eint->pctl; /* If clients don't assign a specific regs, let's use generic one */ if (!eint->regs) @@ -523,11 +524,11 @@ int mtk_eint_do_init(struct mtk_eint *eint) if (!eint->base_pin_num) return -ENOMEM; - if (!eint->pins) { + if (eint->nbase == 1) { size = eint->hw->ap_num * sizeof(struct mtk_eint_pin); eint->pins = devm_kmalloc(eint->dev, size, GFP_KERNEL); if (!eint->pins) - return -ENOMEM; + goto err_eint; eint->base_pin_num[0] = eint->hw->ap_num; for (i = 0; i < eint->hw->ap_num; i++) { @@ -536,34 +537,29 @@ int mtk_eint_do_init(struct mtk_eint *eint) eint->pins[i].debounce = (i < eint->hw->db_cnt) ? 1 : 0; } } else { + eint->pins = hw->soc->eint_pin; for (i = 0; i < eint->hw->ap_num; i++) eint->base_pin_num[eint->pins[i].instance]++; } eint->wake_mask = devm_kmalloc(eint->dev, eint->nbase * sizeof(u32 *), GFP_KERNEL); - if (!eint->wake_mask) - return -ENOMEM; - eint->cur_mask = devm_kmalloc(eint->dev, eint->nbase * sizeof(u32 *), GFP_KERNEL); - if (!eint->wake_mask) - return -ENOMEM; + if (!eint->wake_mask || !eint->wake_mask) + goto err_eint; for (i = 0; i < eint->nbase; i++) { port = (eint->base_pin_num[i] + 31) / 32; eint->wake_mask[i] = devm_kzalloc(eint->dev, port * sizeof(u32), GFP_KERNEL); - if (!eint->wake_mask[i]) - return -ENOMEM; - eint->cur_mask[i] = devm_kzalloc(eint->dev, port * sizeof(u32), GFP_KERNEL); - if (!eint->cur_mask[i]) - return -ENOMEM; + if (!eint->cur_mask[i] || !eint->wake_mask[i]) + goto err_eint; } eint->domain = irq_domain_add_linear(eint->dev->of_node, eint->hw->ap_num, &irq_domain_simple_ops, NULL); if (!eint->domain) - return -ENOMEM; + goto err_eint; if (eint->hw->db_time) { for (i = 0; i < MTK_EINT_DBNC_MAX; i++) @@ -585,6 +581,22 @@ int mtk_eint_do_init(struct mtk_eint *eint) eint); return 0; + +err_eint: + for (i = 0; i < eint->nbase; i++) { + if (eint->wake_mask[i]) + devm_kfree(eint->dev, eint->wake_mask[i]); + if (eint->cur_mask[i]) + devm_kfree(eint->dev, eint->cur_mask[i]); + } + if (eint->cur_mask) + devm_kfree(eint->dev, eint->cur_mask); + if (eint->wake_mask) + devm_kfree(eint->dev, eint->wake_mask); + if (eint->nbase == 1) + devm_kfree(eint->dev, eint->pins); + devm_kfree(eint->dev, eint->base_pin_num); + return -ENOMEM; } EXPORT_SYMBOL_GPL(mtk_eint_do_init);