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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31b718fsm17282655e9.28.2025.01.22.01.30.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Jan 2025 01:30:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [PATCH v2 01/10] hw/core/generic-loader: Do not open-code cpu_set_pc() Date: Wed, 22 Jan 2025 10:30:19 +0100 Message-ID: <20250122093028.52416-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250122093028.52416-1-philmd@linaro.org> References: <20250122093028.52416-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Directly call cpu_set_pc() instead of open-coding it. Signed-off-by: Philippe Mathieu-Daudé --- hw/core/generic-loader.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index fb354693aff..1b9ab600c9c 100644 --- a/hw/core/generic-loader.c +++ b/hw/core/generic-loader.c @@ -48,11 +48,8 @@ static void generic_loader_reset(void *opaque) GenericLoaderState *s = GENERIC_LOADER(opaque); if (s->set_pc) { - CPUClass *cc = CPU_GET_CLASS(s->cpu); cpu_reset(s->cpu); - if (cc) { - cc->set_pc(s->cpu, s->addr); - } + cpu_set_pc(s->cpu, s->addr); } if (s->data_len) { From patchwork Wed Jan 22 09:30:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 859140 Delivered-To: patch@linaro.org Received: by 2002:adf:f78a:0:b0:385:e875:8a9e with SMTP id q10csp244619wrp; Wed, 22 Jan 2025 01:32:49 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXg89ZtICWI/8Ze32/lFaOysLcdOXV0gzMKm6vTcqbZXHAtE2hmSOKvPBoQuZD/83V8+lXfKw==@linaro.org X-Google-Smtp-Source: AGHT+IGJ28JoGD5lQTbaRplhTIabzbI9nu4V9VR3ojE4823RXP4QS2NNNnpcKLU7RYphcIDYpCO6 X-Received: by 2002:a05:620a:44d4:b0:7b6:d237:abe5 with SMTP id af79cd13be357-7be631f305emr2951175285a.20.1737538369263; Wed, 22 Jan 2025 01:32:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1737538369; cv=none; d=google.com; s=arc-20240605; b=XripsB94fWvgFnF8v20/XbWOIIrAKJvC8Zx+TOACSTx9JI71hMaES5XFCPEWgw+XT/ iuKRmQ4aY5puXGCg14eCbjPWrhRkn0yyHjEcC33mwdURf9rGt5MH1K1TdhYNjUGri+7c Ffmvnv1DkgVxa21s1W9/Bvo8Dth4TnWOkVyTSSu19D1ONOaBfHfMQ2/vJfyD9Ms2bl+y 0IskX9VZqanNvoePkhi1kZyXNPV6hFWYWJOvwE1J2sgZPbJrQ5aLzzbO5orRwx2K/4Sw 1Rma2Nu9eqBZQ0JS5K9U6IUcO5xXU4UaRqsyWB12jipQJ9sFVH8/fK0FUv7/bOxkK6YR akbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Exwv2SUshKwTjHy8msyqoapLFQlZN2ZYaumIRAoksx4=; fh=Brec4ZYd5wGCfOwL/9Q1OxqxWlcx8jJnKse3UD0zpBM=; b=OTYLYu1d7qE4jeQCRVn46MwB10tWk1jf0BdhDFLBUeJMpPgbf7np2Eh39Od5iF10rp ByrhNP5JpKFckJPbzWwD/dKRwL79ZjpzfH3hE1KDvX1o8Y6b1Cka+EjxSbJn8oLsJ1z8 3rHoFw8XH4jaU9UdwADy8LO3l0M43MlcKrDFkmy3JMamCq0y9amQC5Pp0LpcXZNE84IX xUWnqSf6cZw5TuXngJwsEs1L1tLC/eoSqb2ToG8SEpFOgTFgq/JlEDYXsLsQ9wGY5xYj Bq6xQbuumUbT+XyhdS3q/x7pDloye/+WJMBHAyvHjKWMpv5LX5qrikMzfl+TgbNSUMyK lJfA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B1uWhsUU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31afb70sm17224715e9.19.2025.01.22.01.30.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Jan 2025 01:30:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [PATCH v2 02/10] gdbstub: Clarify no more than @gdb_num_core_regs can be accessed Date: Wed, 22 Jan 2025 10:30:20 +0100 Message-ID: <20250122093028.52416-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250122093028.52416-1-philmd@linaro.org> References: <20250122093028.52416-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Both CPUClass::gdb_read_register() and CPUClass::gdb_write_register() handlers are called from common gdbstub code, and won't be called with register index over CPUClass::gdb_num_core_regs: int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) { CPUClass *cc = CPU_GET_CLASS(cpu); if (reg < cc->gdb_num_core_regs) { return cc->gdb_read_register(cpu, buf, reg); } ... } static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg) { CPUClass *cc = CPU_GET_CLASS(cpu); if (reg < cc->gdb_num_core_regs) { return cc->gdb_write_register(cpu, mem_buf, reg); } ... } Clarify that in CPUClass docstring, and remove unreachable code on the microblaze and tricore implementations. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 2 ++ target/microblaze/gdbstub.c | 5 ----- target/openrisc/gdbstub.c | 5 ----- 3 files changed, 2 insertions(+), 10 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fb397cdfc53..7b6b22c431b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -124,7 +124,9 @@ struct SysemuCPUOps; * @get_pc: Callback for getting the Program Counter register. * As above, with the semantics of the target architecture. * @gdb_read_register: Callback for letting GDB read a register. + * No more than @gdb_num_core_regs registers can be read. * @gdb_write_register: Callback for letting GDB write a register. + * No more than @gdb_num_core_regs registers can be written. * @gdb_adjust_breakpoint: Callback for adjusting the address of a * breakpoint. Used by AVR to handle a gdb mis-feature with * its Harvard architecture split code and data. diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 09d74e164d0..d493681d38d 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -110,14 +110,9 @@ int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *mem_buf, int n) int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - CPUClass *cc = CPU_GET_CLASS(cs); CPUMBState *env = cpu_env(cs); uint32_t tmp; - if (n > cc->gdb_num_core_regs) { - return 0; - } - tmp = ldl_p(mem_buf); switch (n) { diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c index c2a77d5d4d5..45bba80d878 100644 --- a/target/openrisc/gdbstub.c +++ b/target/openrisc/gdbstub.c @@ -47,14 +47,9 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - CPUClass *cc = CPU_GET_CLASS(cs); CPUOpenRISCState *env = cpu_env(cs); uint32_t tmp; - if (n > cc->gdb_num_core_regs) { - return 0; - } - tmp = ldl_p(mem_buf); if (n < 32) { From patchwork Wed Jan 22 09:30:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 859142 Delivered-To: patch@linaro.org Received: by 2002:adf:f78a:0:b0:385:e875:8a9e with SMTP id q10csp244627wrp; Wed, 22 Jan 2025 01:32:50 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXhTF2yvbInjfSx/i8v+1rg5d0VAy1zFL70eT4RIIiumbKIT7zZdIRUm+RyorkqZ79GedVD+w==@linaro.org X-Google-Smtp-Source: AGHT+IEPKKf6W0QAFFKGej1U1K1wnCLs+x9Bl993Df7pix9ojV4IDDKKdWbNf/YUDl1ForJ4KQYz X-Received: by 2002:a05:620a:2981:b0:7b1:5545:7104 with SMTP id af79cd13be357-7be523b9759mr4989990685a.2.1737538370441; Wed, 22 Jan 2025 01:32:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1737538370; cv=none; d=google.com; s=arc-20240605; b=B8/KJvceKXOo60Rd7f+R9OEpWwJ03zMo3ohoPEGkuo/61k0J2G8am0sSwfmqlP0WGz YWssUiE8fUzIg/I7RjMzz9pcIwWuqM7nPMX+v0gmQkAako1c4OeTDET6NAv/misYPaib IQlxFiUtVU1y8V8DUii7SctPcx2eU5ea9xFrBs5MzrVtPnD/9hVxkFeloiNC+3IoVY2D ebbUsoHKHLuWwD79rto8DbnGCzNdQDht7fTGH82hpfqHrH0rU+3gNnecgyDlwANQzdIB +Fu8FGpIPTqonTOTesxfEoH6225QB+a/F52JeBTIrC5yCxe3WwBUpNSNhRpmDuGQcgur Fl3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=JSvw35u1c/GeD9pKIKqf6WHVcOBbPhJhoq/j5sOwl2I=; fh=Brec4ZYd5wGCfOwL/9Q1OxqxWlcx8jJnKse3UD0zpBM=; b=iVSoG2wrsBTNBdb02Imj5zn4fqL9pedDOgSG/S6OpCduvfrR5b0CEuOwqueiGfmbgH 4oYv6UkcXyUNmRDhvw31MDHjVGeNUvExuOvUQKDUk3DMKb3BITPqKWOxc66XcrZ1Gj53 wBL8dC+mhj8SB8d2KhFZPVm59m95rpVEL63OzmnCRrj/0rgRB+osDNRmtJ0r6NAamd6f q//fdDk/B2LFnlyKn7rq8rPtd4jjbWomY07wRPUG/6uyJrQfJQZejSvUyHL0OjxCLpaV R7v3OovOPtLZvJXOo7qoLZOJBnKgJyDE+QZ/CG4HxDRtLu2nklsBS91BVStb+3XZqn86 YLAg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d5Kprf1h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31a1e7fsm17313825e9.10.2025.01.22.01.30.43 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Jan 2025 01:30:43 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [PATCH v2 03/10] cpus: Cache CPUClass early in instance_init() handler Date: Wed, 22 Jan 2025 10:30:21 +0100 Message-ID: <20250122093028.52416-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250122093028.52416-1-philmd@linaro.org> References: <20250122093028.52416-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Cache CPUClass as early as possible, when the instance is initialized. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- cpu-target.c | 3 --- hw/core/cpu-common.c | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index 667688332c9..89874496a41 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -134,9 +134,6 @@ const VMStateDescription vmstate_cpu_common = { bool cpu_exec_realizefn(CPUState *cpu, Error **errp) { - /* cache the cpu class for the hotpath */ - cpu->cc = CPU_GET_CLASS(cpu); - if (!accel_cpu_common_realize(cpu, errp)) { return false; } diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index cb79566cc51..ff605059c15 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -238,6 +238,9 @@ static void cpu_common_initfn(Object *obj) { CPUState *cpu = CPU(obj); + /* cache the cpu class for the hotpath */ + cpu->cc = CPU_GET_CLASS(cpu); + gdb_init_cpu(cpu); cpu->cpu_index = UNASSIGNED_CPU_INDEX; cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX; From patchwork Wed Jan 22 09:30:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 859141 Delivered-To: patch@linaro.org Received: by 2002:adf:f78a:0:b0:385:e875:8a9e with SMTP id q10csp244621wrp; Wed, 22 Jan 2025 01:32:49 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXOFHZjMImtq+VstQwSib1TILZ2R36lhKJEWWhN3x05Sg8ffsKkITm/M80Eiy/FsdQJhbfvQA==@linaro.org X-Google-Smtp-Source: AGHT+IH2ubdPO/o36kbdFzseU5hRkflH/S0A8kCnPTd6ggkBP1tHzNuNT9RDqBAcz+qXp+Weoc9K X-Received: by 2002:a05:6214:20a6:b0:6d8:99cf:d2e3 with SMTP id 6a1803df08f44-6e1b2180eafmr285336936d6.22.1737538369409; Wed, 22 Jan 2025 01:32:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1737538369; cv=none; d=google.com; s=arc-20240605; b=gkXQ6WKVp7zxT+MY4R8JcCkSjtWYu7z5o3KBEFx0VbhILbGcZo86VTerafuqX50rjC SoUE1FlnpcaGdIvVC6Bl7I1BvuDf0BnG8vztERfQoWMuP7TZ9sNP9ONHXD4hwNO9qgtV OukVG961iaWJCfONKa+VeKUrEgURvAfMM4YOb+39wwoEUXpv6SP/FT8UyzfOTbq/PKQ3 pQnnaG+h3p2B0Mg2whEG7tLwt6xcEnja/JHcYCQTaIX9FkZdA+GN2ek9pZS2DgcIICe2 4/zfKi7SmduxLznc9dW/VI/aK2yOZcccgvgq6hRXtLJUcakJ0TpMsx9H8fLZe2xPaKJw RCQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1UV0l1u1VpXGSm89LpbkaA5vSB88+gDPSxyKKjefn6E=; fh=Brec4ZYd5wGCfOwL/9Q1OxqxWlcx8jJnKse3UD0zpBM=; b=R4wBzPK/YQxwELVZt5u+v+LdGaZiYR7FJIjr/32esd88Hrf9uuahGZAYzhn9nMs2hy h0EcQUtq+MFZO6yX5sBOw/iNi0BuAqjBepF2hXbAscJSB+Qfu8ri0vDPKQaQBC3BuEoa MpI3pKiAqkm0jqls0SbJ1iVgYyReMH2sdvdjmxNyvMA0WqlST2X0MZzsoNQq0449lFwF W72+Z265wuP0gcmvvNb9lrAKqR28Yx1G2g139TprwziI4r3pErUs5VX6TsHO1a+uuz8V 9SYVTcg+nXZPveh0pH3DFUeYKLbroDKeotu3tWr3UFPB/u7Qqqyqf/Pbtg1YIX8Jiivp cRAw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bE20KuZH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318c1a2sm17580255e9.7.2025.01.22.01.30.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Jan 2025 01:30:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [PATCH v2 04/10] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro Date: Wed, 22 Jan 2025 10:30:22 +0100 Message-ID: <20250122093028.52416-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250122093028.52416-1-philmd@linaro.org> References: <20250122093028.52416-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CpuState caches its CPUClass since commit 6fbdff87062 ("cpu: cache CPUClass in CPUState for hot code paths"), use it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 10 +++----- cpu-common.c | 10 ++++---- cpu-target.c | 6 ++--- hw/core/cpu-common.c | 13 ++++------ hw/core/cpu-system.c | 55 +++++++++++++++---------------------------- 5 files changed, 32 insertions(+), 62 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 7b6b22c431b..d9e19d192e4 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -826,10 +826,8 @@ const char *parse_cpu_option(const char *cpu_option); */ static inline bool cpu_has_work(CPUState *cpu) { - CPUClass *cc = CPU_GET_CLASS(cpu); - - g_assert(cc->has_work); - return cc->has_work(cpu); + g_assert(cpu->cc->has_work); + return cpu->cc->has_work(cpu); } /** @@ -968,9 +966,7 @@ void cpu_interrupt(CPUState *cpu, int mask); */ static inline void cpu_set_pc(CPUState *cpu, vaddr addr) { - CPUClass *cc = CPU_GET_CLASS(cpu); - - cc->set_pc(cpu, addr); + cpu->cc->set_pc(cpu, addr); } /** diff --git a/cpu-common.c b/cpu-common.c index 4248b2d727e..3a409aacb2e 100644 --- a/cpu-common.c +++ b/cpu-common.c @@ -389,11 +389,10 @@ void process_queued_cpu_work(CPUState *cpu) int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, CPUBreakpoint **breakpoint) { - CPUClass *cc = CPU_GET_CLASS(cpu); CPUBreakpoint *bp; - if (cc->gdb_adjust_breakpoint) { - pc = cc->gdb_adjust_breakpoint(cpu, pc); + if (cpu->cc->gdb_adjust_breakpoint) { + pc = cpu->cc->gdb_adjust_breakpoint(cpu, pc); } bp = g_malloc(sizeof(*bp)); @@ -419,11 +418,10 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, /* Remove a specific breakpoint. */ int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) { - CPUClass *cc = CPU_GET_CLASS(cpu); CPUBreakpoint *bp; - if (cc->gdb_adjust_breakpoint) { - pc = cc->gdb_adjust_breakpoint(cpu, pc); + if (cpu->cc->gdb_adjust_breakpoint) { + pc = cpu->cc->gdb_adjust_breakpoint(cpu, pc); } QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { diff --git a/cpu-target.c b/cpu-target.c index 89874496a41..98e9e7cc4a1 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -159,10 +159,8 @@ bool cpu_exec_realizefn(CPUState *cpu, Error **errp) void cpu_exec_unrealizefn(CPUState *cpu) { #ifndef CONFIG_USER_ONLY - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (cc->sysemu_ops->legacy_vmsd != NULL) { - vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu); + if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) { + vmstate_unregister(NULL, cpu->cc->sysemu_ops->legacy_vmsd, cpu); } if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { vmstate_unregister(NULL, &vmstate_cpu_common, cpu); diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index ff605059c15..886aa793c04 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -40,9 +40,7 @@ CPUState *cpu_by_arch_id(int64_t id) CPUState *cpu; CPU_FOREACH(cpu) { - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (cc->get_arch_id(cpu) == id) { + if (cpu->cc->get_arch_id(cpu) == id) { return cpu; } } @@ -101,11 +99,9 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg) void cpu_dump_state(CPUState *cpu, FILE *f, int flags) { - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (cc->dump_state) { + if (cpu->cc->dump_state) { cpu_synchronize_state(cpu); - cc->dump_state(cpu, f, flags); + cpu->cc->dump_state(cpu, f, flags); } } @@ -119,11 +115,10 @@ void cpu_reset(CPUState *cpu) static void cpu_common_reset_hold(Object *obj, ResetType type) { CPUState *cpu = CPU(obj); - CPUClass *cc = CPU_GET_CLASS(cpu); if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index); - log_cpu_state(cpu, cc->reset_dump_flags); + log_cpu_state(cpu, cpu->cc->reset_dump_flags); } cpu->interrupt_request = 0; diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index 6aae28a349a..37d54d04bf8 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -25,10 +25,8 @@ bool cpu_paging_enabled(const CPUState *cpu) { - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (cc->sysemu_ops->get_paging_enabled) { - return cc->sysemu_ops->get_paging_enabled(cpu); + if (cpu->cc->sysemu_ops->get_paging_enabled) { + return cpu->cc->sysemu_ops->get_paging_enabled(cpu); } return false; @@ -37,10 +35,8 @@ bool cpu_paging_enabled(const CPUState *cpu) bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, Error **errp) { - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (cc->sysemu_ops->get_memory_mapping) { - return cc->sysemu_ops->get_memory_mapping(cpu, list, errp); + if (cpu->cc->sysemu_ops->get_memory_mapping) { + return cpu->cc->sysemu_ops->get_memory_mapping(cpu, list, errp); } error_setg(errp, "Obtaining memory mappings is unsupported on this CPU."); @@ -50,14 +46,12 @@ bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs) { - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (cc->sysemu_ops->get_phys_page_attrs_debug) { - return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs); + if (cpu->cc->sysemu_ops->get_phys_page_attrs_debug) { + return cpu->cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs); } /* Fallback for CPUs which don't implement the _attrs_ hook */ *attrs = MEMTXATTRS_UNSPECIFIED; - return cc->sysemu_ops->get_phys_page_debug(cpu, addr); + return cpu->cc->sysemu_ops->get_phys_page_debug(cpu, addr); } hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) @@ -81,64 +75,53 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, void *opaque) { - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (!cc->sysemu_ops->write_elf32_qemunote) { + if (!cpu->cc->sysemu_ops->write_elf32_qemunote) { return 0; } - return (*cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque); + return (*cpu->cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque); } int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque) { - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (!cc->sysemu_ops->write_elf32_note) { + if (!cpu->cc->sysemu_ops->write_elf32_note) { return -1; } - return (*cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque); + return (*cpu->cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque); } int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, void *opaque) { - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (!cc->sysemu_ops->write_elf64_qemunote) { + if (!cpu->cc->sysemu_ops->write_elf64_qemunote) { return 0; } - return (*cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque); + return (*cpu->cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque); } int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque) { - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (!cc->sysemu_ops->write_elf64_note) { + if (!cpu->cc->sysemu_ops->write_elf64_note) { return -1; } - return (*cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque); + return (*cpu->cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque); } bool cpu_virtio_is_big_endian(CPUState *cpu) { - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (cc->sysemu_ops->virtio_is_big_endian) { - return cc->sysemu_ops->virtio_is_big_endian(cpu); + if (cpu->cc->sysemu_ops->virtio_is_big_endian) { + return cpu->cc->sysemu_ops->virtio_is_big_endian(cpu); } return target_words_bigendian(); } GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) { - CPUClass *cc = CPU_GET_CLASS(cpu); GuestPanicInformation *res = NULL; - if (cc->sysemu_ops->get_crash_info) { - res = cc->sysemu_ops->get_crash_info(cpu); + if (cpu->cc->sysemu_ops->get_crash_info) { + res = cpu->cc->sysemu_ops->get_crash_info(cpu); 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38bf322acdcsm16022223f8f.55.2025.01.22.01.30.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Jan 2025 01:30:53 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [PATCH v2 05/10] accel: Prefer cached CpuClass over CPU_GET_CLASS() macro Date: Wed, 22 Jan 2025 10:30:23 +0100 Message-ID: <20250122093028.52416-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250122093028.52416-1-philmd@linaro.org> References: <20250122093028.52416-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CpuState caches its CPUClass since commit 6fbdff87062 ("cpu: cache CPUClass in CPUState for hot code paths"), use it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/accel-target.c | 12 +++++------- accel/tcg/tcg-accel-ops.c | 3 +-- accel/tcg/translate-all.c | 2 +- accel/tcg/watchpoint.c | 9 ++++----- 4 files changed, 11 insertions(+), 15 deletions(-) diff --git a/accel/accel-target.c b/accel/accel-target.c index 08626c00c2d..8a16c0c3ae0 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -112,22 +112,20 @@ void accel_init_interfaces(AccelClass *ac) void accel_cpu_instance_init(CPUState *cpu) { - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (cc->accel_cpu && cc->accel_cpu->cpu_instance_init) { - cc->accel_cpu->cpu_instance_init(cpu); + if (cpu->cc->accel_cpu && cpu->cc->accel_cpu->cpu_instance_init) { + cpu->cc->accel_cpu->cpu_instance_init(cpu); } } bool accel_cpu_common_realize(CPUState *cpu, Error **errp) { - CPUClass *cc = CPU_GET_CLASS(cpu); AccelState *accel = current_accel(); AccelClass *acc = ACCEL_GET_CLASS(accel); /* target specific realization */ - if (cc->accel_cpu && cc->accel_cpu->cpu_target_realize - && !cc->accel_cpu->cpu_target_realize(cpu, errp)) { + if (cpu->cc->accel_cpu + && cpu->cc->accel_cpu->cpu_target_realize + && !cpu->cc->accel_cpu->cpu_target_realize(cpu, errp)) { return false; } diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 6e3f1fa92b2..299d6176cfb 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -120,10 +120,9 @@ static inline int xlat_gdb_type(CPUState *cpu, int gdbtype) [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS, }; - CPUClass *cc = CPU_GET_CLASS(cpu); int cputype = xlat[gdbtype]; - if (cc->gdb_stop_before_watchpoint) { + if (cpu->cc->gdb_stop_before_watchpoint) { cputype |= BP_STOP_BEFORE_ACCESS; } return cputype; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index d56ca13cddf..5a378cb0281 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -622,7 +622,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) * to account for the re-execution of the branch. */ n = 1; - cc = CPU_GET_CLASS(cpu); + cc = cpu->cc; if (cc->tcg_ops->io_recompile_replay_branch && cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) { cpu->neg.icount_decr.u16.low++; diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c index af57d182d5b..52e550dec6b 100644 --- a/accel/tcg/watchpoint.c +++ b/accel/tcg/watchpoint.c @@ -69,7 +69,6 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len) void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, MemTxAttrs attrs, int flags, uintptr_t ra) { - CPUClass *cc = CPU_GET_CLASS(cpu); CPUWatchpoint *wp; assert(tcg_enabled()); @@ -85,9 +84,9 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, return; } - if (cc->tcg_ops->adjust_watchpoint_address) { + if (cpu->cc->tcg_ops->adjust_watchpoint_address) { /* this is currently used only by ARM BE32 */ - addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len); + addr = cpu->cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len); } assert((flags & ~BP_MEM_ACCESS) == 0); @@ -119,8 +118,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, wp->hitattrs = attrs; if (wp->flags & BP_CPU - && cc->tcg_ops->debug_check_watchpoint - && !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { + && cpu->cc->tcg_ops->debug_check_watchpoint + && !cpu->cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { wp->flags &= ~BP_WATCHPOINT_HIT; continue; } From patchwork Wed Jan 22 09:30:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 859146 Delivered-To: patch@linaro.org Received: by 2002:adf:f78a:0:b0:385:e875:8a9e with SMTP id q10csp244742wrp; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318c004sm17475455e9.4.2025.01.22.01.30.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Jan 2025 01:30:57 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [PATCH v2 06/10] user: Prefer cached CpuClass over CPU_GET_CLASS() macro Date: Wed, 22 Jan 2025 10:30:24 +0100 Message-ID: <20250122093028.52416-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250122093028.52416-1-philmd@linaro.org> References: <20250122093028.52416-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CpuState caches its CPUClass since commit 6fbdff87062 ("cpu: cache CPUClass in CPUState for hot code paths"), use it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- linux-user/alpha/target_proc.h | 2 +- bsd-user/signal.c | 4 ++-- linux-user/signal.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/linux-user/alpha/target_proc.h b/linux-user/alpha/target_proc.h index dac37dffc9d..da437ee0e56 100644 --- a/linux-user/alpha/target_proc.h +++ b/linux-user/alpha/target_proc.h @@ -15,7 +15,7 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd) const char *p, *q; int t; - p = object_class_get_name(OBJECT_CLASS(CPU_GET_CLASS(env_cpu(cpu_env)))); + p = object_class_get_name(OBJECT_CLASS(env_cpu(cpu_env)->cc)); q = strchr(p, '-'); t = q - p; assert(t < sizeof(model)); diff --git a/bsd-user/signal.c b/bsd-user/signal.c index b4e1458237a..4e32cd64f18 100644 --- a/bsd-user/signal.c +++ b/bsd-user/signal.c @@ -1021,7 +1021,7 @@ void process_pending_signals(CPUArchState *env) void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, MMUAccessType access_type, bool maperr, uintptr_t ra) { - const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; if (tcg_ops->record_sigsegv) { tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); @@ -1037,7 +1037,7 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, MMUAccessType access_type, uintptr_t ra) { - const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; if (tcg_ops->record_sigbus) { tcg_ops->record_sigbus(cpu, addr, access_type, ra); diff --git a/linux-user/signal.c b/linux-user/signal.c index 087c4d270e4..53b40e82261 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -743,7 +743,7 @@ void force_sigsegv(int oldsig) void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, MMUAccessType access_type, bool maperr, uintptr_t ra) { - const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; if (tcg_ops->record_sigsegv) { tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); @@ -759,7 +759,7 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, MMUAccessType access_type, uintptr_t ra) { - const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; if (tcg_ops->record_sigbus) { tcg_ops->record_sigbus(cpu, addr, access_type, ra); From patchwork Wed Jan 22 09:30:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 859143 Delivered-To: patch@linaro.org Received: by 2002:adf:f78a:0:b0:385:e875:8a9e with SMTP id q10csp244722wrp; Wed, 22 Jan 2025 01:33:10 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVrKtkQYiFC3N6cU0CFZZxPENuO32ojFL4nSpSXQS0n8Be1VPwSydP7dAylnbtQVZ02C36o8Q==@linaro.org X-Google-Smtp-Source: AGHT+IFEnoIB3NcGuO+SOrXkp6rYU21uOsemzo06HiM6WzMeJncmSlbJEEEMKEBwlt9r+8HrQ1hr X-Received: by 2002:ac8:4993:0:b0:46e:2d0b:e1bf with SMTP id d75a77b69052e-46e2d0be43cmr156817411cf.11.1737538389847; Wed, 22 Jan 2025 01:33:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1737538389; cv=none; d=google.com; s=arc-20240605; b=UP9vHTrdfYlApgjuVNzVPXwhci98jplYkK1qjNXY+EIaTmzonTc6IiC+mEBSNEBSfm 83eFx43DYLox8s4GTiiE+FMUxohGULs2TkzeerzsvBq8aLe6G7iJhAqXUJZE2tj9gy5n LMYuvKcIoAojv6WvRl5NlET1BoumygxPRvlKTuQmmg6QyKAW9O1eeth2FSlhYB0CZuFO qC2Eo3NTnxCneGGGVFVUUMVHbmnaUkpB5Bs5ixZO7iwGyg1c8E4H91sLaGcSb91Eoqpu iv9VrXh/rAWbtjea/K50pSsJVsdHjR8L+Td7pF58VnAQQz60aVD8e3gBLGjl3hqZRCwG NfWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6euSBLv31aJZp9lvcImTSgTbDVlnwvaPYw0ieO+1v6o=; fh=Brec4ZYd5wGCfOwL/9Q1OxqxWlcx8jJnKse3UD0zpBM=; b=dmNLzu9Z4A+F0rCgR7ZLkb3M8YBdWOPVemeL+xaN0Vi1G/9UmNscxPm7YSksJZkE+h j651n6CIIDPFBnd9cNomPB60zHFiHdNmk8If1RgJAY7gmv+QI5DyIzn3poY41KFq9i1L dJXmLoFFz/lyzxFHf9wvzKRwq47pNXcIBXbQp1Eor7fmN2nxs+8N7A1qXWyuy0qjFxXG fy8aJYDAobA8MwckxkgTI6dlBENZfzOCBPSHUS2pq4g0ypESgY6+M3yXBVExBSc9BuyB y3vtaWmebzKn3tD38dLYmgmrNlh9nGeXOoRJ+b0QR23fVSHFTgyTVJJaGsoVSH7ji+lV tPew==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hWSPv+d2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31adbccsm17547875e9.19.2025.01.22.01.31.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Jan 2025 01:31:02 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [PATCH v2 07/10] disas: Prefer cached CpuClass over CPU_GET_CLASS() macro Date: Wed, 22 Jan 2025 10:30:25 +0100 Message-ID: <20250122093028.52416-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250122093028.52416-1-philmd@linaro.org> References: <20250122093028.52416-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CpuState caches its CPUClass since commit 6fbdff87062 ("cpu: cache CPUClass in CPUState for hot code paths"), use it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- disas/disas-common.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/disas/disas-common.c b/disas/disas-common.c index de61f6d8a12..57505823cb7 100644 --- a/disas/disas-common.c +++ b/disas/disas-common.c @@ -67,9 +67,8 @@ void disas_initialize_debug_target(CPUDebug *s, CPUState *cpu) s->info.endian = BFD_ENDIAN_LITTLE; } - CPUClass *cc = CPU_GET_CLASS(cpu); - if (cc->disas_set_info) { - cc->disas_set_info(cpu, &s->info); + if (cpu->cc->disas_set_info) { + cpu->cc->disas_set_info(cpu, &s->info); } } From patchwork Wed Jan 22 09:30:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 859149 Delivered-To: patch@linaro.org Received: by 2002:adf:f78a:0:b0:385:e875:8a9e with SMTP id q10csp244854wrp; Wed, 22 Jan 2025 01:33:38 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXXqQG4m8H91+W+oiZL5F+l0cS9S83d1lSfs761QBXrRpyuQmv6ers9mMJy8XzcIGety1cDQg==@linaro.org X-Google-Smtp-Source: AGHT+IE28AJXNoLo9PoKaxWktKEYcgxXdtjE/azY/5/U5gQvn5YGbjGLkrIjc/YuklG1h2yj+Q+U X-Received: by 2002:a05:6214:590a:b0:6d3:65ad:5cf9 with SMTP id 6a1803df08f44-6e1b217d2e4mr319619686d6.15.1737538417886; Wed, 22 Jan 2025 01:33:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1737538417; cv=none; d=google.com; s=arc-20240605; b=KrOUbdKW9Igg+NncHhvEXzzcYDE5rmimLt8zU8qqYStDiKYyUbnH4N6cTeR8hv6sHP 9jzyx5xC97DWeviERVbMF/9rgpGgAseKvAbF6S/lpSm/jD5/C6p049Ld2YIYzMAjFixu 75hi6N1IOqtC7mBw/6d4WrhScZJd7syDl/nkOKMtKbcbuL/h4z4TONQmef0qy+QxYOiL 7JckTdQ/vMxuncbjil0RDVgG2pFw65RynIIHnABK61JSiZIDbw/A0Bl2bEsGcZMcGB+2 wcZLKjkTmaJA6N87YPYEttfh8LKkhOFuBjaSw3+8ypZCKGAKiJyJSrjp0GoMtb4ZACtM cAZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oNGgwti16N0RaYgdrpqIsRq0rprgvC+KnfZZxJFop+c=; fh=Brec4ZYd5wGCfOwL/9Q1OxqxWlcx8jJnKse3UD0zpBM=; b=BgEgeoAhyJYBVgZpUQh6O8zDjaxTvpsQQSnRgKw/X43zErfvYBcXnDrvvOQST/gn/H x/yov9U8jSExrqP6Lc8XVbdHK8X91cv7bKDpOKWvX0KHy8uRIOGLD8venXpWAU9edls7 tEennorA+brSr035qeK9BINpTppu2oQeG6OEXMLrJXk+olNZuvuiAHwZ32uCu5b3oHUr DR/Ffy2eNwmLJC8nZ04wXx6sUIYjQ6PdobCg5SfWg8spXdocylQp4sgN+z6cVbMUlYXB BnTtg/HsYiMpHtmUG222U9ykixwL+fMg8gzD7h0XR/fcjYwax3QXnejS7k0ogBhLMote M2og==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kuPihQ+j; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31afaf8sm17294715e9.21.2025.01.22.01.31.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Jan 2025 01:31:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [PATCH v2 08/10] gdbstub: Prefer cached CpuClass over CPU_GET_CLASS() macro Date: Wed, 22 Jan 2025 10:30:26 +0100 Message-ID: <20250122093028.52416-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250122093028.52416-1-philmd@linaro.org> References: <20250122093028.52416-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CpuState caches its CPUClass since commit 6fbdff87062 ("cpu: cache CPUClass in CPUState for hot code paths"), use it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- gdbstub/gdbstub.c | 26 +++++++++----------------- gdbstub/system.c | 7 ++----- gdbstub/user-target.c | 6 ++---- gdbstub/user.c | 7 ++----- 4 files changed, 15 insertions(+), 31 deletions(-) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index e366df12d4a..282e13e163f 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -354,7 +354,6 @@ static const char *get_feature_xml(const char *p, const char **newp, GDBProcess *process) { CPUState *cpu = gdb_get_first_cpu_in_process(process); - CPUClass *cc = CPU_GET_CLASS(cpu); GDBRegisterState *r; size_t len; @@ -377,11 +376,11 @@ static const char *get_feature_xml(const char *p, const char **newp, "" "")); - if (cc->gdb_arch_name) { + if (cpu->cc->gdb_arch_name) { g_ptr_array_add( xml, g_markup_printf_escaped("%s", - cc->gdb_arch_name(cpu))); + cpu->cc->gdb_arch_name(cpu))); } for (guint i = 0; i < cpu->gdb_regs->len; i++) { r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); @@ -520,11 +519,10 @@ GArray *gdb_get_register_list(CPUState *cpu) int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) { - CPUClass *cc = CPU_GET_CLASS(cpu); GDBRegisterState *r; - if (reg < cc->gdb_num_core_regs) { - return cc->gdb_read_register(cpu, buf, reg); + if (reg < cpu->cc->gdb_num_core_regs) { + return cpu->cc->gdb_read_register(cpu, buf, reg); } for (guint i = 0; i < cpu->gdb_regs->len; i++) { @@ -538,11 +536,10 @@ int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg) { - CPUClass *cc = CPU_GET_CLASS(cpu); GDBRegisterState *r; - if (reg < cc->gdb_num_core_regs) { - return cc->gdb_write_register(cpu, mem_buf, reg); + if (reg < cpu->cc->gdb_num_core_regs) { + return cpu->cc->gdb_write_register(cpu, mem_buf, reg); } for (guint i = 0; i < cpu->gdb_regs->len; i++) { @@ -570,7 +567,7 @@ static void gdb_register_feature(CPUState *cpu, int base_reg, void gdb_init_cpu(CPUState *cpu) { - CPUClass *cc = CPU_GET_CLASS(cpu); + CPUClass *cc = cpu->cc; const GDBFeature *feature; cpu->gdb_regs = g_array_new(false, false, sizeof(GDBRegisterState)); @@ -1646,11 +1643,8 @@ void gdb_extend_qsupported_features(char *qflags) static void handle_query_supported(GArray *params, void *user_ctx) { - CPUClass *cc; - g_string_printf(gdbserver_state.str_buf, "PacketSize=%x", MAX_PACKET_LENGTH); - cc = CPU_GET_CLASS(first_cpu); - if (cc->gdb_core_xml_file) { + if (first_cpu->cc->gdb_core_xml_file) { g_string_append(gdbserver_state.str_buf, ";qXfer:features:read+"); } @@ -1697,7 +1691,6 @@ static void handle_query_supported(GArray *params, void *user_ctx) static void handle_query_xfer_features(GArray *params, void *user_ctx) { GDBProcess *process; - CPUClass *cc; unsigned long len, total_len, addr; const char *xml; const char *p; @@ -1708,8 +1701,7 @@ static void handle_query_xfer_features(GArray *params, void *user_ctx) } process = gdb_get_cpu_process(gdbserver_state.g_cpu); - cc = CPU_GET_CLASS(gdbserver_state.g_cpu); - if (!cc->gdb_core_xml_file) { + if (!gdbserver_state.g_cpu->cc->gdb_core_xml_file) { gdb_put_packet(""); return; } diff --git a/gdbstub/system.c b/gdbstub/system.c index 8ce79fa88cf..215a2c5dcad 100644 --- a/gdbstub/system.c +++ b/gdbstub/system.c @@ -452,8 +452,6 @@ static int phy_memory_mode; int gdb_target_memory_rw_debug(CPUState *cpu, hwaddr addr, uint8_t *buf, int len, bool is_write) { - CPUClass *cc; - if (phy_memory_mode) { if (is_write) { cpu_physical_memory_write(addr, buf, len); @@ -463,9 +461,8 @@ int gdb_target_memory_rw_debug(CPUState *cpu, hwaddr addr, return 0; } - cc = CPU_GET_CLASS(cpu); - if (cc->memory_rw_debug) { - return cc->memory_rw_debug(cpu, addr, buf, len, is_write); + if (cpu->cc->memory_rw_debug) { + return cpu->cc->memory_rw_debug(cpu, addr, buf, len, is_write); } return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); diff --git a/gdbstub/user-target.c b/gdbstub/user-target.c index 22bf4008c0f..355b1901b4f 100644 --- a/gdbstub/user-target.c +++ b/gdbstub/user-target.c @@ -233,10 +233,8 @@ void gdb_handle_query_offsets(GArray *params, void *user_ctx) static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr, uint8_t *buf, int len, bool is_write) { - CPUClass *cc; - cc = CPU_GET_CLASS(cpu); - if (cc->memory_rw_debug) { - return cc->memory_rw_debug(cpu, addr, buf, len, is_write); + if (cpu->cc->memory_rw_debug) { + return cpu->cc->memory_rw_debug(cpu, addr, buf, len, is_write); } return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); } diff --git a/gdbstub/user.c b/gdbstub/user.c index c2bdfc3d491..375f7f80653 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -665,11 +665,8 @@ int gdb_continue_partial(char *newstates) int gdb_target_memory_rw_debug(CPUState *cpu, hwaddr addr, uint8_t *buf, int len, bool is_write) { - CPUClass *cc; - - cc = CPU_GET_CLASS(cpu); - if (cc->memory_rw_debug) { - return cc->memory_rw_debug(cpu, addr, buf, len, is_write); + if (cpu->cc->memory_rw_debug) { + return cpu->cc->memory_rw_debug(cpu, addr, buf, len, is_write); } return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); } From patchwork Wed Jan 22 09:30:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 859147 Delivered-To: patch@linaro.org Received: by 2002:adf:f78a:0:b0:385:e875:8a9e with SMTP id q10csp244783wrp; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38bf322a414sm15660432f8f.47.2025.01.22.01.31.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Jan 2025 01:31:11 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [PATCH v2 09/10] hw/acpi: Prefer cached CpuClass over CPU_GET_CLASS() macro Date: Wed, 22 Jan 2025 10:30:27 +0100 Message-ID: <20250122093028.52416-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250122093028.52416-1-philmd@linaro.org> References: <20250122093028.52416-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CpuState caches its CPUClass since commit 6fbdff87062 ("cpu: cache CPUClass in CPUState for hot code paths"), use it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/acpi/cpu.c | 4 ++-- hw/acpi/cpu_hotplug.c | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index f70a2c045e1..6f1ae79edbf 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -235,8 +235,8 @@ void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner, static AcpiCpuStatus *get_cpu_status(CPUHotplugState *cpu_st, DeviceState *dev) { - CPUClass *k = CPU_GET_CLASS(dev); - uint64_t cpu_arch_id = k->get_arch_id(CPU(dev)); + CPUState *cpu = CPU(dev); + uint64_t cpu_arch_id = cpu->cc->get_arch_id(cpu); int i; for (i = 0; i < cpu_st->dev_count; i++) { diff --git a/hw/acpi/cpu_hotplug.c b/hw/acpi/cpu_hotplug.c index 83b8bc5deb8..aa0e1e3efa5 100644 --- a/hw/acpi/cpu_hotplug.c +++ b/hw/acpi/cpu_hotplug.c @@ -62,10 +62,9 @@ static const MemoryRegionOps AcpiCpuHotplug_ops = { static void acpi_set_cpu_present_bit(AcpiCpuHotplug *g, CPUState *cpu, bool *swtchd_to_modern) { - CPUClass *k = CPU_GET_CLASS(cpu); int64_t cpu_id; - cpu_id = k->get_arch_id(cpu); + cpu_id = cpu->cc->get_arch_id(cpu); if ((cpu_id / 8) >= ACPI_GPE_PROC_LEN) { object_property_set_bool(g->device, "cpu-hotplug-legacy", false, &error_abort); From patchwork Wed Jan 22 09:30:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 859150 Delivered-To: patch@linaro.org Received: by 2002:adf:f78a:0:b0:385:e875:8a9e with SMTP id q10csp244886wrp; Wed, 22 Jan 2025 01:33:45 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUMvEnrU1KVQ17Wy91RWHE3jubjVKZBZjhnAQAYiSqV644F8mKVX9bJaZ9756vyKlLXaVSVPw==@linaro.org X-Google-Smtp-Source: AGHT+IEnzZG4qt2pACrDASQqIpVLvtO+R0S1vAkcyOmgtgto3RiVZAfi0LGjAyJrbj4UKHC/i02i X-Received: by 2002:a05:620a:4001:b0:7b6:d28b:42b4 with SMTP id af79cd13be357-7be6321758emr3083592085a.19.1737538425287; Wed, 22 Jan 2025 01:33:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1737538425; cv=none; d=google.com; s=arc-20240605; b=UujCqEZ3yP380FYv0V9jHBKB+QyCVUqnM8/13G3ywMp977S0HDGQXu4KepqS22lqRY EsPC27ByjKdbCKe1LZS2s2qeJmqcr3r9Z9s21oOiVuIkcwZpT3SMrFPcrcMJyoGOGkev rptQwjQlLpRX+IaAEVayupAHUbJY2ht75ilAdql7u2+ZKRZiRjaVtQAm5rmBcuzri2NP 4jwM2H7JpJjMsDdsHDnKyfY/CLzv0O4mVn9q+0/I+O2iqMPIU3sDScB9xK61hcDcq0Ja f0E5MIZzR0X0DjdtxJqC1Wb9BX/16thWjSZU/Z/prjgb65JdrD8yyjUSe7gKVSO+JOvN k7nA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zX6wKmzI06nCmXct1pzxbuNtoEp265I9BJm+57rS6fc=; fh=Brec4ZYd5wGCfOwL/9Q1OxqxWlcx8jJnKse3UD0zpBM=; b=JPUXOgv+Q/JyhU15hHsboEjP3MRZyi5OOp2LSBv86Ez9YXH00qNBO0tdVXxYA9EfRx 2/76mz0p9Cr/hsVJ70l27kBawAMNWbh3kJ+/z+ApX8Nay4nfY/ftL3rG+iWUaZvO+xL5 x6G68O5ldMO4dMpP1nMOAWQWt5Gd/9+XVPFmeVBeRI7Gf5geIy9gco/O4+O/IuHQGxrZ 2i4u6y7hr/5BTjJ8JATBfszbuKDsEcgOLbnPOcA1XnBSKHIASqedH0HDHH2fI7gX1K+k VJSldx8oe+eQmwWuu6ukyc1JVeXcxF6oCs7cgp+fiL2bURnlPGgNCn7VdBWnKA1v0kjN 8hqw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E0XnPb6K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318aae1sm17628795e9.1.2025.01.22.01.31.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Jan 2025 01:31:16 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [PATCH v2 10/10] target/arm: Prefer cached CpuClass over CPU_GET_CLASS() macro Date: Wed, 22 Jan 2025 10:30:28 +0100 Message-ID: <20250122093028.52416-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250122093028.52416-1-philmd@linaro.org> References: <20250122093028.52416-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CpuState caches its CPUClass since commit 6fbdff87062 ("cpu: cache CPUClass in CPUState for hot code paths"), use it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpu.c | 3 +-- target/arm/tcg/cpu-v7m.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index dc0231233a6..048b825a006 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -846,7 +846,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - CPUClass *cc = CPU_GET_CLASS(cs); CPUARMState *env = cpu_env(cs); uint32_t cur_el = arm_current_el(env); bool secure = arm_is_secure(env); @@ -946,7 +945,7 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) found: cs->exception_index = excp_idx; env->exception.target_el = target_el; - cc->tcg_ops->do_interrupt(cs); + cs->cc->tcg_ops->do_interrupt(cs); return true; } diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 03acdf83e00..d2d0b94b630 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -19,7 +19,6 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - CPUClass *cc = CPU_GET_CLASS(cs); ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; bool ret = false; @@ -35,7 +34,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) if (interrupt_request & CPU_INTERRUPT_HARD && (armv7m_nvic_can_take_pending_exception(env->nvic))) { cs->exception_index = EXCP_IRQ; - cc->tcg_ops->do_interrupt(cs); + cs->cc->tcg_ops->do_interrupt(cs); ret = true; } return ret;