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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38bf32222d1sm14183151f8f.38.2025.01.21.10.24.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 21 Jan 2025 10:24:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , Yoshinori Sato , Magnus Damm , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH] hw/sh4/r2d: Convert legacy qemu_allocate_irqs() to qemu_init_irqs() Date: Tue, 21 Jan 2025 19:24:45 +0100 Message-ID: <20250121182445.35309-1-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The FPGA exposes a fixed set of IRQs. Hold them in the FPGA state and initialize them in place calling qemu_init_irqs(). Move r2d_fpga_irq enums earlier so we can use NR_IRQS within the r2d_fpga_t structure. r2d_fpga_init() returns r2d_fpga_t, and we dereference irq from it in r2d_init(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- Based-on: <20250121155526.29982-2-philmd@linaro.org> "hw/irq: Introduce qemu_init_irqs() helper" --- hw/sh4/r2d.c | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 2fa439819e3..d68c94e82ef 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -63,6 +63,12 @@ #define PA_VERREG 0x32 #define PA_OUTPORT 0x36 +enum r2d_fpga_irq { + PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T, + SDCARD, PCI_INTA, PCI_INTB, EXT, TP, + NR_IRQS +}; + typedef struct { uint16_t bcr; uint16_t irlmsk; @@ -88,15 +94,10 @@ typedef struct { /* output pin */ qemu_irq irl; + IRQState irq[NR_IRQS]; MemoryRegion iomem; } r2d_fpga_t; -enum r2d_fpga_irq { - PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T, - SDCARD, PCI_INTA, PCI_INTB, EXT, TP, - NR_IRQS -}; - static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { [CF_IDE] = { 1, 1 << 9 }, [CF_CD] = { 2, 1 << 8 }, @@ -186,8 +187,8 @@ static const MemoryRegionOps r2d_fpga_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem, - hwaddr base, qemu_irq irl) +static r2d_fpga_t *r2d_fpga_init(MemoryRegion *sysmem, + hwaddr base, qemu_irq irl) { r2d_fpga_t *s; @@ -197,7 +198,10 @@ static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem, memory_region_init_io(&s->iomem, NULL, &r2d_fpga_ops, s, "r2d-fpga", 0x40); memory_region_add_subregion(sysmem, base, &s->iomem); - return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS); + + qemu_init_irqs(s->irq, NR_IRQS, r2d_fpga_irq_set, s); + + return s; } typedef struct ResetData { @@ -239,13 +243,13 @@ static void r2d_init(MachineState *machine) ResetData *reset_info; struct SH7750State *s; MemoryRegion *sdram = g_new(MemoryRegion, 1); - qemu_irq *irq; DriveInfo *dinfo; DeviceState *dev; SysBusDevice *busdev; MemoryRegion *address_space_mem = get_system_memory(); PCIBus *pci_bus; USBBus *usb_bus; + r2d_fpga_t *fpga; cpu = SUPERH_CPU(cpu_create(machine->cpu_type)); env = &cpu->env; @@ -260,7 +264,7 @@ static void r2d_init(MachineState *machine) memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram); /* Register peripherals */ s = sh7750_init(cpu, address_space_mem); - irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s)); + fpga = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s)); dev = qdev_new("sh_pci"); busdev = SYS_BUS_DEVICE(dev); @@ -268,10 +272,10 @@ static void r2d_init(MachineState *machine) pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000)); sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000)); - sysbus_connect_irq(busdev, 0, irq[PCI_INTA]); - sysbus_connect_irq(busdev, 1, irq[PCI_INTB]); - sysbus_connect_irq(busdev, 2, irq[PCI_INTC]); - sysbus_connect_irq(busdev, 3, irq[PCI_INTD]); + sysbus_connect_irq(busdev, 0, &fpga->irq[PCI_INTA]); + sysbus_connect_irq(busdev, 1, &fpga->irq[PCI_INTB]); + sysbus_connect_irq(busdev, 2, &fpga->irq[PCI_INTC]); + sysbus_connect_irq(busdev, 3, &fpga->irq[PCI_INTD]); dev = qdev_new("sysbus-sm501"); busdev = SYS_BUS_DEVICE(dev); @@ -281,13 +285,13 @@ static void r2d_init(MachineState *machine) sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, 0x10000000); sysbus_mmio_map(busdev, 1, 0x13e00000); - sysbus_connect_irq(busdev, 0, irq[SM501]); + sysbus_connect_irq(busdev, 0, &fpga->irq[SM501]); /* onboard CF (True IDE mode, Master only). */ dinfo = drive_get(IF_IDE, 0, 0); dev = qdev_new("mmio-ide"); busdev = SYS_BUS_DEVICE(dev); - sysbus_connect_irq(busdev, 0, irq[CF_IDE]); + sysbus_connect_irq(busdev, 0, &fpga->irq[CF_IDE]); qdev_prop_set_uint32(dev, "shift", 1); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, 0x14001000);