From patchwork Fri Jan 17 14:21:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 858695 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C50C413C67C; Fri, 17 Jan 2025 14:23:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123794; cv=none; b=CItMWL5j3gFRai9o4/pdYoGPDP7B/k/c/yn+qx0sQhqkoxMAW4a0hkEzjbQn+oac6h+ytBwb2X+Tr4CG3rg6/zzOC4J5OL1x8zQ4sG9yTuphplUdcYCMal82wgU/4rm7HUF5+yR59zKYtbtqcWGuy+J91VctiX0mG3xPgYm82lc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123794; c=relaxed/simple; bh=U194qO0oDxlacr0GHJ18nz17MA3yydb1arfxnhd39aY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r5yk27STIbdgJmYRcm2wrilCkwdxRVT+QeahUaB5eG9s+L3qbdV7LX7/PtSl4CHv8TtVrTZuJnSi05Asumu2t8sxc62V25q88Cq6pfqpZ/xL75Ww12XtaoVvdbwyp7tyQO0ZdaYP+mI1VBGi8qTCamoAyw2TpSQ0LEFZmt1jFo8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ilapTTo3; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ilapTTo3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737123793; x=1768659793; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=U194qO0oDxlacr0GHJ18nz17MA3yydb1arfxnhd39aY=; b=ilapTTo3NXJsZGHn89KWS3vdOpFuG76rUX6SJcNoa2loYkgAedl8kItk dwHgUEaDBFWLpELTyxs22mK6R4qzu6hylWFvftpX7fCjwcM5Zrx11lVPh dxN1krN+Kvgu8tLJbPf0uSv0fOex2Zs9xYinhmybVgNUPk6/EgBWb/MJJ YclvNU8KKYQ3MrhlLi12Q+gGGSNxebyl/wobK/uwFMuY/FQ60/IhHSuRz Tsow5VcCeGvHEwbbO2VZLPpZpVDY/GWF9QMPd9AbviOAF0BXEhaod6ktQ pD1P1moRimMj/eWvHTDPPk7oWWfTZmpru06K6YEI1aUhyG9b2GaTRVjWy w==; X-CSE-ConnectionGUID: 2NIxqlkfQt+mXo9+UdqFfQ== X-CSE-MsgGUID: P6j9O//GQ2a8PExOhW2CzQ== X-IronPort-AV: E=McAfee;i="6700,10204,11318"; a="41323650" X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="41323650" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2025 06:23:10 -0800 X-CSE-ConnectionGUID: PsupTb20Q1OWZ2Azo0smhg== X-CSE-MsgGUID: to4nBcNqTZ+ZLgBRqG3ztA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="143100379" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa001.jf.intel.com with ESMTP; 17 Jan 2025 06:23:08 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 2D24E2C8; Fri, 17 Jan 2025 16:23:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v1 01/16] pinctrl: cy8c95x0: Respect IRQ trigger settings from firmware Date: Fri, 17 Jan 2025 16:21:45 +0200 Message-ID: <20250117142304.596106-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> References: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Som of the platforms may connect the INT pin via inversion logic effectively make the triggering to be active-low. Remove explicit trigger flag to respect the settings from firmware. Without this change even idling chip produces spurious interrupts and kernel disables the line in the result: irq 33: nobody cared (try booting with the "irqpoll" option) CPU: 0 UID: 0 PID: 125 Comm: irq/33-i2c-INT3 Not tainted 6.12.0-00236-g8b874ed11dae #64 Hardware name: Intel Corp. QUARK/Galileo, BIOS 0x01000900 01/01/2014 ... handlers: [<86e86bea>] irq_default_primary_handler threaded [] cy8c95x0_irq_handler [pinctrl_cy8c95x0] Disabling IRQ #33 Fixes: e6cbbe42944d ("pinctrl: Add Cypress cy8c95x0 support") Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 0d6c2027d4c1..825bd1e528b5 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -1347,7 +1347,7 @@ static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq) ret = devm_request_threaded_irq(chip->dev, irq, NULL, cy8c95x0_irq_handler, - IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_HIGH, + IRQF_ONESHOT | IRQF_SHARED, dev_name(chip->dev), chip); if (ret) { dev_err(chip->dev, "failed to request irq %d\n", irq); From patchwork Fri Jan 17 14:21:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 858696 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB66670825; Fri, 17 Jan 2025 14:23:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123793; cv=none; b=DWsRWn27xGbChqI4NMpoCqtYh1ye9t3dpWPjPG/uat0aeCKRhaNZdH6GjAL1JnRTXZr1QSrmAL5awyojlUTxn6MJeWAhv/9ASZCnomCpJognW+Y5bg6s3nn1XY5PuBHcU64MXOIxomOB8+NFCfKeu+6BqJFTHYHeTbcq6dprWS8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123793; c=relaxed/simple; bh=QLp24WDAzoklZEblJoqFiQkUgp0gzMdJjU3KaVmbl68=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jr5R73LI54bdebrf9FJDVQJonBqh96sIsJ3Xvr/TyT426/Z2xscOPd05eKa6cUeWPdxIR+MTJMMa3ernvk7TssmFnIi88pDq5lddWX9JWJy/3S0F11B/3g0Jfs2pjEM3/xALayrT0B1PWzqH3Qv9Dm1yWiz74tIHTH4JmzIbbYU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CSI69XP4; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CSI69XP4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737123791; x=1768659791; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QLp24WDAzoklZEblJoqFiQkUgp0gzMdJjU3KaVmbl68=; b=CSI69XP4S68T9EIAiD0AobPsO26okpaiaI0+whSdGYiceZKmnXi+IR20 xnlxJkjp+hHU+ubZdpD+wxsNKMkVrW4nDePsXwOzzXaWEfLvnTMK2xiQD 9I71gMkSvEvzmntYAxOo1+qkDuvz2iwz5ajcEvzQ3Z1FX+O4t90X6OWH4 tpd1pVWziX/LyUYpBd2VFg8EyguOHHxMUhE02iboPNyu3ZbXhk9rnS4xw uLJ6RRRPICCdgAYQtTGOTsnSsRX0N0dqJ/YV/kh4wIJ9wGmYC7ljdply/ LPbB6cTYm8kdP0p6uZzD8YaHSMoHpAY88ywttesvQZpUuQbiHouZl1Hcn A==; X-CSE-ConnectionGUID: OcJV1G3xTxK2DUrW8f/IOg== X-CSE-MsgGUID: kx7l8WodTgGZsa9Y+j+nBQ== X-IronPort-AV: E=McAfee;i="6700,10204,11318"; a="37792821" X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="37792821" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2025 06:23:09 -0800 X-CSE-ConnectionGUID: GoGrKLGxQ4e54MhR9GMFeg== X-CSE-MsgGUID: Y2V5SRVCS/Goi32Ye0YfSA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="105671221" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa006.fm.intel.com with ESMTP; 17 Jan 2025 06:23:08 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 32FF9320; Fri, 17 Jan 2025 16:23:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v1 02/16] pinctrl: cy8c95x0: Rename PWMSEL to SELPWM Date: Fri, 17 Jan 2025 16:21:46 +0200 Message-ID: <20250117142304.596106-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> References: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 There are two registers in the hardware, one, "Select PWM", is per-port configuration enabling PWM function instead of GPIO. The other one is "PWM Select" is per-PWM selector to configure PWM itself. Original code uses abbreviation of the latter to describe the former. Rename it to follow the datasheet. Fixes: e6cbbe42944d ("pinctrl: Add Cypress cy8c95x0 support") Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 825bd1e528b5..d767bbc66256 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -42,7 +42,7 @@ #define CY8C95X0_PORTSEL 0x18 /* Port settings, write PORTSEL first */ #define CY8C95X0_INTMASK 0x19 -#define CY8C95X0_PWMSEL 0x1A +#define CY8C95X0_SELPWM 0x1A #define CY8C95X0_INVERT 0x1B #define CY8C95X0_DIRECTION 0x1C /* Drive mode register change state on writing '1' */ @@ -365,8 +365,8 @@ static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg) case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): case CY8C95X0_INTMASK: + case CY8C95X0_SELPWM: case CY8C95X0_INVERT: - case CY8C95X0_PWMSEL: case CY8C95X0_DIRECTION: case CY8C95X0_DRV_PU: case CY8C95X0_DRV_PD: @@ -395,7 +395,7 @@ static bool cy8c95x0_muxed_register(unsigned int reg) { switch (reg) { case CY8C95X0_INTMASK: - case CY8C95X0_PWMSEL: + case CY8C95X0_SELPWM: case CY8C95X0_INVERT: case CY8C95X0_DIRECTION: case CY8C95X0_DRV_PU: @@ -789,7 +789,7 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, reg = CY8C95X0_DIRECTION; break; case PIN_CONFIG_MODE_PWM: - reg = CY8C95X0_PWMSEL; + reg = CY8C95X0_SELPWM; break; case PIN_CONFIG_OUTPUT: reg = CY8C95X0_OUTPUT; @@ -868,7 +868,7 @@ static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip, reg = CY8C95X0_DRV_PP_FAST; break; case PIN_CONFIG_MODE_PWM: - reg = CY8C95X0_PWMSEL; + reg = CY8C95X0_SELPWM; break; case PIN_CONFIG_OUTPUT_ENABLE: return cy8c95x0_pinmux_direction(chip, off, !arg); @@ -1153,7 +1153,7 @@ static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file * bitmap_zero(mask, MAX_LINE); __set_bit(pin, mask); - if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) { + if (cy8c95x0_read_regs_mask(chip, CY8C95X0_SELPWM, pwm, mask)) { seq_puts(s, "not available"); return; } @@ -1198,7 +1198,7 @@ static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bo u8 port = cypress_get_port(chip, off); u8 bit = cypress_get_pin_mask(chip, off); - return cy8c95x0_regmap_write_bits(chip, CY8C95X0_PWMSEL, port, bit, mode ? bit : 0); + return cy8c95x0_regmap_write_bits(chip, CY8C95X0_SELPWM, port, bit, mode ? bit : 0); } static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip, From patchwork Fri Jan 17 14:21:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 858364 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45A6A38DD1; Fri, 17 Jan 2025 14:23:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123792; cv=none; b=Wu3rAUDBvexvfFT7K01U2tBy/5flaTzEQw0wXCiwHX2nE6oQ7m9b5262ZRpPadf2CZVl8I1Yxiyq74y0mYUh/KibtH2zokDYyfusZ9Zv5p7MfYq+ZhgBgMnvln1eUK5UwrzB9W3zYj2+nZsC6RETjQSHt8wonIK/y8n7HzwppDs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123792; c=relaxed/simple; bh=nvHcuhAxp3MMFaxPEPiHMerxA9dBRwrijTUgc/rzR1o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HmpTcYDX7TcqZjgrbHt9KtmBSYtyIKhYZsOyl1D0C3FruP1W8s7D9/ycsEAyZmP7eCtKhPJBV3Xy8zBCdAIs5MvqjIJFLNsstLKB5oiVNmlPedqJsG7ddEJljY77iTKUPzFf9FurRbyDyHF+vREdCdHR37Uhlo0nFit/uj7fSS0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nZbEh7Jg; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nZbEh7Jg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737123791; x=1768659791; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nvHcuhAxp3MMFaxPEPiHMerxA9dBRwrijTUgc/rzR1o=; b=nZbEh7JgC0VaE1w42tNkrRzsC2SmspqL5i3Vr7geYGe33/DKikHPRMEf ICQoiJkkTCYv/q0DrGztuBFc7a6HpLrF99LZd3KY1nW9r2RVE0wKfxCfL tP8rqhrgN8zcBjJOTrZqX+qG3sZfOGGz4WDX3AsgigDzTzLEwzK56eR1S paCu6HscXfVsIKKY2Jhn5wfyrUWt9FxAJ1Ww6i1IABsb2bwJpVmU21KRp uW1aWV1mAxQ/7ylhQdm/XV1o2yk2xDPrtmxch4eTzqbs4n4FAK/sADJfE sVgZeZT2FG1Lb1ymVsc88KNC3IT+u7//KvlqM0Ii/7rFkwKoGRLnC3Xy+ Q==; X-CSE-ConnectionGUID: +PM4dMM2R4uM7qwfitd8UQ== X-CSE-MsgGUID: LVSCfUQ0S/CbDIcShciINA== X-IronPort-AV: E=McAfee;i="6700,10204,11318"; a="41323653" X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="41323653" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2025 06:23:10 -0800 X-CSE-ConnectionGUID: uK0+KijfTDSFOBLFK5PyIQ== X-CSE-MsgGUID: PUHZWFU3Sga688pVJHKDhg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="143100378" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa001.jf.intel.com with ESMTP; 17 Jan 2025 06:23:08 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 47A66399; Fri, 17 Jan 2025 16:23:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v1 03/16] pinctrl: cy8c95x0: Enable regmap locking for debug Date: Fri, 17 Jan 2025 16:21:47 +0200 Message-ID: <20250117142304.596106-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> References: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When regmap locking is disabled, debugfs is also disabled. Enable locking for debug when CONFIG_DEBUG_PINCTRL is set. Fixes: f71aba339a66 ("pinctrl: cy8c95x0: Use single I2C lock") Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index d767bbc66256..6833ac41d419 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -466,7 +466,11 @@ static const struct regmap_config cy8c9520_i2c_regmap = { .max_register = 0, /* Updated at runtime */ .num_reg_defaults_raw = 0, /* Updated at runtime */ .use_single_read = true, /* Workaround for regcache bug */ +#if IS_ENABLED(CONFIG_DEBUG_PINCTRL) + .disable_locking = false, +#else .disable_locking = true, +#endif }; static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip, From patchwork Fri Jan 17 14:21:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 858363 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A4D386337; Fri, 17 Jan 2025 14:23:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123793; cv=none; b=uoNhQqmx0gkhHFBWaG178KXPIAfq7FVdnBtfb7lVMywsWJXXEfrHu95HwWi80WTbyTiIVgzKL+DuvUh4bDIb9rOa9dpDTNEAk/cbbizv+2VUmQlREkTg13og6ODuTuyVOsIiaFWuogWekp10E7bNYTGewYDubldkGMvRs7Yb0qs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123793; c=relaxed/simple; bh=F+XJXT+/fE/nkkU1+BJo/7c9vhFWPsBG/v2E/LfH2+Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Fb9812twqfCuJM0k8btd4KZjkxfeZL54uhn5ER15yDXRwv70ALwGr+9M4nfD9Cuytr8735EP2tebfJfFtT/hUsh5dQ43AmJGPVacaFesGAst7ZgCk4OJh3IxhVj4V6wL1JUTMdMhBCk2vqVrO4HKLHuskuPpdEsWO/ELgdEd4J0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=AnLUcZDR; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="AnLUcZDR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737123792; x=1768659792; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=F+XJXT+/fE/nkkU1+BJo/7c9vhFWPsBG/v2E/LfH2+Q=; b=AnLUcZDRVTGkasMfCs5x7rarg02GMU0jfVdQe8A/EqYt7mXZKqBIUUYS D1zI77SrkAwn89N1ge4mXYZw6+/At0Kse3o+4xYExvyeCD2hj/uPE+B2V zuiVCJMH39MMIkMjLK9HsQW/5xVXTkcviJ9KEzeeSidiXzchL4g66SCJn DAw7mZrfHJO/sjK9wpHzrZ6Eq6Lmy8axHk6SZThy4FAi2ZR4ZapGfcbQV rBWlsklykIXNV2ZogIvet0iFABwrjQKNNajks7pzXyDth3UypGmaruJvU Klo3Z69hRi91pYG1f6wWdGpzJsG2Cl4rUB4BVIAjq6XFVjcVXZ4k0KLRV A==; X-CSE-ConnectionGUID: pB+Z7vwLR86TiDv4seiHyA== X-CSE-MsgGUID: mP9uOvHhTa+juppvloGMgg== X-IronPort-AV: E=McAfee;i="6700,10204,11318"; a="41323655" X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="41323655" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2025 06:23:10 -0800 X-CSE-ConnectionGUID: lABIR2mVRTSDKcqqVflH/A== X-CSE-MsgGUID: JpGprDdmRo6/ZE1vb6Rwng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="143100380" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa001.jf.intel.com with ESMTP; 17 Jan 2025 06:23:08 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 5191B329; Fri, 17 Jan 2025 16:23:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v1 04/16] pinctrl: cy8c95x0: Fix off-by-one in the regmap range settings Date: Fri, 17 Jan 2025 16:21:48 +0200 Message-ID: <20250117142304.596106-5-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> References: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The range_max is inclusive, so we need to use the number of the last accessible register address. Fixes: 8670de9fae49 ("pinctrl: cy8c95x0: Use regmap ranges") Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 6833ac41d419..a94fade0ebc2 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -1442,15 +1442,15 @@ static int cy8c95x0_probe(struct i2c_client *client) switch (chip->tpin) { case 20: strscpy(chip->name, cy8c95x0_id[0].name); - regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE; + regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE - 1; break; case 40: strscpy(chip->name, cy8c95x0_id[1].name); - regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE; + regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE - 1; break; case 60: strscpy(chip->name, cy8c95x0_id[2].name); - regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE; + regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE - 1; break; default: return -ENODEV; From patchwork Fri Jan 17 14:21:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 858694 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D434B1487F4; Fri, 17 Jan 2025 14:23:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123795; cv=none; b=CkppRYVlhRY7czwRw3tz+aJOqboIZh35DdP9SkrVpB113OXsAFRXJjkZoNmhFmRl96YnhsSBRzJKoL4n0xJAp0dMD8jgNSTzqshzEmqD771LSqbOquMRi+9l4YgbRuRbrKo27VK55PYy7P7ybCuFavJ3+kJcHmhRbAUJ1NBNGsU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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d="scan'208";a="143100384" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa001.jf.intel.com with ESMTP; 17 Jan 2025 06:23:10 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 64F253B1; Fri, 17 Jan 2025 16:23:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v1 05/16] pinctrl: cy8c95x0: Remove incorrectly set fields in regmap configuration Date: Fri, 17 Jan 2025 16:21:49 +0200 Message-ID: <20250117142304.596106-6-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> References: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 We don't provide defaults for the regmap, we shouldn't provide the number of them either. Remove incorrectly set fields in regmap configuration. Fixes: 8670de9fae49 ("pinctrl: cy8c95x0: Use regmap ranges") Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index a94fade0ebc2..e98eba17cd13 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -464,7 +464,6 @@ static const struct regmap_config cy8c9520_i2c_regmap = { .ranges = NULL, /* Updated at runtime */ .num_ranges = 1, .max_register = 0, /* Updated at runtime */ - .num_reg_defaults_raw = 0, /* Updated at runtime */ .use_single_read = true, /* Workaround for regcache bug */ #if IS_ENABLED(CONFIG_DEBUG_PINCTRL) .disable_locking = false, @@ -1475,7 +1474,6 @@ static int cy8c95x0_probe(struct i2c_client *client) memcpy(®map_conf, &cy8c9520_i2c_regmap, sizeof(regmap_conf)); regmap_conf.ranges = ®map_range_conf; regmap_conf.max_register = regmap_range_conf.range_max; - regmap_conf.num_reg_defaults_raw = regmap_range_conf.range_max; chip->regmap = devm_regmap_init_i2c(client, ®map_conf); if (IS_ERR(chip->regmap)) From patchwork Fri Jan 17 14:21:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 858362 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF88D78F58; Fri, 17 Jan 2025 14:23:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123795; cv=none; b=rYo29VNsTPYSnsdp25Fy8S4/QvTbjcq1eZPXJCFky6BVEFG94GzOjTrDir6nRs5mJa8FOtuUrXkNkQ5I3q0lrBRuY3O8Z2qbYe+qveMLiiUpCdd0dnFiqE9Ea42wjQLi/KWCFICc2X6tbDdiqOst8PQ29aYw3HxzgRFE2RBW3ss= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123795; 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d="scan'208";a="105671223" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa006.fm.intel.com with ESMTP; 17 Jan 2025 06:23:10 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 6A66539C; Fri, 17 Jan 2025 16:23:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v1 06/16] pinctrl: cy8c95x0: Avoid accessing reserved registers Date: Fri, 17 Jan 2025 16:21:50 +0200 Message-ID: <20250117142304.596106-7-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> References: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The checks for vrtual registers in the cy8c95x0_readable_register() and cy8c95x0_writeable_register() are not aligned and broken. Fix that by explicitly avoiding reserved registers to be accessed. Fixes: 71e4001a0455 ("pinctrl: pinctrl-cy8c95x0: Fix regcache") Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index e98eba17cd13..970b6842b05b 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -328,14 +328,14 @@ static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin) static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg) { /* - * Only 12 registers are present per port (see Table 6 in the - * datasheet). + * Only 12 registers are present per port (see Table 6 in the datasheet). */ - if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) < 12) - return true; + if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) >= 12) + return false; switch (reg) { case 0x24 ... 0x27: + case 0x31 ... 0x3f: return false; default: return true; @@ -344,8 +344,11 @@ static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg) static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg) { - if (reg >= CY8C95X0_VIRTUAL) - return true; + /* + * Only 12 registers are present per port (see Table 6 in the datasheet). + */ + if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) >= 12) + return false; switch (reg) { case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): @@ -353,6 +356,7 @@ static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg) case CY8C95X0_DEVID: return false; case 0x24 ... 0x27: + case 0x31 ... 0x3f: return false; default: return true; From patchwork Fri Jan 17 14:21:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 858360 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 283E614B080; Fri, 17 Jan 2025 14:23:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123796; cv=none; b=mqWmw4YYDi1Tny+JRul4sJi1hayPZxrtUt1SeCGNFmR7UPaG3NfBn/mvMxe/Yh+IuygB01ny90DB1fD77tSu9dadYuxS5L1E8v8MHK8di/xZeSqHEXKew3JvPgmC5t/SvAJMCp7g5FDXmRBonqNYfDYobqrsHa8RykfjBWaBDpA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123796; c=relaxed/simple; bh=OOD3gfnz7T58XAYf2c+N69hHx8SAgM1DlcIedFa0t20=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oUvggxKpUrUELn/4ei4UJmCSDOtkx50VhjXsNaclLK6i1dJ0w/cBdvJjSmNf39glxih95MGfNYT0LGyP2qg8A3TuAFqRkVFgeLjLx99L9B+IGiQrH/6bHVPQmmNXoLmIhHz5gPJLRl9sEQn7cMhYqy39dM/B2E0SB7wDpydAX1E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Z4gbAYie; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Z4gbAYie" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737123794; x=1768659794; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OOD3gfnz7T58XAYf2c+N69hHx8SAgM1DlcIedFa0t20=; b=Z4gbAYiePNiZ3ipK+ubyeSnPTDvasQe1XpCT+fkK32fY5sdB6oO+JiPP plLHuF0lQ4LTMMY0j9Y2VrV7PEbaASG1v3ftiTA14XhVoDY+YnvJgLVoa MkfI6ZxnWf8zzDXZ3PTean1kFxAQW5LOWaWDB0FT8PI2FdAwjVDYcJqGD tAbkOvOFvn6u4a2ExRy3AAm4l8wzHUpbYP0GUa2UyqfQtSihPHEdYvku2 E8kNZEu8IJDQ/IGckzjwJjDqJafhRQ066Y1uN5eERZm1EJBA4ybsg2+Hp nmXCqGcFlPYlVIW+oA4Y6AiKtpSN+DZqFbPBRFFube71FLNgbJJ8sFh7E g==; X-CSE-ConnectionGUID: xIst4NFRRVaqtYM8O+OVDA== X-CSE-MsgGUID: /XEcPfutTA+UdIytvdn1SQ== X-IronPort-AV: E=McAfee;i="6700,10204,11318"; a="37792832" X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="37792832" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2025 06:23:12 -0800 X-CSE-ConnectionGUID: fbfDCHeSQhCOcSv1uwRHNg== X-CSE-MsgGUID: AVWmVrHwRFmhxk3MLQboqg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="105671224" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa006.fm.intel.com with ESMTP; 17 Jan 2025 06:23:11 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 79493400; Fri, 17 Jan 2025 16:23:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v1 07/16] pinctrl: cy8c95x0: Use better bitmap APIs where appropriate Date: Fri, 17 Jan 2025 16:21:51 +0200 Message-ID: <20250117142304.596106-8-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> References: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 There are bitmap_gather() and bitmap_scatter() that are factually reimplemented in the driver. Use better bitmap APIs where appropriate. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 33 +++++++++++------------------- 1 file changed, 12 insertions(+), 21 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 970b6842b05b..d3f4e20d219f 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -137,7 +137,7 @@ static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = { * @irq_trig_low: I/O bits affected by a low voltage level * @irq_trig_high: I/O bits affected by a high voltage level * @push_pull: I/O bits configured as push pull driver - * @shiftmask: Mask used to compensate for Gport2 width + * @map: Mask used to compensate for Gport2 width * @nport: Number of Gports in this chip * @gpio_chip: gpiolib chip * @driver_data: private driver data @@ -158,7 +158,7 @@ struct cy8c95x0_pinctrl { DECLARE_BITMAP(irq_trig_low, MAX_LINE); DECLARE_BITMAP(irq_trig_high, MAX_LINE); DECLARE_BITMAP(push_pull, MAX_LINE); - DECLARE_BITMAP(shiftmask, MAX_LINE); + DECLARE_BITMAP(map, MAX_LINE); unsigned int nport; struct gpio_chip gpio_chip; unsigned long driver_data; @@ -621,13 +621,8 @@ static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, int ret; /* Add the 4 bit gap of Gport2 */ - bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE); - bitmap_shift_left(tmask, tmask, 4, MAX_LINE); - bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3); - - bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE); - bitmap_shift_left(tval, tval, 4, MAX_LINE); - bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3); + bitmap_scatter(tmask, mask, chip->map, MAX_LINE); + bitmap_scatter(tval, val, chip->map, MAX_LINE); for (unsigned int i = 0; i < chip->nport; i++) { /* Skip over unused banks */ @@ -652,19 +647,13 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, { DECLARE_BITMAP(tmask, MAX_LINE); DECLARE_BITMAP(tval, MAX_LINE); - DECLARE_BITMAP(tmp, MAX_LINE); int read_val; u8 bits; int ret; /* Add the 4 bit gap of Gport2 */ - bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE); - bitmap_shift_left(tmask, tmask, 4, MAX_LINE); - bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3); - - bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE); - bitmap_shift_left(tval, tval, 4, MAX_LINE); - bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3); + bitmap_scatter(tmask, mask, chip->map, MAX_LINE); + bitmap_scatter(tval, val, chip->map, MAX_LINE); for (unsigned int i = 0; i < chip->nport; i++) { /* Skip over unused banks */ @@ -684,8 +673,7 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, } /* Fill the 4 bit gap of Gport2 */ - bitmap_shift_right(tmp, tval, 4, MAX_LINE); - bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE); + bitmap_gather(tval, val, chip->map, MAX_LINE); return 0; } @@ -1484,8 +1472,11 @@ static int cy8c95x0_probe(struct i2c_client *client) return PTR_ERR(chip->regmap); bitmap_zero(chip->push_pull, MAX_LINE); - bitmap_zero(chip->shiftmask, MAX_LINE); - bitmap_set(chip->shiftmask, 0, 20); + + /* Setup HW pins mapping */ + bitmap_fill(chip->map, MAX_LINE); + bitmap_clear(chip->map, 20, 4); + mutex_init(&chip->i2c_lock); if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) { From patchwork Fri Jan 17 14:21:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 858691 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2008F185B72; Fri, 17 Jan 2025 14:23:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123797; cv=none; b=l82LnPr3jpD/DsB6BkxtAUj1+3/iSyTLVr1VDm1FKqeSTATRcSBsGhLk6ZJ6rrIFtovjKgCuAqwqI8dztg8d5yzI5NUeFzYC+c3ynWWEC0y5cVIqukEyfXqtCP5AF0A0JaPS/2rYa9VbIcDJTB9+rl7v1zv9VrpII13oCgLf89M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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d="scan'208";a="105671227" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa006.fm.intel.com with ESMTP; 17 Jan 2025 06:23:11 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 898EC41A; Fri, 17 Jan 2025 16:23:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v1 08/16] pinctrl: cy8c95x0; Switch to use for_each_set_clump8() Date: Fri, 17 Jan 2025 16:21:52 +0200 Message-ID: <20250117142304.596106-9-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> References: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 for_each_set_clump8() has embedded check for unset clump to skip. Switch driver to use for_each_set_clump8(). Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index d3f4e20d219f..851b4b4fd4cb 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -616,21 +616,18 @@ static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, { DECLARE_BITMAP(tmask, MAX_LINE); DECLARE_BITMAP(tval, MAX_LINE); + unsigned long bits, offset; int write_val; - u8 bits; int ret; /* Add the 4 bit gap of Gport2 */ bitmap_scatter(tmask, mask, chip->map, MAX_LINE); bitmap_scatter(tval, val, chip->map, MAX_LINE); - for (unsigned int i = 0; i < chip->nport; i++) { - /* Skip over unused banks */ - bits = bitmap_get_value8(tmask, i * BANK_SZ); - if (!bits) - continue; + for_each_set_clump8(offset, bits, tmask, chip->tpin) { + unsigned int i = offset / 8; - write_val = bitmap_get_value8(tval, i * BANK_SZ); + write_val = bitmap_get_value8(tval, offset); ret = cy8c95x0_regmap_update_bits(chip, reg, i, bits, write_val); if (ret < 0) { @@ -647,19 +644,16 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, { DECLARE_BITMAP(tmask, MAX_LINE); DECLARE_BITMAP(tval, MAX_LINE); + unsigned long bits, offset; int read_val; - u8 bits; int ret; /* Add the 4 bit gap of Gport2 */ bitmap_scatter(tmask, mask, chip->map, MAX_LINE); bitmap_scatter(tval, val, chip->map, MAX_LINE); - for (unsigned int i = 0; i < chip->nport; i++) { - /* Skip over unused banks */ - bits = bitmap_get_value8(tmask, i * BANK_SZ); - if (!bits) - continue; + for_each_set_clump8(offset, bits, tmask, chip->tpin) { + unsigned int i = offset / 8; ret = cy8c95x0_regmap_read(chip, reg, i, &read_val); if (ret < 0) { @@ -668,8 +662,8 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, } read_val &= bits; - read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits; - bitmap_set_value8(tval, read_val, i * BANK_SZ); + read_val |= bitmap_get_value8(tval, offset) & ~bits; + bitmap_set_value8(tval, read_val, offset); } /* Fill the 4 bit gap of Gport2 */ From patchwork Fri Jan 17 14:21:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 858693 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7185E1547F0; Fri, 17 Jan 2025 14:23:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123796; cv=none; b=DbyAmkVkVtrTKxcClB24cCTm1Bw6nDsMRQeF0/fIMEvNLgeySzxMwyX1Bkv1EbhJZIRdcraVnCM3mTG8N4leQYuProwGykYLP6XY2Ey/F4puKOODvz3jLGxp9Ceh1jBjYT54DTIud62jgioh+AVMyBNE6kZwiUE0InTAT8wn94k= ARC-Message-Signature: i=1; a=rsa-sha256; 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d="scan'208";a="143100385" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa001.jf.intel.com with ESMTP; 17 Jan 2025 06:23:11 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 8F6EE3C5; Fri, 17 Jan 2025 16:23:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v1 09/16] pinctrl: cy8c95x0: Transform to cy8c95x0_regmap_read_bits() Date: Fri, 17 Jan 2025 16:21:53 +0200 Message-ID: <20250117142304.596106-10-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> References: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The returned value of cy8c95x0_regmap_read() is used always with a bitmask being applied. Move that bitmasking code into the function. At the same time transform it to cy8c95x0_regmap_read_bits() which will be in align with the write and update counterparts. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 45 +++++++++++++++++------------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 851b4b4fd4cb..61225beb0714 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -574,12 +574,13 @@ static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned i } /** - * cy8c95x0_regmap_read() - reads a register using the regmap cache + * cy8c95x0_regmap_read_bits() - reads a register using the regmap cache * @chip: The pinctrl to work on * @reg: The register to read from. Can be direct access or muxed register. * @port: The port to be used for muxed registers or quick path direct access * registers. Otherwise unused. - * @read_val: Value read from hardware or cache + * @mask: Bitmask to apply + * @val: Value read from hardware or cache * * This function handles the register reads from the direct access registers and * the muxed registers while caching all register accesses, internally handling @@ -589,10 +590,12 @@ static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned i * * Return: 0 for successful request, else a corresponding error value */ -static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg, - unsigned int port, unsigned int *read_val) +static int cy8c95x0_regmap_read_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg, + unsigned int port, unsigned int mask, unsigned int *val) { - int off, ret; + unsigned int off; + unsigned int tmp; + int ret; /* Registers behind the PORTSEL mux have their own range in regmap */ if (cy8c95x0_muxed_register(reg)) { @@ -604,11 +607,14 @@ static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg, else off = reg; } - guard(mutex)(&chip->i2c_lock); - ret = regmap_read(chip->regmap, off, read_val); + scoped_guard(mutex, &chip->i2c_lock) + ret = regmap_read(chip->regmap, off, &tmp); + if (ret) + return ret; - return ret; + *val = tmp & mask; + return 0; } static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, @@ -645,7 +651,7 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, DECLARE_BITMAP(tmask, MAX_LINE); DECLARE_BITMAP(tval, MAX_LINE); unsigned long bits, offset; - int read_val; + unsigned int read_val; int ret; /* Add the 4 bit gap of Gport2 */ @@ -655,13 +661,12 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, for_each_set_clump8(offset, bits, tmask, chip->tpin) { unsigned int i = offset / 8; - ret = cy8c95x0_regmap_read(chip, reg, i, &read_val); + ret = cy8c95x0_regmap_read_bits(chip, reg, i, bits, &read_val); if (ret < 0) { dev_err(chip->dev, "failed reading register %d, port %u: err %d\n", reg, i, ret); return ret; } - read_val &= bits; read_val |= bitmap_get_value8(tval, offset) & ~bits; bitmap_set_value8(tval, read_val, offset); } @@ -698,10 +703,10 @@ static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off) struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); u8 port = cypress_get_port(chip, off); u8 bit = cypress_get_pin_mask(chip, off); - u32 reg_val; + unsigned int reg_val; int ret; - ret = cy8c95x0_regmap_read(chip, CY8C95X0_INPUT, port, ®_val); + ret = cy8c95x0_regmap_read_bits(chip, CY8C95X0_INPUT, port, bit, ®_val); if (ret < 0) { /* * NOTE: @@ -712,7 +717,7 @@ static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off) return 0; } - return !!(reg_val & bit); + return reg_val ? 1 : 0; } static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off, @@ -730,14 +735,14 @@ static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off) struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); u8 port = cypress_get_port(chip, off); u8 bit = cypress_get_pin_mask(chip, off); - u32 reg_val; + unsigned int reg_val; int ret; - ret = cy8c95x0_regmap_read(chip, CY8C95X0_DIRECTION, port, ®_val); + ret = cy8c95x0_regmap_read_bits(chip, CY8C95X0_DIRECTION, port, bit, ®_val); if (ret < 0) return ret; - if (reg_val & bit) + if (reg_val) return GPIO_LINE_DIRECTION_IN; return GPIO_LINE_DIRECTION_OUT; @@ -750,8 +755,8 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, enum pin_config_param param = pinconf_to_config_param(*config); u8 port = cypress_get_port(chip, off); u8 bit = cypress_get_pin_mask(chip, off); + unsigned int reg_val; unsigned int reg; - u32 reg_val; u16 arg = 0; int ret; @@ -808,11 +813,11 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, * Writing 1 to one of the drive mode registers will automatically * clear conflicting set bits in the other drive mode registers. */ - ret = cy8c95x0_regmap_read(chip, reg, port, ®_val); + ret = cy8c95x0_regmap_read_bits(chip, reg, port, bit, ®_val); if (ret < 0) return ret; - if (reg_val & bit) + if (reg_val) arg = 1; if (param == PIN_CONFIG_OUTPUT_ENABLE) arg = !arg; From patchwork Fri Jan 17 14:21:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 858692 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 838D51632D9; Fri, 17 Jan 2025 14:23:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123797; cv=none; b=NzbKxND3jz8K2nZTJX7BPVQwrjV96Oc73/akrfG2wsJOVWRnD0ZNwyWLeIi3SL3JgK1cuqN8jOWx+r+5H7OHu5A/FvRgthS5N2GsDkCtpWFC1Fc37IiwxR8DWeSxsP5nlg5UUw0bLGAo6MykwHWqmEaqUIqHTqLbKH/mGnkrI1M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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d="scan'208";a="105671225" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa006.fm.intel.com with ESMTP; 17 Jan 2025 06:23:11 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 997C54CC; Fri, 17 Jan 2025 16:23:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v1 10/16] pinctrl: cy8c95x0: Remove redundant check in cy8c95x0_regmap_update_bits_base() Date: Fri, 17 Jan 2025 16:21:54 +0200 Message-ID: <20250117142304.596106-11-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> References: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The function is never called with the PORTSEL register in the argument. Drop unneeded check, but rescue a comment. While at it, drop inline and allow any compiler to choose better stragy (note, that inline in C code is only a recomendation to most of the modern compilers anyway). Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 61225beb0714..3907970a3e6e 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -476,20 +476,14 @@ static const struct regmap_config cy8c9520_i2c_regmap = { #endif }; -static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip, - unsigned int reg, - unsigned int port, - unsigned int mask, - unsigned int val, - bool *change, bool async, - bool force) +/* Caller should never modify PORTSEL directly */ +static int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip, + unsigned int reg, unsigned int port, + unsigned int mask, unsigned int val, + bool *change, bool async, bool force) { int ret, off, i; - /* Caller should never modify PORTSEL directly */ - if (reg == CY8C95X0_PORTSEL) - return -EINVAL; - /* Registers behind the PORTSEL mux have their own range in regmap */ if (cy8c95x0_muxed_register(reg)) { off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port); From patchwork Fri Jan 17 14:21:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 858359 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11650183CA9; Fri, 17 Jan 2025 14:23:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123797; cv=none; b=F5Q+ium9A3Vi8K+SdG7Y8oLuHwErprA7ZxMXHTB9bst4dmXZL8DlkLBIYcBhWUADBYZ/FeWgOJkGeHziYW0oqFKF/LlT7xZiAZjOvkG287Bds3VX3R8YrnJeVtIXyJzWuL5vGPa0XkLjfLo5nV/A2dTiDjkQmEQJLFIE98KZsJg= ARC-Message-Signature: i=1; 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d="scan'208";a="105671226" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa006.fm.intel.com with ESMTP; 17 Jan 2025 06:23:11 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id A410B4F0; Fri, 17 Jan 2025 16:23:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v1 11/16] pinctrl: cy8c95x0: Replace 'return ret' by 'return 0' in some cases Date: Fri, 17 Jan 2025 16:21:55 +0200 Message-ID: <20250117142304.596106-12-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> References: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When it's known that the returned value can't be non-zero, use 'return 0' explicitly. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 3907970a3e6e..d29898151a9e 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -516,7 +516,7 @@ static int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip, regcache_cache_only(chip->regmap, false); } - return ret; + return 0; } /** @@ -1285,7 +1285,7 @@ static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int num_configs) { struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); - int ret = 0; + int ret; int i; for (i = 0; i < num_configs; i++) { @@ -1294,7 +1294,7 @@ static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, return ret; } - return ret; + return 0; } static const struct pinconf_ops cy8c95x0_pinconf_ops = { From patchwork Fri Jan 17 14:21:56 2025 Content-Type: text/plain; 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X-CSE-ConnectionGUID: EbGZQB+wT/yTC3mCoDjsSw== X-CSE-MsgGUID: 92kMu7UoQUeNMP7rLH5FgA== X-IronPort-AV: E=McAfee;i="6700,10204,11318"; a="41323661" X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="41323661" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2025 06:23:12 -0800 X-CSE-ConnectionGUID: DreMjXnZQx+VKz1S0sTxaA== X-CSE-MsgGUID: Ed2mXTjZSoaF95fbDCmUsQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="143100386" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa001.jf.intel.com with ESMTP; 17 Jan 2025 06:23:11 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id B39F8581; Fri, 17 Jan 2025 16:23:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v1 12/16] pinctrl: cy8c95x0: Initialise boolean variable with boolean values Date: Fri, 17 Jan 2025 16:21:56 +0200 Message-ID: <20250117142304.596106-13-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> References: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The 'ret' variable in cy8c95x0_irq_handler() is defined as bool, but is intialised with integers. Avoid implicit castings and initialise boolean variable with boolean values. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index d29898151a9e..657e9fe40e38 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -1075,7 +1075,7 @@ static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid) if (!ret) return IRQ_RETVAL(0); - ret = 0; + ret = false; for_each_set_bit(level, pending, MAX_LINE) { /* Already accounted for 4bit gap in GPort2 */ nested_irq = irq_find_mapping(gc->irq.domain, level); @@ -1094,7 +1094,7 @@ static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid) else handle_nested_irq(nested_irq); - ret = 1; + ret = true; } return IRQ_RETVAL(ret); From patchwork Fri Jan 17 14:21:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 858357 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B8DC1990C1; Fri, 17 Jan 2025 14:23:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123799; cv=none; b=DQg59yvTpJ+hgL170Xakh1wEVZg+esHFL4yTBqMU84OZK4E0PGpfN4ZB8W0ry6EBaapw58kZn60yPFIytc+8vMQDCZAH6lxY6Ew0VW+ql8V2dLrx/Qk4yiQV+2Gn7Bg7HKdg7uxfsjhBcyLKNfaOOaIML5O3UvmGwlWovhCagig= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123799; c=relaxed/simple; bh=e+vy5gdsWQy17qO5/JqKII1U70Q5O6U013x6DVlLJPk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AL0pqqLYxuWZZzbwYRs2JVh9bd3K8Fa16my+k+bBirMNMG659nJwc9Cj0hvVWyGa0iYeE7o3Tt/w39OPZn8kK2aw/KcsOj/bL4alyvjL67cU2Fc+/A4nlQCLtt9TzWCmTvqGHvufUwcGtFp8pcb3+KqbANJHRYD3zl4Kw6fY4P4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DvhWPoNW; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DvhWPoNW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737123798; x=1768659798; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e+vy5gdsWQy17qO5/JqKII1U70Q5O6U013x6DVlLJPk=; b=DvhWPoNW3HH64i2QxdGjMdeBUgqf7eEXrDHTrIRIE7KYnK2FgJJCHbak IBrIlQp9IjAMHOmeF0HEiF0ri7jzpQ8SKMnlTkdTokzctSHakbmqN9RnN ynBRsYuPm+1ClzRKbvducVTQUEOIceO5TY6Ooep2k3v04XCna2LCfBajd f9FmKlmdo3SC67ULQ7diB1665GceSY3cDsDwVbFejL9mse4KnF9rwrMt3 GORTAjyKaDzm09EESG+XRiK2YF0cm5t/5pIEA/uWeCd3mqRMfOeXqa6Bt vedKpVJLoX4KJ4Xlj+1vycuCoeiL8cKccPftXv2+I/KFhww9MqkkMB6VS Q==; X-CSE-ConnectionGUID: I6H+P4QmSuCLS/lzA3C/JQ== X-CSE-MsgGUID: sWYsERFwT+O9pw3rOECigw== X-IronPort-AV: E=McAfee;i="6700,10204,11318"; a="37792848" X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="37792848" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2025 06:23:12 -0800 X-CSE-ConnectionGUID: ZHD3lPgSQ72bzYiPE2djtw== X-CSE-MsgGUID: OxkXDcCXSryGNjBfr14s1g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="105671229" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa006.fm.intel.com with ESMTP; 17 Jan 2025 06:23:11 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id BD7D256B; Fri, 17 Jan 2025 16:23:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v1 13/16] pinctrl: cy8c95x0: Get rid of cy8c95x0_pinmux_direction() forward declaration Date: Fri, 17 Jan 2025 16:21:57 +0200 Message-ID: <20250117142304.596106-14-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> References: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The function is used before being defined. Just move it up enough to get rid of forward declaration. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 54 ++++++++++++++---------------- 1 file changed, 25 insertions(+), 29 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 657e9fe40e38..fc9c6d293198 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -310,9 +310,6 @@ static const char * const cy8c95x0_groups[] = { "gp77", }; -static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, - unsigned int pin, bool input); - static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin) { /* Account for GPORT2 which only has 4 bits */ @@ -671,6 +668,31 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, return 0; } +static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, unsigned int pin, bool input) +{ + u8 port = cypress_get_port(chip, pin); + u8 bit = cypress_get_pin_mask(chip, pin); + int ret; + + ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, input ? bit : 0); + if (ret) + return ret; + + /* + * Disable driving the pin by forcing it to HighZ. Only setting + * the direction register isn't sufficient in Push-Pull mode. + */ + if (input && test_bit(pin, chip->push_pull)) { + ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, bit, bit); + if (ret) + return ret; + + __clear_bit(pin, chip->push_pull); + } + + return 0; +} + static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off) { return pinctrl_gpio_direction_input(gc, off); @@ -1228,32 +1250,6 @@ static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev, return cy8c95x0_set_mode(chip, pin, false); } -static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, - unsigned int pin, bool input) -{ - u8 port = cypress_get_port(chip, pin); - u8 bit = cypress_get_pin_mask(chip, pin); - int ret; - - ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, input ? bit : 0); - if (ret) - return ret; - - /* - * Disable driving the pin by forcing it to HighZ. Only setting - * the direction register isn't sufficient in Push-Pull mode. - */ - if (input && test_bit(pin, chip->push_pull)) { - ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, bit, bit); - if (ret) - return ret; - - __clear_bit(pin, chip->push_pull); - } - - return 0; -} - static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin, bool input) From patchwork Fri Jan 17 14:21:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 858358 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DF30194A75; Fri, 17 Jan 2025 14:23:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123799; cv=none; b=aDH7WK5Dyr7NwmQ1J5+1GPer058UKIsZRrFammvYQnPtmv8p9ditEal97qEhFE+1vSRAdYidWDhq89Wz1DcHSO4Q0k8f4Npjsv7S6L2u5hKS5tWGXg94N7eXEfNzs5XAd3JmJHW9jCZgJDsDErSVTqJWaGH8zwEA9V/KZ+IIhN8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123799; c=relaxed/simple; bh=9Wmz1zI8hXI0StY74F/i9WoTb5MnW+VzoQWbPjmU8qs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=b+AjrVKPKozoYiRg7t70fdFz6drANfHnDxD6TbEFCut0dlX4L278s98NC0y5r7FqmRAUmmZUH1j36p8yXNH9jkcT8mU4P8Y+eGOFhhRqsza2UcbXmjIx5b/qxpn4+wkaSAHX3tLNE7lGg4EoJ7fFkLVg7NcjvJWDK5JBIurkHxo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kwPzjUd0; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kwPzjUd0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737123797; x=1768659797; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9Wmz1zI8hXI0StY74F/i9WoTb5MnW+VzoQWbPjmU8qs=; b=kwPzjUd0c1kZ4qrSpOzU7WAaIfUIBno9xljfeZoUpKbUCu/71L/ZAysO vVhpth3IksdZawnslIthoiBZ1w169NQ2Ywlw4pxf1g2WeE0CBL6SZYa3B L/qEKadh6XpUyQpIFRKznp3TOFAS2hcH2yWT8PvO65aNN6luKlveN7/Vx xv0fM0MnXDTFm315eU8iBkyGT1hQswuGmzJOS7ZBVTmvRcjxHpd0+idmB Mo7pQLnjPWXGPKegObwiPwac0B2+V2dGNH0tXA1qVBupCUXKTDla4snmn q7dYozHLA57Gx7gEt1rz0T7cYKqzMZwI4BGXgTklF0evawBTdHBi+zBtB Q==; X-CSE-ConnectionGUID: KiktwdILSyKDAIYDXQT/Rg== X-CSE-MsgGUID: lwgC+vP2SHexfaVQyZ/38w== X-IronPort-AV: E=McAfee;i="6700,10204,11318"; a="37792843" X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="37792843" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2025 06:23:12 -0800 X-CSE-ConnectionGUID: HSHz9clsSuma3v3RdDm5VA== X-CSE-MsgGUID: 4HFyIRHFQYGX+0CvTJ1Egg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="105671228" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa006.fm.intel.com with ESMTP; 17 Jan 2025 06:23:11 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id CA97C69C; Fri, 17 Jan 2025 16:23:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v1 14/16] pinctrl: cy8c95x0: Drop unneeded casting Date: Fri, 17 Jan 2025 16:21:58 +0200 Message-ID: <20250117142304.596106-15-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> References: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The 'arg' variable in cy8c95x0_gpio_get_pincfg() is already type of u16. No need to cast it, so drop unneeded casting. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index fc9c6d293198..7f7bc374c2fc 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -838,7 +838,7 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, if (param == PIN_CONFIG_OUTPUT_ENABLE) arg = !arg; - *config = pinconf_to_config_packed(param, (u16)arg); + *config = pinconf_to_config_packed(param, arg); return 0; } From patchwork Fri Jan 17 14:21:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 858690 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1223C1991C9; Fri, 17 Jan 2025 14:23:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123799; cv=none; b=TtcUudNz167E6AI0vg3kOgE+LIagMaLJrjp27OJOuv98tcV4Zv7JhonaGumIvcO/XUN7lhtDYDJf6OWtRANONtIyW+2Iq+G8ijUqUij8y2c3K6hodXLoVrB0794jEbVXiwRBMJ10F+xGvWOp0S/7IawYChSqDd2XpPlUZHJDmqg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123799; c=relaxed/simple; bh=f8CwypOp6E8FOo/N4TKE2gkTwdmXgrBiIFIA5RkH6pM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XMAtGlBQQ8xDB3WgA3ed2rHp243dvx+PnSP+ye6VZYxqjBW1FrKXxrG2tHL/2mBDc4LA9M1uwhsMDV/GEMvj7SNKl8l00cbrq6q6wX0RuF3LaHpWgIqkA4PXGthweSDBX/gLZbLOZ2cmGi3Q1q3IHcQmifwy8sITPfi+m2Fpgms= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=C2P2Kup/; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="C2P2Kup/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737123798; x=1768659798; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=f8CwypOp6E8FOo/N4TKE2gkTwdmXgrBiIFIA5RkH6pM=; b=C2P2Kup/+45Qm0RUJdJG90wsj0/1p5TXo/4uN4w7ov5ZbCr2jnPZVCKX jUiM9c5VI72HQjuCAim7JWxOI9q22rO6fQy5TJOuc9ImYooEaFDdGVZCg bdtvnME57uItJd2fl/jBNchCiHPLt4kpjIFCjlhrRKmh42C7tDDb7UXiL Q5P2eqwk1aSoGb1wbKbl3K1m5Y8B1WUJVJRy23HEK15mGBG4iQ0eOFPkH sVa2pUnUNEhKY/Naay0TIG1wPZpqoc/YGFJvXzH5FBmw36Pk2JVCbIKRU voGS9mlesbotfMwnc1ibfCnpsUzqtpAR1eFwD8sNeonpTG+uAlPsR5QdW w==; X-CSE-ConnectionGUID: 4T9zqStLSFqFp/16K7yzZQ== X-CSE-MsgGUID: yohGFqpYQBCrREPbpDk93Q== X-IronPort-AV: E=McAfee;i="6700,10204,11318"; a="37792853" X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="37792853" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2025 06:23:13 -0800 X-CSE-ConnectionGUID: bV4EFPE7Rbqrxtzq9JOFnQ== X-CSE-MsgGUID: 4TmMcRndTDKD18OJfiVYxA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="105671234" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa006.fm.intel.com with ESMTP; 17 Jan 2025 06:23:12 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id D6B756F4; Fri, 17 Jan 2025 16:23:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v1 15/16] pinctrl: cy8c95x0: Separate EEPROM related register definitios Date: Fri, 17 Jan 2025 16:21:59 +0200 Message-ID: <20250117142304.596106-16-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> References: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently it's not easy to see at a glance the group of the registers that are per port. Add a blank line and a comment to make it better. Also add a missing definition for one of the EEPROM related registers. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 7f7bc374c2fc..6ee21e697e43 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -40,6 +40,7 @@ /* Port Select configures the port */ #define CY8C95X0_PORTSEL 0x18 + /* Port settings, write PORTSEL first */ #define CY8C95X0_INTMASK 0x19 #define CY8C95X0_SELPWM 0x1A @@ -53,6 +54,9 @@ #define CY8C95X0_DRV_PP_FAST 0x21 #define CY8C95X0_DRV_PP_SLOW 0x22 #define CY8C95X0_DRV_HIZ 0x23 + +/* Internal device configuration */ +#define CY8C95X0_ENABLE_WDE 0x2D #define CY8C95X0_DEVID 0x2E #define CY8C95X0_WATCHDOG 0x2F #define CY8C95X0_COMMAND 0x30 From patchwork Fri Jan 17 14:22:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 858689 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 322E919CC0C; Fri, 17 Jan 2025 14:23:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123800; cv=none; b=kWw4M+uL9GpW6Whplu4HfkkLbIIz+mE+lJ+K8jOhysdkJsSeU6KQcZUT9qrkKxrYYXfyBftrkbyMcsuVkHBzQR0cxQZAtTy18m/C6QAJoxqlwjSBppvxMYRKMxDkjWgg6Ap9ZVj/hYBveuVPxO5ALQKzpBSYmXplj5tBb88e/8s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737123800; c=relaxed/simple; bh=iimgZOs9g8vQE0CqP6Y63dqla7aGMw++DUMSU6qigeQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=h2xNXnCLS9zLwPfTjdfNMRLtxgx2SzE1YlUi+AxqRSh0Te0OKpOK3sH0LTCJtDofRJeLpUC6I5yLmeYaKlCFy6wZMvO78PhiwIz8T55oPXaElyst0nCTO6Lp/e9jEzxAUDc7p5nQQaFyYIh29Ql4rZ0Hs0qCJBLHsoN3huZC3nw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=LeWZhI37; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LeWZhI37" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737123799; x=1768659799; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iimgZOs9g8vQE0CqP6Y63dqla7aGMw++DUMSU6qigeQ=; b=LeWZhI37w1SRxUSTlU8AxN1G7UBp8wP1/DxNrCv8myS7efWzw6c8sjXa uDnv60QeObTs5rruuJMk3nsPGiE7pVNJiJo5kLIygvr0AN9TvJnxrMk+T 8uUdpPJDMMfUv4AzwaZHJ40VdaGDZ72x+/R9VYVyrPFIg0KOhfgIm371q BnR8vGNnVvX7zJSfpnMGnL9QI71rjlpXBeHcO+NZHdx2NZCXSRfHB+2iX fRgQj3W/IXOMAOlsdGtRoEgN9653jkBiFCEkwr9+vEw93iIjfk1FPoo63 47a8m1W2CsId1oqeJtpPInYiutzBtQFoxNyXD8ZzZH+xPX5DQsKOQ8dhQ g==; X-CSE-ConnectionGUID: ay836z5XRX+5GIgI205gag== X-CSE-MsgGUID: tQtdK6s6R1KP2G8sTGo6Iw== X-IronPort-AV: E=McAfee;i="6700,10204,11318"; a="37792856" X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="37792856" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2025 06:23:14 -0800 X-CSE-ConnectionGUID: XyNwdmJgRJ20wPIbCprzyg== X-CSE-MsgGUID: 62kDm0XmRw60sQ2LzYaJQg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="105671235" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa006.fm.intel.com with ESMTP; 17 Jan 2025 06:23:12 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id DE224725; Fri, 17 Jan 2025 16:23:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v1 16/16] pinctrl: cy8c95x0: Fix comment style Date: Fri, 17 Jan 2025 16:22:00 +0200 Message-ID: <20250117142304.596106-17-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> References: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 One comment style is not aligned with the rest. Fix that. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 6ee21e697e43..b0e3d675dc8d 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -501,7 +501,8 @@ static int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip, if (ret < 0) return ret; - /* Mimic what hardware does and update the cache when a WC bit is written. + /* + * Mimic what hardware does and update the cache when a WC bit is written. * Allows to mark the registers as non-volatile and reduces I/O cycles. */ if (cy8c95x0_wc_register(reg) && (mask & val)) {