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Fri, 17 Jan 2025 11:06:10 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 17 Jan 2025 03:06:06 -0800 From: Jagadeesh Kona Date: Fri, 17 Jan 2025 16:35:54 +0530 Subject: [PATCH] arm64: dts: qcom: sa8775p: Add LMH interrupts for cpufreq_hw node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250117-sa8775p-lmh-interrupts-v1-1-bae549f0bfe8@quicinc.com> X-B4-Tracking: v=1; b=H4sIAJE5imcC/x3MQQqEMAxA0atI1gZspbbjVWQWZYwacGpJdBDEu 09x+Rb/X6AkTAp9dYHQj5W3VGDqCj5LTDMhj8VgG+saYzxqDN67jOt3QU47iRx5V3RTiJ15daH 1FkqchSY+n/Hwvu8/iFF9S2gAAAA= X-Change-ID: 20250117-sa8775p-lmh-interrupts-5f8a61968372 To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , Jagadeesh Kona X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: s1rV6bG4Ar2MKrJJVxCO9ZDTSFw1Q38j X-Proofpoint-ORIG-GUID: s1rV6bG4Ar2MKrJJVxCO9ZDTSFw1Q38j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-17_04,2025-01-16_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 spamscore=0 malwarescore=0 adultscore=0 mlxlogscore=782 phishscore=0 mlxscore=0 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501170089 Add LMH interrupts for cpufreq_hw node to indicate if there is any thermal throttle. Signed-off-by: Jagadeesh Kona --- This patch was previously included in the below SA8775P DDR & L3 scaling series: https://lore.kernel.org/all/20241112-sa8775p-cpufreq-l3-ddr-scaling-v2-0-53d256b3f2a7@quicinc.com/ Based on Bjorn's review comments on the above series, included DDR & L3 scaling patch in it's dependent interconnect series and posting the LMH interrupts patch separately here. --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++++ 1 file changed, 4 insertions(+) --- base-commit: 0907e7fb35756464aa34c35d6abb02998418164b change-id: 20250117-sa8775p-lmh-interrupts-5f8a61968372 Best regards, diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 3394ae2d13003417a15e64c9e47833725ec779e6..1408b946dfd589aef49f25d805c5fa63d1e64543 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -4660,6 +4660,10 @@ cpufreq_hw: cpufreq@18591000 { <0x0 0x18593000 0x0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate";