From patchwork Thu Jan 16 23:21:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 858116 Received: from out-176.mta1.migadu.com (out-176.mta1.migadu.com [95.215.58.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBCFB241A05 for ; Thu, 16 Jan 2025 23:21:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069696; cv=none; b=In3Psaf+2+5B1UphTpfvkbDCxpFdnUyc2If7XkgQ5Zm1+Am79okoEYPSisOFQG2TGZUriMCjKkjCvR97pxOfYqbsNMfM9fT9za1BYmsdbT0Yd4+VP9NkG+dKqas8kxKxlgY/kRt0UMAF+2Qnv3TjqkzEPHTXr/aiv9HEJHFaKrc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069696; c=relaxed/simple; bh=cGARqq8IjWrrcZ6KdmSNFZSMwkTjtVepKJsEOxCEYMc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VquQ0W+9dUiwM1kfMY/gSi3k62w5uGicrv8VN3QXh+7+SF1vkYjsjpa+OAGClG62yGX0xXVdlchm25Z0qLStDxu5dcF78yY+Q+4FkdsbvzeovLDYRAbWmSPEZzlDI2VVb3CdZnmFQHvMeveGpizCh/MEApR1Wqwy20j3RAlGZ0g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=OZHlBT2E; arc=none smtp.client-ip=95.215.58.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="OZHlBT2E" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1737069692; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=f3kAvIiPvuDbscly1USvzOsklcOMjk05ZoOBm2Yut2w=; b=OZHlBT2EInsgKHaSkHw4Zp/mu/U8KYfBsgR4roeno+oDlFuiQYLIY+Noe2l/rde4Wuidmb bL9U8Dq/8IkbRrP3mXDLK1JcJyKPvpqyhSkeg0dUGrVOwPBgNw7k8EJp91Q6LVN+uVG91h of0+hZ4S9RHUXh/QZ+BL20EnQoVPhQ4= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , linux-arm-kernel@lists.infradead.org, Amit Kumar Mahapatra , linux-kernel@vger.kernel.org, Miquel Raynal , Sean Anderson Subject: [PATCH 2/7] spi: zynqmp-gqspi: Pass speed/mode directly to config_op Date: Thu, 16 Jan 2025 18:21:12 -0500 Message-Id: <20250116232118.2694169-3-sean.anderson@linux.dev> In-Reply-To: <20250116232118.2694169-1-sean.anderson@linux.dev> References: <20250116232118.2694169-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT In preparation for supporting transfer_one, which supplies the speed from the spi_transfer instead of the spi_device, convert config_op to take the speed and mode directly. Signed-off-by: Sean Anderson --- drivers/spi/spi-zynqmp-gqspi.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 95eea7d75f71..ba12adec8632 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -545,8 +545,8 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi, /** * zynqmp_qspi_config_op - Configure QSPI controller for specified * transfer - * @xqspi: Pointer to the zynqmp_qspi structure - * @qspi: Pointer to the spi_device structure + * @xqspi: Pointer to the zynqmp_qspi structure + * @req_speed_hz: Requested frequency * * Sets the operational mode of QSPI controller for the next QSPI transfer and * sets the requested clock frequency. @@ -563,13 +563,10 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi, * by the QSPI controller the driver will set the highest or lowest * frequency supported by controller. */ -static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, - struct spi_device *qspi) +static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, u32 req_speed_hz) { ulong clk_rate; - u32 config_reg, req_speed_hz, baud_rate_val = 0; - - req_speed_hz = qspi->max_speed_hz; + u32 config_reg, baud_rate_val = 0; if (xqspi->speed_hz != req_speed_hz) { xqspi->speed_hz = req_speed_hz; @@ -1094,7 +1091,7 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem, op->dummy.buswidth, op->data.buswidth); mutex_lock(&xqspi->op_lock); - zynqmp_qspi_config_op(xqspi, mem->spi); + zynqmp_qspi_config_op(xqspi, mem->spi->max_speed_hz); zynqmp_qspi_chipselect(mem->spi, false); genfifoentry |= xqspi->genfifocs; genfifoentry |= xqspi->genfifobus; From patchwork Thu Jan 16 23:21:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 858115 Received: from out-175.mta1.migadu.com (out-175.mta1.migadu.com [95.215.58.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAAA0236EAE for ; Thu, 16 Jan 2025 23:21:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069699; cv=none; b=fV8760g9w0ePks8n3gmaGPMreZd4bb3i0gs5qOEHdiewWVXJuqzSocVGw5Oqp7q4HhesxX2Q3QTXBi9GCpXTXKRYijoO0GceVu/4vR8eH48kx0YD5o/BwKraaZxmvHXYtEt1pT2Mtc93SnLwXbcBCbEHOge/k6lhAN5rjNSdW5c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069699; c=relaxed/simple; bh=cmpt93uTXNc+OJZHAOkMie/0u7D5Kgb/EnQQoR11n7Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=toLtOKHT45POZJXZBh2BSkUZs22MtJyVRBdjYK2g6UCy/HjksW49hjkpkd9BiSknQYQekKHgulssnMSPRA6SXzz/Kih7T7nY9zbQSkQ1xFIx4x8XtUrksaSKSqqLOmONPBpyCWSz/6I7bhQR7JgwSL4QqFBCtWvOQr+pmiWqwQE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=Thjwuswf; arc=none smtp.client-ip=95.215.58.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="Thjwuswf" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1737069696; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fStIbrCOb/5ColUxilUsQxP712qLdfKYYHDEiYij27w=; b=ThjwuswfDNPcj2UE4dP0vdjjWbWAYcdXs2jMVU1jT+42ZK8CguBj+r51yWDkZtt6SNPocY uq6JTjleQaOmNDEM6GilRXNXu+lpqzziHkkZ0CRwOPmgLqGihk+FvJxlzmrBqqURYVM9n5 9TXbQ2KWJ39SCpmjBnJ0f7UclKrYQso= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , linux-arm-kernel@lists.infradead.org, Amit Kumar Mahapatra , linux-kernel@vger.kernel.org, Miquel Raynal , Sean Anderson Subject: [PATCH 4/7] spi: zynqmp-gqspi: Refactor out controller initialization Date: Thu, 16 Jan 2025 18:21:14 -0500 Message-Id: <20250116232118.2694169-5-sean.anderson@linux.dev> In-Reply-To: <20250116232118.2694169-1-sean.anderson@linux.dev> References: <20250116232118.2694169-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT In preparation for having multiple SPI busses, refactor out the controller initialization into a separate function. No functional change intended. Signed-off-by: Sean Anderson --- drivers/spi/spi-zynqmp-gqspi.c | 42 +++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index a1233897dc88..d78e114e17e0 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -1253,6 +1253,29 @@ static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = { .exec_op = zynqmp_qspi_exec_op, }; +static int zynqmp_qspi_register_ctlr(struct zynqmp_qspi *xqspi, + struct spi_controller *ctlr) +{ + int ret; + + if (!ctlr) + return 0; + + ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | + SPI_TX_DUAL | SPI_TX_QUAD; + ctlr->max_speed_hz = xqspi->speed_hz; + ctlr->bits_per_word_mask = SPI_BPW_MASK(8); + ctlr->mem_ops = &zynqmp_qspi_mem_ops; + ctlr->setup = zynqmp_qspi_setup_op; + ctlr->auto_runtime_pm = true; + + ret = devm_spi_register_controller(xqspi->dev, ctlr); + if (ret) + dev_err_probe(xqspi->dev, ret, "could not register %pOF\n", + ctlr->dev.of_node); + return ret; +} + /** * zynqmp_qspi_probe - Probe method for the QSPI driver * @pdev: Pointer to the platform_device structure @@ -1329,12 +1352,8 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) goto clk_dis_all; } - ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | - SPI_TX_DUAL | SPI_TX_QUAD; - ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2; - xqspi->speed_hz = ctlr->max_speed_hz; - /* QSPI controller initializations */ + xqspi->speed_hz = clk_get_rate(xqspi->refclk) / 2; ret = zynqmp_qspi_init_hw(xqspi); if (ret) goto clk_dis_all; @@ -1368,18 +1387,9 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) ctlr->num_chipselect = num_cs; } - ctlr->bits_per_word_mask = SPI_BPW_MASK(8); - ctlr->mem_ops = &zynqmp_qspi_mem_ops; - ctlr->setup = zynqmp_qspi_setup_op; - ctlr->bits_per_word_mask = SPI_BPW_MASK(8); - ctlr->dev.of_node = np; - ctlr->auto_runtime_pm = true; - - ret = devm_spi_register_controller(&pdev->dev, ctlr); - if (ret) { - dev_err(&pdev->dev, "spi_register_controller failed\n"); + ret = zynqmp_qspi_register_ctlr(xqspi, ctlr); + if (ret) goto clk_dis_all; - } pm_runtime_mark_last_busy(&pdev->dev); pm_runtime_put_autosuspend(&pdev->dev); From patchwork Thu Jan 16 23:21:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 858114 Received: from out-185.mta1.migadu.com (out-185.mta1.migadu.com [95.215.58.185]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEB2E241A0B for ; Thu, 16 Jan 2025 23:21:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.185 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069703; cv=none; b=HlMRRZ+Y93S5xtocQf5h39Z570+2FjtnOBG12CTYsTS8/U5ZmeDgqwzHLqUOwfGi0v6gUD94yugVHRUPs3MeFv9S7eIxOeC1SISrvTciUVZceRfI/U5h3yHwQsswgYWNl2Sf/9EE9FLj1p3p+PKvz8nwk/At9I4O9rdTFtHwQko= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069703; c=relaxed/simple; bh=t+jiC9zkX1Xh/vs8ZAOS/bTNB7s03aofjGiFfqcq76Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=S+DKfBkUyR6EAxGgw24cU2pUgqreVr+uBq1FjY/Bf/Kf2OKdTygie35pe+I4lVWQherQTHvp+TUIlKOlamhEE57W/c+fABhpywLVIdXh5PrFv5qdkqUrzDgAMDsbkIAHTd9gP/POFlVa18d5+VNWD12otN+8VuttqQ6gqVoP6Bc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=FC8PcUCx; arc=none smtp.client-ip=95.215.58.185 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="FC8PcUCx" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1737069700; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iHGW05zMsRoR73u/6yei3oxj4qrZbmDsPW4oXB+eZkU=; b=FC8PcUCx4FLk+kJ5dUK5PmZ4kNCi7FHBtSOZdcTd1NI9Cv+mzt3FYqh/GEDIQAJplr2LTH +CB0MonTZo3qbrYkTjhmYQ+MJi4fEyQvvGxfpkgZDbrZGPv7+x6WldnxUDrN/3AQR2rY+B g9rKRJZXgpZvbq+Te/7nPRvzt3Y89cM= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , linux-arm-kernel@lists.infradead.org, Amit Kumar Mahapatra , linux-kernel@vger.kernel.org, Miquel Raynal , Sean Anderson Subject: [PATCH 6/7] spi: zynqmp-gqspi: Support GPIO chip selects Date: Thu, 16 Jan 2025 18:21:16 -0500 Message-Id: <20250116232118.2694169-7-sean.anderson@linux.dev> In-Reply-To: <20250116232118.2694169-1-sean.anderson@linux.dev> References: <20250116232118.2694169-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT GPIO chipselects use the traditional SPU API instead of the SPIMEM API. Implement it with transfer_one and set_cs (for non-GPIO chipselects). At the moment we only support half-duplex transfers, which is good enough to access SPI flashes. Signed-off-by: Sean Anderson --- drivers/spi/spi-zynqmp-gqspi.c | 83 ++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 9823d710c4d6..efd01e06b77a 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -528,6 +528,15 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) dev_err(xqspi->dev, "Chip select timed out\n"); } +static void zynqmp_qspi_set_cs(struct spi_device *qspi, bool is_high) +{ + struct zynqmp_qspi *xqspi = spi_controller_get_devdata(qspi->controller); + + mutex_lock(&xqspi->op_lock); + zynqmp_qspi_chipselect(qspi, is_high); + mutex_unlock(&xqspi->op_lock); +} + /** * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4. * @xqspi: xqspi is a pointer to the GQSPI instance @@ -1271,6 +1280,75 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem, return err; } +static int zynqmp_qspi_transfer_one(struct spi_controller *ctlr, + struct spi_device *spi, + struct spi_transfer *transfer) +{ + struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr); + unsigned long timeout; + u32 genfifoentry; + u32 mask = 0; + int ret; + + dev_dbg(xqspi->dev, "xfer %u/%u %u\n", transfer->tx_nbits, + transfer->rx_nbits, transfer->len); + + if (transfer->tx_nbits && transfer->rx_nbits) + return -EOPNOTSUPP; + + guard(mutex)(&xqspi->op_lock); + zynqmp_qspi_config_op(xqspi, transfer->speed_hz, spi->mode); + if (spi_get_csgpiod(spi, 0)) { + if (ctlr == xqspi->lower) { + xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER; + } else { + WARN_ON_ONCE(ctlr != xqspi->upper); + xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER; + } + xqspi->genfifocs = 0; + } + genfifoentry = xqspi->genfifocs | xqspi->genfifobus; + + reinit_completion(&xqspi->data_completion); + if (transfer->tx_nbits) { + xqspi->txbuf = transfer->tx_buf; + xqspi->rxbuf = NULL; + xqspi->bytes_to_transfer = transfer->len; + xqspi->bytes_to_receive = 0; + zynqmp_qspi_write_op(xqspi, transfer->tx_nbits, genfifoentry); + mask = GQSPI_IER_TXEMPTY_MASK | GQSPI_IER_GENFIFOEMPTY_MASK | + GQSPI_IER_TXNOT_FULL_MASK; + timeout = zynqmp_qspi_timeout(xqspi, transfer->tx_nbits, + transfer->len); + } else { + xqspi->txbuf = NULL; + xqspi->rxbuf = transfer->rx_buf; + xqspi->bytes_to_transfer = 0; + xqspi->bytes_to_receive = transfer->len; + ret = zynqmp_qspi_read_op(xqspi, transfer->rx_nbits, + genfifoentry); + if (ret) + return ret; + + if (xqspi->mode != GQSPI_MODE_DMA) + mask = GQSPI_IER_GENFIFOEMPTY_MASK | + GQSPI_IER_RXNEMPTY_MASK | GQSPI_IER_RXEMPTY_MASK; + timeout = zynqmp_qspi_timeout(xqspi, transfer->rx_nbits, + transfer->len); + } + + zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, + zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) | + GQSPI_CFG_START_GEN_FIFO_MASK); + if (mask) + zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, mask); + else + zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST, + GQSPI_QSPIDMA_DST_I_EN_DONE_MASK); + + return zynqmp_qspi_wait(xqspi, timeout); +} + static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = { SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend, zynqmp_runtime_resume, NULL) @@ -1318,6 +1396,7 @@ zynqmp_qspi_alloc_split(struct zynqmp_qspi *xqspi, const char *name) return ERR_PTR(-ENOMEM); ctlr->dev.of_node = np; + ctlr->max_native_cs = 1; if (of_property_read_u32(np, "num-cs", &num_cs)) ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS; else @@ -1337,11 +1416,15 @@ static int zynqmp_qspi_register_ctlr(struct zynqmp_qspi *xqspi, spi_controller_set_devdata(ctlr, xqspi); ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; + ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX; ctlr->max_speed_hz = xqspi->speed_hz; ctlr->bits_per_word_mask = SPI_BPW_MASK(8); ctlr->mem_ops = &zynqmp_qspi_mem_ops; ctlr->setup = zynqmp_qspi_setup_op; + ctlr->set_cs = zynqmp_qspi_set_cs; + ctlr->transfer_one = zynqmp_qspi_transfer_one; ctlr->auto_runtime_pm = true; + ctlr->use_gpio_descriptors = true; ret = devm_spi_register_controller(xqspi->dev, ctlr); if (ret) From patchwork Thu Jan 16 23:21:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 858113 Received: from out-177.mta1.migadu.com (out-177.mta1.migadu.com [95.215.58.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D5F0244FA9 for ; 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DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1737069703; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6Y9p6ibc/bj3AV8FXwHT1h+AI01HJG79MMwLbgeY3aY=; b=I5ESkJp7jccj+p7MTg/3SaqOFMdzqlC543kNhuKXyIO5ET2tSkUSKe4SclpJmgArTud0qH rVfVlL921C/RGjRtFB+PYcyrGq5sPHZbegg5CffrVDVyF1PVBsKx2d5Zk19i9Sa6UGtjgy 8xPc/CE0qvORpLcVkAYDDRHzUhMCkZQ= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , linux-arm-kernel@lists.infradead.org, Amit Kumar Mahapatra , linux-kernel@vger.kernel.org, Miquel Raynal , Sean Anderson , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH 7/7] ARM64: xilinx: zynqmp: Convert to split QSPI bus Date: Thu, 16 Jan 2025 18:21:17 -0500 Message-Id: <20250116232118.2694169-8-sean.anderson@linux.dev> In-Reply-To: <20250116232118.2694169-1-sean.anderson@linux.dev> References: <20250116232118.2694169-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT Convert the ZynqMP devicetrees to use the split QSPI bus binding. This is pretty simple, since all boards use only CS0. Signed-off-by: Sean Anderson --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 5 ++++- .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 5 ++++- .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 5 ++++- .../arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 15 +++++++++++---- 12 files changed, 55 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index bfa7ea6b9224..64b90de5b4ce 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -35,7 +35,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; @@ -129,6 +129,9 @@ mux { &qspi { /* MIO 0-5 - U143 */ status = "okay"; +}; + +&qspi_lower { spi_flash: flash@0 { /* MT25QU512A */ compatible = "jedec,spi-nor"; /* 64MB */ reg = <0>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts index 04079d1704f1..8927e0463cf4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts @@ -19,7 +19,7 @@ / { aliases { serial0 = &uart0; serial1 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; }; chosen { @@ -39,6 +39,9 @@ &dcc { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts index 3dec57cf18be..da07b58706f0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts @@ -20,7 +20,7 @@ / { aliases { serial0 = &uart0; serial1 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; }; chosen { @@ -40,6 +40,9 @@ &dcc { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index 6aff22d43361..ec570d68a4ae 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -27,7 +27,7 @@ aliases { mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; - spi0 = &qspi; + spi0 = &qspi_lower; usb0 = &usb0; }; @@ -354,6 +354,9 @@ &psgtr { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 6ec1d9813973..e1cfdc0db51e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -26,7 +26,7 @@ aliases { rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; - spi0 = &qspi; + spi0 = &qspi_lower; }; chosen { @@ -172,6 +172,9 @@ &i2c1 { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 7e26489a1539..18e323e2aad7 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -31,7 +31,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; usb0 = &usb0; }; @@ -953,6 +953,9 @@ &psgtr { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index eb2090673ec1..026053c4116a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -29,7 +29,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; usb0 = &usb0; }; @@ -439,6 +439,9 @@ &psgtr { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 4694d0a841f1..da56e532dc2b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -29,7 +29,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; usb0 = &usb0; }; @@ -451,6 +451,9 @@ &psgtr { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 7beedd730f94..8dd73b035969 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -31,7 +31,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; usb0 = &usb0; }; @@ -959,6 +959,9 @@ &psgtr { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index b67ff7ecf3c3..9ed7972c3b4e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -30,7 +30,7 @@ aliases { rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; usb0 = &usb0; }; @@ -789,6 +789,9 @@ &psgtr { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts index a38c2baeba6c..99d007b3bfae 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts @@ -20,7 +20,7 @@ / { aliases { serial0 = &uart0; serial1 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; }; chosen { @@ -44,6 +44,9 @@ &gpio { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; reg = <0x0>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 5dac0542a48d..470e0b90382f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -972,21 +972,28 @@ pcie_intc: legacy-interrupt-controller { }; }; - qspi: spi@ff0f0000 { + qspi: spi-controller@ff0f0000 { bootph-all; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = ; interrupt-parent = <&gic>; - num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; - #address-cells = <1>; - #size-cells = <0>; /* iommus = <&smmu 0x873>; */ power-domains = <&zynqmp_firmware PD_QSPI>; resets = <&zynqmp_reset ZYNQMP_RESET_QSPI>; + + qspi_lower: spi-lower { + #address-cells = <1>; + #size-cells = <0>; + }; + + qspi_upper: spi-upper { + #address-cells = <1>; + #size-cells = <0>; + }; }; psgtr: phy@fd400000 {