From patchwork Wed Jan 15 09:30:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Renjiang Han X-Patchwork-Id: 857792 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95BB224386E; Wed, 15 Jan 2025 09:32:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736933532; cv=none; b=qs1Q+tVMXBffuRfKdYS44w7eKYofS+GyFaZCzRRQFjwK1kJA0PvMv5QgRv7d4IH71ItlByVlEvdpExovf1SJAJsH+Va5HhAGs5tBRbtUW+lcdN9InrXrefxSrfN2D/HwIqRcO0VCH0pP0TCVncOkydVHhk99UavOIy48tQsPttI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736933532; c=relaxed/simple; bh=eJd9f4blcegx+BISVVF5j1/hSmcvEDQUFTZlQ0zCixg=; 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Wed, 15 Jan 2025 09:32:04 GMT Received: from hu-renjiang-sha.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 15 Jan 2025 01:32:01 -0800 From: Renjiang Han Date: Wed, 15 Jan 2025 15:00:52 +0530 Subject: [PATCH v3 1/3] clk: qcom: videocc: Use HW_CTRL_TRIGGER flag for video GDSC's Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250115-switch_gdsc_mode-v3-1-9a24d2fd724c@quicinc.com> References: <20250115-switch_gdsc_mode-v3-0-9a24d2fd724c@quicinc.com> In-Reply-To: <20250115-switch_gdsc_mode-v3-0-9a24d2fd724c@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Stanimir Varbanov , Vikash Garodia , Bryan O'Donoghue , Mauro Carvalho Chehab CC: , , , , Renjiang Han , Taniya Das , "Dmitry Baryshkov" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736933518; l=4234; i=quic_renjiang@quicinc.com; s=20241001; h=from:subject:message-id; bh=i/sSEqB62BBrB+Tlclsq4GbdmCj1n3LXGCmyoP/p3IU=; b=J0Rxx/cWSoIr7C2hb5QsWh5pvIEmQHq88HOZI6GCnc40Y+QvMUFScQE3wO+ia/TfPsqSTMU08 1ZhoBLI0GOYBkP2APtH7PHUV9QOVY0Mo3IAlNVdI4/3H5dreqb8htnZ X-Developer-Key: i=quic_renjiang@quicinc.com; a=ed25519; pk=8N59kMJUiVH++5QxJzTyHB/wh/kG5LxQ44j9zhUvZmw= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: OMFtyOscUREDB4sYC64L01WvktiyeOx8 X-Proofpoint-ORIG-GUID: OMFtyOscUREDB4sYC64L01WvktiyeOx8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-15_03,2025-01-15_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxlogscore=698 priorityscore=1501 phishscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 suspectscore=0 bulkscore=0 mlxscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501150072 From: Taniya Das The video driver will be using the newly introduced dev_pm_genpd_set_hwmode() API to switch the video GDSC to HW and SW control modes at runtime. Hence use HW_CTRL_TRIGGER flag instead of HW_CTRL for video GDSC's for Qualcomm SoC SC7180, SDM845, SM7150, SM8150 and SM8450. Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov Signed-off-by: Renjiang Han --- drivers/clk/qcom/videocc-sc7180.c | 2 +- drivers/clk/qcom/videocc-sdm845.c | 4 ++-- drivers/clk/qcom/videocc-sm7150.c | 4 ++-- drivers/clk/qcom/videocc-sm8150.c | 4 ++-- drivers/clk/qcom/videocc-sm8450.c | 4 ++-- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c index d7f84548039699ce6fdd7c0f6675c168d5eaf4c1..dd2441d6aa83bd7cff17deeb42f5d011c1e9b134 100644 --- a/drivers/clk/qcom/videocc-sc7180.c +++ b/drivers/clk/qcom/videocc-sc7180.c @@ -166,7 +166,7 @@ static struct gdsc vcodec0_gdsc = { .pd = { .name = "vcodec0_gdsc", }, - .flags = HW_CTRL, + .flags = HW_CTRL_TRIGGER, .pwrsts = PWRSTS_OFF_ON, }; diff --git a/drivers/clk/qcom/videocc-sdm845.c b/drivers/clk/qcom/videocc-sdm845.c index f77a0777947773dc8902c92098acff71b9b8f10f..6dedc80a8b3e18eca82c08a5bcd7e1fdc374d4b5 100644 --- a/drivers/clk/qcom/videocc-sdm845.c +++ b/drivers/clk/qcom/videocc-sdm845.c @@ -260,7 +260,7 @@ static struct gdsc vcodec0_gdsc = { }, .cxcs = (unsigned int []){ 0x890, 0x930 }, .cxc_count = 2, - .flags = HW_CTRL | POLL_CFG_GDSCR, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR, .pwrsts = PWRSTS_OFF_ON, }; @@ -271,7 +271,7 @@ static struct gdsc vcodec1_gdsc = { }, .cxcs = (unsigned int []){ 0x8d0, 0x950 }, .cxc_count = 2, - .flags = HW_CTRL | POLL_CFG_GDSCR, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR, .pwrsts = PWRSTS_OFF_ON, }; diff --git a/drivers/clk/qcom/videocc-sm7150.c b/drivers/clk/qcom/videocc-sm7150.c index 14ef7f5617537363673662adc3910ddba8ea6a4f..b6912560ef9b7a84e7fd1d9924f5aac6967da780 100644 --- a/drivers/clk/qcom/videocc-sm7150.c +++ b/drivers/clk/qcom/videocc-sm7150.c @@ -271,7 +271,7 @@ static struct gdsc vcodec0_gdsc = { }, .cxcs = (unsigned int []){ 0x890, 0x9ec }, .cxc_count = 2, - .flags = HW_CTRL | POLL_CFG_GDSCR, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR, .pwrsts = PWRSTS_OFF_ON, }; @@ -282,7 +282,7 @@ static struct gdsc vcodec1_gdsc = { }, .cxcs = (unsigned int []){ 0x8d0, 0xa0c }, .cxc_count = 2, - .flags = HW_CTRL | POLL_CFG_GDSCR, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR, .pwrsts = PWRSTS_OFF_ON, }; diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-sm8150.c index daab3237eec19b727d34512d3a2ba1d7bd2743d6..3024f6fc89c8b374f2ef13debc283998cb136f6b 100644 --- a/drivers/clk/qcom/videocc-sm8150.c +++ b/drivers/clk/qcom/videocc-sm8150.c @@ -179,7 +179,7 @@ static struct gdsc vcodec0_gdsc = { .pd = { .name = "vcodec0_gdsc", }, - .flags = HW_CTRL, + .flags = HW_CTRL_TRIGGER, .pwrsts = PWRSTS_OFF_ON, }; @@ -188,7 +188,7 @@ static struct gdsc vcodec1_gdsc = { .pd = { .name = "vcodec1_gdsc", }, - .flags = HW_CTRL, + .flags = HW_CTRL_TRIGGER, .pwrsts = PWRSTS_OFF_ON, }; static struct clk_regmap *video_cc_sm8150_clocks[] = { diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c index f26c7eccb62e7eb8dbd022e2f01fa496eb570b3f..4cefcbbc020f201f19c75c20229415e0bdea2963 100644 --- a/drivers/clk/qcom/videocc-sm8450.c +++ b/drivers/clk/qcom/videocc-sm8450.c @@ -347,7 +347,7 @@ static struct gdsc video_cc_mvs0_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .parent = &video_cc_mvs0c_gdsc.pd, - .flags = RETAIN_FF_ENABLE | HW_CTRL, + .flags = HW_CTRL_TRIGGER | RETAIN_FF_ENABLE, }; static struct gdsc video_cc_mvs1c_gdsc = { @@ -372,7 +372,7 @@ static struct gdsc video_cc_mvs1_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .parent = &video_cc_mvs1c_gdsc.pd, - .flags = RETAIN_FF_ENABLE | HW_CTRL, + .flags = HW_CTRL_TRIGGER | RETAIN_FF_ENABLE, }; static struct clk_regmap *video_cc_sm8450_clocks[] = { From patchwork Wed Jan 15 09:30:54 2025 Content-Type: text/plain; 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Wed, 15 Jan 2025 09:32:10 GMT Received: from hu-renjiang-sha.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 15 Jan 2025 01:32:07 -0800 From: Renjiang Han Date: Wed, 15 Jan 2025 15:00:54 +0530 Subject: [PATCH v3 3/3] venus: pm_helpers: Remove dead code and simplify power management Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250115-switch_gdsc_mode-v3-3-9a24d2fd724c@quicinc.com> References: <20250115-switch_gdsc_mode-v3-0-9a24d2fd724c@quicinc.com> In-Reply-To: <20250115-switch_gdsc_mode-v3-0-9a24d2fd724c@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Stanimir Varbanov , Vikash Garodia , Bryan O'Donoghue , Mauro Carvalho Chehab CC: , , , , Renjiang Han X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736933518; l=5198; i=quic_renjiang@quicinc.com; s=20241001; h=from:subject:message-id; bh=jtOT3BkYpNrmH1/Wt1QRdW0HL0hJh6Rk9yEHeCTvgHI=; b=9kdGYnWZE8MzKOGWBKZJW0ZYnn82FmN41lclkK/1T3JELaxcAlRspEN+NosRI+8Ot8HLzLG7Q 5eITMhts4R4BsHk8Wh92kZTw96a9p4QjAp2yEj6AJlxHs/GOTuZdptZ X-Developer-Key: i=quic_renjiang@quicinc.com; a=ed25519; pk=8N59kMJUiVH++5QxJzTyHB/wh/kG5LxQ44j9zhUvZmw= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _jwoo1-dxA5GmQnLxG9ruNOzPHHsniZr X-Proofpoint-GUID: _jwoo1-dxA5GmQnLxG9ruNOzPHHsniZr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-15_03,2025-01-15_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 suspectscore=0 priorityscore=1501 mlxscore=0 impostorscore=0 phishscore=0 adultscore=0 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501150072 The functions poweron_coreid(), poweroff_coreid() and vcodec_control_v4() are only used for v4 and v6. Remove the dead code by: - Removing vcodec_control_v4() function - Removing the check for !IS_V6(core) && !IS_V4(core) in poweron_coreid() and poweroff_coreid() Directly call dev_pm_genpd_set_hwmode() without vcodec_control_v4(). Signed-off-by: Renjiang Han --- drivers/media/platform/qcom/venus/pm_helpers.c | 73 +++----------------------- 1 file changed, 8 insertions(+), 65 deletions(-) diff --git a/drivers/media/platform/qcom/venus/pm_helpers.c b/drivers/media/platform/qcom/venus/pm_helpers.c index a2062b366d4aedba3eb5e4be456a005847eaec0b..846aa765edbb33df0b0c39bb463dd68c16ce1b68 100644 --- a/drivers/media/platform/qcom/venus/pm_helpers.c +++ b/drivers/media/platform/qcom/venus/pm_helpers.c @@ -406,74 +406,29 @@ static const struct venus_pm_ops pm_ops_v3 = { .load_scale = load_scale_v1, }; -static int vcodec_control_v4(struct venus_core *core, u32 coreid, bool enable) -{ - void __iomem *ctrl, *stat; - u32 val; - int ret; - - if (IS_V6(core) || IS_V4(core)) - return dev_pm_genpd_set_hwmode(core->pmdomains->pd_devs[coreid], !enable); - else if (coreid == VIDC_CORE_ID_1) { - ctrl = core->wrapper_base + WRAPPER_VCODEC0_MMCC_POWER_CONTROL; - stat = core->wrapper_base + WRAPPER_VCODEC0_MMCC_POWER_STATUS; - } else { - ctrl = core->wrapper_base + WRAPPER_VCODEC1_MMCC_POWER_CONTROL; - stat = core->wrapper_base + WRAPPER_VCODEC1_MMCC_POWER_STATUS; - } - - if (enable) { - writel(0, ctrl); - - ret = readl_poll_timeout(stat, val, val & BIT(1), 1, 100); - if (ret) - return ret; - } else { - writel(1, ctrl); - - ret = readl_poll_timeout(stat, val, !(val & BIT(1)), 1, 100); - if (ret) - return ret; - } - - return 0; -} - static int poweroff_coreid(struct venus_core *core, unsigned int coreid_mask) { int ret; if (coreid_mask & VIDC_CORE_ID_1) { - ret = vcodec_control_v4(core, VIDC_CORE_ID_1, true); + ret = dev_pm_genpd_set_hwmode(core->pmdomains->pd_devs[VIDC_CORE_ID_1], false); if (ret) return ret; vcodec_clks_disable(core, core->vcodec0_clks); - if (!IS_V6(core) && !IS_V4(core)) { - ret = vcodec_control_v4(core, VIDC_CORE_ID_1, false); - if (ret) - return ret; - } - ret = pm_runtime_put_sync(core->pmdomains->pd_devs[1]); if (ret < 0) return ret; } if (coreid_mask & VIDC_CORE_ID_2) { - ret = vcodec_control_v4(core, VIDC_CORE_ID_2, true); + ret = dev_pm_genpd_set_hwmode(core->pmdomains->pd_devs[VIDC_CORE_ID_2], false); if (ret) return ret; vcodec_clks_disable(core, core->vcodec1_clks); - if (!IS_V6(core) && !IS_V4(core)) { - ret = vcodec_control_v4(core, VIDC_CORE_ID_2, false); - if (ret) - return ret; - } - ret = pm_runtime_put_sync(core->pmdomains->pd_devs[2]); if (ret < 0) return ret; @@ -491,17 +446,11 @@ static int poweron_coreid(struct venus_core *core, unsigned int coreid_mask) if (ret < 0) return ret; - if (!IS_V6(core) && !IS_V4(core)) { - ret = vcodec_control_v4(core, VIDC_CORE_ID_1, true); - if (ret) - return ret; - } - ret = vcodec_clks_enable(core, core->vcodec0_clks); if (ret) return ret; - ret = vcodec_control_v4(core, VIDC_CORE_ID_1, false); + ret = dev_pm_genpd_set_hwmode(core->pmdomains->pd_devs[VIDC_CORE_ID_1], true); if (ret < 0) return ret; } @@ -511,17 +460,11 @@ static int poweron_coreid(struct venus_core *core, unsigned int coreid_mask) if (ret < 0) return ret; - if (!IS_V6(core) && !IS_V4(core)) { - ret = vcodec_control_v4(core, VIDC_CORE_ID_2, true); - if (ret) - return ret; - } - ret = vcodec_clks_enable(core, core->vcodec1_clks); if (ret) return ret; - ret = vcodec_control_v4(core, VIDC_CORE_ID_2, false); + ret = dev_pm_genpd_set_hwmode(core->pmdomains->pd_devs[VIDC_CORE_ID_2], true); if (ret < 0) return ret; } @@ -802,7 +745,7 @@ static int vdec_power_v4(struct device *dev, int on) if (!legacy_binding) return 0; - ret = vcodec_control_v4(core, VIDC_CORE_ID_1, true); + ret = dev_pm_genpd_set_hwmode(core->pmdomains->pd_devs[VIDC_CORE_ID_1], false); if (ret) return ret; @@ -811,7 +754,7 @@ static int vdec_power_v4(struct device *dev, int on) else vcodec_clks_disable(core, core->vcodec0_clks); - vcodec_control_v4(core, VIDC_CORE_ID_1, false); + dev_pm_genpd_set_hwmode(core->pmdomains->pd_devs[VIDC_CORE_ID_1], true); return ret; } @@ -847,7 +790,7 @@ static int venc_power_v4(struct device *dev, int on) if (!legacy_binding) return 0; - ret = vcodec_control_v4(core, VIDC_CORE_ID_2, true); + ret = dev_pm_genpd_set_hwmode(core->pmdomains->pd_devs[VIDC_CORE_ID_2], false); if (ret) return ret; @@ -856,7 +799,7 @@ static int venc_power_v4(struct device *dev, int on) else vcodec_clks_disable(core, core->vcodec1_clks); - vcodec_control_v4(core, VIDC_CORE_ID_2, false); + dev_pm_genpd_set_hwmode(core->pmdomains->pd_devs[VIDC_CORE_ID_2], true); return ret; }