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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e4c1d13sm16228289f8f.91.2025.01.14.15.13.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 14 Jan 2025 15:13:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Stafford Horne , Jia Liu , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini Subject: [RFC PATCH] target/openrisc: Call cpu_openrisc_clock_init() in cpu_realize() Date: Wed, 15 Jan 2025 00:13:04 +0100 Message-ID: <20250114231304.77150-1-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org OpenRISC timer is architecturally tied to the CPU. It doesn't belong to the machine init() code to instanciate it: move its creation when a vCPU is realized (after being created). Reported-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daudé --- hw/openrisc/openrisc_sim.c | 2 -- hw/openrisc/virt.c | 2 -- target/openrisc/cpu.c | 2 ++ 3 files changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index e0da4067ba3..d7f97d19913 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -306,8 +306,6 @@ static void openrisc_sim_init(MachineState *machine) exit(1); } - cpu_openrisc_clock_init(cpus[n]); - qemu_register_reset(main_cpu_reset, cpus[n]); } diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c index 7b60bf85094..676cf8d692d 100644 --- a/hw/openrisc/virt.c +++ b/hw/openrisc/virt.c @@ -487,8 +487,6 @@ static void openrisc_virt_init(MachineState *machine) exit(1); } - cpu_openrisc_clock_init(cpus[n]); - qemu_register_reset(main_cpu_reset, cpus[n]); } diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b7bab0d7abf..291fec04fda 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -165,6 +165,8 @@ static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); cpu_reset(cs); + cpu_openrisc_clock_init(OPENRISC_CPU(dev)); + occ->parent_realize(dev, errp); }