From patchwork Fri Dec 20 15:05:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 182301 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp647351ilf; Fri, 20 Dec 2019 07:05:59 -0800 (PST) X-Google-Smtp-Source: APXvYqy6IDAAr3EYLMvZ7EeMT7tY7kzZddgfZ1WxUlgo9wf0xQYPY7tfKOfPToHB48v8qFkWbTT4 X-Received: by 2002:a54:4716:: with SMTP id k22mr3794772oik.36.1576854359814; Fri, 20 Dec 2019 07:05:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576854359; cv=none; d=google.com; s=arc-20160816; b=No7w/3quqjiaG+huha0FfymeyZXiB206E22Gpwll8PFl4xKWusqzUNCSWjFSC0rSEW FCuC/4ffmK9lb/rENDiu274qLyTW9BjlRmQdp6BXzzR8XzML1Usdaom1op/0BiTHeolV 47gujvq++ElWro6uandftKNeh45F7BhDIt0PKUbvuTfVYynVvsYcqIJToogfNFdhuk6U +9o6ie9uIQXu0uPhiPxGNTB4ngdiJYmvWKIoxxTUQnPK0PhcKM5FmkTk5RPij/MghX4P 2xHuaUX7cuarUvtSt3+JzA0+NqmfHGEr8wUJ602EXMCPXmwMW3WjlcznAQL4MeJAAbCN Fsdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=/Nt6s9ETl3U8aoPPyXfot2BFzXlzUR8/IsFp27NUZF4=; b=JcEEug4KMS8F8CQg9mgRnwkJG60i6AIvQHkAm+h2IR0d8+6ub0MNNEDUNzFYsz+6Ao m0tmZLMUFhGo9JGF8GZb3LWLlhYolpB49qcLO2y2/M/uA6/8EJHwM3Ttpl7wQT2wpTmh K0LErho/5uOfrnYu6gRVBL2+hdwcgEMtLvHK8eEeldA54rG3+SKK3b8Q5nWR9mva0hSt K74sNYuji8/ivqWjxgEXRKz5UZOUFeWvIhLW+p+hgQHUEHHoiVpswRw5orOOpGcNu81m BXvXwSXTm1C4TIt7geAVoaTAhj7X/DMbWS7kRnVAqDQmQXpPc5h2GFx5ar7ifi131o6Y hP8w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c2si2779188oig.255.2019.12.20.07.05.59; Fri, 20 Dec 2019 07:05:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727359AbfLTPF6 (ORCPT + 14 others); Fri, 20 Dec 2019 10:05:58 -0500 Received: from foss.arm.com ([217.140.110.172]:52194 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727233AbfLTPF6 (ORCPT ); Fri, 20 Dec 2019 10:05:58 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D609C31B; Fri, 20 Dec 2019 07:05:57 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4E1D83F6CF; Fri, 20 Dec 2019 07:05:56 -0800 (PST) From: Mark Rutland To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Mark Rutland , Alexandru Elisei , Drew Jones , James Morse , Julien Thierry , Peter Maydell , Suzuki K Poulose , Will Deacon , stable@vger.kernel.org Subject: [PATCH 1/3] KVM: arm64: correct PSTATE on exception entry Date: Fri, 20 Dec 2019 15:05:47 +0000 Message-Id: <20191220150549.31948-2-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20191220150549.31948-1-mark.rutland@arm.com> References: <20191220150549.31948-1-mark.rutland@arm.com> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org When KVM injects an exception into a guest, it generates the PSTATE value from scratch, configuring PSTATE.{M[4:0],DAIF}, and setting all other bits to zero. This isn't correct, as the architecture specifies that some PSTATE bits are (conditionally) cleared or set upon an exception, and others are unchanged from the original context. This patch adds logic to match the architectural behaviour. To make this simple to follow/audit/extend, documentation references are provided, and bits are configured in order of their layout in SPSR_EL2. This layout can be seen in the diagram on ARM DDI 0487E.a page C5-429. Signed-off-by: Mark Rutland Cc: Alexandru Elisei Cc: Drew Jones Cc: James Morse Cc: Julien Thierry Cc: Marc Zyngier Cc: Peter Maydell Cc: Suzuki K Poulose Cc: Will Deacon Cc: stable@vger.kernel.org --- arch/arm64/include/uapi/asm/ptrace.h | 1 + arch/arm64/kvm/inject_fault.c | 69 +++++++++++++++++++++++++++++++++--- 2 files changed, 65 insertions(+), 5 deletions(-) -- 2.11.0 diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h index 7ed9294e2004..d1bb5b69f1ce 100644 --- a/arch/arm64/include/uapi/asm/ptrace.h +++ b/arch/arm64/include/uapi/asm/ptrace.h @@ -49,6 +49,7 @@ #define PSR_SSBS_BIT 0x00001000 #define PSR_PAN_BIT 0x00400000 #define PSR_UAO_BIT 0x00800000 +#define PSR_DIT_BIT 0x01000000 #define PSR_V_BIT 0x10000000 #define PSR_C_BIT 0x20000000 #define PSR_Z_BIT 0x40000000 diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c index a9d25a305af5..270d91c05246 100644 --- a/arch/arm64/kvm/inject_fault.c +++ b/arch/arm64/kvm/inject_fault.c @@ -14,9 +14,6 @@ #include #include -#define PSTATE_FAULT_BITS_64 (PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | \ - PSR_I_BIT | PSR_D_BIT) - #define CURRENT_EL_SP_EL0_VECTOR 0x0 #define CURRENT_EL_SP_ELx_VECTOR 0x200 #define LOWER_EL_AArch64_VECTOR 0x400 @@ -50,6 +47,68 @@ static u64 get_except_vector(struct kvm_vcpu *vcpu, enum exception_type type) return vcpu_read_sys_reg(vcpu, VBAR_EL1) + exc_offset + type; } +/* + * When an exception is taken, most PSTATE fields are left unchanged in the + * handler. However, some are explicitly overridden (e.g. M[4:0]). Luckily all + * of the inherited bits have the same position in the AArch64/AArch32 SPSR_ELx + * layouts, so we don't need to shuffle these for exceptions from AArch32 EL0. + * + * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429. + * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426. + * + * Here we manipulate the fields in order of the AArch64 SPSR_ELx layout, from + * MSB to LSB. + */ +static unsigned long get_except64_pstate(struct kvm_vcpu *vcpu) +{ + unsigned long sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); + unsigned long old, new; + + old = *vcpu_cpsr(vcpu); + new = 0; + + new |= (old & PSR_N_BIT); + new |= (old & PSR_Z_BIT); + new |= (old & PSR_C_BIT); + new |= (old & PSR_V_BIT); + + // TODO: TCO (if/when ARMv8.5-MemTag is exposed to guests) + + new |= (old & PSR_DIT_BIT); + + // PSTATE.UAO is set to zero upon any exception to AArch64 + // See ARM DDI 0487E.a, page D5-2579. + + // PSTATE.PAN is unchanged unless overridden by SCTLR_ELx.SPAN + // See ARM DDI 0487E.a, page D5-2578. + new |= (old & PSR_PAN_BIT); + if (sctlr & SCTLR_EL1_SPAN) + new |= PSR_PAN_BIT; + + // PSTATE.SS is set to zero upon any exception to AArch64 + // See ARM DDI 0487E.a, page D2-2452. + + // PSTATE.IL is set to zero upon any exception to AArch64 + // See ARM DDI 0487E.a, page D1-2306. + + // PSTATE.SSBS is set to SCTLR_ELx.DSSBS upon any exception to AArch64 + // See ARM DDI 0487E.a, page D13-3258 + if (sctlr & SCTLR_ELx_DSSBS) + new |= PSR_SSBS_BIT; + + // PSTATE.BTYPE is set to zero upon any exception to AArch64 + // See ARM DDI 0487E.a, pages D1-2293 to D1-2294. + + new |= PSR_D_BIT; + new |= PSR_A_BIT; + new |= PSR_I_BIT; + new |= PSR_F_BIT; + + new |= PSR_MODE_EL1h; + + return new; +} + static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr) { unsigned long cpsr = *vcpu_cpsr(vcpu); @@ -59,7 +118,7 @@ static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu)); *vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync); - *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64; + *vcpu_cpsr(vcpu) = get_except64_pstate(vcpu); vcpu_write_spsr(vcpu, cpsr); vcpu_write_sys_reg(vcpu, addr, FAR_EL1); @@ -94,7 +153,7 @@ static void inject_undef64(struct kvm_vcpu *vcpu) vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu)); *vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync); - *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64; + *vcpu_cpsr(vcpu) = get_except64_pstate(vcpu); vcpu_write_spsr(vcpu, cpsr); /* From patchwork Fri Dec 20 15:05:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 182302 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp647388ilf; Fri, 20 Dec 2019 07:06:01 -0800 (PST) X-Google-Smtp-Source: APXvYqzdJQHs/XW+5CbT6uLxKfX3awpczrbdPitSn1vgQlK+XHEw+UTdGVpKmlli3k8UXrn25X7Y X-Received: by 2002:a05:6808:5d0:: with SMTP id d16mr4074763oij.45.1576854361580; Fri, 20 Dec 2019 07:06:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576854361; cv=none; d=google.com; s=arc-20160816; b=exQuiUEkI7AGg+qdlPPlZB5zT/0WT1KulTf3bKhurrNybA0bExzySP4wWDwoh1qeFR m4n3gufcZbhhFEHXV081+5l3OPRLguX5OMMFJQe7KuuOiwv5dp9VtBlZ6i5TGWkDOhs1 3hpEwCnZvbZ8dm7PpIst361NOs+DpjS/ei7pNRLd91hmVwjfnowyIVwMUxsxBN9VvGIo miLlIleWIzfxHSfkM8iPKVxvCRP9KSDBGidrF/aEsajY0zSyzBtctverrIi/GqaA9S1N 8JszMR73iZ2HXAjKBHSw0G0vekO3jfE6RkRq2vamcf1FyMw0W0hYjH8bKLso4qN04jdB S2jw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=7CpZrZ5a4ES2jAagQ0GEFTzVhxdNao8JbcGKDMj2YE4=; b=Zpw+kXWJNDLQ3i+Is/GwaMooRVa9zF3aRYtvgt6O4BgaYhg2AkXCwG0u3XA1T1iRmL oAbzJ+H/MsAijG9CRAwB93+ZPObmhXJ0W7Dua0LX8H49n9VzixAtSFB2ALIFe8kla7kv yl/gkSwtc596YZCpWYfU6hbpzjriui7CuzYYPPw4HLhkmv9s0NsviVpeJdeRW/M6r+50 FnDziykcwI2QoU5vaK6qBzJdnSSotH9PyHE4hy80YN7G4f5va0gihoSqwHIbnEFdXGNS MW64kmWLMe/htqywpBqnDLNfNlYv7dtw9xSBKIKhvAkxFkbu1ux+bR8aDTaJl/18/ONt ADUg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c2si2779188oig.255.2019.12.20.07.06.01; Fri, 20 Dec 2019 07:06:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727381AbfLTPGB (ORCPT + 14 others); Fri, 20 Dec 2019 10:06:01 -0500 Received: from foss.arm.com ([217.140.110.172]:52210 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727233AbfLTPGA (ORCPT ); Fri, 20 Dec 2019 10:06:00 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 184E030E; Fri, 20 Dec 2019 07:06:00 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 88ACE3F6CF; Fri, 20 Dec 2019 07:05:58 -0800 (PST) From: Mark Rutland To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Mark Rutland , Alexandru Elisei , Drew Jones , James Morse , Julien Thierry , Peter Maydell , Suzuki K Poulose , Will Deacon , stable@vger.kernel.org Subject: [PATCH 2/3] KVM: arm/arm64: correct CPSR on exception entry Date: Fri, 20 Dec 2019 15:05:48 +0000 Message-Id: <20191220150549.31948-3-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20191220150549.31948-1-mark.rutland@arm.com> References: <20191220150549.31948-1-mark.rutland@arm.com> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org When KVM injects an exception into a guest, it generates the CPSR value from scratch, configuring CPSR.{M,A,I,T,E}, and setting all other bits to zero. This isn't correct, as the architecture specifies that some CPSR bits are (conditionally) cleared or set upon an exception, and others are unchanged from the original context. This patch adds logic to match the architectural behaviour. To make this simple to follow/audit/extend, documentation references are provided, and bits are configured in order of their layout in SPSR_EL2. This layout can be seen in the diagram on ARM DDI 0487E.a page C5-426. Signed-off-by: Mark Rutland Cc: Alexandru Elisei Cc: Drew Jones Cc: James Morse Cc: Julien Thierry Cc: Marc Zyngier Cc: Peter Maydell Cc: Suzuki K Poulose Cc: Will Deacon Cc: stable@vger.kernel.org --- arch/arm/include/asm/kvm_emulate.h | 12 ++++ arch/arm64/include/asm/ptrace.h | 1 + virt/kvm/arm/aarch32.c | 110 +++++++++++++++++++++++++++++++++---- 3 files changed, 113 insertions(+), 10 deletions(-) -- 2.11.0 diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h index 40002416efec..dee2567661ed 100644 --- a/arch/arm/include/asm/kvm_emulate.h +++ b/arch/arm/include/asm/kvm_emulate.h @@ -14,13 +14,25 @@ #include /* arm64 compatibility macros */ +#define PSR_AA32_MODE_FIQ FIQ_MODE +#define PSR_AA32_MODE_SVC SVC_MODE #define PSR_AA32_MODE_ABT ABT_MODE #define PSR_AA32_MODE_UND UND_MODE #define PSR_AA32_T_BIT PSR_T_BIT +#define PSR_AA32_F_BIT PSR_F_BIT #define PSR_AA32_I_BIT PSR_I_BIT #define PSR_AA32_A_BIT PSR_A_BIT #define PSR_AA32_E_BIT PSR_E_BIT #define PSR_AA32_IT_MASK PSR_IT_MASK +#define PSR_AA32_GE_MASK 0x000f0000 +#define PSR_AA32_PAN_BIT 0x00400000 +#define PSR_AA32_SSBS_BIT 0x00800000 +#define PSR_AA32_DIT_BIT 0x01000000 +#define PSR_AA32_Q_BIT PSR_Q_BIT +#define PSR_AA32_V_BIT PSR_V_BIT +#define PSR_AA32_C_BIT PSR_C_BIT +#define PSR_AA32_Z_BIT PSR_Z_BIT +#define PSR_AA32_N_BIT PSR_N_BIT unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num); diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h index fbebb411ae20..bf57308fcd63 100644 --- a/arch/arm64/include/asm/ptrace.h +++ b/arch/arm64/include/asm/ptrace.h @@ -62,6 +62,7 @@ #define PSR_AA32_I_BIT 0x00000080 #define PSR_AA32_A_BIT 0x00000100 #define PSR_AA32_E_BIT 0x00000200 +#define PSR_AA32_PAN_BIT 0x00400000 #define PSR_AA32_SSBS_BIT 0x00800000 #define PSR_AA32_DIT_BIT 0x01000000 #define PSR_AA32_Q_BIT 0x08000000 diff --git a/virt/kvm/arm/aarch32.c b/virt/kvm/arm/aarch32.c index c4c57ba99e90..17bcde5c2451 100644 --- a/virt/kvm/arm/aarch32.c +++ b/virt/kvm/arm/aarch32.c @@ -10,6 +10,7 @@ * Author: Christoffer Dall */ +#include #include #include #include @@ -28,22 +29,111 @@ static const u8 return_offsets[8][2] = { [7] = { 4, 4 }, /* FIQ, unused */ }; +/* + * When an exception is taken, most CPSR fields are left unchanged in the + * handler. However, some are explicitly overridden (e.g. M[4:0]). + * + * The SPSR/SPSR_ELx layouts differ, and the below is intended to work with + * either format. Note: SPSR.J bit doesn't exist in SPSR_ELx, but this bit was + * obsoleted by the ARMv7 virtualization extensions and is RES0. + * + * For the SPSR layout seen from AArch32, see: + * - ARM DDI 0406C.d, page B1-1148 + * - ARM DDI 0487E.a, page G8-6264 + * + * For the SPSR_ELx layout for AArch32 seen from AArch64, see: + * - ARM DDI 0487E.a, page C5-426 + * + * Here we manipulate the fields in order of the AArch32 SPSR_ELx layout, from + * MSB to LSB. + */ +static unsigned long get_except32_cpsr(struct kvm_vcpu *vcpu, u32 mode) +{ + u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR); + unsigned long old, new; + + old = *vcpu_cpsr(vcpu); + new = 0; + + new |= (old & PSR_AA32_N_BIT); + new |= (old & PSR_AA32_Z_BIT); + new |= (old & PSR_AA32_C_BIT); + new |= (old & PSR_AA32_V_BIT); + new |= (old & PSR_AA32_Q_BIT); + + // CPSR.IT[7:0] are set to zero upon any exception + // See ARM DDI 0487E.a, section G1.12.3 + // See ARM DDI 0406C.d, section B1.8.3 + + new |= (old & PSR_AA32_DIT_BIT); + + // CPSR.SSBS is set to SCTLR.DSSBS upon any exception + // See ARM DDI 0487E.a, page G8-6244 + if (sctlr & BIT(31)) + new |= PSR_AA32_SSBS_BIT; + + // CPSR.PAN is unchanged unless overridden by SCTLR.SPAN + // See ARM DDI 0487E.a, page G8-6246 + new |= (old & PSR_AA32_PAN_BIT); + if (sctlr & BIT(23)) + new |= PSR_AA32_PAN_BIT; + + // SS does not exist in AArch32, so ignore + + // CPSR.IL is set to zero upon any exception + // See ARM DDI 0487E.a, page G1-5527 + + new |= (old & PSR_AA32_GE_MASK); + + // CPSR.IT[7:0] are set to zero upon any exception + // See prior comment above + + // CPSR.E is set to SCTLR.EE upon any exception + // See ARM DDI 0487E.a, page G8-6245 + // See ARM DDI 0406C.d, page B4-1701 + if (sctlr & BIT(25)) + new |= PSR_AA32_E_BIT; + + // CPSR.A is unchanged upon an exception to Undefined, Supervisor + // CPSR.A is set upon an exception to other modes + // See ARM DDI 0487E.a, pages G1-5515 to G1-5516 + // See ARM DDI 0406C.d, page B1-1182 + new |= (old & PSR_AA32_A_BIT); + if (mode != PSR_AA32_MODE_UND && mode != PSR_AA32_MODE_SVC) + new |= PSR_AA32_A_BIT; + + // CPSR.I is set upon any exception + // See ARM DDI 0487E.a, pages G1-5515 to G1-5516 + // See ARM DDI 0406C.d, page B1-1182 + new |= PSR_AA32_I_BIT; + + // CPSR.F is set upon an exception to FIQ + // CPSR.F is unchanged upon an exception to other modes + // See ARM DDI 0487E.a, pages G1-5515 to G1-5516 + // See ARM DDI 0406C.d, page B1-1182 + new |= (old & PSR_AA32_F_BIT); + if (mode == PSR_AA32_MODE_FIQ) + new |= PSR_AA32_F_BIT; + + // CPSR.T is set to SCTLR.TE upon any exception + // See ARM DDI 0487E.a, page G8-5514 + // See ARM DDI 0406C.d, page B1-1181 + if (sctlr & BIT(30)) + new |= PSR_AA32_T_BIT; + + new |= mode; + + return new; +} + static void prepare_fault32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset) { - unsigned long cpsr; unsigned long new_spsr_value = *vcpu_cpsr(vcpu); bool is_thumb = (new_spsr_value & PSR_AA32_T_BIT); u32 return_offset = return_offsets[vect_offset >> 2][is_thumb]; u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR); - cpsr = mode | PSR_AA32_I_BIT; - - if (sctlr & (1 << 30)) - cpsr |= PSR_AA32_T_BIT; - if (sctlr & (1 << 25)) - cpsr |= PSR_AA32_E_BIT; - - *vcpu_cpsr(vcpu) = cpsr; + *vcpu_cpsr(vcpu) = get_except32_cpsr(vcpu, mode); /* Note: These now point to the banked copies */ vcpu_write_spsr(vcpu, new_spsr_value); @@ -84,7 +174,7 @@ static void inject_abt32(struct kvm_vcpu *vcpu, bool is_pabt, fsr = &vcpu_cp15(vcpu, c5_DFSR); } - prepare_fault32(vcpu, PSR_AA32_MODE_ABT | PSR_AA32_A_BIT, vect_offset); + prepare_fault32(vcpu, PSR_AA32_MODE_ABT, vect_offset); *far = addr; From patchwork Fri Dec 20 15:05:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 182303 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp647438ilf; Fri, 20 Dec 2019 07:06:03 -0800 (PST) X-Google-Smtp-Source: APXvYqwqBjICRDCwMvLAjfKj/xtlSMtYihzkHLXf22wfx0L5fWRgakx0O+65camoAKkIKxWjboXK X-Received: by 2002:a05:6830:593:: with SMTP id c19mr12000607oth.224.1576854363616; Fri, 20 Dec 2019 07:06:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576854363; cv=none; d=google.com; s=arc-20160816; b=H5/EnbEIpXvSQNDPu0FVnUYThdFa6QAIvEB2gTNQvA8bLFs1XVw18/ZGVQ7Bk4DBI1 pmx23I5TF4IdYhS73dq8n83zKduo8sZOmD94ltGDEPg0fUgz+fdfhpfDug/QMis+w7uk 02FGAKDwNzgtDiPTX/r+8eYLwd7vJ65UOFo3pKfpuhwxEAm3+LfrD1ZEPsWsLGPx6YPQ USnSJf/Kxh3B7ebCvZ2DmAlPbpOSy8ydrY8yni1++/iC1c6lNTyJm9Z7VMIiuyK3RSjZ fT3wiEHdkqR7FOqINxc3Fsg45+ZaJmdEvYUrnwZyDXw6JwNoNWBjnjRnL0bAFcbpBKUS mb9Q== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id c2si2779188oig.255.2019.12.20.07.06.03; Fri, 20 Dec 2019 07:06:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727391AbfLTPGD (ORCPT + 14 others); Fri, 20 Dec 2019 10:06:03 -0500 Received: from foss.arm.com ([217.140.110.172]:52226 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727233AbfLTPGC (ORCPT ); Fri, 20 Dec 2019 10:06:02 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4AEEF31B; Fri, 20 Dec 2019 07:06:02 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BB7753F6CF; Fri, 20 Dec 2019 07:06:00 -0800 (PST) From: Mark Rutland To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Mark Rutland , Alexandru Elisei , Drew Jones , James Morse , Julien Thierry , Peter Maydell , Suzuki K Poulose , Will Deacon , stable@vger.kernel.org Subject: [PATCH 3/3] KVM: arm/arm64: correct AArch32 SPSR on exception entry Date: Fri, 20 Dec 2019 15:05:49 +0000 Message-Id: <20191220150549.31948-4-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20191220150549.31948-1-mark.rutland@arm.com> References: <20191220150549.31948-1-mark.rutland@arm.com> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Confusingly, there are three SPSR layouts that a kernel may need to deal with: (1) An AArch64 SPSR_ELx view of an AArch64 pstate (2) An AArch64 SPSR_ELx view of an AArch32 pstate (3) An AArch32 SPSR_* view of an AArch32 pstate When the KVM AArch32 support code deals with SPSR_{EL2,HYP}, it's either dealing with #2 or #3 consistently. On arm64 the PSR_AA32_* definitions match the AArch64 SPSR_ELx view, and on arm the PSR_AA32_* definitions match the AArch32 SPSR_* view. However, when we inject an exception into an AArch32 guest, we have to synthesize the AArch32 SPSR_* that the guest will see. Thus, an AArch64 host needs to synthesize layout #3 from layout #2. This patch adds a new host_spsr_to_spsr32() helper for this, and makes use of it in the KVM AArch32 support code. For arm64 we need to shuffle the DIT bit around, and remove the SS bit, while for arm we can use the value as-is. I've open-coded the bit manipulation for now to avoid having to rework the existing PSR_* definitions into PSR64_AA32_* and PSR32_AA32_* definitions. I hope to perform a more thorough refactoring in future so that we can handle pstate view manipulation more consistently across the kernel tree. Signed-off-by: Mark Rutland Cc: Alexandru Elisei Cc: Drew Jones Cc: James Morse Cc: Julien Thierry Cc: Marc Zyngier Cc: Peter Maydell Cc: Suzuki K Poulose Cc: Will Deacon Cc: stable@vger.kernel.org --- arch/arm/include/asm/kvm_emulate.h | 5 +++++ arch/arm64/include/asm/kvm_emulate.h | 32 ++++++++++++++++++++++++++++++++ virt/kvm/arm/aarch32.c | 6 +++--- 3 files changed, 40 insertions(+), 3 deletions(-) -- 2.11.0 Reviewed-by: Alexandru Elisei diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h index dee2567661ed..b811576bc456 100644 --- a/arch/arm/include/asm/kvm_emulate.h +++ b/arch/arm/include/asm/kvm_emulate.h @@ -53,6 +53,11 @@ static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v) *__vcpu_spsr(vcpu) = v; } +static inline unsigned long host_spsr_to_spsr32(unsigned long spsr) +{ + return spsr; +} + static inline unsigned long vcpu_get_reg(struct kvm_vcpu *vcpu, u8 reg_num) { diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index d69c1efc63e7..98672938f9f9 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -204,6 +204,38 @@ static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v) vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1] = v; } +/* + * The layout of SPSR for an AArch32 state is different when observed from an + * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32 + * view given an AArch64 view. + * + * In ARM DDI 0487E.a see: + * + * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426 + * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256 + * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280 + * + * Which show the following differences: + * + * | Bit | AA64 | AA32 | Notes | + * +-----+------+------+-----------------------------| + * | 24 | DIT | J | J is RES0 in ARMv8 | + * | 21 | SS | DIT | SS doesn't exist in AArch32 | + * + * ... and all other bits are (currently) common. + */ +static inline unsigned long host_spsr_to_spsr32(unsigned long spsr) +{ + const unsigned long overlap = BIT(24) | BIT(21); + unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT); + + spsr &= overlap; + + spsr |= dit << 21; + + return spsr; +} + static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) { u32 mode; diff --git a/virt/kvm/arm/aarch32.c b/virt/kvm/arm/aarch32.c index 17bcde5c2451..115210e64682 100644 --- a/virt/kvm/arm/aarch32.c +++ b/virt/kvm/arm/aarch32.c @@ -128,15 +128,15 @@ static unsigned long get_except32_cpsr(struct kvm_vcpu *vcpu, u32 mode) static void prepare_fault32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset) { - unsigned long new_spsr_value = *vcpu_cpsr(vcpu); - bool is_thumb = (new_spsr_value & PSR_AA32_T_BIT); + unsigned long spsr = *vcpu_cpsr(vcpu); + bool is_thumb = (spsr & PSR_AA32_T_BIT); u32 return_offset = return_offsets[vect_offset >> 2][is_thumb]; u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR); *vcpu_cpsr(vcpu) = get_except32_cpsr(vcpu, mode); /* Note: These now point to the banked copies */ - vcpu_write_spsr(vcpu, new_spsr_value); + vcpu_write_spsr(vcpu, host_spsr_to_spsr32(spsr)); *vcpu_reg32(vcpu, 14) = *vcpu_pc(vcpu) + return_offset; /* Branch to exception vector */