From patchwork Fri Dec 20 14:30:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 182280 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp607479ilf; Fri, 20 Dec 2019 06:32:03 -0800 (PST) X-Google-Smtp-Source: APXvYqwZHOUC5jCUhVNOTAIVuoRiKbyZ3CBcnv84EfhBmeDpumTlte6NgEMoy7KioAasRgXeA7xm X-Received: by 2002:a9d:4706:: with SMTP id a6mr14158821otf.331.1576852323654; Fri, 20 Dec 2019 06:32:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576852323; cv=none; d=google.com; s=arc-20160816; b=izDWx4Wslqji2P0pdAUVMup9BRoAaRTEtihKn2xPLBfoSwU/wopZHFn00C+TtT+8y1 HAxRtk3OfbuUil2mJPtMmxD6hj8lWtm7D8H25sodHzMEZcnYGAGvMtbvoQhLfDaWWZlz a6I/rym+lIyPcTTczhRJLQyPp5FRzixg1YPjSOt/EfavRQu2dQmrZtvo4wy5wQNnPtiU l4r6Wp6tyX1IdudeZqN01MNrLKPZowecmyU2WaN2/Dt6hxl3RQlxS2XFfOXnoHuFx0bi 62bjhrD9qJDiczVedSU353dVKfl6CbLZjWcHpoaSe/tWvikntW4p0Ti3mo44HJ5M2ygf mtVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=EFxXNdRXys1JcqCgsENOUtZggHQO69hlwPH2tF6F4pY=; b=sZlu3+iSUa6TKyZl16kzmMQHqrjaAvRHvMVTSn7OD9C7wXlGxJpMTnyICXw6ddNzM7 YRZ3uDO+wwIDEMC5u2XYS1aEXELGt/i8j9ylK8cjIgnuAUh65oIFMW5E/LGK0iSelLgx M3GjGUx5RbwoIJyv9PZ/cosfxtiIqoQtgr3pbwUcb63waYS3ns197KW7KuNBe80KpzDn CIjhlNouDksWC4KzqsmaeSfxIk98TFTlFGnPwXtTQ4XPaaPuuien0DeJOzNttrRXMKiJ PbKSFxgFuQBvx4QZIoF9THVR1kq+4gw4SaUFtpltYm33sGkzDl/g5zMQ59JWds4xz7kW fZZg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w64si4972237oib.185.2019.12.20.06.31.58; Fri, 20 Dec 2019 06:32:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727797AbfLTOai (ORCPT + 27 others); Fri, 20 Dec 2019 09:30:38 -0500 Received: from foss.arm.com ([217.140.110.172]:51180 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727754AbfLTOaf (ORCPT ); Fri, 20 Dec 2019 09:30:35 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8CAC431B; Fri, 20 Dec 2019 06:30:34 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B39603F718; Fri, 20 Dec 2019 06:30:32 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 01/18] dt-bindings: ARM SPE: highlight the need for PPI partitions on heterogeneous systems Date: Fri, 20 Dec 2019 14:30:08 +0000 Message-Id: <20191220143025.33853-2-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sudeep Holla It's not entirely clear for the binding document that the only way to express ARM SPE affined to a subset of CPUs on a heterogeneous systems is through the use of PPI partitions available in the interrupt controller bindings. Let's make it clear. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- Documentation/devicetree/bindings/arm/spe-pmu.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.21.0 diff --git a/Documentation/devicetree/bindings/arm/spe-pmu.txt b/Documentation/devicetree/bindings/arm/spe-pmu.txt index 93372f2a7df9..4f4815800f6e 100644 --- a/Documentation/devicetree/bindings/arm/spe-pmu.txt +++ b/Documentation/devicetree/bindings/arm/spe-pmu.txt @@ -9,8 +9,9 @@ performance sample data using an in-memory trace buffer. "arm,statistical-profiling-extension-v1" - interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where - SPE is only supported on a subset of the CPUs, please consult - the arm,gic-v3 binding for details on describing a PPI partition. + SPE is only supported on a subset of the CPUs, a PPI partition + described in the arm,gic-v3 binding must be used to describe + the set of CPUs this interrupt is affine to. ** Example: From patchwork Fri Dec 20 14:30:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 182293 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp611427ilf; Fri, 20 Dec 2019 06:35:01 -0800 (PST) X-Google-Smtp-Source: APXvYqxYAo0/VFItcSmKUrM0K3xzOLQiBRqWgQCoO9f4ZtjXufMjNVAog1c1SkAOwan19kTJhPsg X-Received: by 2002:aca:4d0f:: with SMTP id a15mr4061836oib.21.1576852501570; Fri, 20 Dec 2019 06:35:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576852501; cv=none; d=google.com; s=arc-20160816; b=EJjO6bZ2DTSjHRO6SFCYfNkrDigBOSZ78oHd9TzcQW5K4M7+mcVr/DLOASMcJFYIJL pQYP76u9J/WT+TVyVsCx7dlUV2jAvR9fw9JqMkGQegc2Fwyr731UNvoZzei6gocWEqa7 8auSu0Nee4ESlCSeu6G6ZbzjKeIiPbxUMwbYgrFxl8sJ4PL9ESaYJONNrjFtsqqrOjCt fF78ZAGfB42APUIUusZ0dPkEKeWEPotYcf8IPID0Gt40WWhFI527SDvauK4N1HFg1SnR +c8QcrzkWROipC8SH1NnqC+/jd31Hy0+QRGTUICe4rA5uuhR14cmwmt1czuwv9DbGVxR YaTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=U5cfUB13gZ6ngZv8z37SBvkIfdLEmK98/ZTWG4essNo=; b=NcTTijS6EH5wK58QMpWJAgwNW2LSxd2rlguTuRQoObhvVPUW9tTqO89ctWK1NxDWHe oE1w2ve20c5lCfnDdQRRyklfX1yPj1CWNcAOsdtnKIFHlU5DLZOPlTtWnecppCQEbiTC eTxlTsnJLEj/Qo8AjmWeqv44OkEkttjqEOpvlKEOiP/SFAeLQRCA+ujlez8aNugDXFND 0STwowT0X6htTvqURFkKtMw4k9ARmMLOTIziVm2lVMAofcfS5OMNhJBMcZovZdNFTX+I 71WVVsyEM8SwAr/naM/xt/jZRixFApKXhZzG0RY6mSUUl/M+F9xRkYpJpOqYcIwWqmhB PQ5A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w64si4972237oib.185.2019.12.20.06.35.01; Fri, 20 Dec 2019 06:35:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728026AbfLTOdo (ORCPT + 27 others); Fri, 20 Dec 2019 09:33:44 -0500 Received: from foss.arm.com ([217.140.110.172]:51188 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727783AbfLTOah (ORCPT ); Fri, 20 Dec 2019 09:30:37 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B569D106F; Fri, 20 Dec 2019 06:30:36 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DC14E3F718; Fri, 20 Dec 2019 06:30:34 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 02/18] arm64: KVM: reset E2PB correctly in MDCR_EL2 when exiting the guest(VHE) Date: Fri, 20 Dec 2019 14:30:09 +0000 Message-Id: <20191220143025.33853-3-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sudeep Holla On VHE systems, the reset value for MDCR_EL2.E2PB=b00 which defaults to profiling buffer using the EL2 stage 1 translations. However if the guest are allowed to use profiling buffers changing E2PB settings, we need to ensure we resume back MDCR_EL2.E2PB=b00. Currently we just do bitwise '&' with MDCR_EL2_E2PB_MASK which will retain the value. So fix it by clearing all the bits in E2PB. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- arch/arm64/kvm/hyp/switch.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) -- 2.21.0 diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 72fbbd86eb5e..250f13910882 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -228,9 +228,7 @@ void deactivate_traps_vhe_put(void) { u64 mdcr_el2 = read_sysreg(mdcr_el2); - mdcr_el2 &= MDCR_EL2_HPMN_MASK | - MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT | - MDCR_EL2_TPMS; + mdcr_el2 &= MDCR_EL2_HPMN_MASK | MDCR_EL2_TPMS; write_sysreg(mdcr_el2, mdcr_el2); From patchwork Fri Dec 20 14:30:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 182283 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp608066ilf; Fri, 20 Dec 2019 06:32:31 -0800 (PST) X-Google-Smtp-Source: APXvYqz4egb3bmXOuiDmLKK6LzcHHaQ/SzA3S6JX6pvaSZFkPX7FGUy3k9KTumuOYuu9sIUDVTeO X-Received: by 2002:a9d:61c4:: with SMTP id h4mr15910365otk.310.1576852351862; Fri, 20 Dec 2019 06:32:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576852351; cv=none; d=google.com; s=arc-20160816; b=fae7J6LUkE3AFV4dJN3CUgpC0j/EXFjFKh408Ef8b8PeMed1n1YgLVlE98KbDJ9veM yws8vQ5jSYA559Wja6mAL0PNLcsFmVy5HZbGCdGOWTB1c27hWaXVcc7GSOe8GEAqP2J/ GWQc83e2Qf1TSTh5woO5FfxNp7Jznmf7rD8RtxIpMUbJn+8GXk6pgaJuMH6CTr4ACGby 50EZXpaYlzLZvAJ2muZ4tERudvTI1yZ24KslT07fGpOvwzyj/ZYIglVYWQXeGAzYSAx4 XxfvXAsR1a50Y7eSWBXBGP8BYfovzZfId3oR2Z1luYmpIH1x4a/zyrEAeqxmVh8K276R BTuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=6TowpFpBYiy/I8Im0zP6he1uH+y6EKepLd+I8iR+MCg=; b=UjtdK4+MHRvY6UsrYHar7qtL3Q0Ar0gVLWjz9ZOrMmrOiZsoNmgyRAJjWSmDfda5iJ Puj/H3tU7ye+YP/pPv2enOw7TwbybodUYpJyHc/w3bfOtBIWmWhJlJMu7lombO7f+/1R //hQ57jWHKbp9XdT+UFuwDmL1UsvODexmLW9ZznmL/LEz7pd3+FmRue/7rZmwGMh3t0s jFDlXRi6lo+Ew8O54nzM68giDXDx+MXWjOQ66IwxhDycM4st6eUzcGALv0jp3rozG8iB ZK7vqk05Cddlj5dG5BE2PXdFkkdoS3GhdWb1um/d1h2MibxZZefjQF1pDeayeTx7x6ae ZgHQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w64si4972237oib.185.2019.12.20.06.32.25; Fri, 20 Dec 2019 06:32:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727866AbfLTOap (ORCPT + 27 others); Fri, 20 Dec 2019 09:30:45 -0500 Received: from foss.arm.com ([217.140.110.172]:51198 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727809AbfLTOaj (ORCPT ); Fri, 20 Dec 2019 09:30:39 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DF45611D4; Fri, 20 Dec 2019 06:30:38 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1120D3F718; Fri, 20 Dec 2019 06:30:36 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 03/18] arm64: KVM: define SPE data structure for each vcpu Date: Fri, 20 Dec 2019 14:30:10 +0000 Message-Id: <20191220143025.33853-4-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sudeep Holla In order to support virtual SPE for guest, so define some basic structs. This features depends on host having hardware with SPE support. Since we can support this only on ARM64, add a separate config symbol for the same. Signed-off-by: Sudeep Holla [ Add irq_level, rename irq to irq_num for kvm_spe ] Signed-off-by: Andrew Murray --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/kvm/Kconfig | 7 +++++++ include/kvm/arm_spe.h | 19 +++++++++++++++++++ 3 files changed, 28 insertions(+) create mode 100644 include/kvm/arm_spe.h -- 2.21.0 diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index c61260cf63c5..f5dcff912645 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -35,6 +35,7 @@ #include #include #include +#include #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS @@ -302,6 +303,7 @@ struct kvm_vcpu_arch { struct vgic_cpu vgic_cpu; struct arch_timer_cpu timer_cpu; struct kvm_pmu pmu; + struct kvm_spe spe; /* * Anything that is not used directly from assembly code goes diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig index a475c68cbfec..af5be2c57dcb 100644 --- a/arch/arm64/kvm/Kconfig +++ b/arch/arm64/kvm/Kconfig @@ -35,6 +35,7 @@ config KVM select HAVE_KVM_EVENTFD select HAVE_KVM_IRQFD select KVM_ARM_PMU if HW_PERF_EVENTS + select KVM_ARM_SPE if (HW_PERF_EVENTS && ARM_SPE_PMU) select HAVE_KVM_MSI select HAVE_KVM_IRQCHIP select HAVE_KVM_IRQ_ROUTING @@ -61,6 +62,12 @@ config KVM_ARM_PMU Adds support for a virtual Performance Monitoring Unit (PMU) in virtual machines. +config KVM_ARM_SPE + bool + ---help--- + Adds support for a virtual Statistical Profiling Extension(SPE) in + virtual machines. + config KVM_INDIRECT_VECTORS def_bool KVM && (HARDEN_BRANCH_PREDICTOR || HARDEN_EL2_VECTORS) diff --git a/include/kvm/arm_spe.h b/include/kvm/arm_spe.h new file mode 100644 index 000000000000..48d118fdb174 --- /dev/null +++ b/include/kvm/arm_spe.h @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 ARM Ltd. + */ + +#ifndef __ASM_ARM_KVM_SPE_H +#define __ASM_ARM_KVM_SPE_H + +#include +#include + +struct kvm_spe { + int irq_num; + bool ready; /* indicates that SPE KVM instance is ready for use */ + bool created; /* SPE KVM instance is created, may not be ready yet */ + bool irq_level; +}; + +#endif /* __ASM_ARM_KVM_SPE_H */ From patchwork Fri Dec 20 14:30:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 182292 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp611314ilf; Fri, 20 Dec 2019 06:34:56 -0800 (PST) X-Google-Smtp-Source: APXvYqxgOeXDQXm9+bXkJH5rxwCkuwbtoCw8sR9fiWelSO44zL81i7iiDeh39CezJMHsi4NuahZB X-Received: by 2002:aca:53c6:: with SMTP id h189mr4058795oib.11.1576852496532; Fri, 20 Dec 2019 06:34:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576852496; cv=none; d=google.com; s=arc-20160816; b=p5Mce/EgVw0gZXYV5LJNaWx2BhKUL8Nb2wC9/pudp10s4cJiMixPhp6QD9tQUjvmhY 1xIy7zvVdbJQCSUW3gyfKWIzvxDHSIF3fhQsQlPZZ6eOYkOOIcrKIxETgKfu9Br5pawH IMxenqHOq/LBvNHhqy/UrG7w/Jv6nEYdfCIEP8sWixfdypo6AJU0OyW712fByyCmuVHf pnmgpMjnACL51YL0zx0K0KrXmhbkg+BcliDduSuUD1+NsZXFZ8bZEzC/fktKIa52pEID BIO/oCJO+/HxNXBTztRVcbigW7+iM2rMw2OfpxaoMVguhSMNMnBFe5LpvRW+cgLRiPBc I31Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Vs/H7VBklGiw49nsVlases4Qdp7j/djRRpwFU+fxpoc=; b=Fc4YqxAhvoluxjV7ieL3CPG5x/N4iTkH4HKCZlrAlKe/WrkKsfkTHle2SqdIIEv2ol KfoyPAWCLPR/zlqSAHw9bfL6g9MohDPIKUxBoZ+z/jaNp5kDmpdkx6sMs/RElgahrIW0 illpQumXAqRiIhRrCscsQ3CJJO9ACF3Ez0VEfxbOgZVP+Fqa+eyir2WMUJpdOp6y0RHQ EL9YVHxd8XJwhVi6dCx2G/wxrhS11eLpHUem05Yp6JZtNCN700Jj9FNKACelXzjOOJq1 zpWatwVnvBtRvARCXB+5/TQRhUNkf2zf6KUkVz8PWx6koZ8BS+AwOQEdRLfPnv5M2vTk wAoQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w64si4972237oib.185.2019.12.20.06.34.56; Fri, 20 Dec 2019 06:34:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728080AbfLTOdT (ORCPT + 27 others); Fri, 20 Dec 2019 09:33:19 -0500 Received: from foss.arm.com ([217.140.110.172]:51206 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727815AbfLTOal (ORCPT ); Fri, 20 Dec 2019 09:30:41 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1304311FB; Fri, 20 Dec 2019 06:30:41 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 39E3A3F718; Fri, 20 Dec 2019 06:30:39 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 04/18] arm64: KVM: add SPE system registers to sys_reg_descs Date: Fri, 20 Dec 2019 14:30:11 +0000 Message-Id: <20191220143025.33853-5-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sudeep Holla Add the Statistical Profiling Extension(SPE) Profiling Buffer controls registers such that we can provide initial register values and use the sys_regs structure as a store for our SPE context. Signed-off-by: Sudeep Holla [ Reword commit, remove access/reset handlers, defer kvm_arm_support_spe_v1 ] Signed-off-by: Andrew Murray --- arch/arm64/include/asm/kvm_host.h | 12 ++++++++++++ arch/arm64/kvm/sys_regs.c | 11 +++++++++++ 2 files changed, 23 insertions(+) -- 2.21.0 diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index f5dcff912645..9eb85f14df90 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -145,6 +145,18 @@ enum vcpu_sysreg { MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ DISR_EL1, /* Deferred Interrupt Status Register */ + /* Statistical Profiling Extension Registers */ + PMSCR_EL1, + PMSICR_EL1, + PMSIRR_EL1, + PMSFCR_EL1, + PMSEVFR_EL1, + PMSLATFR_EL1, + PMSIDR_EL1, + PMBLIMITR_EL1, + PMBPTR_EL1, + PMBSR_EL1, + /* Performance Monitors Registers */ PMCR_EL0, /* Control Register */ PMSELR_EL0, /* Event Counter Selection Register */ diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 46822afc57e0..955b157f9cc5 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1506,6 +1506,17 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, + { SYS_DESC(SYS_PMSCR_EL1), NULL, reset_val, PMSCR_EL1, 0 }, + { SYS_DESC(SYS_PMSICR_EL1), NULL, reset_val, PMSICR_EL1, 0 }, + { SYS_DESC(SYS_PMSIRR_EL1), NULL, reset_val, PMSIRR_EL1, 0 }, + { SYS_DESC(SYS_PMSFCR_EL1), NULL, reset_val, PMSFCR_EL1, 0 }, + { SYS_DESC(SYS_PMSEVFR_EL1), NULL, reset_val, PMSEVFR_EL1, 0 }, + { SYS_DESC(SYS_PMSLATFR_EL1), NULL, reset_val, PMSLATFR_EL1, 0 }, + { SYS_DESC(SYS_PMSIDR_EL1), NULL, reset_val, PMSIDR_EL1, 0 }, + { SYS_DESC(SYS_PMBLIMITR_EL1), NULL, reset_val, PMBLIMITR_EL1, 0 }, + { SYS_DESC(SYS_PMBPTR_EL1), NULL, reset_val, PMBPTR_EL1, 0 }, + { SYS_DESC(SYS_PMBSR_EL1), NULL, reset_val, PMBSR_EL1, 0 }, + { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, NULL, PMINTENSET_EL1 }, From patchwork Fri Dec 20 14:30:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 182284 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp608888ilf; Fri, 20 Dec 2019 06:33:08 -0800 (PST) X-Google-Smtp-Source: APXvYqyZcSf92Eznu5cW7Tiq88c0PL1xtsXwDivIxYq5/GEOaWNJ91ZST58g0H/BpKXIaqYToorY X-Received: by 2002:aca:f484:: with SMTP id s126mr3676618oih.48.1576852388663; Fri, 20 Dec 2019 06:33:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576852388; cv=none; d=google.com; s=arc-20160816; b=jm0TK5glOgfBxwr/TX//nUrymhD5GAr1sTMU6FZplVjAn5UdIzXlBMfVZ1oDyGpInV Ie+DyRggG3SKf2HhqAiHo87zAHrJDr+Ahp/1iE7p+mI5aE2Y+Nan8AwXGwJbF6RwLPOH t9vYIvAFsJA7r2EuqIwO0ONJHKP3fdwLltqDbRtNlEqwhg/HvTS9FPku2dGFbabeph2N ScCNdZ9YYLqIOoCLRUpEzdpTQ6xugbarooqEAH/psmBGVSh6A1nANathGfrfuOdoUEdT PXZHstRrRHaTZ8cA1o9h3nPNyepFQqpe/mfG8D4qohVNqsYt2rKZxVmUOhBvvRFbQs7l 4GOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=ioeCicH+JZf02sBp5Wz7enjBNxJXm9k1A+Cvi42eW9E=; b=eqW5Kglt9B7h5r9XreMWXYCivF6DXRTdr1g5jAHZdvzRowusAjTa/exYL8g7AQPsFl StRiDI5idczfWXrEuCu2yzhEVbItp1RDR/Wlm13Geuw3ElIKLIEQFVnMD8+XaoBYZTJq DVwSknd1dwMQn2KTZmjplEHR4MOQNahpsrA0B77Kp4+ayfwLkHswwj/5CUBcRiMAUYUL 1j0etxi/oIteXR9eTd1DkM+DqE3sNbvgJ3OZMDTnV/Y5lPpvtaF8XrvPC5Xyc8jI83eK d8WgS4ByxsIETl4vS5LdAlwGobIWtO/fR4ElJ4ChI7evVHHcfh7cjcw6py55jWrVGz+v 1keQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w64si4972237oib.185.2019.12.20.06.33.02; Fri, 20 Dec 2019 06:33:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727953AbfLTOaz (ORCPT + 27 others); Fri, 20 Dec 2019 09:30:55 -0500 Received: from foss.arm.com ([217.140.110.172]:51218 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727790AbfLTOan (ORCPT ); Fri, 20 Dec 2019 09:30:43 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3C03411B3; Fri, 20 Dec 2019 06:30:43 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6302E3F718; Fri, 20 Dec 2019 06:30:41 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 05/18] arm64: KVM/VHE: enable the use PMSCR_EL12 on VHE systems Date: Fri, 20 Dec 2019 14:30:12 +0000 Message-Id: <20191220143025.33853-6-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sudeep Holla Currently, we are just using PMSCR_EL1 in the host for non VHE systems. We already have the {read,write}_sysreg_el*() accessors for accessing particular ELs' sysregs in the presence of VHE. Lets just define PMSCR_EL12 and start making use of it here which will access the right register on both VHE and non VHE systems. This change is required to add SPE guest support on VHE systems. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- arch/arm64/include/asm/sysreg.h | 1 + arch/arm64/kvm/hyp/debug-sr.c | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) -- 2.21.0 diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 6e919fafb43d..6c0b0ad97688 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -468,6 +468,7 @@ #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0) +#define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0) #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) diff --git a/arch/arm64/kvm/hyp/debug-sr.c b/arch/arm64/kvm/hyp/debug-sr.c index 0fc9872a1467..98be2f11c16c 100644 --- a/arch/arm64/kvm/hyp/debug-sr.c +++ b/arch/arm64/kvm/hyp/debug-sr.c @@ -108,8 +108,8 @@ static void __hyp_text __debug_save_spe_nvhe(u64 *pmscr_el1) return; /* Yes; save the control register and disable data generation */ - *pmscr_el1 = read_sysreg_s(SYS_PMSCR_EL1); - write_sysreg_s(0, SYS_PMSCR_EL1); + *pmscr_el1 = read_sysreg_el1(SYS_PMSCR); + write_sysreg_el1(0, SYS_PMSCR); isb(); /* Now drain all buffered data to memory */ @@ -126,7 +126,7 @@ static void __hyp_text __debug_restore_spe_nvhe(u64 pmscr_el1) isb(); /* Re-enable data generation */ - write_sysreg_s(pmscr_el1, SYS_PMSCR_EL1); + write_sysreg_el1(pmscr_el1, SYS_PMSCR); } static void __hyp_text __debug_save_state(struct kvm_vcpu *vcpu, From patchwork Fri Dec 20 14:30:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 182285 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp609134ilf; Fri, 20 Dec 2019 06:33:20 -0800 (PST) X-Google-Smtp-Source: APXvYqwU3/v9g/tFLYseZmuuJbjAXZuncY9vjNT7tIw1Q42j1+UempOdnFMrVi1dNYihlBeoU3AH X-Received: by 2002:aca:3141:: with SMTP id x62mr3601227oix.108.1576852399941; Fri, 20 Dec 2019 06:33:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576852399; cv=none; d=google.com; s=arc-20160816; b=jJDl58fx3EQKPePnl7xH1sZzOzA4ltBeO9JWgsu6F39ycnDSn8QFZd+AdMryQ/PMXX gUVsr9+2uXol6b40tmgfHdynnDG5WpkmJ7IIu/DbVGj9xWZNmS9MpbIMx6SbvlujClBX FOTsaSokF/1S00sVaw8zH5f1/IdH/fBFRE8GbK3LxOSQSxMWUjowDTtoCKTPx0i+7H2B 3n8IdJl1VhihQ2gItORLO0P/v7kkD5+/6OgNBm0yix8+HR6b/WPUIHElb9z3y51OOVpN hqMoGxVdBJzi9/9IaF+XOFtrJ+6/zade7+FzDvVhDfHEXvKbNgEtfCVYmuucoEV1DsV2 f3yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=CDNsz6Hrxz7XQGEprMoxl9HVZOcneojc3HzKPigK2eY=; b=N5+/ArCnrJhutJQbg6UuPjJCLbq0+zy4Wq6fFHw23u2ErwQvgmW5xWv3Bi/bQIuLUd WAYHTNnb4DbYDl7Q4GlEpBE/Vy6RtMdJ5XhWW2HibnwPVrtiV9DoTI+qGw++N92y8t8m 2nU9mW3Wr1Xl7FWD6SuGn8OISUAQZBBwc0HDmFkO41QEGXxtkplxkLdLkLgkgwhpGKMF qYw2q/wamZeUX2KSqzKBiycrfNSp1njFqrRLE2iRPjZ6GD3Og9HVgWsspCnf7CyirgO9 Wklr2sZLNFL9RkCIBOyS57bkU2rYhmnexw8HCtiboRqa5sSty5gTx5ot73No1ztFypl9 qGsQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w64si4972237oib.185.2019.12.20.06.33.14; Fri, 20 Dec 2019 06:33:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728001AbfLTObD (ORCPT + 27 others); Fri, 20 Dec 2019 09:31:03 -0500 Received: from foss.arm.com ([217.140.110.172]:51232 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727864AbfLTOaq (ORCPT ); Fri, 20 Dec 2019 09:30:46 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8CFB930E; Fri, 20 Dec 2019 06:30:45 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8C12B3F718; Fri, 20 Dec 2019 06:30:43 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 06/18] arm64: KVM: split debug save restore across vm/traps activation Date: Fri, 20 Dec 2019 14:30:13 +0000 Message-Id: <20191220143025.33853-7-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sudeep Holla If we enable profiling buffer controls at EL1 generate a trap exception to EL2, it also changes profiling buffer to use EL1&0 stage 1 translation regime in case of VHE. To support SPE both in the guest and host, we need to first stop profiling and flush the profiling buffers before we activate/switch vm or enable/disable the traps. In prepartion to do that, lets split the debug save restore functionality into 4 steps: 1. debug_save_host_context - saves the host context 2. debug_restore_guest_context - restore the guest context 3. debug_save_guest_context - saves the guest context 4. debug_restore_host_context - restores the host context Lets rename existing __debug_switch_to_{host,guest} to make sure it's aligned to the above and just add the place holders for new ones getting added here as we need them to support SPE in guests. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- arch/arm64/include/asm/kvm_hyp.h | 6 ++++-- arch/arm64/kvm/hyp/debug-sr.c | 25 ++++++++++++++++--------- arch/arm64/kvm/hyp/switch.c | 12 ++++++++---- 3 files changed, 28 insertions(+), 15 deletions(-) -- 2.21.0 diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h index 97f21cc66657..011e7963f772 100644 --- a/arch/arm64/include/asm/kvm_hyp.h +++ b/arch/arm64/include/asm/kvm_hyp.h @@ -69,8 +69,10 @@ void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt); void __sysreg32_save_state(struct kvm_vcpu *vcpu); void __sysreg32_restore_state(struct kvm_vcpu *vcpu); -void __debug_switch_to_guest(struct kvm_vcpu *vcpu); -void __debug_switch_to_host(struct kvm_vcpu *vcpu); +void __debug_save_host_context(struct kvm_vcpu *vcpu); +void __debug_restore_guest_context(struct kvm_vcpu *vcpu); +void __debug_save_guest_context(struct kvm_vcpu *vcpu); +void __debug_restore_host_context(struct kvm_vcpu *vcpu); void __fpsimd_save_state(struct user_fpsimd_state *fp_regs); void __fpsimd_restore_state(struct user_fpsimd_state *fp_regs); diff --git a/arch/arm64/kvm/hyp/debug-sr.c b/arch/arm64/kvm/hyp/debug-sr.c index 98be2f11c16c..c803daebd596 100644 --- a/arch/arm64/kvm/hyp/debug-sr.c +++ b/arch/arm64/kvm/hyp/debug-sr.c @@ -168,20 +168,13 @@ static void __hyp_text __debug_restore_state(struct kvm_vcpu *vcpu, write_sysreg(ctxt->sys_regs[MDCCINT_EL1], mdccint_el1); } -void __hyp_text __debug_switch_to_guest(struct kvm_vcpu *vcpu) +void __hyp_text __debug_restore_guest_context(struct kvm_vcpu *vcpu) { struct kvm_cpu_context *host_ctxt; struct kvm_cpu_context *guest_ctxt; struct kvm_guest_debug_arch *host_dbg; struct kvm_guest_debug_arch *guest_dbg; - /* - * Non-VHE: Disable and flush SPE data generation - * VHE: The vcpu can run, but it can't hide. - */ - if (!has_vhe()) - __debug_save_spe_nvhe(&vcpu->arch.host_debug_state.pmscr_el1); - if (!(vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)) return; @@ -194,7 +187,7 @@ void __hyp_text __debug_switch_to_guest(struct kvm_vcpu *vcpu) __debug_restore_state(vcpu, guest_dbg, guest_ctxt); } -void __hyp_text __debug_switch_to_host(struct kvm_vcpu *vcpu) +void __hyp_text __debug_restore_host_context(struct kvm_vcpu *vcpu) { struct kvm_cpu_context *host_ctxt; struct kvm_cpu_context *guest_ctxt; @@ -218,6 +211,20 @@ void __hyp_text __debug_switch_to_host(struct kvm_vcpu *vcpu) vcpu->arch.flags &= ~KVM_ARM64_DEBUG_DIRTY; } +void __hyp_text __debug_save_host_context(struct kvm_vcpu *vcpu) +{ + /* + * Non-VHE: Disable and flush SPE data generation + * VHE: The vcpu can run, but it can't hide. + */ + if (!has_vhe()) + __debug_save_spe_nvhe(&vcpu->arch.host_debug_state.pmscr_el1); +} + +void __hyp_text __debug_save_guest_context(struct kvm_vcpu *vcpu) +{ +} + u32 __hyp_text __kvm_get_mdcr_el2(void) { return read_sysreg(mdcr_el2); diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 250f13910882..67b7c160f65b 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -626,6 +626,7 @@ int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) guest_ctxt = &vcpu->arch.ctxt; sysreg_save_host_state_vhe(host_ctxt); + __debug_save_host_context(vcpu); /* * ARM erratum 1165522 requires us to configure both stage 1 and @@ -642,7 +643,7 @@ int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) __activate_traps(vcpu); sysreg_restore_guest_state_vhe(guest_ctxt); - __debug_switch_to_guest(vcpu); + __debug_restore_guest_context(vcpu); __set_guest_arch_workaround_state(vcpu); @@ -656,6 +657,7 @@ int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) __set_host_arch_workaround_state(vcpu); sysreg_save_guest_state_vhe(guest_ctxt); + __debug_save_guest_context(vcpu); __deactivate_traps(vcpu); @@ -664,7 +666,7 @@ int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) __fpsimd_save_fpexc32(vcpu); - __debug_switch_to_host(vcpu); + __debug_restore_host_context(vcpu); return exit_code; } @@ -698,6 +700,7 @@ int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu) pmu_switch_needed = __pmu_switch_to_guest(host_ctxt); __sysreg_save_state_nvhe(host_ctxt); + __debug_save_host_context(vcpu); /* * We must restore the 32-bit state before the sysregs, thanks @@ -716,7 +719,7 @@ int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu) __hyp_vgic_restore_state(vcpu); __timer_enable_traps(vcpu); - __debug_switch_to_guest(vcpu); + __debug_restore_guest_context(vcpu); __set_guest_arch_workaround_state(vcpu); @@ -730,6 +733,7 @@ int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu) __set_host_arch_workaround_state(vcpu); __sysreg_save_state_nvhe(guest_ctxt); + __debug_save_guest_context(vcpu); __sysreg32_save_state(vcpu); __timer_disable_traps(vcpu); __hyp_vgic_save_state(vcpu); @@ -746,7 +750,7 @@ int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu) * This must come after restoring the host sysregs, since a non-VHE * system may enable SPE here and make use of the TTBRs. */ - __debug_switch_to_host(vcpu); + __debug_restore_host_context(vcpu); if (pmu_switch_needed) __pmu_switch_to_host(host_ctxt); From patchwork Fri Dec 20 14:30:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 182294 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp613266ilf; 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[209.132.180.67]) by mx.google.com with ESMTP id w64si4972237oib.185.2019.12.20.06.34.51; Fri, 20 Dec 2019 06:34:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728244AbfLTOdC (ORCPT + 27 others); Fri, 20 Dec 2019 09:33:02 -0500 Received: from foss.arm.com ([217.140.110.172]:51246 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727875AbfLTOas (ORCPT ); Fri, 20 Dec 2019 09:30:48 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B549531B; Fri, 20 Dec 2019 06:30:47 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DCF893F718; Fri, 20 Dec 2019 06:30:45 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 07/18] arm64: KVM/debug: drop pmscr_el1 and use sys_regs[PMSCR_EL1] in kvm_cpu_context Date: Fri, 20 Dec 2019 14:30:14 +0000 Message-Id: <20191220143025.33853-8-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sudeep Holla kvm_cpu_context now has support to stash the complete SPE buffer control context. We no longer need the pmscr_el1 kvm_vcpu_arch and it can be dropped. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- arch/arm64/include/asm/kvm_host.h | 2 -- arch/arm64/kvm/hyp/debug-sr.c | 26 +++++++++++++++----------- 2 files changed, 15 insertions(+), 13 deletions(-) -- 2.21.0 diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 9eb85f14df90..333c6491bec7 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -307,8 +307,6 @@ struct kvm_vcpu_arch { struct { /* {Break,watch}point registers */ struct kvm_guest_debug_arch regs; - /* Statistical profiling extension */ - u64 pmscr_el1; } host_debug_state; /* VGIC state */ diff --git a/arch/arm64/kvm/hyp/debug-sr.c b/arch/arm64/kvm/hyp/debug-sr.c index c803daebd596..8a70a493345e 100644 --- a/arch/arm64/kvm/hyp/debug-sr.c +++ b/arch/arm64/kvm/hyp/debug-sr.c @@ -85,19 +85,19 @@ default: write_debug(ptr[0], reg, 0); \ } -static void __hyp_text __debug_save_spe_nvhe(u64 *pmscr_el1) +static void __hyp_text __debug_save_spe_nvhe(struct kvm_cpu_context *ctxt) { u64 reg; /* Clear pmscr in case of early return */ - *pmscr_el1 = 0; + ctxt->sys_regs[PMSCR_EL1] = 0; /* SPE present on this CPU? */ if (!cpuid_feature_extract_unsigned_field(read_sysreg(id_aa64dfr0_el1), ID_AA64DFR0_PMSVER_SHIFT)) return; - /* Yes; is it owned by EL3? */ + /* Yes; is it owned by higher EL? */ reg = read_sysreg_s(SYS_PMBIDR_EL1); if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) return; @@ -108,7 +108,7 @@ static void __hyp_text __debug_save_spe_nvhe(u64 *pmscr_el1) return; /* Yes; save the control register and disable data generation */ - *pmscr_el1 = read_sysreg_el1(SYS_PMSCR); + ctxt->sys_regs[PMSCR_EL1] = read_sysreg_el1(SYS_PMSCR); write_sysreg_el1(0, SYS_PMSCR); isb(); @@ -117,16 +117,16 @@ static void __hyp_text __debug_save_spe_nvhe(u64 *pmscr_el1) dsb(nsh); } -static void __hyp_text __debug_restore_spe_nvhe(u64 pmscr_el1) +static void __hyp_text __debug_restore_spe_nvhe(struct kvm_cpu_context *ctxt) { - if (!pmscr_el1) + if (!ctxt->sys_regs[PMSCR_EL1]) return; /* The host page table is installed, but not yet synchronised */ isb(); /* Re-enable data generation */ - write_sysreg_el1(pmscr_el1, SYS_PMSCR); + write_sysreg_el1(ctxt->sys_regs[PMSCR_EL1], SYS_PMSCR); } static void __hyp_text __debug_save_state(struct kvm_vcpu *vcpu, @@ -194,14 +194,15 @@ void __hyp_text __debug_restore_host_context(struct kvm_vcpu *vcpu) struct kvm_guest_debug_arch *host_dbg; struct kvm_guest_debug_arch *guest_dbg; + host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); + guest_ctxt = &vcpu->arch.ctxt; + if (!has_vhe()) - __debug_restore_spe_nvhe(vcpu->arch.host_debug_state.pmscr_el1); + __debug_restore_spe_nvhe(host_ctxt); if (!(vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)) return; - host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); - guest_ctxt = &vcpu->arch.ctxt; host_dbg = &vcpu->arch.host_debug_state.regs; guest_dbg = kern_hyp_va(vcpu->arch.debug_ptr); @@ -217,8 +218,11 @@ void __hyp_text __debug_save_host_context(struct kvm_vcpu *vcpu) * Non-VHE: Disable and flush SPE data generation * VHE: The vcpu can run, but it can't hide. */ + struct kvm_cpu_context *host_ctxt; + + host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); if (!has_vhe()) - __debug_save_spe_nvhe(&vcpu->arch.host_debug_state.pmscr_el1); + __debug_save_spe_nvhe(host_ctxt); } void __hyp_text __debug_save_guest_context(struct kvm_vcpu *vcpu) From patchwork Fri Dec 20 14:30:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 182289 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp610729ilf; Fri, 20 Dec 2019 06:34:33 -0800 (PST) X-Google-Smtp-Source: APXvYqy5gacfIutFn0qN4hD2nkuRGKNEDiUGSFVkhBcRiOgckTdDyRCZJGCZC4Dw+bsJYHpSXtnY X-Received: by 2002:a05:6808:197:: with SMTP id w23mr4080525oic.46.1576852473652; Fri, 20 Dec 2019 06:34:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576852473; cv=none; d=google.com; s=arc-20160816; b=bbKo9YJw03X2Z4sqmBOOHGqqjFpWj+fj6+q89FvRs9cqVSq51dWHXqsUM95fQfbFod K1/4AkuI/cZxBahb517T0fvQjt4+hmSpdIQDccrak7SRtDh3hWGPrclAP3KGuswyxZkk wK+icnGSWP3Ei1leh6wFFcNQkLMcjZuRIyxUPyTKOZwZaBHYtMpADMSJW+7dZpjv9K4C IFSyFEtDp/m7w2YIHQG1LIKnlW7KkKVSz/dp63dpU2aFK/qd1zWAX/s16jPqzMVBrFpB RzM3TKhlTPvaif9daOfdpWyKEfm9uDRd5Z56wyC9J4PMfwvOcz9roHaFpAZ7UzUq/Lqf 0Plg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=v4/tCrisS5WWhYOScfAjThyrG4vqdSgmcgDonb3Pah4=; b=S+4+yDgqYixO+0DBBDKkSbnXpfNeSczTdDCDMhtOvYj2piOuSEhEzYPua1moFUzv8l rzRA6BuU2WzCPzV+88Mc54KPxq9KuYu+NnGVRjqWsYVKcQxNx5ircDXADQgKSot4DFcV DVmcJjFTfjdjj0Gpq+iUE0RPO1QTsv7yJYmIEX13HF+thUfmxRpMlT7QbvVDsGqw3iBB IKiWl10uarANVpqA9yTSnxZbDduV3zQoV5dbVX8Cb1iaWGoiQNB43lb3hUGIiJjreeyW mQedwV6TLqLtB4Nwrnae5ZPj8gCPs07QTYqrbRDxBM5zI290uukvBcBcM4+kMc80kZxs hBJQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w64si4972237oib.185.2019.12.20.06.34.09; Fri, 20 Dec 2019 06:34:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728033AbfLTObG (ORCPT + 27 others); Fri, 20 Dec 2019 09:31:06 -0500 Received: from foss.arm.com ([217.140.110.172]:51258 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727806AbfLTOau (ORCPT ); Fri, 20 Dec 2019 09:30:50 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DDD54106F; Fri, 20 Dec 2019 06:30:49 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 113893F718; Fri, 20 Dec 2019 06:30:47 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 08/18] arm64: KVM: add support to save/restore SPE profiling buffer controls Date: Fri, 20 Dec 2019 14:30:15 +0000 Message-Id: <20191220143025.33853-9-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sudeep Holla Currently since we don't support profiling using SPE in the guests, we just save the PMSCR_EL1, flush the profiling buffers and disable sampling. However in order to support simultaneous sampling both in the host and guests, we need to save and reatore the complete SPE profiling buffer controls' context. Let's add the support for the same and keep it disabled for now. We can enable it conditionally only if guests are allowed to use SPE. Signed-off-by: Sudeep Holla [ Clear PMBSR bit when saving state to prevent spurious interrupts ] Signed-off-by: Andrew Murray --- arch/arm64/kvm/hyp/debug-sr.c | 51 +++++++++++++++++++++++++++++------ 1 file changed, 43 insertions(+), 8 deletions(-) -- 2.21.0 diff --git a/arch/arm64/kvm/hyp/debug-sr.c b/arch/arm64/kvm/hyp/debug-sr.c index 8a70a493345e..12429b212a3a 100644 --- a/arch/arm64/kvm/hyp/debug-sr.c +++ b/arch/arm64/kvm/hyp/debug-sr.c @@ -85,7 +85,8 @@ default: write_debug(ptr[0], reg, 0); \ } -static void __hyp_text __debug_save_spe_nvhe(struct kvm_cpu_context *ctxt) +static void __hyp_text +__debug_save_spe_nvhe(struct kvm_cpu_context *ctxt, bool full_ctxt) { u64 reg; @@ -102,22 +103,46 @@ static void __hyp_text __debug_save_spe_nvhe(struct kvm_cpu_context *ctxt) if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) return; - /* No; is the host actually using the thing? */ - reg = read_sysreg_s(SYS_PMBLIMITR_EL1); - if (!(reg & BIT(SYS_PMBLIMITR_EL1_E_SHIFT))) + /* Save the control register and disable data generation */ + ctxt->sys_regs[PMSCR_EL1] = read_sysreg_el1(SYS_PMSCR); + + if (!ctxt->sys_regs[PMSCR_EL1]) return; /* Yes; save the control register and disable data generation */ - ctxt->sys_regs[PMSCR_EL1] = read_sysreg_el1(SYS_PMSCR); write_sysreg_el1(0, SYS_PMSCR); isb(); /* Now drain all buffered data to memory */ psb_csync(); dsb(nsh); + + if (!full_ctxt) + return; + + ctxt->sys_regs[PMBLIMITR_EL1] = read_sysreg_s(SYS_PMBLIMITR_EL1); + write_sysreg_s(0, SYS_PMBLIMITR_EL1); + + /* + * As PMBSR is conditionally restored when returning to the host we + * must ensure the service bit is unset here to prevent a spurious + * host SPE interrupt from being raised. + */ + ctxt->sys_regs[PMBSR_EL1] = read_sysreg_s(SYS_PMBSR_EL1); + write_sysreg_s(0, SYS_PMBSR_EL1); + + isb(); + + ctxt->sys_regs[PMSICR_EL1] = read_sysreg_s(SYS_PMSICR_EL1); + ctxt->sys_regs[PMSIRR_EL1] = read_sysreg_s(SYS_PMSIRR_EL1); + ctxt->sys_regs[PMSFCR_EL1] = read_sysreg_s(SYS_PMSFCR_EL1); + ctxt->sys_regs[PMSEVFR_EL1] = read_sysreg_s(SYS_PMSEVFR_EL1); + ctxt->sys_regs[PMSLATFR_EL1] = read_sysreg_s(SYS_PMSLATFR_EL1); + ctxt->sys_regs[PMBPTR_EL1] = read_sysreg_s(SYS_PMBPTR_EL1); } -static void __hyp_text __debug_restore_spe_nvhe(struct kvm_cpu_context *ctxt) +static void __hyp_text +__debug_restore_spe_nvhe(struct kvm_cpu_context *ctxt, bool full_ctxt) { if (!ctxt->sys_regs[PMSCR_EL1]) return; @@ -126,6 +151,16 @@ static void __hyp_text __debug_restore_spe_nvhe(struct kvm_cpu_context *ctxt) isb(); /* Re-enable data generation */ + if (full_ctxt) { + write_sysreg_s(ctxt->sys_regs[PMBPTR_EL1], SYS_PMBPTR_EL1); + write_sysreg_s(ctxt->sys_regs[PMBLIMITR_EL1], SYS_PMBLIMITR_EL1); + write_sysreg_s(ctxt->sys_regs[PMSFCR_EL1], SYS_PMSFCR_EL1); + write_sysreg_s(ctxt->sys_regs[PMSEVFR_EL1], SYS_PMSEVFR_EL1); + write_sysreg_s(ctxt->sys_regs[PMSLATFR_EL1], SYS_PMSLATFR_EL1); + write_sysreg_s(ctxt->sys_regs[PMSIRR_EL1], SYS_PMSIRR_EL1); + write_sysreg_s(ctxt->sys_regs[PMSICR_EL1], SYS_PMSICR_EL1); + write_sysreg_s(ctxt->sys_regs[PMBSR_EL1], SYS_PMBSR_EL1); + } write_sysreg_el1(ctxt->sys_regs[PMSCR_EL1], SYS_PMSCR); } @@ -198,7 +233,7 @@ void __hyp_text __debug_restore_host_context(struct kvm_vcpu *vcpu) guest_ctxt = &vcpu->arch.ctxt; if (!has_vhe()) - __debug_restore_spe_nvhe(host_ctxt); + __debug_restore_spe_nvhe(host_ctxt, false); if (!(vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)) return; @@ -222,7 +257,7 @@ void __hyp_text __debug_save_host_context(struct kvm_vcpu *vcpu) host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); if (!has_vhe()) - __debug_save_spe_nvhe(host_ctxt); + __debug_save_spe_nvhe(host_ctxt, false); } void __hyp_text __debug_save_guest_context(struct kvm_vcpu *vcpu) From patchwork Fri Dec 20 14:30:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 182291 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp611089ilf; Fri, 20 Dec 2019 06:34:47 -0800 (PST) X-Google-Smtp-Source: APXvYqxmforJvubd4xBsVSTUfRGbAe7F4XJdnAiOLrwnpmUs0nmRGGvIWmhuRZgU0gVk9GO2KGqj X-Received: by 2002:a9d:3425:: with SMTP id v34mr14634573otb.142.1576852486874; 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mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w64si4972237oib.185.2019.12.20.06.34.46; Fri, 20 Dec 2019 06:34:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728218AbfLTOck (ORCPT + 27 others); Fri, 20 Dec 2019 09:32:40 -0500 Received: from foss.arm.com ([217.140.110.172]:51268 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727926AbfLTOaw (ORCPT ); Fri, 20 Dec 2019 09:30:52 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 11DCF30E; Fri, 20 Dec 2019 06:30:52 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 39ABD3F718; Fri, 20 Dec 2019 06:30:50 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 09/18] arm64: KVM: enable conditional save/restore full SPE profiling buffer controls Date: Fri, 20 Dec 2019 14:30:16 +0000 Message-Id: <20191220143025.33853-10-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sudeep Holla Now that we can save/restore the full SPE controls, we can enable it if SPE is setup and ready to use in KVM. It's supported in KVM only if all the CPUs in the system supports SPE. However to support heterogenous systems, we need to move the check if host supports SPE and do a partial save/restore. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- arch/arm64/kvm/hyp/debug-sr.c | 33 ++++++++++++++++----------------- include/kvm/arm_spe.h | 6 ++++++ 2 files changed, 22 insertions(+), 17 deletions(-) -- 2.21.0 diff --git a/arch/arm64/kvm/hyp/debug-sr.c b/arch/arm64/kvm/hyp/debug-sr.c index 12429b212a3a..d8d857067e6d 100644 --- a/arch/arm64/kvm/hyp/debug-sr.c +++ b/arch/arm64/kvm/hyp/debug-sr.c @@ -86,18 +86,13 @@ } static void __hyp_text -__debug_save_spe_nvhe(struct kvm_cpu_context *ctxt, bool full_ctxt) +__debug_save_spe_context(struct kvm_cpu_context *ctxt, bool full_ctxt) { u64 reg; /* Clear pmscr in case of early return */ ctxt->sys_regs[PMSCR_EL1] = 0; - /* SPE present on this CPU? */ - if (!cpuid_feature_extract_unsigned_field(read_sysreg(id_aa64dfr0_el1), - ID_AA64DFR0_PMSVER_SHIFT)) - return; - /* Yes; is it owned by higher EL? */ reg = read_sysreg_s(SYS_PMBIDR_EL1); if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) @@ -142,7 +137,7 @@ __debug_save_spe_nvhe(struct kvm_cpu_context *ctxt, bool full_ctxt) } static void __hyp_text -__debug_restore_spe_nvhe(struct kvm_cpu_context *ctxt, bool full_ctxt) +__debug_restore_spe_context(struct kvm_cpu_context *ctxt, bool full_ctxt) { if (!ctxt->sys_regs[PMSCR_EL1]) return; @@ -210,11 +205,14 @@ void __hyp_text __debug_restore_guest_context(struct kvm_vcpu *vcpu) struct kvm_guest_debug_arch *host_dbg; struct kvm_guest_debug_arch *guest_dbg; + host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); + guest_ctxt = &vcpu->arch.ctxt; + + __debug_restore_spe_context(guest_ctxt, kvm_arm_spe_v1_ready(vcpu)); + if (!(vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)) return; - host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); - guest_ctxt = &vcpu->arch.ctxt; host_dbg = &vcpu->arch.host_debug_state.regs; guest_dbg = kern_hyp_va(vcpu->arch.debug_ptr); @@ -232,8 +230,7 @@ void __hyp_text __debug_restore_host_context(struct kvm_vcpu *vcpu) host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); guest_ctxt = &vcpu->arch.ctxt; - if (!has_vhe()) - __debug_restore_spe_nvhe(host_ctxt, false); + __debug_restore_spe_context(host_ctxt, kvm_arm_spe_v1_ready(vcpu)); if (!(vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)) return; @@ -249,19 +246,21 @@ void __hyp_text __debug_restore_host_context(struct kvm_vcpu *vcpu) void __hyp_text __debug_save_host_context(struct kvm_vcpu *vcpu) { - /* - * Non-VHE: Disable and flush SPE data generation - * VHE: The vcpu can run, but it can't hide. - */ struct kvm_cpu_context *host_ctxt; host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); - if (!has_vhe()) - __debug_save_spe_nvhe(host_ctxt, false); + if (cpuid_feature_extract_unsigned_field(read_sysreg(id_aa64dfr0_el1), + ID_AA64DFR0_PMSVER_SHIFT)) + __debug_save_spe_context(host_ctxt, kvm_arm_spe_v1_ready(vcpu)); } void __hyp_text __debug_save_guest_context(struct kvm_vcpu *vcpu) { + bool kvm_spe_ready = kvm_arm_spe_v1_ready(vcpu); + + /* SPE present on this vCPU? */ + if (kvm_spe_ready) + __debug_save_spe_context(&vcpu->arch.ctxt, kvm_spe_ready); } u32 __hyp_text __kvm_get_mdcr_el2(void) diff --git a/include/kvm/arm_spe.h b/include/kvm/arm_spe.h index 48d118fdb174..30c40b1bc385 100644 --- a/include/kvm/arm_spe.h +++ b/include/kvm/arm_spe.h @@ -16,4 +16,10 @@ struct kvm_spe { bool irq_level; }; +#ifdef CONFIG_KVM_ARM_SPE +#define kvm_arm_spe_v1_ready(v) ((v)->arch.spe.ready) +#else +#define kvm_arm_spe_v1_ready(v) (false) +#endif /* CONFIG_KVM_ARM_SPE */ + #endif /* __ASM_ARM_KVM_SPE_H */ From patchwork Fri Dec 20 14:30:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 182290 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp611046ilf; Fri, 20 Dec 2019 06:34:45 -0800 (PST) X-Google-Smtp-Source: APXvYqxUYWcdO0wcFRdaxOeWkDzu3fBbs0F5+Fi62dhk9qiyrobxOIs7LX+v9BRxtAFbRh3VcnKt X-Received: by 2002:aca:ec4f:: with SMTP id k76mr1632567oih.156.1576852485255; Fri, 20 Dec 2019 06:34:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576852485; cv=none; d=google.com; s=arc-20160816; b=JI3hjmLTI04tVKYvFhJHxOPwPu92aiQz47PWxLlEpxZMuY+XSLs+vzw45hOSZYOHV3 QCjCc8bzf3eO7e2t9/u9KnZujWyxTwEXHqKV5Ja6NliXoPJycdq1TtqmeAx92A3okVSe KOlLSgTvhTZx1mWRIfndAAq1cDUM5fNwEI+UBKvFKSW4O8V0VlwDxy3R8DQ0Tti/+9Az 2SA0h2u20nCiS65hJ5tx1/F6H4g7Uiw8/HT8h7M46W3WrtgwdxaNTRTKJWR7QL2JHQOq 05IbFNFc7ymdH3iZ4FoNtj9V5SmfYdYIfalZ4LMuTzxJIr1Q9jcHgJvFDQsngrjJyveC LzWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=tyXcipWvSgJKvjvVdDvo593Z3XPmHSDMoXkO3Ii76Qg=; b=gxWkOUdchMkAwG875IAfqyiQuNr5/xC/6m7Ma0Orhpm2SQE5UHBf7z9BTo2CpJNZXS 4lVsgsfvhX13o9zs0xCdLp+dk0Sw4j75qPFZOXOdVUAEeJrPsd3MLb2OK7gopv0pkRiE 2F1HQqEXLKGQP79Z81Z1fGA04T6l/KhRh4opxNy2DYKrHp5QbnttY49SMLUaLMQIBURK 2XZWTKprfUNV0gWnO3VF+X9yPr9guQus+57QHYufV/aHqVwpIEBQi7azhdFhLjUxMnt0 JDnaKNOgT4v5L2xNGX75czp2DS9CQZpsOvCFuQgi9T80lfwHc7aY4cDnKDEg1Z/L2RUC yelg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w64si4972237oib.185.2019.12.20.06.34.45; Fri, 20 Dec 2019 06:34:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728193AbfLTOca (ORCPT + 27 others); Fri, 20 Dec 2019 09:32:30 -0500 Received: from foss.arm.com ([217.140.110.172]:51282 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727946AbfLTOay (ORCPT ); Fri, 20 Dec 2019 09:30:54 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3A33711D4; Fri, 20 Dec 2019 06:30:54 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 61B7D3F718; Fri, 20 Dec 2019 06:30:52 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 10/18] arm64: KVM/debug: use EL1&0 stage 1 translation regime Date: Fri, 20 Dec 2019 14:30:17 +0000 Message-Id: <20191220143025.33853-11-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sudeep Holla Now that we have all the save/restore mechanism in place, lets enable the translation regime used by buffer from EL2 stage 1 to EL1 stage 1 on VHE systems. Signed-off-by: Sudeep Holla [ Reword commit, don't trap to EL2 ] Signed-off-by: Andrew Murray --- arch/arm64/kvm/hyp/switch.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.21.0 diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 67b7c160f65b..6c153b79829b 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -100,6 +100,7 @@ static void activate_traps_vhe(struct kvm_vcpu *vcpu) write_sysreg(val, cpacr_el1); + write_sysreg(vcpu->arch.mdcr_el2 | 3 << MDCR_EL2_E2PB_SHIFT, mdcr_el2); write_sysreg(kvm_get_hyp_vector(), vbar_el1); } NOKPROBE_SYMBOL(activate_traps_vhe); @@ -117,6 +118,7 @@ static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu) __activate_traps_fpsimd32(vcpu); } + write_sysreg(vcpu->arch.mdcr_el2 | 3 << MDCR_EL2_E2PB_SHIFT, mdcr_el2); write_sysreg(val, cptr_el2); if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) { From patchwork Fri Dec 20 14:30:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 182286 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp609529ilf; Fri, 20 Dec 2019 06:33:39 -0800 (PST) X-Google-Smtp-Source: APXvYqyFE3eg2v00batIZtElRaCP2/TSdfrjrsV+ox7rRBFqJ85nTQd4zX1yQ9eX3D10oUxiaumG X-Received: by 2002:aca:4d0f:: with SMTP id a15mr4057471oib.21.1576852419761; Fri, 20 Dec 2019 06:33:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576852419; cv=none; d=google.com; s=arc-20160816; b=NujwozPdT787vGSLvi4YnzB0A+8nUkyBLj6sEysLArppSyQsGoFGj0ZlZSzvEK1ua7 hKURAg//F3Ta2y9/VOqOtNXs+JVvURxpEnQ8+4wVIyYBWggo3f2VhQzddxuoBL5RtTZV GU2ik+EfacJYmiYnxmbxasbXWHc/vK5+BAvWMlVx239ZJTOd/Mbi4aBFsinjQeNOHneJ v0Z/+M9oGoIXBMxaxXdTfmR2pKJtvja0yxn0CiGA7IBJFj5IYDVKXYcgc0rCqnTbKVt2 1bFZmp8fVsCYPbCN/RHTP5Oei2/cDMk0pyxW1LYnPoUBgQUdhWXepKMDOHbHUtv+mdHd XKiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=TUFdVVMlk5PSpeJIkDG6TzZSRPJV6Uf1ku9nTGLCdCo=; b=ApJJQxJB7ULagu47vVEXamdIkaPUSsPWwdur1b/Nc4F459PpBvPQ8QPzH/2H9tx5+y FxTsI+kJYTQSif+o0cltokys5KqLOFWksQ3MVSfeje90jtuH9lmeYQHIUpwLoyRf337l y5UMYvP+UOquIl8fe/5g5YmwfvjavAL9/ahT/UKLMWnUR7AteA4RM8e/cQEerRGfLP+c OBhW013CvkinTH9F71o2BgjxqQ8mR5vzEBYtlYVtAoaCpWpsjeax8d/8BPGkDqaZ9lrF shCeYF12CHnDvHUXTNbitqMvHy7+iDaonPE0OJj8IRKjlUQW8lh2cGu7wnThaE9QiJv9 tGYg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w64si4972237oib.185.2019.12.20.06.33.34; Fri, 20 Dec 2019 06:33:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728083AbfLTObN (ORCPT + 27 others); Fri, 20 Dec 2019 09:31:13 -0500 Received: from foss.arm.com ([217.140.110.172]:51302 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727849AbfLTOa7 (ORCPT ); Fri, 20 Dec 2019 09:30:59 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B3B7711FB; Fri, 20 Dec 2019 06:30:58 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B2CE23F718; Fri, 20 Dec 2019 06:30:56 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 12/18] KVM: arm64: add a new vcpu device control group for SPEv1 Date: Fri, 20 Dec 2019 14:30:19 +0000 Message-Id: <20191220143025.33853-13-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sudeep Holla To configure the virtual SPEv1 overflow interrupt number, we use the vcpu kvm_device ioctl, encapsulating the KVM_ARM_VCPU_SPE_V1_IRQ attribute within the KVM_ARM_VCPU_SPE_V1_CTRL group. After configuring the SPEv1, call the vcpu ioctl with attribute KVM_ARM_VCPU_SPE_V1_INIT to initialize the SPEv1. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- Documentation/virt/kvm/devices/vcpu.txt | 28 ++++ arch/arm64/include/asm/kvm_host.h | 2 +- arch/arm64/include/uapi/asm/kvm.h | 4 + arch/arm64/kvm/Makefile | 1 + arch/arm64/kvm/guest.c | 6 + arch/arm64/kvm/reset.c | 3 + include/kvm/arm_spe.h | 45 +++++++ include/uapi/linux/kvm.h | 1 + virt/kvm/arm/arm.c | 1 + virt/kvm/arm/spe.c | 163 ++++++++++++++++++++++++ 10 files changed, 253 insertions(+), 1 deletion(-) create mode 100644 virt/kvm/arm/spe.c -- 2.21.0 diff --git a/Documentation/virt/kvm/devices/vcpu.txt b/Documentation/virt/kvm/devices/vcpu.txt index 6f3bd64a05b0..cefad056d677 100644 --- a/Documentation/virt/kvm/devices/vcpu.txt +++ b/Documentation/virt/kvm/devices/vcpu.txt @@ -74,3 +74,31 @@ Specifies the base address of the stolen time structure for this VCPU. The base address must be 64 byte aligned and exist within a valid guest memory region. See Documentation/virt/kvm/arm/pvtime.txt for more information including the layout of the stolen time structure. + +4. GROUP: KVM_ARM_VCPU_SPE_V1_CTRL +Architectures: ARM64 + +4.1. ATTRIBUTE: KVM_ARM_VCPU_SPE_V1_IRQ +Parameters: in kvm_device_attr.addr the address for SPE buffer overflow interrupt + is a pointer to an int +Returns: -EBUSY: The SPE overflow interrupt is already set + -ENXIO: The overflow interrupt not set when attempting to get it + -ENODEV: SPEv1 not supported + -EINVAL: Invalid SPE overflow interrupt number supplied or + trying to set the IRQ number without using an in-kernel + irqchip. + +A value describing the SPEv1 (Statistical Profiling Extension v1) overflow +interrupt number for this vcpu. This interrupt should be PPI and the interrupt +type and number must be same for each vcpu. + +4.2 ATTRIBUTE: KVM_ARM_VCPU_SPE_V1_INIT +Parameters: no additional parameter in kvm_device_attr.addr +Returns: -ENODEV: SPEv1 not supported or GIC not initialized + -ENXIO: SPEv1 not properly configured or in-kernel irqchip not + configured as required prior to calling this attribute + -EBUSY: SPEv1 already initialized + +Request the initialization of the SPEv1. If using the SPEv1 with an in-kernel +virtual GIC implementation, this must be done after initializing the in-kernel +irqchip. diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 333c6491bec7..d00f450dc4cd 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -39,7 +39,7 @@ #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS -#define KVM_VCPU_MAX_FEATURES 7 +#define KVM_VCPU_MAX_FEATURES 8 #define KVM_REQ_SLEEP \ KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index 820e5751ada7..905a73f30079 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -106,6 +106,7 @@ struct kvm_regs { #define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */ #define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */ #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */ +#define KVM_ARM_VCPU_SPE_V1 7 /* Support guest SPEv1 */ struct kvm_vcpu_init { __u32 target; @@ -326,6 +327,9 @@ struct kvm_vcpu_events { #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 #define KVM_ARM_VCPU_PVTIME_CTRL 2 #define KVM_ARM_VCPU_PVTIME_IPA 0 +#define KVM_ARM_VCPU_SPE_V1_CTRL 3 +#define KVM_ARM_VCPU_SPE_V1_IRQ 0 +#define KVM_ARM_VCPU_SPE_V1_INIT 1 /* KVM_IRQ_LINE irq field index values */ #define KVM_ARM_IRQ_VCPU2_SHIFT 28 diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile index 5ffbdc39e780..526f3bf09321 100644 --- a/arch/arm64/kvm/Makefile +++ b/arch/arm64/kvm/Makefile @@ -37,3 +37,4 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-debug.o kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/irqchip.o kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arch_timer.o kvm-$(CONFIG_KVM_ARM_PMU) += $(KVM)/arm/pmu.o +kvm-$(CONFIG_KVM_ARM_SPE) += $(KVM)/arm/spe.o diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 2fff06114a8f..50fea538b8bd 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -874,6 +874,8 @@ int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, break; case KVM_ARM_VCPU_PVTIME_CTRL: ret = kvm_arm_pvtime_set_attr(vcpu, attr); + case KVM_ARM_VCPU_SPE_V1_CTRL: + ret = kvm_arm_spe_v1_set_attr(vcpu, attr); break; default: ret = -ENXIO; @@ -897,6 +899,8 @@ int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, break; case KVM_ARM_VCPU_PVTIME_CTRL: ret = kvm_arm_pvtime_get_attr(vcpu, attr); + case KVM_ARM_VCPU_SPE_V1_CTRL: + ret = kvm_arm_spe_v1_get_attr(vcpu, attr); break; default: ret = -ENXIO; @@ -920,6 +924,8 @@ int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, break; case KVM_ARM_VCPU_PVTIME_CTRL: ret = kvm_arm_pvtime_has_attr(vcpu, attr); + case KVM_ARM_VCPU_SPE_V1_CTRL: + ret = kvm_arm_spe_v1_has_attr(vcpu, attr); break; default: ret = -ENXIO; diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index f4a8ae918827..cf17aff1489d 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -80,6 +80,9 @@ int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext) case KVM_CAP_ARM_INJECT_SERROR_ESR: r = cpus_have_const_cap(ARM64_HAS_RAS_EXTN); break; + case KVM_CAP_ARM_SPE_V1: + r = kvm_arm_support_spe_v1(); + break; case KVM_CAP_SET_GUEST_DEBUG: case KVM_CAP_VCPU_ATTRIBUTES: r = 1; diff --git a/include/kvm/arm_spe.h b/include/kvm/arm_spe.h index 30c40b1bc385..d1f3c564dfd0 100644 --- a/include/kvm/arm_spe.h +++ b/include/kvm/arm_spe.h @@ -8,6 +8,7 @@ #include #include +#include struct kvm_spe { int irq_num; @@ -18,8 +19,52 @@ struct kvm_spe { #ifdef CONFIG_KVM_ARM_SPE #define kvm_arm_spe_v1_ready(v) ((v)->arch.spe.ready) +#define kvm_arm_spe_irq_initialized(v) \ + ((v)->arch.spe.irq_num >= VGIC_NR_SGIS && \ + (v)->arch.spe.irq_num <= VGIC_MAX_PRIVATE) + +static inline bool kvm_arm_support_spe_v1(void) +{ + u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + + return !!cpuid_feature_extract_unsigned_field(dfr0, + ID_AA64DFR0_PMSVER_SHIFT); +} + +int kvm_arm_spe_v1_set_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr); +int kvm_arm_spe_v1_get_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr); +int kvm_arm_spe_v1_has_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr); +int kvm_arm_spe_v1_enable(struct kvm_vcpu *vcpu); #else #define kvm_arm_spe_v1_ready(v) (false) +#define kvm_arm_support_spe_v1() (false) +#define kvm_arm_spe_irq_initialized(v) (false) + +static inline int kvm_arm_spe_v1_set_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + return -ENXIO; +} + +static inline int kvm_arm_spe_v1_get_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + return -ENXIO; +} + +static inline int kvm_arm_spe_v1_has_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + return -ENXIO; +} + +static inline int kvm_arm_spe_v1_enable(struct kvm_vcpu *vcpu) +{ + return 0; +} #endif /* CONFIG_KVM_ARM_SPE */ #endif /* __ASM_ARM_KVM_SPE_H */ diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index f0a16b4adbbd..1a362c230e4a 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1009,6 +1009,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_PPC_GUEST_DEBUG_SSTEP 176 #define KVM_CAP_ARM_NISV_TO_USER 177 #define KVM_CAP_ARM_INJECT_EXT_DABT 178 +#define KVM_CAP_ARM_SPE_V1 179 #ifdef KVM_CAP_IRQ_ROUTING diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index 12e0280291ce..340d2388ee2c 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -22,6 +22,7 @@ #include #include #include +#include #define CREATE_TRACE_POINTS #include "trace.h" diff --git a/virt/kvm/arm/spe.c b/virt/kvm/arm/spe.c new file mode 100644 index 000000000000..83ac2cce2cc3 --- /dev/null +++ b/virt/kvm/arm/spe.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 ARM Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +int kvm_arm_spe_v1_enable(struct kvm_vcpu *vcpu) +{ + if (!vcpu->arch.spe.created) + return 0; + + /* + * A valid interrupt configuration for the SPE is either to have a + * properly configured interrupt number and using an in-kernel irqchip. + */ + if (irqchip_in_kernel(vcpu->kvm)) { + int irq = vcpu->arch.spe.irq_num; + + if (!kvm_arm_spe_irq_initialized(vcpu)) + return -EINVAL; + + if (!irq_is_ppi(irq)) + return -EINVAL; + } + + vcpu->arch.spe.ready = true; + + return 0; +} + +static int kvm_arm_spe_v1_init(struct kvm_vcpu *vcpu) +{ + if (!kvm_arm_support_spe_v1()) + return -ENODEV; + + if (!test_bit(KVM_ARM_VCPU_SPE_V1, vcpu->arch.features)) + return -ENXIO; + + if (vcpu->arch.spe.created) + return -EBUSY; + + if (irqchip_in_kernel(vcpu->kvm)) { + int ret; + + /* + * If using the SPE with an in-kernel virtual GIC + * implementation, we require the GIC to be already + * initialized when initializing the SPE. + */ + if (!vgic_initialized(vcpu->kvm)) + return -ENODEV; + + ret = kvm_vgic_set_owner(vcpu, vcpu->arch.spe.irq_num, + &vcpu->arch.spe); + if (ret) + return ret; + } + + vcpu->arch.spe.created = true; + return 0; +} + +/* + * For one VM the interrupt type must be same for each vcpu. + * As a PPI, the interrupt number is the same for all vcpus, + * while as an SPI it must be a separate number per vcpu. + */ +static bool spe_irq_is_valid(struct kvm *kvm, int irq) +{ + int i; + struct kvm_vcpu *vcpu; + + kvm_for_each_vcpu(i, vcpu, kvm) { + if (!kvm_arm_spe_irq_initialized(vcpu)) + continue; + + if (vcpu->arch.spe.irq_num != irq) + return false; + } + + return true; +} + +int kvm_arm_spe_v1_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) +{ + switch (attr->attr) { + case KVM_ARM_VCPU_SPE_V1_IRQ: { + int __user *uaddr = (int __user *)(long)attr->addr; + int irq; + + if (!irqchip_in_kernel(vcpu->kvm)) + return -EINVAL; + + if (!test_bit(KVM_ARM_VCPU_SPE_V1, vcpu->arch.features)) + return -ENODEV; + + if (get_user(irq, uaddr)) + return -EFAULT; + + /* The SPE overflow interrupt can be a PPI only */ + if (!(irq_is_ppi(irq))) + return -EINVAL; + + if (!spe_irq_is_valid(vcpu->kvm, irq)) + return -EINVAL; + + if (kvm_arm_spe_irq_initialized(vcpu)) + return -EBUSY; + + kvm_debug("Set kvm ARM SPE irq: %d\n", irq); + vcpu->arch.spe.irq_num = irq; + return 0; + } + case KVM_ARM_VCPU_SPE_V1_INIT: + return kvm_arm_spe_v1_init(vcpu); + } + + return -ENXIO; +} + +int kvm_arm_spe_v1_get_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) +{ + switch (attr->attr) { + case KVM_ARM_VCPU_SPE_V1_IRQ: { + int __user *uaddr = (int __user *)(long)attr->addr; + int irq; + + if (!irqchip_in_kernel(vcpu->kvm)) + return -EINVAL; + + if (!test_bit(KVM_ARM_VCPU_SPE_V1, vcpu->arch.features)) + return -ENODEV; + + if (!kvm_arm_spe_irq_initialized(vcpu)) + return -ENXIO; + + irq = vcpu->arch.spe.irq_num; + return put_user(irq, uaddr); + } + } + + return -ENXIO; +} + +int kvm_arm_spe_v1_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) +{ + switch (attr->attr) { + case KVM_ARM_VCPU_SPE_V1_IRQ: + case KVM_ARM_VCPU_SPE_V1_INIT: + if (kvm_arm_support_spe_v1() && + test_bit(KVM_ARM_VCPU_SPE_V1, vcpu->arch.features)) + return 0; + } + + return -ENXIO; +} From patchwork Fri Dec 20 14:30:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 182287 Delivered-To: patch@linaro.org Received: by 2002:a92:1f98:0:0:0:0:0 with SMTP id f24csp609868ilf; Fri, 20 Dec 2019 06:33:55 -0800 (PST) X-Google-Smtp-Source: APXvYqxMnc9xmALwY63mtqqhgHfSuZZcZcefrxfFSFoTNoaEnvYhKYssOX1V14ANJRu9j3hYDbNR X-Received: by 2002:a05:6830:1e8a:: with SMTP id n10mr4680736otr.303.1576852435575; Fri, 20 Dec 2019 06:33:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576852435; cv=none; d=google.com; s=arc-20160816; b=kX8b6rm2hcG2HMi9b1sKOKADc5tCOtxPbyNLUeRF1iAgh/Yh6ssNv3M/p/Db8rwUCQ Simg9NouljveKmVGsYba0EaWKTZKeHjvAY05hiJSiWS9suewFGGLRrokC7yCwWNdt3ac qatOSZiZBwwhgKSTC9t8FJzZ7J4wrpHGqgi/D8x9UlWqzgCeNPRBgUHdKag4lBuFyALm XFdg3ywqnjRGpT8K3/y9JZmtx67PW/XIhqRRYRO4cmjJOFkd3Hcben0zBR5YPkUHqpI0 QjhRQBKkuMp6YUzgnuQrj12z9foRGCbrKY+XsVub2lMXr6FObE3bGPRvILYNRx8pR8nA +7Jw== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id w64si4972237oib.185.2019.12.20.06.33.47; Fri, 20 Dec 2019 06:33:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728111AbfLTObT (ORCPT + 27 others); Fri, 20 Dec 2019 09:31:19 -0500 Received: from foss.arm.com ([217.140.110.172]:51340 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728039AbfLTObH (ORCPT ); Fri, 20 Dec 2019 09:31:07 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5FC1811B3; Fri, 20 Dec 2019 06:31:07 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 87C853F86C; Fri, 20 Dec 2019 06:31:05 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 16/18] KVM: arm64: enable SPE support Date: Fri, 20 Dec 2019 14:30:23 +0000 Message-Id: <20191220143025.33853-17-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sudeep Holla We have all the bits and pieces to enable SPE for guest in place, so lets enable it. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- virt/kvm/arm/arm.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.21.0 diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index a66085c8e785..fb3ad0835255 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -611,6 +611,10 @@ static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu) return ret; ret = kvm_arm_pmu_v3_enable(vcpu); + if (ret) + return ret; + + ret = kvm_arm_spe_v1_enable(vcpu); return ret; }