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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2dc0babsm186910895e9.14.2025.01.13.11.55.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:55:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 01/19] hw/mips/cps: Keep reference of vCPUs in MIPSCPSState Date: Mon, 13 Jan 2025 20:55:07 +0100 Message-ID: <20250113195525.57150-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When a QOM object create children with object_new(), it is better to keep reference to them for further use. In particular, this allow to remove one global &first_cpu use. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/cps.h | 1 + hw/mips/cps.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index 05ef9f76b74..0968b57c5a0 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -40,6 +40,7 @@ struct MIPSCPSState { char *cpu_type; bool cpu_is_bigendian; + MIPSCPU **cpus; MemoryRegion container; MIPSGCRState gcr; MIPSGICState gic; diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 293b405b965..494213b2ab6 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -73,6 +73,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) return; } + s->cpus = g_new(MIPSCPU *, s->num_vp); for (int i = 0; i < s->num_vp; i++) { MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type)); CPUMIPSState *env = &cpu->env; @@ -91,6 +92,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) { return; } + s->cpus[i] = cpu; /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); @@ -146,7 +148,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0)); /* Global Configuration Registers */ - gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4; + gcr_base = s->cpus[0]->env.CP0_CMGCRBase << 4; object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, From patchwork Mon Jan 13 19:55:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856947 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1601275wrc; Mon, 13 Jan 2025 11:57:33 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUw4nHUOIK5uSg7OFZrJHDvb0Bmb5QAvQ3ASbseU5FXcGdG5xYNhSjdnQtlHeYkWKdIjz1iag==@linaro.org X-Google-Smtp-Source: AGHT+IGzceDfc2bepDNF7OyPD2Ob9IgY9Fs28lbrcSWB8oZFjIEP/I/L54IRRo5hFpa02EOEfZPF X-Received: by 2002:a05:622a:2c6:b0:467:83f1:71d2 with SMTP id d75a77b69052e-46c7108ed5fmr331971091cf.45.1736798252985; Mon, 13 Jan 2025 11:57:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736798252; cv=none; d=google.com; s=arc-20240605; b=iJT7fvld1uXnovyO6RqOHgmFInyayOg6ja3PnioVloL4lleVg5BBegFYSh9uGxcmHG 0j2qEB/NkGmmLS3ADo+opUd/7xsXIBCqGGOGFBZATHyO/51qUBXwaqk+fVzFE/v6/Jci 4Rid4m/crx8e2ZBIPsLBJYq7W2zfEMQSzDawv+Q7kFHsSWk1pJrwx1npj35o/Db1E9ks TgH1mfB6LxAXfCotqIxBJmZ1jEeDYVLAQc4x9h4oljP3YZxTAe0bVy5KW9lYQJ5H+myS kWFZ4ip4KyTtDUMeroMEPmnt9uicwkPmlXikUZQVyHKS6NnyvFnUGPvoVdGElrtxo716 oDTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wTM7kJDrHWUpg1IPISR4zuSM03kjMUv0Xm2Dmwxq0M8=; fh=wMwPlu6s3WDa+luMUca6ONpSmNJKUwF5E3uCFeq1PI4=; b=RbaSfsjm/a6hBnxe7dfQdMbcEu3HpbxW40hXstl4j/f5wZMcLTvmsdeuiTA/sebc1u Ml7nsqHKujCJk7tGBhOBSgcSYal/T1HWWcjePyKJKqyQ3x+9K+L9xXMmKJyu5mCfO5kg LjfamWfvWJr3U1AvUrgOxx0P/DKm6azV7rXVqlpKzPSmYneeDQF8n8NrEz0Is2b6rusA F574aEt/nbRDoDCXsRJ2ZiK7tf3EF+3WQnXkHOlH3u/iUZt9n3dvJZf6uNzE1E6xXZ2j /ZOn93jUQORo1JHKMD4W9xZRpicv8xtwKaeVkVft8rmm7HxZtXZFqSE+qUcntbCYpT0a a3VA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HhcYBZ+f; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d8fc67sm154645675e9.8.2025.01.13.11.55.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:55:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 02/19] hw/mips/malta: Check CPU index instead of using &first_cpu Date: Mon, 13 Jan 2025 20:55:08 +0100 Message-ID: <20250113195525.57150-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since create_cpu_without_cps() creates the vCPUs iterating up to the machine SMP count, it knows the first CPU is created upon the first iteration, at index #0 :) Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 4e9cccaa347..37be2330eda 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1042,12 +1042,13 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s, cpu_mips_irq_init_cpu(cpu); cpu_mips_clock_init(cpu); qemu_register_reset(main_cpu_reset, cpu); - } - cpu = MIPS_CPU(first_cpu); - env = &cpu->env; - *i8259_irq = env->irq[2]; - *cbus_irq = env->irq[4]; + if (i == 0) { + env = &cpu->env; + *i8259_irq = env->irq[2]; + *cbus_irq = env->irq[4]; + } + } } static void create_cps(MachineState *ms, MaltaState *s, From patchwork Mon Jan 13 19:55:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856941 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1601034wrc; Mon, 13 Jan 2025 11:56:38 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCViKRfIlEx+iIl8UGU97Ez6XMVoYgXVVCtaUCavLZTPr8yLIk/b9o9+DQvq6uI+DJwwD+PF8Q==@linaro.org X-Google-Smtp-Source: AGHT+IG1oeGKN8Iy0+hPbAVpuY7zyDCS/O+FVt8n/VHrI3t6T+hi7J1cFEPetpgbJkqpoHpsNMsZ X-Received: by 2002:ac8:570e:0:b0:46c:791f:bf4e with SMTP id d75a77b69052e-46c791fc13cmr250061021cf.12.1736798198325; Mon, 13 Jan 2025 11:56:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736798198; cv=none; d=google.com; s=arc-20240605; b=CiR4pUl/4yTwKvVFN4E/B89bW0qvKLmp2Q7bDKC/laUrhS4Ioyz6KaAlFwH0j9yW02 9RGxQ83/MDTA0p7D0/dLcHgrOC4YYwTQyoAbLf3k/N1r6EhObub1Gkxnl3BjdGfWE/NT rZOKOL9gaG+hnPLx7GwVB7vLkY1smZyghET2DNn2Z7ZD1RemjMh71yREvKbuqdIxvTf9 59k2ojYJgOy297bVR0jt1ule3qSv6QBiMf5oFh9lMBTkCM9Op/AIj4mUlXf7OoHjgdBm 0zHnC6N7vfZkVyDXY7DfQyT+uV35Ery22MIcRpQVlxje16sYqTXcdQ3F3WxriRhOzjP3 igVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4iArtLIkc1Hfsjezw19sEsPpI58c9SSiC6oECSiSyLM=; fh=wMwPlu6s3WDa+luMUca6ONpSmNJKUwF5E3uCFeq1PI4=; b=asjSOC3CMR7WLHIFpA8VLryaMgWDfxZ2r9YiszHWi1V4rQu4Jz2YbNS+9qpf+Rf2Az GUbeQVMPveXoIkcda/96EJ0vPRkbUhn34lBXEm/YLX0ZkgLriP5w8qIiBjgc7ZxiEoCp Z+EH41s5Gw5lxIckcoEofDHv8gYRvPcB1EQPxFY2rZaFoQJJab3NPzsdGATT/dKp6R0i 01nA3iSRt7uknhAXMMp/fo5tMw6GbGayVPQa6XCV8YI6hWTir8u4amduaEH9Jza7XPMT H1ZMbeVATvooTsVJc7VjjOI7p5gcpYfoj6xs+CGNOdVGbOFxOiMgL9y/eei+Ofdgqp5J 7yGA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BTAl5rs5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2df3610sm186513515e9.20.2025.01.13.11.55.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:55:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 03/19] hw/mips/malta: Keep reference of vCPUs in MaltaState Date: Mon, 13 Jan 2025 20:55:09 +0100 Message-ID: <20250113195525.57150-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When a QOM object create children with object_new(), it is better to keep reference to them for further use. This will be helpful to remove &first_cpu uses in few commits. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 37be2330eda..090c2514354 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -107,6 +107,7 @@ struct MaltaState { SysBusDevice parent_obj; Clock *cpuclk; + MIPSCPU **cpus; MIPSCPSState cps; }; @@ -1037,6 +1038,7 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s, for (i = 0; i < ms->smp.cpus; i++) { cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk, TARGET_BIG_ENDIAN); + s->cpus[i] = cpu; /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); @@ -1063,6 +1065,7 @@ static void create_cps(MachineState *ms, MaltaState *s, &error_fatal); qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); + memcpy(s->cpus, s->cps.cpus, ms->smp.cpus * sizeof(MIPSCPU *)); sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); @@ -1070,9 +1073,11 @@ static void create_cps(MachineState *ms, MaltaState *s, *cbus_irq = NULL; } -static void mips_create_cpu(MachineState *ms, MaltaState *s, - qemu_irq *cbus_irq, qemu_irq *i8259_irq) +/* Initialize MaltaState::cpus[] */ +static void mips_create_cpus(MachineState *ms, MaltaState *s, + qemu_irq *cbus_irq, qemu_irq *i8259_irq) { + s->cpus = g_new(MIPSCPU *, ms->smp.cpus); if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) { create_cps(ms, s, cbus_irq, i8259_irq); } else { @@ -1111,7 +1116,7 @@ void mips_malta_init(MachineState *machine) sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal); /* create CPU */ - mips_create_cpu(machine, s, &cbus_irq, &i8259_irq); + mips_create_cpus(machine, s, &cbus_irq, &i8259_irq); /* allocate RAM */ if (ram_size > 2 * GiB) { From patchwork Mon Jan 13 19:55:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856959 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1601707wrc; Mon, 13 Jan 2025 11:58:59 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW7Yh1LZNmEs2oFPIcysxvmW4Npm74qGKhmpvTcSiVFI8dSNOPAQdfvyXKy+Q57VU5lDJWTLw==@linaro.org X-Google-Smtp-Source: AGHT+IFzdfLzPNdHBjOlHK+dZyE4EUvhtzvt2bcWgQVM2Msiig3+IT7XEppc8w6sNZ5DW2KHuSP/ X-Received: by 2002:a05:620a:19a9:b0:7b6:dedf:b6c2 with SMTP id af79cd13be357-7bcd96e61b0mr3763863585a.5.1736798339331; Mon, 13 Jan 2025 11:58:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736798339; cv=none; d=google.com; s=arc-20240605; b=lBWYxJo484D7Ac+yyvdsX7cyAPvJRJ/KNFJMzyZXnTJ70/PTMTHli9ta7jhKEQZ4kF EipjMOwF0KcemqFAruPMMtlF1uwcsB9jCytNwEGUpeoChfL307+dymQx4j+/yK5uEUgg oT1jbwwZ5rKhaHYzHBQuEuUXOfCRVJjZjyjd1HVUzAPMipZrpwoOpNgRz/0OlqLR/QEH 10SpLfRlwajlixQJbmBG2IUE3oNG2dKeg5yL8SYgmMwY+0ahhdcSP3Iz236v+jTdjmCW fOE2dUggpQ16RO2invlKtRKOLzIQBgYqyosJXDMR3vbYQ/OpzU9/6zmiYLAfddhj35Gq ytKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=90vMRgdrB/kNHL2lPqK50NFXkY3ERKj+k5MjSo7lg7I=; fh=wMwPlu6s3WDa+luMUca6ONpSmNJKUwF5E3uCFeq1PI4=; b=f9Y8bg0osfK1tlae4P33NkGsxudkKMBYQznsXCuQS4KR/pBwJbBFa+GoCZWoYQU5p1 hsF8Vw/sThCrKSZqMahtGJxhlO3ltcprIv5fct97AUi1PYjAAmMfrr8CtPwFJsFbOUT3 +xnlKifD6BzTYrRJzI51MqZPL+9GftmjAo35us3o9gdGsar4aG4iq3n+eqMQYQr0+eo3 BVBHLoK+nsAuXOVrCGCRnit1fqWtwy5JToyuLQUwbafucTvbgRay68h5kNUMIIsyd1km 25Cw4v8rZ8lZ/PCrTvX+EhLxtGsUa0CjVVQhzmiMeiCuJF2Hj7l+LEcIYmfkthLwU+wZ 1BZw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jLrBMHiS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e38c1d6sm13190857f8f.50.2025.01.13.11.55.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:55:47 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 04/19] hw/mips/malta: Propagate MaltaState to write_bootloader() Date: Mon, 13 Jan 2025 20:55:10 +0100 Message-ID: <20250113195525.57150-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass MaltaState as argument to write_bootloader() so next commit can propagate it to bl_setup_gt64120_jump_kernel(). Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 090c2514354..ec8fd954b4b 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -692,7 +692,8 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, kernel_entry); } -static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, +static void write_bootloader_nanomips(MaltaState *s, + uint8_t *base, uint64_t run_addr, uint64_t kernel_entry) { uint16_t *p; @@ -744,7 +745,8 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, * a2 - 32-bit address of the environment variables table * a3 - RAM size in bytes */ -static void write_bootloader(uint8_t *base, uint64_t run_addr, +static void write_bootloader(MaltaState *s, + uint8_t *base, uint64_t run_addr, uint64_t kernel_entry) { uint32_t *p; @@ -1172,10 +1174,10 @@ void mips_malta_init(MachineState *machine) kernel_entry = load_kernel(); if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { - write_bootloader(memory_region_get_ram_ptr(bios), + write_bootloader(s, memory_region_get_ram_ptr(bios), bootloader_run_addr, kernel_entry); } else { - write_bootloader_nanomips(memory_region_get_ram_ptr(bios), + write_bootloader_nanomips(s, memory_region_get_ram_ptr(bios), bootloader_run_addr, kernel_entry); } } else { From patchwork Mon Jan 13 19:55:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856953 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1601460wrc; Mon, 13 Jan 2025 11:58:10 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWN8f29bvxJ1QSqYXPlPb7BEhf5yumhma3w98ECcQxvEgYudjHovF7YBy4RGfh+uPxPPzz2MQ==@linaro.org X-Google-Smtp-Source: AGHT+IHhNltrB+/vw87OWCHYmm+WsFTleECZQa48DL8q1bptCJ/SwI/ADF4cNxzPgrccZvETBluY X-Received: by 2002:a05:622a:4011:b0:461:7558:892f with SMTP id d75a77b69052e-46c7b01fb9fmr298079851cf.15.1736798289850; Mon, 13 Jan 2025 11:58:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736798289; cv=none; d=google.com; s=arc-20240605; b=UPgamor4559Zh7fiiQVpOc/GPqn5iZodHjG/Fy+XZmWs+T4CtZe2pVxdTGKbjtOuEy xoS0g04nPAyy4P19CvWYohlhDgd+nxsi+JzYs+dEAp6t5YnTutbA6giyyFktzFou30IZ TDVzK2mhOm0fKoMMrD8uJTWh0PtjaIc9e3jQTt7pvc0q8gZ9FZy84B38Thh9vUNqQ5LR 27OOJn2TOaHs2nVRPL2cLiq/AiimMX6mLIKIjzNccZkRfppkv2Cl+H6CbO4gMmsz7hrE 4hTpEXruV51NTuQMP+WFgoBxR+ffHLlBJH119Nb0rjAb3Bhssy6CYPBgvJocIXHaFgW+ 4O1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Jys96smoYe/UFvAgEu5KOk6WoWGY0ynuT+FPBUQuY0w=; fh=wMwPlu6s3WDa+luMUca6ONpSmNJKUwF5E3uCFeq1PI4=; b=PypN+WqyDfetixZpVdPQNBNuD5qYNSbfb0dfBiDxGA5pfRGczqdG4cd20O1LDR2ciq 2CHf/44dknJvRwh+pt9wTjGgjwTBqd40c0xva9KHLuhE45xkSQxKYxy3xKbkIqTqE4Fd LA4Cfsq0hbgSNu0ewQv0rRruAJECYQJ+Mb+miAouf33SrRPyDMV8V1EkkYJhOIzqi8oS aOEZb0MaC/bwZM9K2809UdHGw/5hDdC8wz3W2d8y3BqhmNOu8eKcJLYsJVq8TU/3jktt 4v6TMCF4Z1KXfb2y1NuqAWDTKh1QOXXhiiG4HEMhrHlICNjIlwuo0sQP+ehlX41tS16J QSXg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Zn+ttxDX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2dc0bb7sm185609735e9.16.2025.01.13.11.55.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:55:52 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 05/19] hw/mips/malta: Propagate MaltaState to bl_setup_gt64120_jump_kernel() Date: Mon, 13 Jan 2025 20:55:11 +0100 Message-ID: <20250113195525.57150-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Propagate MaltaState to bl_setup_gt64120_jump_kernel() so it can access the MaltaState::cpus[] array. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index ec8fd954b4b..f7eb990c629 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -620,7 +620,8 @@ static void network_init(PCIBus *pci_bus) pci_init_nic_devices(pci_bus, "pcnet"); } -static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, +static void bl_setup_gt64120_jump_kernel(MaltaState *s, void **p, + uint64_t run_addr, uint64_t kernel_entry) { static const char pci_pins_cfg[PCI_NUM_PINS] = { @@ -720,7 +721,7 @@ static void write_bootloader_nanomips(MaltaState *s, /* to_here: */ - bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry); + bl_setup_gt64120_jump_kernel(s, (void **)&p, run_addr, kernel_entry); } /* @@ -786,7 +787,7 @@ static void write_bootloader(MaltaState *s, * */ - bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry); + bl_setup_gt64120_jump_kernel(s, (void **)&p, run_addr, kernel_entry); /* YAMON subroutines */ p = (uint32_t *) (base + 0x800); From patchwork Mon Jan 13 19:55:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856956 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1601627wrc; Mon, 13 Jan 2025 11:58:43 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVFTRSTY0gs63zX8JZSL/zUTyL/nPJNNCIg5pjyIrMcDUU7e6eXCT3xd3pOyuoAeTB1vJCPOg==@linaro.org X-Google-Smtp-Source: AGHT+IFwE4q5iiTxOitTAQEeOyu+jRmRV+Rzf1kYEhuVvYwSn1U7BymbtbMSn9/hjNd1pLxlMG99 X-Received: by 2002:a05:622a:198a:b0:467:68a2:cb55 with SMTP id d75a77b69052e-46c710a93eemr338963021cf.28.1736798323414; Mon, 13 Jan 2025 11:58:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736798323; cv=none; d=google.com; s=arc-20240605; b=STRqIOyJwCqU6I+hHQZ4ckDWvCiev12XVkiAT/qNEW7LoMT3iL6PjU/g3Mc59DmK8V zC3dugjn5bKYnSpiCqsmjjDb6ml4HMSKpDM9jwXUoUZue6FcyzoX0xvHvP/59ArqufKF hITbCFwu09Dzx0zH4/W5ocwebtBK8hDyYUKk6PVSOuZVnnGLqqjE4UINmOTxwdu84pqs vJY+6G83WXQGi+lS0ntlypbwXWIDkp0HVJrDRH8k5X69s7hbuS/jV5C7LHFxmTIkF8dn uOPl5HrQyyrnNgNJwM+FKfY6zV/+JoUOKqkeI3E8CIyq+nEl4LwJa0tPTNm+R/+OBsUw +UVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=raovzkxW4bgEPUiYxpxT8OAVJQxeHZnj+ixMLAGuiZ0=; fh=wMwPlu6s3WDa+luMUca6ONpSmNJKUwF5E3uCFeq1PI4=; b=VWARbqIc5H8lb6znKMmvG0Q3KOFskoLpeWe9ClWTH5K6Pd01CKmP3RwH/Qom+EZ2Px kRtJw7xqEDXYZcr81ZnVFyiyEVtWTMmzsb1kRX/H/+WwWUtnc2c/SqbKgHBlyqqQV8u2 bQoPkykXtuLF2MuUIjkawIBfZ0LmnWCw3tXZLeC528hMhBZ8NcpQGDgRqG9BaQW/morL loamMDQXv6xqod2HIIKeRs1SBsVsGRObh8FnBsYvZurDLUKtwdeT4+PJKKAMd179dUTe C3BxkV3twzegvRs+J9WThcrWva2FDnBhWgIUX3LzM5F5an9n9ydPw+pCq92wCM5Nr9lN Eo/A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cf4XBmsu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2e8a326sm188258975e9.35.2025.01.13.11.55.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:55:57 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 06/19] hw/mips/boston: Replace bl_gen_write_ulong() -> bl_gen_write_u64() Date: Mon, 13 Jan 2025 20:55:12 +0100 Message-ID: <20250113195525.57150-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "exec/hwaddr.h" defines: typedef uint64_t hwaddr; typedef struct MemMapEntry { hwaddr base; hwaddr size; } MemMapEntry; Since MemMapEntry::base is always of type uint64_t, we can directly use bl_gen_write_u64(). Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/boston.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 67044af962a..63dc654192a 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -329,20 +329,20 @@ static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) /* Move CM GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, - boston_memmap[BOSTON_CM].base); + bl_gen_write_u64(&p, regaddr, + boston_memmap[BOSTON_CM].base); /* Move & enable GIC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_GIC_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, - boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK); + bl_gen_write_u64(&p, regaddr, + boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK); /* Move & enable CPC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_CPC_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, - boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK); + bl_gen_write_u64(&p, regaddr, + boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK); /* * Setup argument registers to follow the UHI boot protocol: From patchwork Mon Jan 13 19:55:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856943 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1601120wrc; Mon, 13 Jan 2025 11:56:58 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVTJiK5yw699z+u4gl8SgGCKf023u6cDYWzCwe6mi0GOSxo6Y813OiMl8D36dM+qNWK4s1KMg==@linaro.org X-Google-Smtp-Source: AGHT+IEeThSWzm9LLyJCktvqR8Nm+d7kGT+XxUwEIdFQaUlhr/T3B1rmJqT/1mPjGMmNXFxod1fn X-Received: by 2002:ad4:5d64:0:b0:6d8:9838:d3a9 with SMTP id 6a1803df08f44-6df9b22d71cmr259611746d6.26.1736798218156; Mon, 13 Jan 2025 11:56:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736798218; cv=none; d=google.com; s=arc-20240605; b=YjozfgSbsKKf7IOdOg6MzMu7HkS8HS6oQ3F/ckQA0nVPFX0iHn9MXD8ZD5xUQcJs7s HPgjkng0DYzyA3yLPFSCOeFbx52JDrgnftmb/bjAV+V9I2WTUhhqz1i/v0Fp+ao2au+V Auq0yHRkXhqGBQI6X0IftDeP/lVdvlnAxO/s7wbaF4IKVFp5eXkLnwoQJDOQUcUMLcR6 tuh4D41FDKvUb6fG5RJaeuHSIKXhMjhN/idIb+RixbTwdO+nO2a64jTAL3fEMW6z1KMo Kx201bcWEXuQwJeGJ4u9LklsQM66/GPMc59BdHuSBj31N0gesxNJ7rlMsV1Ao33h//H0 d4nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=tkdKuqLsU14ZzZ0juxUu8/huKQ0KKnNGQSOpTw7EA2I=; fh=wMwPlu6s3WDa+luMUca6ONpSmNJKUwF5E3uCFeq1PI4=; b=HGu1Ea5uw3GtWmNRygE9osNao2zIZKysMc4d2tqIpl4IxmaKAhoOjNS8HaD0uX0bc+ lUrUwair2ypmFzqQeRdk0IBWYz2PmeHq38jbZwd/sSOk/lUxprEgbA/ImobOkmeZKQdZ B8ZkaP2Z8uHXEfOdGuLbBczJEZDWuRzytFHSFt3TdWhAR78CVYuBW5+Y0jjvEVFQysgY P3f5z+xO9LBNwqLd+VsFqx6w5OIRG8a0MYlC41Lf5tkcXmUazxRldmBNQxJ5/biaORoK dlew0zoCSRfG5iN++DjbpwhEGPzAffgEMd/16ke+WIr7iDmUkqdbnmIptZcRFd2pE0It BCzA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iCANKKMB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9e37d74sm153210325e9.29.2025.01.13.11.56.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:56:03 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 07/19] hw/mips/boston: Propagate CPU to gen_firmware() Date: Mon, 13 Jan 2025 20:55:13 +0100 Message-ID: <20250113195525.57150-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Propagate a CPU to gen_firmware(). Since we expect the first CPU to run the firmware, get it from the CPS in boston_mach_init(), resolving it using its QOM path. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/boston.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 63dc654192a..491e1c4f7ea 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -323,7 +323,8 @@ static void boston_register_types(void) } type_init(boston_register_types) -static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) +static void gen_firmware(const MIPSCPU *cpu, void *p, + hwaddr kernel_entry, hwaddr fdt_addr) { uint64_t regaddr; @@ -825,7 +826,9 @@ static void boston_mach_init(MachineState *machine) } } - gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000, + gen_firmware(MIPS_CPU(object_resolve_path_component(OBJECT(&s->cps), + "cpu[0]")), + memory_region_get_ram_ptr(flash) + 0x7c00000, s->kernel_entry, s->fdt_base); } else if (!qtest_enabled()) { error_report("Please provide either a -kernel or -bios argument"); From patchwork Mon Jan 13 19:55:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856950 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1601416wrc; Mon, 13 Jan 2025 11:58:01 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUfPWrTLuRncLk8J4G2EyQuRKrjVUpvUfQGUaryYUKugs5NNe1ZvU4K7A+y2XIdyxcxVT9Oog==@linaro.org X-Google-Smtp-Source: AGHT+IG7uCcc386cBkLxqRiI7SL7DrqmAkc+1ygpzgOV2+dRgSWzRjhtjjmDlbmMoORBLVWKEaI1 X-Received: by 2002:a05:620a:40c4:b0:7b6:d420:7867 with SMTP id af79cd13be357-7bcd972775amr3056453185a.11.1736798281110; Mon, 13 Jan 2025 11:58:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736798281; cv=none; d=google.com; s=arc-20240605; b=kK7Q2duAnNmnswOdKqJPtjc3FcRjm0xvLpU20X0XW8zKgsPxX8qKMrSzSqeqxsChTe 2+CyWZbMu4NMygkZLPgXDcePYOovS68WjvEt0M5U7id3IekoFrlsNVrFyWmgOqa9Cicb LcQcP/M8SA8bwflb2g0bXaqUlLbGXfl43xO7Y4hMuW02yJUFUPrAfUacQT3c8muK5ODl wAE7HZOw4pvIMjIAeGsNH5S06ONiM1ym591sC87X3f1jfvcH2GPtXHfqQ6tEDruIU76E u7qRbZSe51GDZ6+tYh/Y6/1fpELHdua3MLL92f6aL3jdz+HamRF0tEiBkrLBWoVmtjEQ Ekew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=N4kmZyv0O5bHo8aW0lg7ydcay6cFbqBLxdZksmJ/bR0=; fh=wMwPlu6s3WDa+luMUca6ONpSmNJKUwF5E3uCFeq1PI4=; b=aoxTvbIAh5yJDcpDSbdrECoBGt5Qf5ZLoyC/QgZZ4Wr8YfL8pM/J+sjYsfUkknXaIG OJu/E7k2rd0bd82e5z4OtOyf1D7QFdzoQ/K9Gin97AAJvZ7TcEugWrJnWVvPKwgm1diG XsT3l5RR2K9t7JNtyuwTdVJHmla5WO1Mh91zNFInaKt1Pr03tbiPlxzUuvvAKRFURQjl Gd28J54tWzgRRaOmibREx0bvXubwiAZu/KrlFqnAfrT04ap8jwNNCIxI7DfYD8ohcFml MD+XTZBjbUALRjYjDfVbjH9t6Frp2eUOxQFnuUtWBDa/tfbt/Quyau5vix2zUyVb5Uyt fshQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZFqVV6SU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d8fba4sm153973325e9.4.2025.01.13.11.56.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:56:08 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 08/19] hw/mips/fuloong: Propagate CPU to write_bootloader() Date: Mon, 13 Jan 2025 20:55:14 +0100 Message-ID: <20250113195525.57150-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org mips_fuloong2e_init() created the vCPU so has its reference, propagate it to write_bootloader(), removing the &first_cpu use. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/fuloong2e.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 16b6a5129e7..c4080a8a6e3 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -163,7 +163,7 @@ static uint64_t load_kernel(MIPSCPU *cpu) return kernel_entry; } -static void write_bootloader(CPUMIPSState *env, uint8_t *base, +static void write_bootloader(const MIPSCPU *cpu, uint8_t *base, uint64_t kernel_addr) { uint32_t *p; @@ -258,7 +258,7 @@ static void mips_fuloong2e_init(MachineState *machine) loaderparams.kernel_cmdline = kernel_cmdline; loaderparams.initrd_filename = initrd_filename; kernel_entry = load_kernel(cpu); - write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry); + write_bootloader(cpu, memory_region_get_ram_ptr(bios), kernel_entry); } else { filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware ?: FULOONG_BIOSNAME); From patchwork Mon Jan 13 19:55:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856942 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1601058wrc; Mon, 13 Jan 2025 11:56:45 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVVL7l/Kef3QWK+hpoj15//aChyLVf2IYOYKELWy0y82vC4BW/C5AfjMBqVdgKLeBq8WqOmMA==@linaro.org X-Google-Smtp-Source: AGHT+IHlyY3nkF7zhagozRxFFqBAjFQEimAj0zeQidkqNGWR5BJ/GULdWSB+ELvla7RXKnTaXkFo X-Received: by 2002:a05:622a:c5:b0:467:6283:3c9d with SMTP id d75a77b69052e-46c710032fdmr408791461cf.13.1736798205364; Mon, 13 Jan 2025 11:56:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736798205; cv=none; d=google.com; s=arc-20240605; b=hsIwEYzr4/5FUGIiAvyoFa0ttKrJvvJhU7jGqO8bm3+qoj51ydERMTSoys/NYMuCvE d7/3qC5VLqvO3cYCI3iFKCbCbabFaEVqpLT/QnC7508DgvVqa2lsQPq1UsWRveEzZJw3 gS8dRCeeuFj042RUNXABXjc1mQwd3bVH5wX2OcyhAQiyjHwETT6eZfQaWLw9WjqVtx9f 6hyMRUhZ6/FwAWXuKYKmxoiv9M5CA/toInlTceIyrgG7Zri9Ejijugv7uUBCZTF5W7cB 95b7FRBs/KFlc+pyyTLYZEBHZGPN4omrClrxg2nPaGZ35FVCSQx8F+nrGJw6m61yZGl8 w1Sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TyQ/od43vNMa0q6wCQy5fR9/uoB2I9o4Ue/+fqk0SAo=; fh=wMwPlu6s3WDa+luMUca6ONpSmNJKUwF5E3uCFeq1PI4=; b=jH6UBMz+icOwh3/uEktfcJakEtUkhvgnPeC3C6+ca8Yyujt89oDNcQjSbVdOo9k79n UZFGGy7EQVuRqXmP8y71XD8QSOWh+4wG94f4I5RoHcTOlZwHr0s+Olxl+HcJ/gjvTajO Z5xh7D/WliA7ahPxElIgQawdzEyov2xLRUNRVtBRT+2vyzXmnSo4tewa5rCBmMpb+FBK SnbjDTGn9XZ2TVJQIlxIYznVi8clOExEhbsSfcFl3hNKqr/ZUpKFoSO7VmmCxsgVzGld hRB4gYzivQ5rS/2biH16G0VzY8v6g8BCiUWMaB9i3E0CgmSlBbCt7hsicmQ/L5aMlzKo 6KvA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ehqSbI4u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e38d008sm13296048f8f.59.2025.01.13.11.56.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:56:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 09/19] hw/mips/bootloader: Document public API Date: Mon, 13 Jan 2025 20:55:15 +0100 Message-ID: <20250113195525.57150-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Document bl_gen_write_u[32,64,long]() and bl_gen_jump_[to,kernel]() prototypes. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/bootloader.h | 50 ++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index c32f6c28356..8533a16ca62 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -11,7 +11,30 @@ #include "exec/cpu-defs.h" +/** + * bl_gen_jump_to: Generate bootloader code to jump to an address + * + * @ptr: Pointer to buffer where to write the bootloader code + * @jump_addr: Address to jump to + */ void bl_gen_jump_to(void **ptr, target_ulong jump_addr); + +/** + * bl_gen_jump_kernel: Generate bootloader code to jump to a Linux kernel + * + * @ptr: Pointer to buffer where to write the bootloader code + * @set_sp: Whether to set $sp register + * @set_a0: Whether to set $a0 register + * @set_a1: Whether to set $a1 register + * @set_a2: Whether to set $a2 register + * @set_a3: Whether to set $a3 register + * @sp: Value to set $sp to if @set_sp is set + * @a0: Value to set $a0 to if @set_a0 is set + * @a1: Value to set $a0 to if @set_a1 is set + * @a2: Value to set $a0 to if @set_a2 is set + * @a3: Value to set $a0 to if @set_a3 is set + * @kernel_addr: Start address of the kernel to jump to + */ void bl_gen_jump_kernel(void **ptr, bool set_sp, target_ulong sp, bool set_a0, target_ulong a0, @@ -19,8 +42,35 @@ void bl_gen_jump_kernel(void **ptr, bool set_a2, target_ulong a2, bool set_a3, target_ulong a3, target_ulong kernel_addr); + +/** + * bl_gen_write_ulong: Generate bootloader code to write an unsigned long + * value at an address + * + * @ptr: Pointer to buffer where to write the bootloader code + * @addr: Address to write to + * @val: Value to write at @addr + */ void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val); + +/** + * bl_gen_write_u32: Generate bootloader code to write a 32-bit unsigned + * value at an address + * + * @ptr: Pointer to buffer where to write the bootloader code + * @addr: Address to write to + * @val: Value to write at @addr + */ void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val); + +/** + * bl_gen_write_u64: Generate bootloader code to write a 64-bit unsigned + * value at an address + * + * @ptr: Pointer to buffer where to write the bootloader code + * @addr: Address to write to + * @val: Value to write at @addr + */ void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val); #endif From patchwork Mon Jan 13 19:55:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856955 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1601612wrc; Mon, 13 Jan 2025 11:58:41 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCV80VpWkX7kT/br/E8izerAEgd95DYtPh6XPPLktfgWWhEeDd66n/DPtkBCl0VNeIkFEwEE1w==@linaro.org X-Google-Smtp-Source: AGHT+IEtI4rw9W0Ce409Ph081/pZZH2968xfoZzPhiTVu3K9LB6JVL/BTgOnipi4nGDPop36arag X-Received: by 2002:a05:620a:1992:b0:7b1:3bf5:11f8 with SMTP id af79cd13be357-7bcd973aa13mr3020515985a.25.1736798321530; Mon, 13 Jan 2025 11:58:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736798321; cv=none; d=google.com; s=arc-20240605; b=Eljb7cB/ZVX2PV0IKcaGvPlIygY6ELXUEX073zuMaWWR1I1lrWF166maH64Orn0rXV IOhLKYcJ3zP/SoeVuhADPdDi096UgaMUHHNrtJf8QcIUn5xOSvwevUXqxUmotL0kHtbu ej8F+qCW6zGjSqc8cB57SFpCVxypuOQnIuEL1T8v7DVj2qXO+vQmMzhqZR4uPJEfEoZd vNg+dA7Mhzu7oafpvA5AKmbsigrEqD/SAhh2tRp7H7T9Jd8KMwRg2cHwi/n2OsS3+ruA 3i+R1myan1Rpwl5Cn1CyrD7XT3kEl7nAmkZh/ZmNXaffZgeoKUpfTV3o15zuQOdok3E8 Hp0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PieuWU0nqmvAznlB9XhRFnXCB0Z6Na0267ppDpJt9t8=; fh=wMwPlu6s3WDa+luMUca6ONpSmNJKUwF5E3uCFeq1PI4=; b=FAaY9MrRAlJV7RTbgusDP9nvOHzqwQurNDdQpeloUke20aa5/IHWOpQ6HZ5ZISYjfp 5cZZAlexmKaIXnrfPltYBY1zJKFG4F6PYSeXN6OI3wtaoB2eh0ytC+LNMj7leO/fDoI0 WbgI5VHSfV7aWwLCUFYGelO8tjFusRoeRc56yT0D1f/5ZQOnldZkcyBRl7VBwOs1plpD PgWfTf7AKKEFSaC6CY4y9qpLW5hOoP+HpsxVakeWsJCqoQB37/uR1wnEBlBfuxO10C6d 8gv+eOYSamXUWsoPNJ51khOlHqjzQYojtQpuC8fvk4Rm1tQMpm4najWbD++VppqZ4tCU UonA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ub2kOUEW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=fail header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e4b81a4sm13245516f8f.68.2025.01.13.11.56.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:56:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 10/19] hw/mips/bootloader: Propagate CPU to bl_gen_write_u[32, 64, long]() Date: Mon, 13 Jan 2025 20:55:16 +0100 Message-ID: <20250113195525.57150-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Propagate the target agnostic CPU pointer to the publicly declared bl_gen_write_u32(), bl_gen_write_u64() and bl_gen_write_ulong() functions. For the Malta machine in bl_setup_gt64120_jump_kernel(), pass its first CPU (the one we want to start running the bootloader). Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/bootloader.h | 13 ++++++++++--- hw/mips/bootloader.c | 9 ++++++--- hw/mips/boston.c | 6 +++--- hw/mips/malta.c | 19 ++++++++++--------- 4 files changed, 29 insertions(+), 18 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index 8533a16ca62..bc54ea8c7fb 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -10,6 +10,7 @@ #define HW_MIPS_BOOTLOADER_H #include "exec/cpu-defs.h" +#include "target/mips/cpu-qom.h" /** * bl_gen_jump_to: Generate bootloader code to jump to an address @@ -47,30 +48,36 @@ void bl_gen_jump_kernel(void **ptr, * bl_gen_write_ulong: Generate bootloader code to write an unsigned long * value at an address * + * @cpu: The MIPS CPU which will run the bootloader code * @ptr: Pointer to buffer where to write the bootloader code * @addr: Address to write to * @val: Value to write at @addr */ -void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val); +void bl_gen_write_ulong(const MIPSCPU *cpu, void **ptr, + target_ulong addr, target_ulong val); /** * bl_gen_write_u32: Generate bootloader code to write a 32-bit unsigned * value at an address * + * @cpu: The MIPS CPU which will run the bootloader code * @ptr: Pointer to buffer where to write the bootloader code * @addr: Address to write to * @val: Value to write at @addr */ -void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val); +void bl_gen_write_u32(const MIPSCPU *cpu, void **ptr, + target_ulong addr, uint32_t val); /** * bl_gen_write_u64: Generate bootloader code to write a 64-bit unsigned * value at an address * + * @cpu: The MIPS CPU which will run the bootloader code * @ptr: Pointer to buffer where to write the bootloader code * @addr: Address to write to * @val: Value to write at @addr */ -void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val); +void bl_gen_write_u64(const MIPSCPU *cpu, void **ptr, + target_ulong addr, uint64_t val); #endif diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 1dd6ef20968..7db3bf7511f 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -277,7 +277,8 @@ void bl_gen_jump_kernel(void **p, bl_gen_jump_to(p, kernel_addr); } -void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) +void bl_gen_write_ulong(const MIPSCPU *cpu, void **p, + target_ulong addr, target_ulong val) { bl_gen_load_ulong(p, BL_REG_K0, val); bl_gen_load_ulong(p, BL_REG_K1, addr); @@ -288,14 +289,16 @@ void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) } } -void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val) +void bl_gen_write_u32(const MIPSCPU *cpu, void **p, + target_ulong addr, uint32_t val) { bl_gen_li(p, BL_REG_K0, val); bl_gen_load_ulong(p, BL_REG_K1, addr); bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); } -void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val) +void bl_gen_write_u64(const MIPSCPU *cpu, void **p, + target_ulong addr, uint64_t val) { bl_gen_dli(p, BL_REG_K0, val); bl_gen_load_ulong(p, BL_REG_K1, addr); diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 491e1c4f7ea..b646c104df7 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -330,19 +330,19 @@ static void gen_firmware(const MIPSCPU *cpu, void *p, /* Move CM GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS), - bl_gen_write_u64(&p, regaddr, + bl_gen_write_u64(cpu, &p, regaddr, boston_memmap[BOSTON_CM].base); /* Move & enable GIC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_GIC_BASE_OFS), - bl_gen_write_u64(&p, regaddr, + bl_gen_write_u64(cpu, &p, regaddr, boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK); /* Move & enable CPC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_CPC_BASE_OFS), - bl_gen_write_u64(&p, regaddr, + bl_gen_write_u64(cpu, &p, regaddr, boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK); /* diff --git a/hw/mips/malta.c b/hw/mips/malta.c index f7eb990c629..9bc3fc9da3e 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -627,6 +627,7 @@ static void bl_setup_gt64120_jump_kernel(MaltaState *s, void **p, static const char pci_pins_cfg[PCI_NUM_PINS] = { 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ }; + const MIPSCPU *cpu = s->cpus[0]; /* Bus endianness is always reversed */ #if TARGET_BIG_ENDIAN @@ -638,29 +639,29 @@ static void bl_setup_gt64120_jump_kernel(MaltaState *s, void **p, /* setup MEM-to-PCI0 mapping as done by YAMON */ /* move GT64120 registers from 0x14000000 to 0x1be00000 */ - bl_gen_write_u32(p, /* GT_ISD */ + bl_gen_write_u32(cpu, p, /* GT_ISD */ cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68), cpu_to_gt32(0x1be00000 << 3)); /* setup PCI0 io window to 0x18000000-0x181fffff */ - bl_gen_write_u32(p, /* GT_PCI0IOLD */ + bl_gen_write_u32(cpu, p, /* GT_PCI0IOLD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48), cpu_to_gt32(0x18000000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0IOHD */ + bl_gen_write_u32(cpu, p, /* GT_PCI0IOHD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50), cpu_to_gt32(0x08000000 << 3)); /* setup PCI0 mem windows */ - bl_gen_write_u32(p, /* GT_PCI0M0LD */ + bl_gen_write_u32(cpu, p, /* GT_PCI0M0LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58), cpu_to_gt32(0x10000000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M0HD */ + bl_gen_write_u32(cpu, p, /* GT_PCI0M0HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60), cpu_to_gt32(0x07e00000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M1LD */ + bl_gen_write_u32(cpu, p, /* GT_PCI0M1LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80), cpu_to_gt32(0x18200000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M1HD */ + bl_gen_write_u32(cpu, p, /* GT_PCI0M1HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88), cpu_to_gt32(0x0bc00000 << 3)); @@ -671,12 +672,12 @@ static void bl_setup_gt64120_jump_kernel(MaltaState *s, void **p, * Load the PIIX IRQC[A:D] routing config address, then * write routing configuration to the config data register. */ - bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */ + bl_gen_write_u32(cpu, p, /* GT_PCI0_CFGADDR */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), tswap32((1 << 31) /* ConfigEn */ | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 | PIIX_PIRQCA)); - bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */ + bl_gen_write_u32(cpu, p, /* GT_PCI0_CFGDATA */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), tswap32(ldl_be_p(pci_pins_cfg))); From patchwork Mon Jan 13 19:55:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856944 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1601154wrc; Mon, 13 Jan 2025 11:57:06 -0800 (PST) X-Forwarded-Encrypted: i=2; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436ed48f4b2sm140328005e9.24.2025.01.13.11.56.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:56:22 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 11/19] hw/mips/bootloader: Propagate CPU to bl_gen_jump_[to, kernel]() Date: Mon, 13 Jan 2025 20:55:17 +0100 Message-ID: <20250113195525.57150-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Propagate the target agnostic CPU pointer to the publicly declared bl_gen_jump_to() and bl_gen_jump_kernel() functions. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/bootloader.h | 6 ++++-- hw/mips/bootloader.c | 6 +++--- hw/mips/boston.c | 2 +- hw/mips/fuloong2e.c | 2 +- hw/mips/malta.c | 2 +- 5 files changed, 10 insertions(+), 8 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index bc54ea8c7fb..173410f54ea 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -15,14 +15,16 @@ /** * bl_gen_jump_to: Generate bootloader code to jump to an address * + * @cpu: The MIPS CPU which will run the bootloader code * @ptr: Pointer to buffer where to write the bootloader code * @jump_addr: Address to jump to */ -void bl_gen_jump_to(void **ptr, target_ulong jump_addr); +void bl_gen_jump_to(const MIPSCPU *cpu, void **ptr, target_ulong jump_addr); /** * bl_gen_jump_kernel: Generate bootloader code to jump to a Linux kernel * + * @cpu: The MIPS CPU which will run the bootloader code * @ptr: Pointer to buffer where to write the bootloader code * @set_sp: Whether to set $sp register * @set_a0: Whether to set $a0 register @@ -36,7 +38,7 @@ void bl_gen_jump_to(void **ptr, target_ulong jump_addr); * @a3: Value to set $a0 to if @set_a3 is set * @kernel_addr: Start address of the kernel to jump to */ -void bl_gen_jump_kernel(void **ptr, +void bl_gen_jump_kernel(const MIPSCPU *cpu, void **ptr, bool set_sp, target_ulong sp, bool set_a0, target_ulong a0, bool set_a1, target_ulong a1, diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 7db3bf7511f..9b074d9903b 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -243,14 +243,14 @@ static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm) } /* Helpers */ -void bl_gen_jump_to(void **p, target_ulong jump_addr) +void bl_gen_jump_to(const MIPSCPU *cpu, void **p, target_ulong jump_addr) { bl_gen_load_ulong(p, BL_REG_T9, jump_addr); bl_gen_jalr(p, BL_REG_T9); bl_gen_nop(p); /* delay slot */ } -void bl_gen_jump_kernel(void **p, +void bl_gen_jump_kernel(const MIPSCPU *cpu, void **p, bool set_sp, target_ulong sp, bool set_a0, target_ulong a0, bool set_a1, target_ulong a1, @@ -274,7 +274,7 @@ void bl_gen_jump_kernel(void **p, bl_gen_load_ulong(p, BL_REG_A3, a3); } - bl_gen_jump_to(p, kernel_addr); + bl_gen_jump_to(cpu, p, kernel_addr); } void bl_gen_write_ulong(const MIPSCPU *cpu, void **p, diff --git a/hw/mips/boston.c b/hw/mips/boston.c index b646c104df7..f2c0e335e73 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -353,7 +353,7 @@ static void gen_firmware(const MIPSCPU *cpu, void *p, * a2/$6 = 0 * a3/$7 = 0 */ - bl_gen_jump_kernel(&p, + bl_gen_jump_kernel(cpu, &p, true, 0, true, (int32_t)-2, true, fdt_addr, true, 0, true, 0, kernel_entry); diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index c4080a8a6e3..1e55adacdd2 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -179,7 +179,7 @@ static void write_bootloader(const MIPSCPU *cpu, uint8_t *base, /* Second part of the bootloader */ p = (uint32_t *)(base + 0x040); - bl_gen_jump_kernel((void **)&p, + bl_gen_jump_kernel(cpu, (void **)&p, true, ENVP_VADDR - 64, true, 2, true, ENVP_VADDR, true, ENVP_VADDR + 8, diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 9bc3fc9da3e..f96a78d2939 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -681,7 +681,7 @@ static void bl_setup_gt64120_jump_kernel(MaltaState *s, void **p, cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), tswap32(ldl_be_p(pci_pins_cfg))); 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9dc8826sm152686025e9.11.2025.01.13.11.56.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:56:27 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 12/19] hw/mips/bootloader: Propagate CPU env to bl_gen_load_ulong() Date: Mon, 13 Jan 2025 20:55:18 +0100 Message-ID: <20250113195525.57150-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Propagate the target specific CPU env to the locally declared bl_gen_load_ulong() function. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 9b074d9903b..198506431c5 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -233,7 +233,8 @@ static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm) bl_gen_ori(p, rt, rt, extract64(imm, 0, 16)); } -static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm) +static void bl_gen_load_ulong(const CPUMIPSState *env, void **p, + bl_reg rt, target_ulong imm) { if (bootcpu_supports_isa(ISA_MIPS3)) { bl_gen_dli(p, rt, imm); /* 64bit */ @@ -245,7 +246,9 @@ static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm) /* Helpers */ void bl_gen_jump_to(const MIPSCPU *cpu, void **p, target_ulong jump_addr) { - bl_gen_load_ulong(p, BL_REG_T9, jump_addr); + const CPUMIPSState *env = &cpu->env; + + bl_gen_load_ulong(env, p, BL_REG_T9, jump_addr); bl_gen_jalr(p, BL_REG_T9); bl_gen_nop(p); /* delay slot */ } @@ -258,20 +261,22 @@ void bl_gen_jump_kernel(const MIPSCPU *cpu, void **p, bool set_a3, target_ulong a3, target_ulong kernel_addr) { + const CPUMIPSState *env = &cpu->env; + if (set_sp) { - bl_gen_load_ulong(p, BL_REG_SP, sp); + bl_gen_load_ulong(env, p, BL_REG_SP, sp); } if (set_a0) { - bl_gen_load_ulong(p, BL_REG_A0, a0); + bl_gen_load_ulong(env, p, BL_REG_A0, a0); } if (set_a1) { - bl_gen_load_ulong(p, BL_REG_A1, a1); + bl_gen_load_ulong(env, p, BL_REG_A1, a1); } if (set_a2) { - bl_gen_load_ulong(p, BL_REG_A2, a2); + bl_gen_load_ulong(env, p, BL_REG_A2, a2); } if (set_a3) { - bl_gen_load_ulong(p, BL_REG_A3, a3); + bl_gen_load_ulong(env, p, BL_REG_A3, a3); } bl_gen_jump_to(cpu, p, kernel_addr); @@ -280,8 +285,10 @@ void bl_gen_jump_kernel(const MIPSCPU *cpu, void **p, void bl_gen_write_ulong(const MIPSCPU *cpu, void **p, target_ulong addr, target_ulong val) { - bl_gen_load_ulong(p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); + const CPUMIPSState *env = &cpu->env; + + bl_gen_load_ulong(env, p, BL_REG_K0, val); + bl_gen_load_ulong(env, p, BL_REG_K1, addr); if (bootcpu_supports_isa(ISA_MIPS3)) { bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); } else { @@ -292,15 +299,19 @@ void bl_gen_write_ulong(const MIPSCPU *cpu, void **p, void bl_gen_write_u32(const MIPSCPU *cpu, void **p, target_ulong addr, uint32_t val) { + const CPUMIPSState *env = &cpu->env; + bl_gen_li(p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); + bl_gen_load_ulong(env, p, BL_REG_K1, addr); bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); } void bl_gen_write_u64(const MIPSCPU *cpu, void **p, target_ulong addr, uint64_t val) { + const CPUMIPSState *env = &cpu->env; + bl_gen_dli(p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); + bl_gen_load_ulong(env, p, BL_REG_K1, addr); bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); } From patchwork Mon Jan 13 19:55:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856946 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1601274wrc; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2ddcb5bsm190228695e9.23.2025.01.13.11.56.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:56:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 13/19] hw/mips/bootloader: Propagate CPU env to bl_gen_[d]li() Date: Mon, 13 Jan 2025 20:55:19 +0100 Message-ID: <20250113195525.57150-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Propagate the target specific CPU env to the locally declared bl_gen_li() and bl_gen_dli() functions. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 198506431c5..464ed5f4f1a 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -213,7 +213,8 @@ static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset) } /* Pseudo instructions */ -static void bl_gen_li(void **p, bl_reg rt, uint32_t imm) +static void bl_gen_li(const CPUMIPSState *env, void **p, + bl_reg rt, uint32_t imm) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { bl_gen_lui_nm(p, rt, extract32(imm, 12, 20)); @@ -224,9 +225,10 @@ static void bl_gen_li(void **p, bl_reg rt, uint32_t imm) } } -static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm) +static void bl_gen_dli(const CPUMIPSState *env, void **p, + bl_reg rt, uint64_t imm) { - bl_gen_li(p, rt, extract64(imm, 32, 32)); + bl_gen_li(env, p, rt, extract64(imm, 32, 32)); bl_gen_dsll(p, rt, rt, 16); bl_gen_ori(p, rt, rt, extract64(imm, 16, 16)); bl_gen_dsll(p, rt, rt, 16); @@ -237,9 +239,9 @@ static void bl_gen_load_ulong(const CPUMIPSState *env, void **p, bl_reg rt, target_ulong imm) { if (bootcpu_supports_isa(ISA_MIPS3)) { - bl_gen_dli(p, rt, imm); /* 64bit */ + bl_gen_dli(env, p, rt, imm); /* 64bit */ } else { - bl_gen_li(p, rt, imm); /* 32bit */ + bl_gen_li(env, p, rt, imm); /* 32bit */ } } @@ -301,7 +303,7 @@ void bl_gen_write_u32(const MIPSCPU *cpu, void **p, { const CPUMIPSState *env = &cpu->env; - bl_gen_li(p, BL_REG_K0, val); + bl_gen_li(env, p, BL_REG_K0, val); bl_gen_load_ulong(env, p, BL_REG_K1, addr); bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); } @@ -311,7 +313,7 @@ void bl_gen_write_u64(const MIPSCPU *cpu, void **p, { const CPUMIPSState *env = &cpu->env; - bl_gen_dli(p, BL_REG_K0, val); + bl_gen_dli(env, p, BL_REG_K0, val); bl_gen_load_ulong(env, p, BL_REG_K1, addr); bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); } From patchwork Mon Jan 13 19:55:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856954 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1601484wrc; Mon, 13 Jan 2025 11:58:15 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVK2Fh0eOgIL+CH3x0Arr3Dok+iyFerbv2V0m4wozpSN8mxfjp1zASX6hxjUhShxoaelWqNEQ==@linaro.org X-Google-Smtp-Source: AGHT+IG4UWsV7ni0XNoo1POXNZFH28k8BDBTDihDd51YLc3E4NIq74Vak6h763Tw8/87vEs1sE6u X-Received: by 2002:a05:620a:1a04:b0:7ac:a0a5:9bf4 with SMTP id af79cd13be357-7bcd97622efmr3847946985a.40.1736798295208; Mon, 13 Jan 2025 11:58:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736798295; cv=none; d=google.com; s=arc-20240605; b=C/Pdte6kiN5SNrdKuXUholErH5eYiMVPaiDsJEN+4u4hecoNScLIiQY+2Jui7Ry3i3 HKmeoLdQDbBUsqCk4n3SfZTC6ot+IaRh3EHhtCmUkXYYAlauWQMTK4yVXz46+8SzA6iF MarS5StD/Hy6zUYiL0cM28F/ojiX7/194Vpz4I7nC3bDikcV5wyCq5lZ4Qz2CtUAowih xbP07Rfe8tQiN8Ls9tEdl0dueWlIfmtYR0x0YB200os9++ZLWwd+b5UgpfSdGa/qF+c2 D5tjSxF0O0+oOgxtPAseV9qdsXRVr7d4IbqNYja7/mXZGTAJrV12yBHmqdGwPAi70KqD EJEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8+YIN1f80FVmcBoMH1oRH2tR6JuH5Kh9JlAiouQJECQ=; fh=wMwPlu6s3WDa+luMUca6ONpSmNJKUwF5E3uCFeq1PI4=; b=kRcWlBlKuKKfwVUZrrQCZRCCulaek5iUT5kdb3qe/i8TGT00OzBKDGNbJbqzhZtPJI fHyt4AX7vCvsxrmmlw4L/rUw55x2CkigQWZEskLMi7459C23RFN/6aZvNdxLqK9TLtVi hzPH/rRNX/2a1XK8deUtuyFU2SF4+R0ysTvNyi1KKN5ViYncUI7etX92peKMKgJ4AvfU au8GHXDNPc4qV0M84QQfncZ48TDeAx6WMOGnwjMnNc7Fq4B/DmS53Rw6J8+vZj7P4Tp2 +oeoMsB0ESpJVzumfP7Ktza7bVhaLHs4qTVT5IsLrTyzeCTw5Gy8zoNYGVBgOp8erFDe HCoA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bYG0stNo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=fail header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e3840bfsm13212260f8f.39.2025.01.13.11.56.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:56:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 14/19] hw/mips/bootloader: Propagate CPU env to bl_gen_s[w, d]() Date: Mon, 13 Jan 2025 20:55:20 +0100 Message-ID: <20250113195525.57150-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Propagate the target specific CPU env to the locally declared bl_gen_sw() and bl_gen_sd() functions. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 464ed5f4f1a..288dccce473 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -194,7 +194,8 @@ static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12) st_nm32_p(ptr, insn); } -static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset) +static void bl_gen_sw(const CPUMIPSState *env, void **p, + bl_reg rt, uint8_t base, uint16_t offset) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { bl_gen_sw_nm(p, rt, base, offset); @@ -203,7 +204,8 @@ static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset) } } -static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset) +static void bl_gen_sd(const CPUMIPSState *env, void **p, + bl_reg rt, uint8_t base, uint16_t offset) { if (bootcpu_supports_isa(ISA_MIPS3)) { bl_gen_i_type(p, 0x3f, base, rt, offset); @@ -292,9 +294,9 @@ void bl_gen_write_ulong(const MIPSCPU *cpu, void **p, bl_gen_load_ulong(env, p, BL_REG_K0, val); bl_gen_load_ulong(env, p, BL_REG_K1, addr); if (bootcpu_supports_isa(ISA_MIPS3)) { - bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sd(env, p, BL_REG_K0, BL_REG_K1, 0x0); } else { - bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sw(env, p, BL_REG_K0, BL_REG_K1, 0x0); } } @@ -305,7 +307,7 @@ void bl_gen_write_u32(const MIPSCPU *cpu, void **p, bl_gen_li(env, p, BL_REG_K0, val); bl_gen_load_ulong(env, p, BL_REG_K1, addr); - bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sw(env, p, BL_REG_K0, BL_REG_K1, 0x0); } void bl_gen_write_u64(const MIPSCPU *cpu, void **p, @@ -315,5 +317,5 @@ void bl_gen_write_u64(const MIPSCPU *cpu, void **p, bl_gen_dli(env, p, BL_REG_K0, val); bl_gen_load_ulong(env, p, BL_REG_K1, addr); - bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sd(env, p, BL_REG_K0, BL_REG_K1, 0x0); } From patchwork Mon Jan 13 19:55:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856957 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1601637wrc; Mon, 13 Jan 2025 11:58:44 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCViBJu1T2ib6IintNGgFJ+60DcDnZNlT4BKhuvjQb0zopL2g3b+MrVvHYn2bHiZntb57maW0Q==@linaro.org X-Google-Smtp-Source: AGHT+IFBy1Heou+ig2W/gkVPDatblLUWqARC0+R6wl6hNK0TnZXXOMy2Pyi00nwbnkJ5mBnEjmlK X-Received: by 2002:a05:6214:5004:b0:6d8:9e64:c9d3 with SMTP id 6a1803df08f44-6df9b2d5d2dmr250085916d6.30.1736798324518; Mon, 13 Jan 2025 11:58:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736798324; cv=none; d=google.com; s=arc-20240605; b=ScsSMvEJd6DGGHPSM8c5AOjU63fBvsNw6QSEEmzmIi6zym1nS+Mq0AfZdixRIB8bee iZjpXoTVmbemiK3igJxYXONzidqyAFEB1vgyKXJVmgJ0igXsFA0KHwr55k1MbN+TDdJ0 2pqQvD0RR6xy2G8scc820OU8HhjJLBVX2xNA5vGisWO2qkCeD0VY2f08kK3n2KXW8EmM i1B+MztDytzBfHvdpwRtb06anrSiE1iuL5C7atuPfyZk7B8QXFMFjUiO3hXAnlVTVdTo Ad8PucNGEJHc+Ebj7DRKqyW5lisVCthiKHEloF36Eof/4hnZ72sot6qI8B5tP7N+p5ln T9HQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=FqRH3YIN+zJIf0SKXmNG5cYuASAzw080yXp4y743Edg=; fh=wMwPlu6s3WDa+luMUca6ONpSmNJKUwF5E3uCFeq1PI4=; b=RNCIHF+/wUO8VXyzeu7pg6V3JkXqJvhXYAmnOaj0GL9b/t6W8zSCkn+pamsnosoa9m NLVxj62hYGdmAJOazCrWY+4h4G33Fdy6JfvshOipt8sewJa7hQN6Jjl3FHaML4uYFaFZ cKEHLs4V+y0nG2cIE389yseKFuMtIUDjOUySUEWly6ty/l7/vggQ/ekB5sRc5iz9JGsZ 6U+GSlZ/wUNYobUJcySL5q2+4qY4F434mCeTfhPJ70cZuzzkKrmU4fxk0z4yd3V7cY3/ IRIHtV5Wg/AoNRXAV5scjXPkr1yrIQ2y19Y591Uybnjwli+7sT8eB0wOwiHSqynB2vyZ Ikew==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R8vnZS0a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e4b8299sm12997724f8f.74.2025.01.13.11.56.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:56:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 15/19] hw/mips/bootloader: Propagate CPU env to bl_gen_jalr() Date: Mon, 13 Jan 2025 20:55:21 +0100 Message-ID: <20250113195525.57150-16-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Propagate the target specific CPU env to the locally declared bl_gen_jalr() function. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 288dccce473..a0fc840e89f 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -127,7 +127,7 @@ static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa) } } -static void bl_gen_jalr(void **p, bl_reg rs) +static void bl_gen_jalr(const CPUMIPSState *env, void **p, bl_reg rs) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { uint32_t insn = 0; @@ -253,7 +253,7 @@ void bl_gen_jump_to(const MIPSCPU *cpu, void **p, target_ulong jump_addr) const CPUMIPSState *env = &cpu->env; bl_gen_load_ulong(env, p, BL_REG_T9, jump_addr); - bl_gen_jalr(p, BL_REG_T9); + bl_gen_jalr(env, p, BL_REG_T9); bl_gen_nop(p); /* delay slot */ } From patchwork Mon Jan 13 19:55:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856948 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1601320wrc; Mon, 13 Jan 2025 11:57:45 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCV7ftSla7VuiiK1GTe3xiSFXJoLHJEY3iM4s9CmPzf8FmfVCn/AhTAicju3NlIo2O4mHlP6WA==@linaro.org X-Google-Smtp-Source: AGHT+IHZSd30qNdHVhQBmM1so/fgGRUwouL0axxudeOi9T7bTU+3OzybTmNdX//DlZherRzNllL/ X-Received: by 2002:a05:620a:4792:b0:7bc:dec0:2bed with SMTP id af79cd13be357-7bcdec02e42mr2748894785a.7.1736798265162; Mon, 13 Jan 2025 11:57:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736798265; cv=none; d=google.com; s=arc-20240605; b=FWd7J9An9wq2+s3PEGidsWDltycU6Ce5s5dATQZFX+F9Ih8/9XhGaDDMS8plgPf4LC LJCpv/+GihQtgdAgwV6fUrfeDi34r6NAmitp2ztelXPojifcLq5S1JzDXwJgQT+JeP5v /JV6op5sBA9RyfsdzsE0iqBL06I34yW6qYpqdvHUDc6F2PfL8w85p+NnM/1kMJOyU2qF MS+7TUclf0gIArRR3KC3MZjd0NvU05dWXm5ydVzDN8nUZ6gtwp7Cg6eZjipAaX3znj0s 4E1fvOnjZRCgQ1egDCFWRbSgycKljq1nzLLTfRibuJv7NqYwlvg4mPbZoax2gy9VWeap z+LQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=JbHDNHtZHrM8bnAI4XGM3Ol5IwOL8ZDw/7AER4oObB8=; fh=wMwPlu6s3WDa+luMUca6ONpSmNJKUwF5E3uCFeq1PI4=; b=M112chdaG00ZCeqcWOViwkKKwQxhjKq7J6JiDWDUQs7SZpxC2sv1Ks8rkEuvwo3RHc 2jlIaGmGmhUJw3PChkO2MAWWMlI14CgusQIwwBK7WNVXPnmILfyPVnlW6bAQVumnbsfV 7YdVYsfZVneFO+QHqvsSCZCgxbfzfJ03sxobrayb9UFdgtf6WyC96dx2cQIbg9FnOiyE u4xTJozDeWrHuro2BCX/a1V8HPyZEP91jhWol87ZTYJuNZajTMt9THcmixH1dwpzL8Er 5tNcLZpi8bQgTAxaMKe6wlpSerxvv++q7zYuUR9wlSS+fYAEVaVTklFvW19pyga5UJuf OOyQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fKCTQ2aG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index a0fc840e89f..e57d5c3278f 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -118,7 +118,8 @@ static void bl_gen_i_type(void **ptr, uint8_t opcode, } /* Single instructions */ -static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa) +static void bl_gen_dsll(const CPUMIPSState *env, void **p, + bl_reg rd, bl_reg rt, uint8_t sa) { if (bootcpu_supports_isa(ISA_MIPS3)) { bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38); @@ -231,9 +232,9 @@ static void bl_gen_dli(const CPUMIPSState *env, void **p, bl_reg rt, uint64_t imm) { bl_gen_li(env, p, rt, extract64(imm, 32, 32)); - bl_gen_dsll(p, rt, rt, 16); + bl_gen_dsll(env, p, rt, rt, 16); bl_gen_ori(p, rt, rt, extract64(imm, 16, 16)); - bl_gen_dsll(p, rt, rt, 16); + bl_gen_dsll(env, p, rt, rt, 16); bl_gen_ori(p, rt, rt, extract64(imm, 0, 16)); } From patchwork Mon Jan 13 19:55:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856945 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1601208wrc; Mon, 13 Jan 2025 11:57:18 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVBv2qYsIkvn/+wKaU9DVbF7FBf3V9wNPj31A3wgl4j6RPoAHBjwAG2FEVwSyxbGXPL9UT2Bg==@linaro.org X-Google-Smtp-Source: AGHT+IF0YAVOhsHowLJh/zmEft5J1+dWCIUFUcUKrBK+FrAPoJHyA3GKEavw5/7NnfI6r5+tBOj1 X-Received: by 2002:a05:620a:318b:b0:7b6:6a3b:539b with SMTP id af79cd13be357-7bcd973ef38mr3084538585a.17.1736798238192; Mon, 13 Jan 2025 11:57:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736798238; cv=none; d=google.com; s=arc-20240605; b=lKb76mZx8fRdsCXgGd6aC7EPrxI5WA6nd/uTscJgCEzs34yfAZl2PDcuiIeBq7MCzl imuUOXa72s2I77Xk2YhaJneKyN9QMNlMZ6T31Qa8mlTDSrwd3VSE8ReLz91K8AmUXnlU QMi1gLZFMge/FySfsnGddmLTUc643oSvOJKaqnR8SjOtHJBGiXgdkfj5mVu8QsUNmxSv PGvd9XVZ1VczmM4VRm7TxUxu9nA150pCeJGMUSJa6+qTxaNRHmNvrL0rqwARA2Wbedsp MzFRYiOP+QrnzUvcMQmO/P2/Uwx6uOkSuxgBBF+Sv5OgqYjO007opnqyZHNDPNNFbniN RUqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=T91VVeNWf9GIIc/CEXCMK78y9ZI5LIeof3gskqolzuI=; fh=wMwPlu6s3WDa+luMUca6ONpSmNJKUwF5E3uCFeq1PI4=; b=AU5VZhW19pr4YDdZs0v6g54Y80gFRuitL1jocd77munxHnh0S+9c+4ZCb5qOMwYwNW fbVjcMudZj+Xy6B8tiHao1lhU8e+weLN8oPjLEbzEHZiJHQOiXG9wtzxqyMYCb2xN6hX bJxDt2Wf+XqI0RXz+y/VJBJCOB2ug58KagUWmevAyrGbHBmJkGPAtNrPZRBT65INv/KQ N1lUMb4jMGclG78QPWC79t7dgJ9d24qDcNBhF9KZfipF9FghRE9r0YTFNRUmMwcPe50n wylTEOZnHfQc94w0gjlWKKk/fXyph4iwAVHqPDR8oL+zlmmZbN9U357sVMoil3x//zOr hrdg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=axpLU6q3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index e57d5c3278f..a54af8160ef 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -67,7 +67,7 @@ static void st_nm32_p(void **ptr, uint32_t insn) } /* Base types */ -static void bl_gen_nop(void **ptr) +static void bl_gen_nop(const CPUMIPSState *env, void **ptr) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { st_nm32_p(ptr, 0x8000c000); @@ -255,7 +255,7 @@ void bl_gen_jump_to(const MIPSCPU *cpu, void **p, target_ulong jump_addr) bl_gen_load_ulong(env, p, BL_REG_T9, jump_addr); bl_gen_jalr(env, p, BL_REG_T9); - bl_gen_nop(p); /* delay slot */ + bl_gen_nop(env, p); /* delay slot */ } void bl_gen_jump_kernel(const MIPSCPU *cpu, void **p, From patchwork Mon Jan 13 19:55:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 856949 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1601355wrc; Mon, 13 Jan 2025 11:57:51 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVV31yCeU06v9pk8c8c4SjkauwFCw4+8M5JPioJXFT4FpfrQZ3A2q3Pb8jK/gS8IBs/JnPExA==@linaro.org X-Google-Smtp-Source: AGHT+IGQXY2fY/ySgEVw++B8y94mqkOl7tjF5h6uMOo9dki4mwVkbBACrkJt9ruRfLQpitaaxi63 X-Received: by 2002:a05:622a:1817:b0:46c:7844:963e with SMTP id d75a77b69052e-46c78452596mr270542301cf.8.1736798271197; Mon, 13 Jan 2025 11:57:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736798271; cv=none; d=google.com; s=arc-20240605; b=abfMO8HnCGQFae2PFmqdd0FZiLOK1kkc9iZ2uHvYqxSA/6yVNLwHaLfeg1JROZ8db2 eEbCbJWGMCv+7ApEu/jxya5e1waTAsVoeGFsDEvaRZ4Jag21YMcsi0gnUdHGkhntVBLs HM1FPDCUgUXZ6cJEtkODIquMntsMCL3UqadPxPKhnzeFubVRYvxscj8KeV5ktXA+m0ZD +bBWYb9rYwzwinyFQFgKUY93rzFo65qGza1XQncHaNi23wOrKTA0GvpDaydjTgJ0PW9u R2OVtO7IsVTj0+oNSG+FXq+/P1/+cFNDRx5n5gspk6/npTUII+0ie/YPPQ+yRADMsF10 rsRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8lF9ZX3ePxEP+Ja3OcSq5ETj9a2lfeHBgYz0T+6A3ww=; fh=wMwPlu6s3WDa+luMUca6ONpSmNJKUwF5E3uCFeq1PI4=; b=GKrJPJPdVqdyHiVL1v3SGg+H5heLJjksvmwgzrgOGPJJhKmgG+i89z+vD+vFl+jESy ILrsAL+cDvXIRSluEnqmDUBEHDKrT0Bvxy3QW07mq9N7xXaCPPByZXGME6w/UVnZGj46 DTKOVu0mXrEcRNrqvq4GbS9JyrnkT2bC2YYEg/Xb5lDVgJSth7eOiGLo8dy6n3rOl0dW 4EXeqmnE09bWRFoFiDDoB7HqnpKA5LixLA0eVlaTwen4WEg2lcRWTksagMDygO0IAUX0 J1WHIwExyDFPq+23IQzKgDMAyxXtxKXGG6JKrvfYCxm6+/KiFUv4/0FHGuETJviJVAQF i5ZQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="U/ziuPYs"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2df2faesm188925685e9.26.2025.01.13.11.56.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:56:57 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 18/19] hw/mips/bootloader: Propagate CPU env to bootcpu_supports_isa() Date: Mon, 13 Jan 2025 20:55:24 +0100 Message-ID: <20250113195525.57150-19-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Propagate the target specific CPU env to the locally declared bootcpu_supports_isa() function. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index a54af8160ef..f02e5aabe48 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -49,7 +49,7 @@ typedef enum bl_reg { BL_REG_RA = 31, } bl_reg; -static bool bootcpu_supports_isa(uint64_t isa_mask) +static bool bootcpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) { return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask); } @@ -69,7 +69,7 @@ static void st_nm32_p(void **ptr, uint32_t insn) /* Base types */ static void bl_gen_nop(const CPUMIPSState *env, void **ptr) { - if (bootcpu_supports_isa(ISA_NANOMIPS32)) { + if (bootcpu_supports_isa(env, ISA_NANOMIPS32)) { st_nm32_p(ptr, 0x8000c000); } else { uint32_t *p = *ptr; @@ -121,7 +121,7 @@ static void bl_gen_i_type(void **ptr, uint8_t opcode, static void bl_gen_dsll(const CPUMIPSState *env, void **p, bl_reg rd, bl_reg rt, uint8_t sa) { - if (bootcpu_supports_isa(ISA_MIPS3)) { + if (bootcpu_supports_isa(env, ISA_MIPS3)) { bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38); } else { g_assert_not_reached(); /* unsupported */ @@ -130,7 +130,7 @@ static void bl_gen_dsll(const CPUMIPSState *env, void **p, static void bl_gen_jalr(const CPUMIPSState *env, void **p, bl_reg rs) { - if (bootcpu_supports_isa(ISA_NANOMIPS32)) { + if (bootcpu_supports_isa(env, ISA_NANOMIPS32)) { uint32_t insn = 0; insn = deposit32(insn, 26, 6, 0b010010); /* JALRC */ @@ -198,7 +198,7 @@ static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12) static void bl_gen_sw(const CPUMIPSState *env, void **p, bl_reg rt, uint8_t base, uint16_t offset) { - if (bootcpu_supports_isa(ISA_NANOMIPS32)) { + if (bootcpu_supports_isa(env, ISA_NANOMIPS32)) { bl_gen_sw_nm(p, rt, base, offset); } else { bl_gen_i_type(p, 0x2b, base, rt, offset); @@ -208,7 +208,7 @@ static void bl_gen_sw(const CPUMIPSState *env, void **p, static void bl_gen_sd(const CPUMIPSState *env, void **p, bl_reg rt, uint8_t base, uint16_t offset) { - if (bootcpu_supports_isa(ISA_MIPS3)) { + if (bootcpu_supports_isa(env, ISA_MIPS3)) { bl_gen_i_type(p, 0x3f, base, rt, offset); } else { g_assert_not_reached(); /* unsupported */ @@ -219,7 +219,7 @@ static void bl_gen_sd(const CPUMIPSState *env, void **p, static void bl_gen_li(const CPUMIPSState *env, void **p, bl_reg rt, uint32_t imm) { - if (bootcpu_supports_isa(ISA_NANOMIPS32)) { + if (bootcpu_supports_isa(env, ISA_NANOMIPS32)) { bl_gen_lui_nm(p, rt, extract32(imm, 12, 20)); bl_gen_ori_nm(p, rt, rt, extract32(imm, 0, 12)); } else { @@ -241,7 +241,7 @@ static void bl_gen_dli(const CPUMIPSState *env, void **p, static void bl_gen_load_ulong(const CPUMIPSState *env, void **p, bl_reg rt, target_ulong imm) { - if (bootcpu_supports_isa(ISA_MIPS3)) { + if (bootcpu_supports_isa(env, ISA_MIPS3)) { bl_gen_dli(env, p, rt, imm); /* 64bit */ } else { bl_gen_li(env, p, rt, imm); /* 32bit */ @@ -294,7 +294,7 @@ void bl_gen_write_ulong(const MIPSCPU *cpu, void **p, bl_gen_load_ulong(env, p, BL_REG_K0, val); bl_gen_load_ulong(env, p, BL_REG_K1, addr); - if (bootcpu_supports_isa(ISA_MIPS3)) { + if (bootcpu_supports_isa(env, ISA_MIPS3)) { bl_gen_sd(env, p, BL_REG_K0, BL_REG_K1, 0x0); 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2da66fcsm189336025e9.6.2025.01.13.11.57.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:57:03 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 19/19] hw/mips/bootloader: Remove use of &first_cpu in bootcpu_supports_isa() Date: Mon, 13 Jan 2025 20:55:25 +0100 Message-ID: <20250113195525.57150-20-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index f02e5aabe48..1969610224d 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -51,7 +51,7 @@ typedef enum bl_reg { static bool bootcpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) { - return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask); + return cpu_supports_isa(env, isa_mask); } static void st_nm32_p(void **ptr, uint32_t insn)