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[209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-46c8735079asi87756361cf.186.2025.01.13.05.55.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 13 Jan 2025 05:55:00 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H71Rx1zB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tXKtk-0005ZA-9c; Mon, 13 Jan 2025 08:54:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tXKtV-0005Xd-AU for qemu-devel@nongnu.org; Mon, 13 Jan 2025 08:54:17 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tXKtR-0007eI-T1 for qemu-devel@nongnu.org; Mon, 13 Jan 2025 08:54:15 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4361f796586so44620625e9.3 for ; Mon, 13 Jan 2025 05:54:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1736776451; x=1737381251; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=6HdlJP/oiGVeqg3ZfL2mL0VTspYLYi3EUJzilx+oDbA=; b=H71Rx1zBpsW/rJ4hb9u2EylLBlNZFpglbLTso+jIcI4uh7V9ARrDrbdIehdO/y7CAY ahd1jHDNY9kcw5yN7cN044DQvsCCgHnK1Z+OpcljKfA+mRP+kua1EThX5lx+85XG10Ag c38bLayAFoopPBSVlqJ0k00J95wHJfAULJjsC/jaesYnfgAz2IwiylV+rNnBSj+T/MSm ePCuTlg1AXd3xbHbrhIB0vpnRk9FERvKM2xW3W2tfFn44fToUBWXjUi3ZQF6e0tKCkxC +lzuPrsQI5TXdPiPTGrfIsdZaTw77hsGFasBoDQlBsunUwdAllsfWlRlqBO5UVCzpcer PQyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736776451; x=1737381251; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6HdlJP/oiGVeqg3ZfL2mL0VTspYLYi3EUJzilx+oDbA=; b=qyzHn8VbvbD94UWIn58zI3KgZdMEIVD3/KbyNkFmXCHDIGabu9SYtFV0/R7icLPeNE zwlqFkGKXdiVEUoLnb/7+gplgSbCnWObktFR6KK6lyYpetCJbsdkNdVKltuzUfs1uJVg GIr1+IQ/dydQ+FgfvaODAI7GG7JfvLYcnHbHi8NG+e374dWK5kKR31UndHzKIH6sZtU8 TLZoD6vOFWTS6FCn8HVzSeaR1qHnCGNP3YDlSFUIVCUrMlNQGIiLe/eFPzdxEualIUOd 5QGKqyYmbWKrs0kr4KQJnbpBBKJU9YNPXR6YQDBZAvdn0bBlFl6LgpMmzICcFUjRMGgO rUBA== X-Gm-Message-State: AOJu0YxDWDd2WzVKjsN02L1JxQ8B2yfoVc/2eJZyy02xAgLxli1G7YYI KmVhu/yw+ncSO/xBlo/wwhOsgBzFJrEyjKH6OuAnRP+FxzIpIpcd/LwBULlm7IFbQSsoYRE8msO 8 X-Gm-Gg: ASbGncsyVSDLDGu5xzKNhiH/BZRCdSaw1NgxBTKQlorl28/VOpX1TZmSQl+ZL1qhi3Z /Pfw9vIPnAEJt19o2aMnYjBxFWhCSBvUTc29uE1d2yXWfJvsQrZ0rYIDQYU4oIBL1k1cXgRlmI6 TcJhONOFlpohVtydhSKuBrcs07ny7pkWe0TRSpm1xFm3aB4dl1kVJhGdwWEZUeFXB6OV8C/u3Vy qRWco4flYcjI91kruu83r10MqRjuN+UfuDUBai+tmrX0qQFL0E04Ug8bH+TU0k= X-Received: by 2002:a05:600c:1987:b0:434:fddf:5c0c with SMTP id 5b1f17b1804b1-436e2679e05mr192322235e9.4.1736776451605; Mon, 13 Jan 2025 05:54:11 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d8fba4sm145245205e9.4.2025.01.13.05.54.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 05:54:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/11] hw/arm_sysctl: fix extracting 31th bit of val Date: Mon, 13 Jan 2025 13:53:58 +0000 Message-Id: <20250113135408.3164401-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250113135408.3164401-1-peter.maydell@linaro.org> References: <20250113135408.3164401-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Anastasia Belova 1 << 31 is casted to uint64_t while bitwise and with val. So this value may become 0xffffffff80000000 but only 31th "start" bit is required. This is not possible in practice because the MemoryRegionOps uses the default max access size of 4 bytes and so none of the upper bytes of val will be set, but the bitfield extract API is clearer anyway. Use the bitfield extract() API instead. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Anastasia Belova Message-id: 20241220125429.7552-1-abelova@astralinux.ru Reviewed-by: Peter Maydell [PMM: add clarification to commit message] Signed-off-by: Peter Maydell --- hw/misc/arm_sysctl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/misc/arm_sysctl.c b/hw/misc/arm_sysctl.c index 016a302e679..01663407eca 100644 --- a/hw/misc/arm_sysctl.c +++ b/hw/misc/arm_sysctl.c @@ -520,7 +520,7 @@ static void arm_sysctl_write(void *opaque, hwaddr offset, * as zero. */ s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31)); - if (val & (1 << 31)) { + if (extract64(val, 31, 1)) { /* Start bit set -- actually do something */ unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4); unsigned int function = extract32(s->sys_cfgctrl, 20, 6); From patchwork Mon Jan 13 13:53:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 856923 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1434546wrc; Mon, 13 Jan 2025 05:55:36 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUJ2rYAebGnWDsT1OkLMxhqE/F6G2pZzmqxIJBZW8NuFJaNHmtLdOwarA5PLuhLJsUpiQWt+A==@linaro.org X-Google-Smtp-Source: AGHT+IEAAmf8kp3PTsvHV6qU9mRz3/lAMZ+aLX3s9VDBbWk7+CkSCueJSb3kDKPkrwWVCp7VH1C1 X-Received: by 2002:ac8:5fd2:0:b0:467:81f0:6d63 with SMTP id d75a77b69052e-46c71003325mr329326991cf.17.1736776536693; Mon, 13 Jan 2025 05:55:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736776536; cv=none; d=google.com; s=arc-20240605; b=a/uSZcS7G8d4c3KxaIZZDgBr5Dg8WR+Yu+f9rmL74Z3OCbj/fse1uqrJb5xDiyEhOV gyhw+UBBPVG8kBxiGsz/bCCKdxBqNcdHHDHOLNSDPgoDbuJ2xTO7uiuExb5/d2/YNeBF uXgnwyDdleaT/b9SYzzjubKM8XGi4iunlt/gEeIIT6612L9lG/Bn+tcK61JJrmFrkvYU JMF9IVvBCZfKz1v5RCiZXirgn8hbPALRWzsZZ/geqSJJ5zLmszdex47g/IC7Llb9blIr 5M0fsDKSAIYqe5Azwl4k+NEpWuVr1ApxWa+K0lU0aF/E3SSnjwK264SOrOVlLNyuv+/j 5YcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HQO9GVDNQTUiwYqISYlU2glyJAveShyUsrRw4PZ/cEo=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=ktw+N64e+suY/sb2G9JV5UZQ2hlDMK5cRSHwCO8mtZsyGw5He6T+X8a4mhz7fptGo4 tUirbSL7TU5Fc+NFQfl+VWNDCcyGV3CKcbGW2/N8pT+1H7EX/n6WkYj7unuxRyDbTxaF S8lYh6R7joUBXvbW54qD27TU+JynsYOEyXQUzSUFDrHqIc6LGbcTpyUsTmi83Q6i0JeU /y2ztA/pvFXcReOiaehT8Z7Y7DR+JlPQT2AIyUzfAuW418N2xizQoF+TnoTOW0dLjRQ8 +xW0jLoHubeqRZv3KckzylF8ON/9npitYrEErpycFi1BmFrUxeanWVaIIB5ZldJ9asLM EMhA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ihP0b7lE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d8fba4sm145245205e9.4.2025.01.13.05.54.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 05:54:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/11] hw/misc: cast rpm to uint64_t Date: Mon, 13 Jan 2025 13:53:59 +0000 Message-Id: <20250113135408.3164401-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250113135408.3164401-1-peter.maydell@linaro.org> References: <20250113135408.3164401-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Tigran Sogomonian The value of an arithmetic expression 'rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION' is a subject to overflow because its operands are not cast to a larger data type before performing arithmetic. Thus, need to cast rpm to uint64_t. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Tigran Sogomonian Reviewed-by: Patrick Leis Reviewed-by: Hao Wu Message-id: 20241226130311.1349-1-tsogomonian@astralinux.ru Signed-off-by: Peter Maydell --- hw/misc/npcm7xx_mft.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/misc/npcm7xx_mft.c b/hw/misc/npcm7xx_mft.c index 9fcc69fe5c5..e565cac05d8 100644 --- a/hw/misc/npcm7xx_mft.c +++ b/hw/misc/npcm7xx_mft.c @@ -172,8 +172,9 @@ static NPCM7xxMFTCaptureState npcm7xx_mft_compute_cnt( * RPM = revolution/min. The time for one revlution (in ns) is * MINUTE_TO_NANOSECOND / RPM. */ - count = clock_ns_to_ticks(clock, (60 * NANOSECONDS_PER_SECOND) / - (rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION)); + count = clock_ns_to_ticks(clock, + (uint64_t)(60 * NANOSECONDS_PER_SECOND) / + ((uint64_t)rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION)); } if (count > NPCM7XX_MFT_MAX_CNT) { From patchwork Mon Jan 13 13:54:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 856931 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1435588wrc; Mon, 13 Jan 2025 05:58:24 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVLj21XqZ41PWDdKV4Q7Mk2Zvg+Y7VVpepovOw9AyUFE64xYE7Et5na1qki+a6HOzUz8UJwoA==@linaro.org X-Google-Smtp-Source: AGHT+IEim561z+JXzJaLxPByziNCfKEzl9rAXUnZMJCzLxX2aMHlLGBBn7v//PHKYUj6ary6TLm7 X-Received: by 2002:a05:620a:2add:b0:7bc:e736:27f2 with SMTP id af79cd13be357-7bce73628eamr1747498285a.18.1736776704687; Mon, 13 Jan 2025 05:58:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736776704; cv=none; d=google.com; s=arc-20240605; b=OcJHxpBfxqPEA5GB5vJJJW1AKqE2O2mO4k08nY2gNt9lEhhX5OJulHY8N+/A1vZWWX yXabEHs6em6NGUj0MluQaBH/afqyB4msZ8BwZHDjQFzsixLN8LSC4YTTz7sDS6juBWud C6FfftkuPLub1f1OX08UZx4crofWz/tcHo5HeyfKRSbz4dDItG/ajpUvjxbA1QdcMNzI Y8ez2E737r8QlPcFqD4w52eMfjfBnJ4rLQWSFPTUfHpd3x7t10iGmvBiQBVupUKEy5KQ G/v4cYQlji9NESK7BD/17SaE8TUI745GX+KI6eYWE4t3Dw7YCZ5/2P6wygqaCK+yNg17 rkbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=79v/1gKgmYQk7SK0X40y7DTYrx0JaX5qxpw+HIAXaes=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=D/NP2FKAhGkcuRh0UaNpq3+BnSfz68mEY9Wax2/gNnepDSK5OlvrbudM8t9W/RCNix CgjwFosXF+I/BCSI+4qaZBgKr5ea9L2Ko6ruPJdKPlIsuZ339O9sKdb3u1tRW8EGm7rG PKVy+O5obPMHMCmWD5R8n0Jhns0Km1hETHjSzS2Bsx2VkCTsBsKabCWbjWVAOngpFHMn YlTrYuXZCezukG3T+bFCOQgJMh+23n4+Pk4TJ5rvE6mvo/h5BCnHc+wtZjyP4akWrEA+ gBX3EVakeL7nNe6tnPoFcXheqtN99LcSvIylD+MbNgYWCLg2GO4CkmF+kE6+cCCTL89T GUXg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rBw3TyTO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d8fba4sm145245205e9.4.2025.01.13.05.54.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 05:54:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/11] tests/qtest/boot-serial-test: Improve ASM comments of PL011 tests Date: Mon, 13 Jan 2025 13:54:00 +0000 Message-Id: <20250113135408.3164401-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250113135408.3164401-1-peter.maydell@linaro.org> References: <20250113135408.3164401-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Re-indent ASM comments adding the 'loop:' label. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Fabiano Rosas Signed-off-by: Peter Maydell --- tests/qtest/boot-serial-test.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c index 3b92fa5d506..a71d2857807 100644 --- a/tests/qtest/boot-serial-test.c +++ b/tests/qtest/boot-serial-test.c @@ -70,18 +70,18 @@ static const uint8_t kernel_plml605[] = { }; static const uint8_t bios_raspi2[] = { - 0x08, 0x30, 0x9f, 0xe5, /* ldr r3,[pc,#8] Get base */ - 0x54, 0x20, 0xa0, 0xe3, /* mov r2,#'T' */ - 0x00, 0x20, 0xc3, 0xe5, /* strb r2,[r3] */ - 0xfb, 0xff, 0xff, 0xea, /* b loop */ - 0x00, 0x10, 0x20, 0x3f, /* 0x3f201000 = UART0 base addr */ + 0x08, 0x30, 0x9f, 0xe5, /* loop: ldr r3, [pc, #8] Get &UART0 */ + 0x54, 0x20, 0xa0, 0xe3, /* mov r2, #'T' */ + 0x00, 0x20, 0xc3, 0xe5, /* strb r2, [r3] *TXDAT = 'T' */ + 0xfb, 0xff, 0xff, 0xea, /* b -12 (loop) */ + 0x00, 0x10, 0x20, 0x3f, /* UART0: 0x3f201000 */ }; static const uint8_t kernel_aarch64[] = { - 0x81, 0x0a, 0x80, 0x52, /* mov w1, #0x54 */ - 0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 */ - 0x41, 0x00, 0x00, 0x39, /* strb w1, [x2] */ - 0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */ + 0x81, 0x0a, 0x80, 0x52, /* loop: mov w1, #'T' */ + 0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 Load UART0 */ + 0x41, 0x00, 0x00, 0x39, /* strb w1, [x2] *TXDAT = 'T' */ + 0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */ }; static const uint8_t kernel_nrf51[] = { From patchwork Mon Jan 13 13:54:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 856930 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1435507wrc; Mon, 13 Jan 2025 05:58:11 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW6LZ8pg+X5x8JZlAoC/TZ8iZUN2kvheLG05ZQr953Bje9vNJ/ElJDrm4NtEqtKBKwSh7xumw==@linaro.org X-Google-Smtp-Source: AGHT+IExILEbry2hForn3WdK5Uuh242ysaVryQ5hzGb6qoWiHT4Nbl5UiFeT9obz8dKNwpwVxuRj X-Received: by 2002:a05:620a:318b:b0:7b8:627c:5fc3 with SMTP id af79cd13be357-7bcd96e5824mr3318618785a.5.1736776690864; Mon, 13 Jan 2025 05:58:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736776690; cv=none; d=google.com; s=arc-20240605; b=YbxZnJBiNw+0+LS9GLfYvxBkzPSkF1nhKSGDhYl8KN2mBYZ06gpEa/7mBZXKUDv172 psWJRIoK5ToxmIYbglURhhdXcIGv4gCNlIx+UPRHlQz4teDDh421MeKvzywWXeDe5U6g w5zz5SY6J0cXmV9btwv9dywYp5xqNLXasQ+WyaZXQeMaoREoY+BSibuq+EA2Eb65vM9h JS73Rt3FFLyQncD/Pa+Bz47gNSSv2o75k9Yv3iow8GsZREYgQQeLv+ghmIuo+Mulpq4u 4uLImtuJxM77JOMFRyHt6PE7JRWRZ4fJflFdFIdZbVXH8S07EqDAUhpamSpXPc47d2P6 xg1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1ldNjIBGlXcB7GHvIaahhXw/jNRalb5uO3ZvAdqQJUU=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Op2m0S1S5zGtDsJqNyl929JSV7bJ1b0PN/njFT0e1FrUmdqsML9MtZntUbG5xIzBlT gs7/h77Dczi5gw8Puap+4olsJOxo33A0Wt+THe2XCq2G/oEPz3MXZGVrliJ7yb+YElHT b2jaM+JqH5gBfQBvmyB+7zfjwHFXzmnHobbBj3WXv2t7Ut7+6Y6CjKFUoTESsXcWR7BG Wz3jSG0Orq+t78k1yb1CPMGc5pVd4bBgYk+7lyxQjW5ynLksoatnpE0R16qUaXpZ1iLa YpimN+HxEKi3WiHC6dg/96em5cSAZwQhC8gMazrZ4mD7z0npkiZ0xZYcccpgi89z2ma1 gpQQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Tv5KBuYT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d8fba4sm145245205e9.4.2025.01.13.05.54.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 05:54:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/11] tests/qtest/boot-serial-test: Reduce for() loop in PL011 tests Date: Mon, 13 Jan 2025 13:54:01 +0000 Message-Id: <20250113135408.3164401-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250113135408.3164401-1-peter.maydell@linaro.org> References: <20250113135408.3164401-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Since registers are not modified, we don't need to refill their values. Directly jump to the previous store instruction to keep filling the TXDAT register. The equivalent C code remains: while (true) { *UART_DATA = 'T'; } Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Fabiano Rosas Signed-off-by: Peter Maydell --- tests/qtest/boot-serial-test.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c index a71d2857807..553575ca75c 100644 --- a/tests/qtest/boot-serial-test.c +++ b/tests/qtest/boot-serial-test.c @@ -70,18 +70,18 @@ static const uint8_t kernel_plml605[] = { }; static const uint8_t bios_raspi2[] = { - 0x08, 0x30, 0x9f, 0xe5, /* loop: ldr r3, [pc, #8] Get &UART0 */ + 0x08, 0x30, 0x9f, 0xe5, /* ldr r3, [pc, #8] Get &UART0 */ 0x54, 0x20, 0xa0, 0xe3, /* mov r2, #'T' */ - 0x00, 0x20, 0xc3, 0xe5, /* strb r2, [r3] *TXDAT = 'T' */ - 0xfb, 0xff, 0xff, 0xea, /* b -12 (loop) */ + 0x00, 0x20, 0xc3, 0xe5, /* loop: strb r2, [r3] *TXDAT = 'T' */ + 0xff, 0xff, 0xff, 0xea, /* b -4 (loop) */ 0x00, 0x10, 0x20, 0x3f, /* UART0: 0x3f201000 */ }; static const uint8_t kernel_aarch64[] = { - 0x81, 0x0a, 0x80, 0x52, /* loop: mov w1, #'T' */ + 0x81, 0x0a, 0x80, 0x52, /* mov w1, #'T' */ 0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 Load UART0 */ - 0x41, 0x00, 0x00, 0x39, /* strb w1, [x2] *TXDAT = 'T' */ - 0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */ + 0x41, 0x00, 0x00, 0x39, /* loop: strb w1, [x2] *TXDAT = 'T' */ + 0xff, 0xff, 0xff, 0x17, /* b -4 (loop) */ }; static const uint8_t kernel_nrf51[] = { From patchwork Mon Jan 13 13:54:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 856928 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1435084wrc; Mon, 13 Jan 2025 05:57:01 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWGUbcAS05LAaE9LSiDe5OVm/aTjl1e6Cw+tsQutf/Bj1UuZAdiwdLaz1DvBsUBpT45CSOlDA==@linaro.org X-Google-Smtp-Source: AGHT+IF1U7p9l8mFeOpVT5+fnSe7a+3kn9PfsTUbukpo2J0wSc8ysQHMT43EOiekm2fgZOtMytce X-Received: by 2002:a05:620a:4245:b0:7b6:dac1:cb73 with SMTP id af79cd13be357-7bcd97c921fmr3624339185a.56.1736776620824; Mon, 13 Jan 2025 05:57:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736776620; cv=none; d=google.com; s=arc-20240605; b=AuZcVpv10C2SEMnkxtJg7ZSSTETflwIfdluK8wmxNseX5LzAaMv7fR04FSNL52U85X rKW4sILcb2fDkFNy1/cmB7aeCFVAS/kmcISmwMMaJ0gLN67V/ZEa2FGVBm0HKMZl3Op8 nnzHRjwngPjuzqh2p+4Lit/B+J1HCsPMQHXtq5ed4Cal5u9bOpZmKNTLGLWozY30YOcZ dSYqxEMiCB89HbSG1JiINeifTg5isLAnmv0QlN6rALsdqjOWhlVPRCIr2nkyP4Z6v3v+ f30Utw/ZVV3h6e0V+VGRRbIexV7ZO4kXI//7WmORxSiiHzf9aA/dZYj/CM5qQn2189/E Incw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GWUNcZKxKH1utC8rl9Z3vhv6hG0D9P5xMDHSC53HwPo=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=lizYA2zDS5oU16AClEod0u2hgsUUqBd6+ZYUv/vlMeNHdyRGtvgyCGUXS8W7rYW4Pl IgoQXk5itNgAVztTWgNIaB+9vvuJyimbrpP9GXk2JAPuOjNpcU5sC7EJQOS8e175Z5Yo lvpqcS4vo9oKwB7WxAYLEnjcR03ZMUVHS7kw2GWsLf/HFeQqd/dd20CjYHywLgf8TWji eMiUM9bzhPYTDOajIQQXnb6/9tQ0rz9cUxRd5m59VgzU+oZ4s5tleA0Cy0Tm9BeWx5Yd 0DsH8IFYtGQ47XGTblmTa0WZadMJXh58nLPXZ3qqRcqQ8bJc/n/i3hbM/7xz6FRUgAbF GSpQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CCthGWrH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d8fba4sm145245205e9.4.2025.01.13.05.54.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 05:54:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/11] tests/qtest/boot-serial-test: Reorder pair of instructions in PL011 test Date: Mon, 13 Jan 2025 13:54:02 +0000 Message-Id: <20250113135408.3164401-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250113135408.3164401-1-peter.maydell@linaro.org> References: <20250113135408.3164401-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé In the next commit we are going to use a different value for the $w1 register, maintaining the same $x2 value. In order to keep the next commit trivial to review, set $x2 before $w1. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Fabiano Rosas Signed-off-by: Peter Maydell --- tests/qtest/boot-serial-test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c index 553575ca75c..bcfa504826c 100644 --- a/tests/qtest/boot-serial-test.c +++ b/tests/qtest/boot-serial-test.c @@ -78,8 +78,8 @@ static const uint8_t bios_raspi2[] = { }; static const uint8_t kernel_aarch64[] = { - 0x81, 0x0a, 0x80, 0x52, /* mov w1, #'T' */ 0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 Load UART0 */ + 0x81, 0x0a, 0x80, 0x52, /* mov w1, #'T' */ 0x41, 0x00, 0x00, 0x39, /* loop: strb w1, [x2] *TXDAT = 'T' */ 0xff, 0xff, 0xff, 0x17, /* b -4 (loop) */ }; From patchwork Mon Jan 13 13:54:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 856929 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1435132wrc; Mon, 13 Jan 2025 05:57:08 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUW+uecy+5FH+rr57oyp6eyrgtvDaRH/gQPS63ReB6rQ9z3HidtmFfDTXiwQ+U88rKfq91VfA==@linaro.org X-Google-Smtp-Source: AGHT+IGIDtIyhTUdeNb6kvACWUjYOcQ1yjrep5Wto9oSTfBEa8xvN5jys5CIILnoaf3OFLeS+ekE X-Received: by 2002:a05:6214:1949:b0:6d8:9960:b063 with SMTP id 6a1803df08f44-6df9b1e93f6mr325216236d6.14.1736776628090; Mon, 13 Jan 2025 05:57:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736776628; cv=none; d=google.com; s=arc-20240605; b=bxBWB/mmbzGDydN7xdjFTmnl/eD0LhN8skKCj3DGZGo4GEvLNspASSyrq0DyKu5XVT cxr2hlapwJhlsg2GKXBS8D5zCqFKIqBTVaxqsxRP10UtnGkO/Aq2VHRq5RWSjw0H0/kS NumZ8rG8e1b0PykqiOCLK5doB/L9LPFBvgA/91nDdvsYmIrxMirD/TN1U3lZ4hn2iEKS yZN47ouEK+QeZ4I4mU60y0s/hI2tkNQ/5FARGhMvwFc1hAj2TnEJohVh7R819iVzQZk1 ljBkoRZlljFRmKOKyEz1l9KBX0KSlWMbJX6yPm8ZwK6CiQ8QdpD83NC1WG7RJSJLkzal OK1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XyxQFIaesklbSi1xUcLqY7yAiP7hbZCiorkIOLRK+G8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=JWknPvAhO48Nf2k6eLgfQZML7ziC+i+Cz9mTCM+b66APgB19d7bWhhsrRUZJFlHFk6 N++nQ6qPa7gKQQz95NwlDdLVbmpjPXyL9w2pNRotYg03+/xFvDbTueIlm80vXTLl5gU3 9hE/dEGbICh++v1uZ9rAGq9zytWESuZ/XZ2iHFlhJYHicJwkVhI43KJk/g4Gzaa0Dfxh 0r5hBRGuny86JQEMVfmVadJUpryclosHyQBdrTaWGlSvKnS1JBMKg81ZQmhyWOaSjmIu ipvNrCmpr6nJgj3HAwh5SEucEoIIdysnpjUQ1dhc8a0/qQEjGUsuw4OpVMzTNs0H9VdL xG7w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JUpdaGnX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d8fba4sm145245205e9.4.2025.01.13.05.54.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 05:54:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/11] tests/qtest/boot-serial-test: Initialize PL011 Control register Date: Mon, 13 Jan 2025 13:54:03 +0000 Message-Id: <20250113135408.3164401-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250113135408.3164401-1-peter.maydell@linaro.org> References: <20250113135408.3164401-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé The tests using the PL011 UART of the virt and raspi machines weren't properly enabling the UART and its transmitter previous to sending characters. Follow the PL011 manual initialization recommendation by setting the proper bits of the control register. Update the ASM code prefixing: *UART_CTRL = UART_ENABLE | TX_ENABLE; to: while (true) { *UART_DATA = 'T'; } Note, since commit 51b61dd4d56 ("hw/char/pl011: Warn when using disabled transmitter") incomplete PL011 initialization can be logged using the '-d guest_errors' command line option. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- tests/qtest/boot-serial-test.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c index bcfa504826c..ffa9e780ad6 100644 --- a/tests/qtest/boot-serial-test.c +++ b/tests/qtest/boot-serial-test.c @@ -70,15 +70,20 @@ static const uint8_t kernel_plml605[] = { }; static const uint8_t bios_raspi2[] = { - 0x08, 0x30, 0x9f, 0xe5, /* ldr r3, [pc, #8] Get &UART0 */ + 0x10, 0x30, 0x9f, 0xe5, /* ldr r3, [pc, #16] Get &UART0 */ + 0x10, 0x20, 0x9f, 0xe5, /* ldr r2, [pc, #16] Get &CR */ + 0xb0, 0x23, 0xc3, 0xe1, /* strh r2, [r3, #48] Set CR */ 0x54, 0x20, 0xa0, 0xe3, /* mov r2, #'T' */ 0x00, 0x20, 0xc3, 0xe5, /* loop: strb r2, [r3] *TXDAT = 'T' */ 0xff, 0xff, 0xff, 0xea, /* b -4 (loop) */ 0x00, 0x10, 0x20, 0x3f, /* UART0: 0x3f201000 */ + 0x01, 0x01, 0x00, 0x00, /* CR: 0x101 = UARTEN|TXE */ }; static const uint8_t kernel_aarch64[] = { 0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 Load UART0 */ + 0x21, 0x20, 0x80, 0x52, /* mov w1, 0x101 CR = UARTEN|TXE */ + 0x41, 0x60, 0x00, 0x79, /* strh w1, [x2, #48] Set CR */ 0x81, 0x0a, 0x80, 0x52, /* mov w1, #'T' */ 0x41, 0x00, 0x00, 0x39, /* loop: strb w1, [x2] *TXDAT = 'T' */ 0xff, 0xff, 0xff, 0x17, /* b -4 (loop) */ From patchwork Mon Jan 13 13:54:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 856924 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1434849wrc; Mon, 13 Jan 2025 05:56:21 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXSrhP6dfhL4soJHsWOCZezDtU5KIAoqvNtnmmvWp2szkhUSAiMvhCGAbHtRI8LNn5r2B5eIg==@linaro.org X-Google-Smtp-Source: AGHT+IHoyevXCdIImrLJLftwD0PKP4KX0gb1uNczMo6//ruHN+AWAW1ps3rLDS84zt3/6iVNmP6n X-Received: by 2002:a05:622a:1986:b0:461:3653:54f with SMTP id d75a77b69052e-46c70fd1df1mr347882321cf.11.1736776580899; Mon, 13 Jan 2025 05:56:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736776580; cv=none; d=google.com; s=arc-20240605; b=XhHSBdelAhZBnIRMTRhB27/zojx0h28rvzItrYoMlnueQwm0rugIgORnDCWBkQfBQj MfY4yyDBDii28TGT1PVhT8A6M8vPYnT5/rscrZ7hqJd3pLIziS5roiV5fskkG2yF7VGe NPOtCHxJ1zblZsZmkA57tCXr9xVry9XaZm1vdse1xYIFqhrs3Awpowe+gjgBSIMeAnxA D3J6LNN1vhlddT/brbyq7RBp3bj8RfG9T6vdnb64uyKDUu+qRit+R3nPnvxyleTw+1R8 qqYisL/SPR/EeQcXEXJgP/gUgj1znEuS/RsWpRuINzdr/UTGqYiF3LC9cSzW7EBlfOqS Q/Pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=C07GAu6RWSDUye/+eR4LCu02qedXs1CpujcY5K6FNkQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=OgwDLeEoocBT5dLGJvikLPWyFdrMh4f9q8ARd20goxW953uGTaTn4eDvznfq9aGE3u HGPJDeGK01J8+hD6ABrgR+X/nyXgG5mSyuWihB7mq5nTZYv9e+qoXnzxg2A/PzhsuLUI gaBp4oMYJr1jvB0+LHAvbtEMVSmejAJENQ5A0YQ5GiaY5sHhLCiw6Je8Dq0KZI5lau1P JmSG7ifrcoad7oURHF9vKi1x1MQZP7+soQL8jEBiatSbamfU3g1lpWvj/3YuGIdTSn4a N93tyDRfFOvSC1YUd+rmbq94JXatCCu05S/eGylUQZKo7ztsp56Eudkg162aqwsiCLss 2ziQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tPs4dsXp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d8fba4sm145245205e9.4.2025.01.13.05.54.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 05:54:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/11] target/arm: Move minor arithmetic helpers out of helper.c Date: Mon, 13 Jan 2025 13:54:04 +0000 Message-Id: <20250113135408.3164401-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250113135408.3164401-1-peter.maydell@linaro.org> References: <20250113135408.3164401-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org helper.c includes some small TCG helper functions used for mostly arithmetic instructions. These are TCG only and there's no need for them to be in the large and unwieldy helper.c. Move them out to their own source file in the tcg/ subdirectory, together with the op_addsub.h multiply-included template header that they use. Since we are moving op_addsub.h, we take the opportunity to give it a name which matches our convention for files which are not true header files but which are #included from other C files: op_addsub.c.inc. (Ironically, this means that helper.c no longer contains any TCG helper function definitions at all.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20250110131211.2546314-1-peter.maydell@linaro.org Reviewed-by: Alex Bennée --- target/arm/helper.c | 285 ----------------- target/arm/tcg/arith_helper.c | 296 ++++++++++++++++++ .../arm/{op_addsub.h => tcg/op_addsub.c.inc} | 0 target/arm/tcg/meson.build | 1 + 4 files changed, 297 insertions(+), 285 deletions(-) create mode 100644 target/arm/tcg/arith_helper.c rename target/arm/{op_addsub.h => tcg/op_addsub.c.inc} (100%) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5b595f951b4..63997678513 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -17,11 +17,9 @@ #include "qemu/main-loop.h" #include "qemu/timer.h" #include "qemu/bitops.h" -#include "qemu/crc32c.h" #include "qemu/qemu-print.h" #include "exec/exec-all.h" #include "exec/translation-block.h" -#include /* for crc32 */ #include "hw/irq.h" #include "system/cpu-timers.h" #include "system/kvm.h" @@ -10984,289 +10982,6 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, }; } -/* - * Note that signed overflow is undefined in C. The following routines are - * careful to use unsigned types where modulo arithmetic is required. - * Failure to do so _will_ break on newer gcc. - */ - -/* Signed saturating arithmetic. */ - -/* Perform 16-bit signed saturating addition. */ -static inline uint16_t add16_sat(uint16_t a, uint16_t b) -{ - uint16_t res; - - res = a + b; - if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { - if (a & 0x8000) { - res = 0x8000; - } else { - res = 0x7fff; - } - } - return res; -} - -/* Perform 8-bit signed saturating addition. */ -static inline uint8_t add8_sat(uint8_t a, uint8_t b) -{ - uint8_t res; - - res = a + b; - if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { - if (a & 0x80) { - res = 0x80; - } else { - res = 0x7f; - } - } - return res; -} - -/* Perform 16-bit signed saturating subtraction. */ -static inline uint16_t sub16_sat(uint16_t a, uint16_t b) -{ - uint16_t res; - - res = a - b; - if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { - if (a & 0x8000) { - res = 0x8000; - } else { - res = 0x7fff; - } - } - return res; -} - -/* Perform 8-bit signed saturating subtraction. */ -static inline uint8_t sub8_sat(uint8_t a, uint8_t b) -{ - uint8_t res; - - res = a - b; - if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { - if (a & 0x80) { - res = 0x80; - } else { - res = 0x7f; - } - } - return res; -} - -#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); -#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); -#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); -#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); -#define PFX q - -#include "op_addsub.h" - -/* Unsigned saturating arithmetic. */ -static inline uint16_t add16_usat(uint16_t a, uint16_t b) -{ - uint16_t res; - res = a + b; - if (res < a) { - res = 0xffff; - } - return res; -} - -static inline uint16_t sub16_usat(uint16_t a, uint16_t b) -{ - if (a > b) { - return a - b; - } else { - return 0; - } -} - -static inline uint8_t add8_usat(uint8_t a, uint8_t b) -{ - uint8_t res; - res = a + b; - if (res < a) { - res = 0xff; - } - return res; -} - -static inline uint8_t sub8_usat(uint8_t a, uint8_t b) -{ - if (a > b) { - return a - b; - } else { - return 0; - } -} - -#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); -#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); -#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); -#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); -#define PFX uq - -#include "op_addsub.h" - -/* Signed modulo arithmetic. */ -#define SARITH16(a, b, n, op) do { \ - int32_t sum; \ - sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ - RESULT(sum, n, 16); \ - if (sum >= 0) \ - ge |= 3 << (n * 2); \ - } while (0) - -#define SARITH8(a, b, n, op) do { \ - int32_t sum; \ - sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ - RESULT(sum, n, 8); \ - if (sum >= 0) \ - ge |= 1 << n; \ - } while (0) - - -#define ADD16(a, b, n) SARITH16(a, b, n, +) -#define SUB16(a, b, n) SARITH16(a, b, n, -) -#define ADD8(a, b, n) SARITH8(a, b, n, +) -#define SUB8(a, b, n) SARITH8(a, b, n, -) -#define PFX s -#define ARITH_GE - -#include "op_addsub.h" - -/* Unsigned modulo arithmetic. */ -#define ADD16(a, b, n) do { \ - uint32_t sum; \ - sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ - RESULT(sum, n, 16); \ - if ((sum >> 16) == 1) \ - ge |= 3 << (n * 2); \ - } while (0) - -#define ADD8(a, b, n) do { \ - uint32_t sum; \ - sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ - RESULT(sum, n, 8); \ - if ((sum >> 8) == 1) \ - ge |= 1 << n; \ - } while (0) - -#define SUB16(a, b, n) do { \ - uint32_t sum; \ - sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ - RESULT(sum, n, 16); \ - if ((sum >> 16) == 0) \ - ge |= 3 << (n * 2); \ - } while (0) - -#define SUB8(a, b, n) do { \ - uint32_t sum; \ - sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ - RESULT(sum, n, 8); \ - if ((sum >> 8) == 0) \ - ge |= 1 << n; \ - } while (0) - -#define PFX u -#define ARITH_GE - -#include "op_addsub.h" - -/* Halved signed arithmetic. */ -#define ADD16(a, b, n) \ - RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) -#define SUB16(a, b, n) \ - RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) -#define ADD8(a, b, n) \ - RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) -#define SUB8(a, b, n) \ - RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) -#define PFX sh - -#include "op_addsub.h" - -/* Halved unsigned arithmetic. */ -#define ADD16(a, b, n) \ - RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) -#define SUB16(a, b, n) \ - RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) -#define ADD8(a, b, n) \ - RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) -#define SUB8(a, b, n) \ - RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) -#define PFX uh - -#include "op_addsub.h" - -static inline uint8_t do_usad(uint8_t a, uint8_t b) -{ - if (a > b) { - return a - b; - } else { - return b - a; - } -} - -/* Unsigned sum of absolute byte differences. */ -uint32_t HELPER(usad8)(uint32_t a, uint32_t b) -{ - uint32_t sum; - sum = do_usad(a, b); - sum += do_usad(a >> 8, b >> 8); - sum += do_usad(a >> 16, b >> 16); - sum += do_usad(a >> 24, b >> 24); - return sum; -} - -/* For ARMv6 SEL instruction. */ -uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) -{ - uint32_t mask; - - mask = 0; - if (flags & 1) { - mask |= 0xff; - } - if (flags & 2) { - mask |= 0xff00; - } - if (flags & 4) { - mask |= 0xff0000; - } - if (flags & 8) { - mask |= 0xff000000; - } - return (a & mask) | (b & ~mask); -} - -/* - * CRC helpers. - * The upper bytes of val (above the number specified by 'bytes') must have - * been zeroed out by the caller. - */ -uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) -{ - uint8_t buf[4]; - - stl_le_p(buf, val); - - /* zlib crc32 converts the accumulator and output to one's complement. */ - return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; -} - -uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) -{ - uint8_t buf[4]; - - stl_le_p(buf, val); - - /* Linux crc32c converts the output to one's complement. */ - return crc32c(acc, buf, bytes) ^ 0xffffffff; -} /* * Return the exception level to which FP-disabled exceptions should diff --git a/target/arm/tcg/arith_helper.c b/target/arm/tcg/arith_helper.c new file mode 100644 index 00000000000..9a555c7966c --- /dev/null +++ b/target/arm/tcg/arith_helper.c @@ -0,0 +1,296 @@ +/* + * ARM generic helpers for various arithmetical operations. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "qemu/crc32c.h" +#include /* for crc32 */ + +/* + * Note that signed overflow is undefined in C. The following routines are + * careful to use unsigned types where modulo arithmetic is required. + * Failure to do so _will_ break on newer gcc. + */ + +/* Signed saturating arithmetic. */ + +/* Perform 16-bit signed saturating addition. */ +static inline uint16_t add16_sat(uint16_t a, uint16_t b) +{ + uint16_t res; + + res = a + b; + if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { + if (a & 0x8000) { + res = 0x8000; + } else { + res = 0x7fff; + } + } + return res; +} + +/* Perform 8-bit signed saturating addition. */ +static inline uint8_t add8_sat(uint8_t a, uint8_t b) +{ + uint8_t res; + + res = a + b; + if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { + if (a & 0x80) { + res = 0x80; + } else { + res = 0x7f; + } + } + return res; +} + +/* Perform 16-bit signed saturating subtraction. */ +static inline uint16_t sub16_sat(uint16_t a, uint16_t b) +{ + uint16_t res; + + res = a - b; + if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { + if (a & 0x8000) { + res = 0x8000; + } else { + res = 0x7fff; + } + } + return res; +} + +/* Perform 8-bit signed saturating subtraction. */ +static inline uint8_t sub8_sat(uint8_t a, uint8_t b) +{ + uint8_t res; + + res = a - b; + if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { + if (a & 0x80) { + res = 0x80; + } else { + res = 0x7f; + } + } + return res; +} + +#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); +#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); +#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); +#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); +#define PFX q + +#include "op_addsub.c.inc" + +/* Unsigned saturating arithmetic. */ +static inline uint16_t add16_usat(uint16_t a, uint16_t b) +{ + uint16_t res; + res = a + b; + if (res < a) { + res = 0xffff; + } + return res; +} + +static inline uint16_t sub16_usat(uint16_t a, uint16_t b) +{ + if (a > b) { + return a - b; + } else { + return 0; + } +} + +static inline uint8_t add8_usat(uint8_t a, uint8_t b) +{ + uint8_t res; + res = a + b; + if (res < a) { + res = 0xff; + } + return res; +} + +static inline uint8_t sub8_usat(uint8_t a, uint8_t b) +{ + if (a > b) { + return a - b; + } else { + return 0; + } +} + +#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); +#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); +#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); +#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); +#define PFX uq + +#include "op_addsub.c.inc" + +/* Signed modulo arithmetic. */ +#define SARITH16(a, b, n, op) do { \ + int32_t sum; \ + sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ + RESULT(sum, n, 16); \ + if (sum >= 0) \ + ge |= 3 << (n * 2); \ + } while (0) + +#define SARITH8(a, b, n, op) do { \ + int32_t sum; \ + sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ + RESULT(sum, n, 8); \ + if (sum >= 0) \ + ge |= 1 << n; \ + } while (0) + + +#define ADD16(a, b, n) SARITH16(a, b, n, +) +#define SUB16(a, b, n) SARITH16(a, b, n, -) +#define ADD8(a, b, n) SARITH8(a, b, n, +) +#define SUB8(a, b, n) SARITH8(a, b, n, -) +#define PFX s +#define ARITH_GE + +#include "op_addsub.c.inc" + +/* Unsigned modulo arithmetic. */ +#define ADD16(a, b, n) do { \ + uint32_t sum; \ + sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ + RESULT(sum, n, 16); \ + if ((sum >> 16) == 1) \ + ge |= 3 << (n * 2); \ + } while (0) + +#define ADD8(a, b, n) do { \ + uint32_t sum; \ + sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ + RESULT(sum, n, 8); \ + if ((sum >> 8) == 1) \ + ge |= 1 << n; \ + } while (0) + +#define SUB16(a, b, n) do { \ + uint32_t sum; \ + sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ + RESULT(sum, n, 16); \ + if ((sum >> 16) == 0) \ + ge |= 3 << (n * 2); \ + } while (0) + +#define SUB8(a, b, n) do { \ + uint32_t sum; \ + sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ + RESULT(sum, n, 8); \ + if ((sum >> 8) == 0) \ + ge |= 1 << n; \ + } while (0) + +#define PFX u +#define ARITH_GE + +#include "op_addsub.c.inc" + +/* Halved signed arithmetic. */ +#define ADD16(a, b, n) \ + RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) +#define SUB16(a, b, n) \ + RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) +#define ADD8(a, b, n) \ + RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) +#define SUB8(a, b, n) \ + RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) +#define PFX sh + +#include "op_addsub.c.inc" + +/* Halved unsigned arithmetic. */ +#define ADD16(a, b, n) \ + RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) +#define SUB16(a, b, n) \ + RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) +#define ADD8(a, b, n) \ + RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) +#define SUB8(a, b, n) \ + RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) +#define PFX uh + +#include "op_addsub.c.inc" + +static inline uint8_t do_usad(uint8_t a, uint8_t b) +{ + if (a > b) { + return a - b; + } else { + return b - a; + } +} + +/* Unsigned sum of absolute byte differences. */ +uint32_t HELPER(usad8)(uint32_t a, uint32_t b) +{ + uint32_t sum; + sum = do_usad(a, b); + sum += do_usad(a >> 8, b >> 8); + sum += do_usad(a >> 16, b >> 16); + sum += do_usad(a >> 24, b >> 24); + return sum; +} + +/* For ARMv6 SEL instruction. */ +uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) +{ + uint32_t mask; + + mask = 0; + if (flags & 1) { + mask |= 0xff; + } + if (flags & 2) { + mask |= 0xff00; + } + if (flags & 4) { + mask |= 0xff0000; + } + if (flags & 8) { + mask |= 0xff000000; + } + return (a & mask) | (b & ~mask); +} + +/* + * CRC helpers. + * The upper bytes of val (above the number specified by 'bytes') must have + * been zeroed out by the caller. + */ +uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) +{ + uint8_t buf[4]; + + stl_le_p(buf, val); + + /* zlib crc32 converts the accumulator and output to one's complement. */ + return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; +} + +uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) +{ + uint8_t buf[4]; + + stl_le_p(buf, val); + + /* Linux crc32c converts the output to one's complement. */ + return crc32c(acc, buf, bytes) ^ 0xffffffff; +} diff --git a/target/arm/op_addsub.h b/target/arm/tcg/op_addsub.c.inc similarity index 100% rename from target/arm/op_addsub.h rename to target/arm/tcg/op_addsub.c.inc diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 09238989c5a..1f9077c372c 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -40,6 +40,7 @@ arm_ss.add(files( 'tlb_helper.c', 'vec_helper.c', 'tlb-insns.c', + 'arith_helper.c', )) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( From patchwork Mon Jan 13 13:54:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 856921 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1434318wrc; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d8fba4sm145245205e9.4.2025.01.13.05.54.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 05:54:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/11] target/arm: add new property to select pauth-qarma5 Date: Mon, 13 Jan 2025 13:54:05 +0000 Message-Id: <20250113135408.3164401-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250113135408.3164401-1-peter.maydell@linaro.org> References: <20250113135408.3164401-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Pierrick Bouvier Before changing default pauth algorithm, we need to make sure current default one (QARMA5) can still be selected. $ qemu-system-aarch64 -cpu max,pauth-qarma5=on ... Signed-off-by: Pierrick Bouvier Reviewed-by: Richard Henderson Message-id: 20241219183211.3493974-2-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/cpu-features.rst | 5 ++++- target/arm/cpu.h | 1 + target/arm/arm-qmp-cmds.c | 2 +- target/arm/cpu64.c | 20 ++++++++++++++------ tests/qtest/arm-cpu-features.c | 15 +++++++++++---- 5 files changed, 31 insertions(+), 12 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst index a5fb929243c..d69ebc2b852 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -219,7 +219,10 @@ Below is the list of TCG VCPU features and their descriptions. ``pauth-qarma3`` When ``pauth`` is enabled, select the architected QARMA3 algorithm. -Without either ``pauth-impdef`` or ``pauth-qarma3`` enabled, +``pauth-qarma5`` + When ``pauth`` is enabled, select the architected QARMA5 algorithm. + +Without ``pauth-impdef``, ``pauth-qarma3`` or ``pauth-qarma5`` enabled, the architected QARMA5 algorithm is used. The architected QARMA5 and QARMA3 algorithms have good cryptographic properties, but can be quite slow to emulate. The impdef algorithm used by QEMU is diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 12b84665427..01d9ff1781a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1062,6 +1062,7 @@ struct ArchCPU { bool prop_pauth; bool prop_pauth_impdef; bool prop_pauth_qarma3; + bool prop_pauth_qarma5; bool prop_lpa2; /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c index 3cc8cc738bb..33cea080d11 100644 --- a/target/arm/arm-qmp-cmds.c +++ b/target/arm/arm-qmp-cmds.c @@ -94,7 +94,7 @@ static const char *cpu_model_advertised_features[] = { "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280", "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048", "kvm-no-adjvtime", "kvm-steal-time", - "pauth", "pauth-impdef", "pauth-qarma3", + "pauth", "pauth-impdef", "pauth-qarma3", "pauth-qarma5", NULL }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index dca83e45181..6ee0af69121 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -520,9 +520,12 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) } if (cpu->prop_pauth) { - if (cpu->prop_pauth_impdef && cpu->prop_pauth_qarma3) { + if ((cpu->prop_pauth_impdef && cpu->prop_pauth_qarma3) || + (cpu->prop_pauth_impdef && cpu->prop_pauth_qarma5) || + (cpu->prop_pauth_qarma3 && cpu->prop_pauth_qarma5)) { error_setg(errp, - "cannot enable both pauth-impdef and pauth-qarma3"); + "cannot enable pauth-impdef, pauth-qarma3 and " + "pauth-qarma5 at the same time"); return; } @@ -532,13 +535,15 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) } else if (cpu->prop_pauth_qarma3) { isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, features); isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 1); - } else { + } else { /* default is pauth-qarma5 */ isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, features); isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1); } - } else if (cpu->prop_pauth_impdef || cpu->prop_pauth_qarma3) { - error_setg(errp, "cannot enable pauth-impdef or " - "pauth-qarma3 without pauth"); + } else if (cpu->prop_pauth_impdef || + cpu->prop_pauth_qarma3 || + cpu->prop_pauth_qarma5) { + error_setg(errp, "cannot enable pauth-impdef, pauth-qarma3 or " + "pauth-qarma5 without pauth"); error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); } } @@ -553,6 +558,8 @@ static const Property arm_cpu_pauth_impdef_property = DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); static const Property arm_cpu_pauth_qarma3_property = DEFINE_PROP_BOOL("pauth-qarma3", ARMCPU, prop_pauth_qarma3, false); +static Property arm_cpu_pauth_qarma5_property = + DEFINE_PROP_BOOL("pauth-qarma5", ARMCPU, prop_pauth_qarma5, false); void aarch64_add_pauth_properties(Object *obj) { @@ -573,6 +580,7 @@ void aarch64_add_pauth_properties(Object *obj) } else { qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_qarma3_property); + qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_qarma5_property); } } diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index cfd6f773535..98d6c970ea5 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -419,21 +419,28 @@ static void pauth_tests_default(QTestState *qts, const char *cpu_type) assert_has_feature_enabled(qts, cpu_type, "pauth"); assert_has_feature_disabled(qts, cpu_type, "pauth-impdef"); assert_has_feature_disabled(qts, cpu_type, "pauth-qarma3"); + assert_has_feature_disabled(qts, cpu_type, "pauth-qarma5"); assert_set_feature(qts, cpu_type, "pauth", false); assert_set_feature(qts, cpu_type, "pauth", true); assert_set_feature(qts, cpu_type, "pauth-impdef", true); assert_set_feature(qts, cpu_type, "pauth-impdef", false); assert_set_feature(qts, cpu_type, "pauth-qarma3", true); assert_set_feature(qts, cpu_type, "pauth-qarma3", false); + assert_set_feature(qts, cpu_type, "pauth-qarma5", true); + assert_set_feature(qts, cpu_type, "pauth-qarma5", false); assert_error(qts, cpu_type, - "cannot enable pauth-impdef or pauth-qarma3 without pauth", + "cannot enable pauth-impdef, pauth-qarma3 or pauth-qarma5 without pauth", "{ 'pauth': false, 'pauth-impdef': true }"); assert_error(qts, cpu_type, - "cannot enable pauth-impdef or pauth-qarma3 without pauth", + "cannot enable pauth-impdef, pauth-qarma3 or pauth-qarma5 without pauth", "{ 'pauth': false, 'pauth-qarma3': true }"); assert_error(qts, cpu_type, - "cannot enable both pauth-impdef and pauth-qarma3", - "{ 'pauth': true, 'pauth-impdef': true, 'pauth-qarma3': true }"); + "cannot enable pauth-impdef, pauth-qarma3 or pauth-qarma5 without pauth", + "{ 'pauth': false, 'pauth-qarma5': true }"); + assert_error(qts, cpu_type, + "cannot enable pauth-impdef, pauth-qarma3 and pauth-qarma5 at the same time", + "{ 'pauth': true, 'pauth-impdef': true, 'pauth-qarma3': true," + " 'pauth-qarma5': true }"); } static void test_query_cpu_model_expansion(const void *data) From patchwork Mon Jan 13 13:54:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 856927 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1435061wrc; Mon, 13 Jan 2025 05:56:56 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW2NfktenuUZJuy67dqpNvy+IHi1vw1K2EIi5DiG4p9yxbYEdSJsQ+s3ahW2m5uCuZVrVMItA==@linaro.org X-Google-Smtp-Source: AGHT+IE0UTOPvsAmiDd+JDr/Kj2WAf6mTrddLJoe6vEJs+WOICk6cvbm3g3ijsVnDkEO3yCk64ng X-Received: by 2002:a05:620a:4086:b0:7b6:fdb9:1be6 with SMTP id af79cd13be357-7bcd971aee6mr3125620185a.29.1736776616541; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d8fba4sm145245205e9.4.2025.01.13.05.54.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 05:54:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/11] tests/tcg/aarch64: force qarma5 for pauth-3 test Date: Mon, 13 Jan 2025 13:54:06 +0000 Message-Id: <20250113135408.3164401-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250113135408.3164401-1-peter.maydell@linaro.org> References: <20250113135408.3164401-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The pauth-3 test explicitly tests that a computation of the pointer-authentication produces the expected result. This means that it must be run with the QARMA5 algorithm. Explicitly set the pauth algorithm when running this test, so that it doesn't break when we change the default algorithm the 'max' CPU uses. Signed-off-by: Peter Maydell --- tests/tcg/aarch64/Makefile.softmmu-target | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target index d08d9b01ded..9c52475b7ae 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -91,6 +91,9 @@ EXTRA_RUNS+=run-memory-replay ifneq ($(CROSS_CC_HAS_ARMV8_3),) pauth-3: CFLAGS += $(CROSS_CC_HAS_ARMV8_3) +# This test explicitly checks the output of the pauth operation so we +# must force the use of the QARMA5 algorithm for it. +run-pauth-3: QEMU_BASE_MACHINE=-M virt -cpu max,pauth-qarma5=on -display none else pauth-3: $(call skip-test, "BUILD of $@", "missing compiler support") From patchwork Mon Jan 13 13:54:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 856926 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1435052wrc; Mon, 13 Jan 2025 05:56:55 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWRUJ12aUY13CIhtj9imcrzjKuChITCy9fZI1zkHkEIcf6fRWb+MiFeSJDOo/7oWLje96SUnw==@linaro.org X-Google-Smtp-Source: AGHT+IGdWZiKDhz+TnV027Wg7VmTq7gc5rs2sT75+hxqXVm9ZoWepHqC+zIRSyr4GiCBKQscvbPa X-Received: by 2002:a05:622a:2511:b0:46c:7646:4a3b with SMTP id d75a77b69052e-46c76464d35mr329804301cf.11.1736776614872; Mon, 13 Jan 2025 05:56:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736776614; cv=none; d=google.com; s=arc-20240605; b=CeTIUFw8IFoDnGroOPncbsUeKohOF/NxFMPVfEY6OHeNyN48G+//L5Amu3ZfykfAqz PEtEmzJD2QrAoVV1mULpswo5lePZJ7El7jf9TEmi4gRwfZtJm7fFZ0MPFZfxmY8iNG7f RA4Cz1fuKVNtRq4LTW4/6962Fvx3rLr2yugzjWFnpf+Kwp8X8iNyutf1pWfvE08I9kHk 4aFMCnfzvThDwU+aYhdtmk9j7+YuCkVPTHqq7BRCtwoMfePMCrSWltI2bJE/GDDIqUBi JKCwlBrlQvfkzCXi/+ydgSsK+MVNU5u2tEPTfzI5bkRNSeJvrh0o9NW8gefxaS5TWV67 IJOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Q/xHE0NI+koHolsava9KtIliJ8DziA/VOxDpuG+77Kg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Dy5dNc7szZCulcXJdj/Qik72ZQYO4CdilPTbCT1z9xAbzr+m5bMNajfmO+uan1YOOn rvg8A+hWPNNxr82r4xws/Y3UTVMhTwjNZLOJT+VAsZ6KS06Lsxn2Nrtqpxp3UtBMtxLj rn56ZN6/zxC3XVcxzaR0TPIOchL6vfQ5ej52IndGS+s20JkXtCDzVwsDKUeRRmY8jmZu THwegS9i9QYfJwcyLyAvgYgyzbX3jGV3gjnR34iawOaCNh8St+TeaLDmh1uuG66ZKFcL cJC4FNsAXta56DFetzmuH/umqq7eJQZo25S+ARw9e6H7sH6WOhnDX93UfdTd6ZNJOw3X Twuw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ImzQJ/t/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d8fba4sm145245205e9.4.2025.01.13.05.54.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 05:54:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/11] target/arm: change default pauth algorithm to impdef Date: Mon, 13 Jan 2025 13:54:07 +0000 Message-Id: <20250113135408.3164401-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250113135408.3164401-1-peter.maydell@linaro.org> References: <20250113135408.3164401-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Pierrick Bouvier Pointer authentication on aarch64 is pretty expensive (up to 50% of execution time) when running a virtual machine with tcg and -cpu max (which enables pauth=on). The advice is always: use pauth-impdef=on. Our documentation even mentions it "by default" in docs/system/introduction.rst. Thus, we change the default to use impdef by default. This does not affect kvm or hvf acceleration, since pauth algorithm used is the one from host cpu. This change is retro compatible, in terms of cli, with previous versions, as the semantic of using -cpu max,pauth-impdef=on, and -cpu max,pauth-qarma3=on is preserved. The new option introduced in previous patch and matching old default is -cpu max,pauth-qarma5=on. It is retro compatible with migration as well, by defining a backcompat property, that will use qarma5 by default for virt machine <= 9.2. Tested by saving and restoring a vm from qemu 9.2.0 into qemu-master (10.0) for cpus neoverse-n2 and max. Signed-off-by: Pierrick Bouvier Reviewed-by: Richard Henderson Message-id: 20241219183211.3493974-3-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/cpu-features.rst | 2 +- docs/system/introduction.rst | 2 +- target/arm/cpu.h | 3 +++ hw/core/machine.c | 4 +++- target/arm/cpu.c | 2 ++ target/arm/cpu64.c | 22 ++++++++++++++++------ 6 files changed, 26 insertions(+), 9 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst index d69ebc2b852..37d5dfd15b3 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -223,7 +223,7 @@ Below is the list of TCG VCPU features and their descriptions. When ``pauth`` is enabled, select the architected QARMA5 algorithm. Without ``pauth-impdef``, ``pauth-qarma3`` or ``pauth-qarma5`` enabled, -the architected QARMA5 algorithm is used. The architected QARMA5 +the QEMU impdef algorithm is used. The architected QARMA5 and QARMA3 algorithms have good cryptographic properties, but can be quite slow to emulate. The impdef algorithm used by QEMU is non-cryptographic but significantly faster. diff --git a/docs/system/introduction.rst b/docs/system/introduction.rst index 746707eb00e..338d3745c3c 100644 --- a/docs/system/introduction.rst +++ b/docs/system/introduction.rst @@ -169,7 +169,7 @@ would default to it anyway. .. code:: - -cpu max,pauth-impdef=on \ + -cpu max \ -smp 4 \ -accel tcg \ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 01d9ff1781a..9a6e8e589cc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -972,6 +972,9 @@ struct ArchCPU { /* QOM property to indicate we should use the back-compat CNTFRQ default */ bool backcompat_cntfrq; + /* QOM property to indicate we should use the back-compat QARMA5 default */ + bool backcompat_pauth_default_use_qarma5; + /* Specify the number of cores in this CPU cluster. Used for the L2CTLR * register. */ diff --git a/hw/core/machine.c b/hw/core/machine.c index c949af97668..c23b3994964 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -36,7 +36,9 @@ #include "hw/virtio/virtio-iommu.h" #include "audio/audio.h" -GlobalProperty hw_compat_9_2[] = {}; +GlobalProperty hw_compat_9_2[] = { + {"arm-cpu", "backcompat-pauth-default-use-qarma5", "true"}, +}; const size_t hw_compat_9_2_len = G_N_ELEMENTS(hw_compat_9_2); GlobalProperty hw_compat_9_1[] = { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index dcedadc89ea..dc0231233a6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2653,6 +2653,8 @@ static const Property arm_cpu_properties[] = { DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */ DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false), + DEFINE_PROP_BOOL("backcompat-pauth-default-use-qarma5", ARMCPU, + backcompat_pauth_default_use_qarma5, false), }; static const gchar *arm_gdb_arch_name(CPUState *cs) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6ee0af69121..8188ede5cc8 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -529,15 +529,25 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) return; } - if (cpu->prop_pauth_impdef) { - isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, features); - isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 1); + bool use_default = !cpu->prop_pauth_qarma5 && + !cpu->prop_pauth_qarma3 && + !cpu->prop_pauth_impdef; + + if (cpu->prop_pauth_qarma5 || + (use_default && + cpu->backcompat_pauth_default_use_qarma5)) { + isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, features); + isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1); } else if (cpu->prop_pauth_qarma3) { isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, features); isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 1); - } else { /* default is pauth-qarma5 */ - isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, features); - isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1); + } else if (cpu->prop_pauth_impdef || + (use_default && + !cpu->backcompat_pauth_default_use_qarma5)) { + isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, features); + isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 1); + } else { + g_assert_not_reached(); } } else if (cpu->prop_pauth_impdef || cpu->prop_pauth_qarma3 || From patchwork Mon Jan 13 13:54:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 856925 Delivered-To: patch@linaro.org Received: by 2002:a5d:525c:0:b0:385:e875:8a9e with SMTP id k28csp1435046wrc; Mon, 13 Jan 2025 05:56:54 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXbSliYMqbwa44owLkFOh+y+oHzNklWUZZkPcnjaPjsM8GbLQxbk6dFPzp8Q4EETpHv6UaOUw==@linaro.org X-Google-Smtp-Source: AGHT+IExoBqZBbR0eTzXGHdx7olmcdc8RDNRC5KF2wQ/c93xrqWVhAIKBkq/8sm4iSFWgSniQMHV X-Received: by 2002:a05:6214:2349:b0:6d4:1f86:b1e6 with SMTP id 6a1803df08f44-6df9b2328b9mr266621716d6.22.1736776613987; Mon, 13 Jan 2025 05:56:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736776613; cv=none; d=google.com; s=arc-20240605; b=SLglKzL2+z9w/75SplmFjeqPDk29MzxtvYQBgGPN5D3hsDGy47Fr7KHRwPV7dTC6Hc XwwfB9b6KWyJDaCVPog3+Sn1Fg6otmV9nItsnFeWyGtReUpLGO5KY53z9TOM0dAn2E6s KnKz5PlX/jK9k1UxN+ntksA/1g47ntizsvHFCGNf2toRCqZrt24JPm9m+fpKywpg69Pm 5AMCRO46e6rf4EvVk4VwioMjnjf1ltMUfGMBImgOyp3ipg/FLmEEgnTqLh9286pObs73 A2Z4bn+Vd+sVNVSVuKkWqBfliTtg7mFpq7sfMzEL22aaNn0fh3CLl2h4WIihSeU/aQHr AN1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bdXp5MXnTPFsp7BfsgfQJ16h4dh9YOVZw5yJW/TGR84=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=IoFPJBpdfYcltUNd/hI5tSYUoACsX/gk06565d8YFL8i/Qc7S/p0cZD/CG1yqeiSAt 5DN2Sy9Nyj28E/X02PAFhcrm/UqaYF/FHFYDC7VvSOQopSmKRkV6ZJEfYh5Ne/8Cho4H ISNUpTqYSWv1X0gm95Va+pHzOmJ1FnPUwqE/4XcywcOCL+NYTYX+35Cr8LgpRKrnWNDA rSGi9FfGiA6r7CakZNra/PayxzWEyfUOAxxYEAEM+RpWBwzAX7pta/mIgrAbOJzjgc6X m5kCMuF50YCgc9YgezXCgMSWHytIMld7ncpJaob6Lzq/cBeMHDnkHtk9MMAXdOflJV/s 1yDg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=c51LVue+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d8fba4sm145245205e9.4.2025.01.13.05.54.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 05:54:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/11] docs/system/arm/virt: mention specific migration information Date: Mon, 13 Jan 2025 13:54:08 +0000 Message-Id: <20250113135408.3164401-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250113135408.3164401-1-peter.maydell@linaro.org> References: <20250113135408.3164401-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Pierrick Bouvier Signed-off-by: Pierrick Bouvier Message-id: 20241219183211.3493974-4-pierrick.bouvier@linaro.org [PMM: Removed a paragraph about using non-versioned models.] Signed-off-by: Peter Maydell --- docs/system/arm/virt.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index f87adeb444c..766a7455f03 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -19,6 +19,10 @@ of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration is not guaranteed to work between different QEMU releases for the non-versioned ``virt`` machine type. +VM migration is not guaranteed when using ``-cpu max``, as features +supported may change between QEMU versions. To ensure your VM can be +migrated, it is recommended to use another cpu model instead. + Supported devices """""""""""""""""