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Sat, 11 Jan 2025 16:14:59 GMT Received: from 4206f847eb12.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 11 Jan 2025 08:14:55 -0800 From: Raviteja Laggyshetty To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Odelu Kukatla , "Mike Tipton" , Vivek Aknurwar CC: Sibi Sankar , , , , Subject: [PATCH V7 2/5] interconnect: qcom: Add multidev EPSS L3 support Date: Sat, 11 Jan 2025 16:14:26 +0000 Message-ID: <20250111161429.51-3-quic_rlaggysh@quicinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250111161429.51-1-quic_rlaggysh@quicinc.com> References: <20250111161429.51-1-quic_rlaggysh@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: AYXkRSNb30QssqBuiVC23hoKYxfdcbtC X-Proofpoint-ORIG-GUID: AYXkRSNb30QssqBuiVC23hoKYxfdcbtC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 clxscore=1015 spamscore=0 adultscore=0 suspectscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501110138 EPSS on SA8775P has two instances which requires creation of two device nodes with different compatible and device data because of unique icc node id and name limitation in interconnect framework. Add multidevice support to osm-l3 code to get unique node id from icc framework. Signed-off-by: Raviteja Laggyshetty --- drivers/interconnect/qcom/osm-l3.c | 91 ++++++++++++++++++++++-------- 1 file changed, 67 insertions(+), 24 deletions(-) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index 6a656ed44d49..8e98d1c9a840 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -11,6 +12,7 @@ #include #include #include +#include #include #include @@ -34,6 +36,9 @@ #define OSM_L3_MAX_LINKS 1 +#define OSM_L3_NODE_ID_START 10000 +#define OSM_NODE_NAME_SUFFIX_SIZE 10 + #define to_osm_l3_provider(_provider) \ container_of(_provider, struct qcom_osm_l3_icc_provider, provider) @@ -55,46 +60,40 @@ struct qcom_osm_l3_icc_provider { */ struct qcom_osm_l3_node { const char *name; - u16 links[OSM_L3_MAX_LINKS]; + const char *links[OSM_L3_MAX_LINKS]; u16 id; u16 num_links; u16 buswidth; }; struct qcom_osm_l3_desc { - const struct qcom_osm_l3_node * const *nodes; + struct qcom_osm_l3_node * const *nodes; size_t num_nodes; unsigned int lut_row_size; unsigned int reg_freq_lut; unsigned int reg_perf_state; }; -enum { - OSM_L3_MASTER_NODE = 10000, - OSM_L3_SLAVE_NODE, -}; - -#define DEFINE_QNODE(_name, _id, _buswidth, ...) \ - static const struct qcom_osm_l3_node _name = { \ +#define DEFINE_QNODE(_name, _buswidth, ...) \ + static struct qcom_osm_l3_node _name = { \ .name = #_name, \ - .id = _id, \ .buswidth = _buswidth, \ .num_links = COUNT_ARGS(__VA_ARGS__), \ - .links = { __VA_ARGS__ }, \ + __VA_OPT__(.links = { #__VA_ARGS__ }) \ } -DEFINE_QNODE(osm_l3_master, OSM_L3_MASTER_NODE, 16, OSM_L3_SLAVE_NODE); -DEFINE_QNODE(osm_l3_slave, OSM_L3_SLAVE_NODE, 16); +DEFINE_QNODE(osm_l3_master, 16, osm_l3_slave); +DEFINE_QNODE(osm_l3_slave, 16); -static const struct qcom_osm_l3_node * const osm_l3_nodes[] = { +static struct qcom_osm_l3_node * const osm_l3_nodes[] = { [MASTER_OSM_L3_APPS] = &osm_l3_master, [SLAVE_OSM_L3] = &osm_l3_slave, }; -DEFINE_QNODE(epss_l3_master, OSM_L3_MASTER_NODE, 32, OSM_L3_SLAVE_NODE); -DEFINE_QNODE(epss_l3_slave, OSM_L3_SLAVE_NODE, 32); +DEFINE_QNODE(epss_l3_master, 32, epss_l3_slave); +DEFINE_QNODE(epss_l3_slave, 32); -static const struct qcom_osm_l3_node * const epss_l3_nodes[] = { +static struct qcom_osm_l3_node * const epss_l3_nodes[] = { [MASTER_EPSS_L3_APPS] = &epss_l3_master, [SLAVE_EPSS_L3_SHARED] = &epss_l3_slave, }; @@ -123,6 +122,19 @@ static const struct qcom_osm_l3_desc epss_l3_l3_vote = { .reg_perf_state = EPSS_REG_L3_VOTE, }; +static u16 get_node_id_by_name(const char *node_name, + const struct qcom_osm_l3_desc *desc) +{ + struct qcom_osm_l3_node *const *nodes = desc->nodes; + int i; + + for (i = 0; i < desc->num_nodes; i++) { + if (!strcmp(nodes[i]->name, node_name)) + return nodes[i]->id; + } + return 0; +} + static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst) { struct qcom_osm_l3_icc_provider *qp; @@ -164,10 +176,11 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) const struct qcom_osm_l3_desc *desc; struct icc_onecell_data *data; struct icc_provider *provider; - const struct qcom_osm_l3_node * const *qnodes; + struct qcom_osm_l3_node * const *qnodes; struct icc_node *node; size_t num_nodes; struct clk *clk; + u64 addr; int ret; clk = clk_get(&pdev->dev, "xo"); @@ -188,6 +201,10 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) if (!qp) return -ENOMEM; + ret = of_property_read_reg(pdev->dev.of_node, 0, &addr, NULL); + if (ret) + return ret; + qp->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(qp->base)) return PTR_ERR(qp->base); @@ -242,26 +259,51 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) icc_provider_init(provider); + /* create icc nodes */ for (i = 0; i < num_nodes; i++) { - size_t j; + char *node_name; + size_t len; - node = icc_node_create(qnodes[i]->id); + node = icc_node_create_alloc_id(OSM_L3_NODE_ID_START); if (IS_ERR(node)) { ret = PTR_ERR(node); goto err; } + qnodes[i]->id = node->id; + + /* len = strlen(node->name) + @ + 8 (base-address) + NULL */ + len = strlen(qnodes[i]->name) + OSM_NODE_NAME_SUFFIX_SIZE; + node_name = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); + if (!node_name) { + ret = -ENOMEM; + goto err; + } + + snprintf(node_name, len, "%s@%08llx", qnodes[i]->name, addr); + node->name = node_name; - node->name = qnodes[i]->name; /* Cast away const and add it back in qcom_osm_l3_set() */ node->data = (void *)qnodes[i]; icc_node_add(node, provider); - for (j = 0; j < qnodes[i]->num_links; j++) - icc_link_create(node, qnodes[i]->links[j]); - data->nodes[i] = node; } + /* create links in topolgy */ + for (i = 0; i < num_nodes; i++) { + size_t j; + + node = data->nodes[i]; + for (j = 0; j < qnodes[i]->num_links; j++) { + u16 link_node_id = get_node_id_by_name(qnodes[i]->links[j], desc); + + if (link_node_id) + icc_link_create(node, link_node_id); + else + goto err; + } + } + ret = icc_provider_register(provider); if (ret) goto err; @@ -284,6 +326,7 @@ static const struct of_device_id osm_l3_of_match[] = { { .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state }, + { .compatible = "qcom,sa8775p-epss-l3", .data = &epss_l3_perf_state }, { } }; MODULE_DEVICE_TABLE(of, osm_l3_of_match); From patchwork Sat Jan 11 16:14:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raviteja Laggyshetty X-Patchwork-Id: 856719 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F16991B4F0A; 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Signed-off-by: Raviteja Laggyshetty --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 368bcf7c9802..c6a889d4ddaf 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -4282,6 +4283,15 @@ rpmhpd_opp_turbo_l1: opp-9 { }; }; + epss_l3_cl0: interconnect@18590000 { + compatible = "qcom,sa8775p-epss-l3", + "qcom,epss-l3"; + reg = <0x0 0x18590000 0x0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,sa8775p-cpufreq-epss", "qcom,cpufreq-epss"; @@ -4295,6 +4305,15 @@ cpufreq_hw: cpufreq@18591000 { #freq-domain-cells = <1>; }; + epss_l3_cl1: interconnect@18592000 { + compatible = "qcom,sa8775p-epss-l3", + "qcom,epss-l3"; + reg = <0x0 0x18592000 0x0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + remoteproc_gpdsp0: remoteproc@20c00000 { compatible = "qcom,sa8775p-gpdsp0-pas"; reg = <0x0 0x20c00000 0x0 0x10000>;