From patchwork Sat Jan 11 16:14:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raviteja Laggyshetty X-Patchwork-Id: 856583 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FE521B3926; Sat, 11 Jan 2025 16:14:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736612100; cv=none; b=VMOahrnxU6bBLU3bqHOzNpR75OZvx9ZyimRFVksVI2spu0AYaiBamDjbqTU1v3J5XBxwAhTL8lzqfcHx+/K79W+4shYygI60EtSBPm/infDoJLrnNk+KK8B6acKExsOhD3DPNkqCl0aRHrEnsqPgR16Yaj/xhvtFZXgtJUxgCx8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736612100; c=relaxed/simple; bh=QhIR6IVNhDKIGvS9mrCQN+vy8fYDqP+FrI/vAQE6KCM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=A1/d8/e19yw573NnMbDh1lYvZzqIPsREYmOAMiwMaynFBqbNkkkv6sHdgqQeUTXyleVpOexEZ4FLKm7k4YksfDHuLFMq1K/0ixcFBUzgmFSpRqEI02LOrglp+XXY5i3hP4YPO8QkWFxdbF9Qz/1HkyZ+hqm3o3cDHvSjyUIBlkI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=c+QW8i5m; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="c+QW8i5m" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50BFt2qj025825; Sat, 11 Jan 2025 16:14:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ah78BFGjD6Fm34xergrtStLVEB9suSsnXRU0tvf5bN8=; b=c+QW8i5m5ZnAjNmp 6UxBWDeqPUlVjpNDbFz3XUD+JuwFIIwAtTrJcgv890ygDrDUKZ65fqeVGzLHFShH xi95dABUo6U1cVweQHWmacC5P9q5UHlom/aCSHryT7L4btTxzFc8LZb/iGEMxL0B G+9nDkRjd6tLtUB73ryQP1FfhrSCDV8xWEcC1FzN5WOqpYbsvRVgw4pxuqzN0gH6 YyfLGvWXlwHufLb21puSCeOEniC+dAIeQUAB6UhjaQwHJm9QRzzpmQSQKjf0Wwp5 4BRBFX1ejFjke5ahZ5BT+n3lssdsQ088w5mGVJKxTJMHlWICEDdaHHOEoq9bC0W/ Ig4LmQ== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 443hmy8s5s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 11 Jan 2025 16:14:56 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50BGEtOP008030 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 11 Jan 2025 16:14:55 GMT Received: from 4206f847eb12.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 11 Jan 2025 08:14:51 -0800 From: Raviteja Laggyshetty To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Odelu Kukatla , "Mike Tipton" , Vivek Aknurwar CC: Sibi Sankar , , , , Subject: [PATCH V7 1/5] interconnect: core: Add dynamic id allocation support Date: Sat, 11 Jan 2025 16:14:25 +0000 Message-ID: <20250111161429.51-2-quic_rlaggysh@quicinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250111161429.51-1-quic_rlaggysh@quicinc.com> References: <20250111161429.51-1-quic_rlaggysh@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: BYiuIdzH9mf4e1M5lIXHM0zQSAyfFAlv X-Proofpoint-GUID: BYiuIdzH9mf4e1M5lIXHM0zQSAyfFAlv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 clxscore=1015 impostorscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=999 suspectscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501110138 Current interconnect framework is based on static IDs for creating node and registering with framework. This becomes a limitation for topologies where there are multiple instances of same interconnect provider. Add icc_node_create_alloc_id() API to create icc node with dynamic id, this will help to overcome the dependency on static IDs. Signed-off-by: Raviteja Laggyshetty --- drivers/interconnect/core.c | 32 +++++++++++++++++++++++++++ include/linux/interconnect-provider.h | 6 +++++ 2 files changed, 38 insertions(+) diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c index 9d5404a07e8a..0b7093eb51af 100644 --- a/drivers/interconnect/core.c +++ b/drivers/interconnect/core.c @@ -858,6 +858,38 @@ struct icc_node *icc_node_create(int id) } EXPORT_SYMBOL_GPL(icc_node_create); +/** + * icc_node_create_alloc_id() - create node and dynamically allocate id + * @start_id: min id to be allocated + * + * Return: icc_node pointer on success, or ERR_PTR() on error + */ +struct icc_node *icc_node_create_alloc_id(int start_id) +{ + struct icc_node *node; + int id; + + mutex_lock(&icc_lock); + + node = kzalloc(sizeof(*node), GFP_KERNEL); + if (!node) + return ERR_PTR(-ENOMEM); + + id = idr_alloc(&icc_idr, node, start_id, 0, GFP_KERNEL); + if (id < 0) { + WARN(1, "%s: couldn't get idr\n", __func__); + kfree(node); + node = ERR_PTR(id); + goto out; + } + node->id = id; +out: + mutex_unlock(&icc_lock); + + return node; +} +EXPORT_SYMBOL_GPL(icc_node_create_alloc_id); + /** * icc_node_destroy() - destroy a node * @id: node id diff --git a/include/linux/interconnect-provider.h b/include/linux/interconnect-provider.h index f5aef8784692..4fc7a5884374 100644 --- a/include/linux/interconnect-provider.h +++ b/include/linux/interconnect-provider.h @@ -117,6 +117,7 @@ struct icc_node { int icc_std_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, u32 peak_bw, u32 *agg_avg, u32 *agg_peak); struct icc_node *icc_node_create(int id); +struct icc_node *icc_node_create_alloc_id(int start_id); void icc_node_destroy(int id); int icc_link_create(struct icc_node *node, const int dst_id); void icc_node_add(struct icc_node *node, struct icc_provider *provider); @@ -141,6 +142,11 @@ static inline struct icc_node *icc_node_create(int id) return ERR_PTR(-ENOTSUPP); } +static inline struct icc_node *icc_node_create_alloc_id(int start_id) +{ + return ERR_PTR(-EOPNOTSUPP); +} + static inline void icc_node_destroy(int id) { } From patchwork Sat Jan 11 16:14:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raviteja Laggyshetty X-Patchwork-Id: 856582 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 919561B2184; Sat, 11 Jan 2025 16:15:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736612109; cv=none; b=anODo+RRbjMPWv2jYVdqU4jHx45XC4U1ISIsfoMh3L54ld6GboF9t9owzLBTWyNYkv/Hl6/PoYCXIrxr50SoWy9CjUmzeyb2WFstNPKwaJ5L0blpaCOjyE1EWjiToaeI47cs4YQ8Uw0pG2n8PI00xV+g1BmwgqnZRNQGb9fuhvs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736612109; c=relaxed/simple; bh=h2kzfShbY+qmHX/y4NEs8u08Si9FlnqsM3crhkhlwVo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QrZ/IrL/NDbsLSTz1dyIMIt5qBELO88ZAr9coiAUt2Zw0I15TOU4+SOJknS0fVhbSNBSY+0xEaPGyc7icFq2onCNeCVcxeJbMD7m+V6HhRBZ8ZkxGTe2Tts9gZb7jUR8ZI7phqWt0zu4KyydH45JYKQ86rNq6G1SlwOWIdh2juA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=O17PcWSl; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="O17PcWSl" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50BDt2aC025053; Sat, 11 Jan 2025 16:15:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= eOMpmWbAruPxIm6z1uRwAcRJwsCmhMZwJIHPma/mPrg=; b=O17PcWSlFJQFiCBY pGy9pnBnJQNcYezjttlfFIY7TABFprIv8waPDHz+Nd1SnaHsPOAE9PkkW2AZ2/PD KNDVg2byMihlL4CX3z9wDGHoiDpl3YiCTFkNTpWt1DFVH3s4N8X9x7DBFDm9hc3Q RaKVPHqkvPurxC2s3aA3Oh6iL5EXCiUIGjxCjxjHnZgKHsqePhfg19Mx0UYqQdyq ymbZBJj+cwH8moQ7zKSJOcPlPS1F/ROnbPqvDRZ572kn8nJgDs9lqvcPELhFwBwH DVwR4EFMKQBnYIjAF2gTG4FO5r28j6JkLPg2Ax4bNIT1Vx8cUEwht2hhAvUFgg6b G3w9fw== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 443hjdgshj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 11 Jan 2025 16:15:04 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50BGF4Tg025487 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 11 Jan 2025 16:15:04 GMT Received: from 4206f847eb12.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 11 Jan 2025 08:14:59 -0800 From: Raviteja Laggyshetty To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Odelu Kukatla , "Mike Tipton" , Vivek Aknurwar CC: Sibi Sankar , , , , Subject: [PATCH V7 3/5] dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P Date: Sat, 11 Jan 2025 16:14:27 +0000 Message-ID: <20250111161429.51-4-quic_rlaggysh@quicinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250111161429.51-1-quic_rlaggysh@quicinc.com> References: <20250111161429.51-1-quic_rlaggysh@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: PZcD8TbaKN8aSW47zw9j7RTLBlUn0XzD X-Proofpoint-GUID: PZcD8TbaKN8aSW47zw9j7RTLBlUn0XzD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 bulkscore=0 mlxscore=0 priorityscore=1501 spamscore=0 impostorscore=0 mlxlogscore=979 lowpriorityscore=0 clxscore=1015 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501110138 Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SA8775P SoCs. Signed-off-by: Raviteja Laggyshetty --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 21dae0b92819..94f7f283787a 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -33,6 +33,7 @@ properties: - qcom,sm6375-cpucp-l3 - qcom,sm8250-epss-l3 - qcom,sm8350-epss-l3 + - qcom,sa8775p-epss-l3 - const: qcom,epss-l3 reg: From patchwork Sat Jan 11 16:14:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raviteja Laggyshetty X-Patchwork-Id: 856581 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3772D1AF0C4; Sat, 11 Jan 2025 16:15:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736612119; cv=none; b=dXGEsSznqm2/Tk5GF4ABlrUMk/pOQXHT0pAJbRYT5KlMb4LYZqnW542bCSaqMkNDkdGp9qAWlLCwFZw4iT7VQnRja+XRY4VjiY1a7jXetEcO2GJ1OckCsjN+5fpaEW1AoOoCROx53GJam6RP7SmVUTlf1ln2DJj0anSCyoIfL6M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736612119; c=relaxed/simple; bh=m58ZUu+U5WoOnc2WhNOfgkrycbBwdSg3+lcKmWxSiJo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=US2QkVFCbLzuMwgU+FndFSxoYnCI+bAu7RqWv1DxVdlCs0R98W8FB4iUVbIWjKU920iS4hl8BLBN24V3StoQv74yAUfwMFIwhrneXMS5FftikpVBcofksIUJUV0b+xMcwQkyuANOX30bdv942z1wXw0kKzF7SIyrCIByhqJ/CfA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=J64ztOrB; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="J64ztOrB" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50BFKYYB014799; Sat, 11 Jan 2025 16:15:13 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= qEU8ccAFRoOn9oGJyphWK0yNLySYV5Zg1SywAKNpopM=; b=J64ztOrBmakFmdw/ skHVV9GWj62a9c9YMxREy9eO24YMaG9xDQsbtoymlZYHkmDJVTtSvQkVYxzP+vpt GtDkDokEbraGwcEmSSfPaz6Ar9+/9BhD1CS+5WbIAkK1vkD3CvtWaeIscHFeh6t6 Jd1QNSvhm3T2Uyj7B11DXML+Un0Ct6sepSDDn8cypUnr3fHqG9wP8AuyqfrRrXdd qnDLwZ1/FhcVSy/3AbymMa22QmGrhGJ9CfFGnYFlSvZvchbbsZrD1RGSivYTnmTw egLiqIXWqSj0YdqVaoUm3rM0JStu9ROb4sBCPRNiRVtA5vXJbRBc655aslblR/YQ NA0kqg== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 443hx70rft-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 11 Jan 2025 16:15:13 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50BGFCAf015251 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 11 Jan 2025 16:15:12 GMT Received: from 4206f847eb12.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 11 Jan 2025 08:15:08 -0800 From: Raviteja Laggyshetty To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Odelu Kukatla , "Mike Tipton" , Vivek Aknurwar CC: Sibi Sankar , , , , , Shivnandan Kumar Subject: [PATCH V7 5/5] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3 Date: Sat, 11 Jan 2025 16:14:29 +0000 Message-ID: <20250111161429.51-6-quic_rlaggysh@quicinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250111161429.51-1-quic_rlaggysh@quicinc.com> References: <20250111161429.51-1-quic_rlaggysh@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gNG2wkyMQFomrz_UZBN_3YaO8rWBwYzK X-Proofpoint-ORIG-GUID: gNG2wkyMQFomrz_UZBN_3YaO8rWBwYzK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 clxscore=1015 spamscore=0 adultscore=0 suspectscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501110138 From: Jagadeesh Kona Add OPP tables required to scale DDR and L3 per freq-domain on SA8775P platform. If a single OPP table is used for both CPU domains, then _allocate_opp_table() won't be invoked for CPU4 but instead CPU4 will be added as device under the CPU0 OPP table. Due to this, dev_pm_opp_of_find_icc_paths() won't be invoked for CPU4 device and hence CPU4 won't be able to independently scale it's interconnects. Both CPU0 and CPU4 devices will scale the same ICC path which can lead to one device overwriting the BW vote placed by other device. Hence CPU0 and CPU4 require separate OPP tables to allow independent scaling of DDR and L3 frequencies for each CPU domain, with the final DDR and L3 frequencies being an aggregate of both. Co-developed-by: Shivnandan Kumar Signed-off-by: Shivnandan Kumar Signed-off-by: Jagadeesh Kona Signed-off-by: Raviteja Laggyshetty --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 210 ++++++++++++++++++++++++++ 1 file changed, 210 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index c6a889d4ddaf..7c52bca958fe 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -49,6 +49,11 @@ cpu0: cpu@0 { next-level-cache = <&l2_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -71,6 +76,11 @@ cpu1: cpu@100 { next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_1: l2-cache { compatible = "cache"; cache-level = <2>; @@ -88,6 +98,11 @@ cpu2: cpu@200 { next-level-cache = <&l2_2>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_2: l2-cache { compatible = "cache"; cache-level = <2>; @@ -105,6 +120,11 @@ cpu3: cpu@300 { next-level-cache = <&l2_3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_3: l2-cache { compatible = "cache"; cache-level = <2>; @@ -122,6 +142,11 @@ cpu4: cpu@10000 { next-level-cache = <&l2_4>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_4: l2-cache { compatible = "cache"; cache-level = <2>; @@ -145,6 +170,11 @@ cpu5: cpu@10100 { next-level-cache = <&l2_5>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_5: l2-cache { compatible = "cache"; cache-level = <2>; @@ -162,6 +192,11 @@ cpu6: cpu@10200 { next-level-cache = <&l2_6>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_6: l2-cache { compatible = "cache"; cache-level = <2>; @@ -179,6 +214,11 @@ cpu7: cpu@10300 { next-level-cache = <&l2_7>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_7: l2-cache { compatible = "cache"; cache-level = <2>; @@ -268,6 +308,176 @@ cluster_sleep_apss_rsc_pc: cluster-sleep-1 { }; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp_1267mhz: opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu0_opp_1363mhz: opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu0_opp_1459mhz: opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu0_opp_1536mhz: opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu0_opp_1632mhz: opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_1708mhz: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_1785mhz: opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_1862mhz: opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_1939mhz: opp-1939200000 { + opp-hz = /bits/ 64 <1939200000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_2016mhz: opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_2112mhz: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu0_opp_2188mhz: opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu0_opp_2265mhz: opp-2265600000 { + opp-hz = /bits/ 64 <2265600000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu0_opp_2361mhz: opp-2361600000 { + opp-hz = /bits/ 64 <2361600000>; + opp-peak-kBps = <12787200 51609600>; + }; + + cpu0_opp_2457mhz: opp-2457600000 { + opp-hz = /bits/ 64 <2457600000>; + opp-peak-kBps = <12787200 51609600>; + }; + + cpu0_opp_2553mhz: opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <12787200 54681600>; + }; + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible = "operating-points-v2"; + opp-shared; + + cpu4_opp_1267mhz: opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu4_opp_1363mhz: opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu4_opp_1459mhz: opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu4_opp_1536mhz: opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu4_opp_1632mhz: opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_1708mhz: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_1785mhz: opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_1862mhz: opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_1939mhz: opp-1939200000 { + opp-hz = /bits/ 64 <1939200000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_2016mhz: opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_2112mhz: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu4_opp_2188mhz: opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu4_opp_2265mhz: opp-2265600000 { + opp-hz = /bits/ 64 <2265600000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu4_opp_2361mhz: opp-2361600000 { + opp-hz = /bits/ 64 <2361600000>; + opp-peak-kBps = <12787200 51609600>; + }; + + cpu4_opp_2457mhz: opp-2457600000 { + opp-hz = /bits/ 64 <2457600000>; + opp-peak-kBps = <12787200 51609600>; + }; + + cpu4_opp_2553mhz: opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <12787200 54681600>; + }; + }; + dummy-sink { compatible = "arm,coresight-dummy-sink";