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Fri, 10 Jan 2025 07:21:24 -0800 (PST) From: Neil Armstrong Date: Fri, 10 Jan 2025 16:21:18 +0100 Subject: [PATCH 1/4] dt-bindings: interconnect: OSM L3: Document sm8650 OSM L3 compatible Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250110-topic-sm8650-ddr-bw-scaling-v1-1-041d836b084c@linaro.org> References: <20250110-topic-sm8650-ddr-bw-scaling-v1-0-041d836b084c@linaro.org> In-Reply-To: <20250110-topic-sm8650-ddr-bw-scaling-v1-0-041d836b084c@linaro.org> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=861; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=6x20OZAZDWy1n/Lp2uA0gIfP0RiekaAArUBAmfzhPLk=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBngTrxlbDN8zf+COXdCpUdXQR2nXiX4+hMgzlbf6bJ yMSGzUKJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ4E68QAKCRB33NvayMhJ0bcnEA DAj2swcSJPRv8vfiExrlBZCOQsC3Aqebwfj7CDQbggLFualRA2eQLtwOnrXOQCmh4udUcLnIRlIpAM kRjp8fxmDRYcraN9LezmI6xM60Nt349J6JGBy3ArzGqu52G9liUhDcoa15K69h0zA2gn28igjxMnSL /fvhl4Dr9J2YL8R8LKgdNB++7E/v58oFPsRheE1XZfCQmixUju/z9mD2hRy1hJOu2Gqrclskd/c/Vt oXX2j06UunlUrPYa8HnKb0OmG88kSELaimYJtbwrhSunCNgAcbgxiqVDMxLnakknoGfedyJPKfdiiE H4wLc9U5bf/AvVKJvyXDy0kkecsERfLD2OPp2Brn0/QjOOnzOMsh7/zsGWgsC9qatOOPDvSkBuhHdU JVnfGmCqXpRMR3+Gr2blsUMOb8kY/4NWn4S4WPXZX7CbKtNN4O0972PLwdO3+YqkDrF8Sqt0auHz6o L0um3XVlMf1a1pV8om9Y7LNNd33fwArHI1pppo3c63CxG9TNtYkrx6M+qrdivoJsqDzsVeTojepJ1+ CJOyIjXklxt2HqG6HUEdyekVPzw4/BnTRiDLQuAgppm5eLlr9XKfLbGJ4q832NRPu9zPLGclkwlzcM 3baByQ3cyPaluwAoeOAF0eHVrIbkQRGpJM8cpPs7Q9Vy8J7J3mnOMG6Nzhxw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Document the OSM L3 found in the Qualcomm SM8650 platform. Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 21dae0b92819622fa56b0a46beaeb6f585cdec35..4ac0863205b3b30cdfcde6fe1bf5abc3b122a2f5 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -33,6 +33,7 @@ properties: - qcom,sm6375-cpucp-l3 - qcom,sm8250-epss-l3 - qcom,sm8350-epss-l3 + - qcom,sm8650-epss-l3 - const: qcom,epss-l3 reg: From patchwork Fri Jan 10 15:21:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 856447 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EBFB2116EF for ; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add the interconnect entry for each cpu, with 3 different paths: - CPU to Last Level Cache Controller (LLCC) - Last Level Cache Controller (LLCC) to DDR - L3 Cache from CPU to DDR interface Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 57 ++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index bc09e879c1440873a52daf3fc7a38f451f1f972c..e194a95cdcc0f0f692e62b942331cd9e07a4eae0 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -85,6 +86,13 @@ cpu0: cpu@0 { qcom,freq-domain = <&cpufreq_hw 0>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; l2_0: l2-cache { @@ -118,6 +126,13 @@ cpu1: cpu@100 { qcom,freq-domain = <&cpufreq_hw 0>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; }; @@ -138,6 +153,13 @@ cpu2: cpu@200 { qcom,freq-domain = <&cpufreq_hw 3>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; l2_200: l2-cache { @@ -165,6 +187,13 @@ cpu3: cpu@300 { qcom,freq-domain = <&cpufreq_hw 3>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; }; @@ -185,6 +214,13 @@ cpu4: cpu@400 { qcom,freq-domain = <&cpufreq_hw 3>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; l2_400: l2-cache { @@ -212,6 +248,13 @@ cpu5: cpu@500 { qcom,freq-domain = <&cpufreq_hw 1>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; l2_500: l2-cache { @@ -239,6 +282,13 @@ cpu6: cpu@600 { qcom,freq-domain = <&cpufreq_hw 1>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; l2_600: l2-cache { @@ -266,6 +316,13 @@ cpu7: cpu@700 { qcom,freq-domain = <&cpufreq_hw 2>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; l2_700: l2-cache {