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Wed, 8 Jan 2025 03:06:29 -0800 From: Kartik Rajput To: , , , , , , , , , , , , Subject: [PATCH 1/5] i2c: tegra: Add HS mode support Date: Wed, 8 Jan 2025 16:36:16 +0530 Message-ID: <20250108110620.86900-2-kkartik@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250108110620.86900-1-kkartik@nvidia.com> References: <20250108110620.86900-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013E:EE_|IA1PR12MB6626:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c73ae70-71f6-4abc-e761-08dd2fd486ef X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|7416014|376014|1800799024|82310400026|921020; X-Microsoft-Antispam-Message-Info: b0DB0LWKrvNvihoEv/G2OYzfe9+2MFVpVeyTpk1z853PNQOMwIZOonYeUBS9fsyKihWWv0uCEl9JBEFErXpbU0Yv/luHhAOkQJoQhgB+RvOgBhuKBGBi+dBBT32yQa0OXzbAtdoapdpXAZc8ffvwHlSw9iWdpqEnBg015p5OjyvJ0TrT084yBIUrmy3w6WcBpM15bepYKrb62HnAluKYWx2vU2GntFk6GO+5kJqvFCvXd0pZyf2QjkOVkBWyF8izpANNvpegU9Pu7u5gVafni1VjKaP7mr4fbkTgNBq88pNAY5JGbPf7r5KT1yK8Om6MV3FML8dWNlyBbASfy0Rr8hNJIR56S/ttY7Kq7XhIOCMp62BPRx2xPxc37sAfDBC2kJO9n2iCIKpLWv4xVninNez+pPIWF8yc50UZTJD/epIf1MA5jUc/5mwWZHoCCpavkCql6VL2EDR6ocFN4pIjo7a7tAnLMQ73O2ipN3/CwXjWJkc4uBl3pi+q9SbbGinWJ6RKk1+SdauAmvUQuuuZ4LuVi9Yu598DAJ5LH/UeTQYrWkiAw7GxqVdHTEWZU7sBfnGMjIHBtXBlqORCFQz3R9r85+0Y7blBtTnliAN+RSmppvn8eGHGusjglMdNvc56MeXF8VZZWnKB/bCTKpZ1a/8UCHvT94zJjOHuwM/V5R6pe/XrdO+K8d01hJN/rkDWcBUI+w6O3Bsz0hBM9Jc+bmu0InFaMWZ7rFr6LM2O0WM14P4+vf0dNYZBwRuElNE8N/F9hygoHf8ZUtHY7RM09dkOQJQ4AjhPSjivywQIoHXDKPFeFNhkmLZ6fowGiJoX1n1tFZFbPa3wJUYv3sn5jCzUR4E8jGLoVGUTlz77XyaalK8/LbgEAsa595uYqso+ILNQSjuhagRhBhgAMU3UHa48YsA0d4OIPTqzwCDY/QMg4K6Uagi9j4sTd6Km/ykXm7OJjNW2InVNlcosGx4k+SxIF8rf/NjtQBzTJJyKwZCJbrBEN7cNp5LKYUgwoZu4L+R/jGm1O/KB2C6/xwSANk1vLX/bv8SYAU8DqbnisR6xkQ6uO8lo+xRJ1k0Eva8sH5onio/LELIr/+2BGWV63OqZ/rKfMLmOIpv6xqD2MAGu4jiziu/hSH9ToBrzLX7Z8f3+wWRe/JVlu4VDuj5frpCDazjtGIf+w39pPy2m+u2RjC0w2rpcMor00F6+hVYAdDwrHwA04BDaWwiFlEOLHyf4F8KlX6FgNNC3QrRlSsgtIIRl/0LwSYgC5xLchO52A9RyN8YrRH5w45uiwaE5ERPmrwo7/GKxZI15aeXA8J+kJCDnfC7ugZjNlzfBHiX2qITrdrNRMVD6CvDjwdwwW2tN4weObVFoBy9E4cDLb8wpQs1XTLw8GJ2OkMKwdMZGCviBNrfdXsMQ69Za/JwuD4CC7O6q7Vxoc9RAwFoJnu6FkElxwBN6hb49OPjPyJt9qe8u/ieOnnoXiVoJWZG5DP2cOST4OpDo2Q2uBzZ21NGK/oGGpcrJjFxVM4kZbbra X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(7416014)(376014)(1800799024)(82310400026)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jan 2025 11:06:39.8357 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c73ae70-71f6-4abc-e761-08dd2fd486ef X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6626 From: Akhil R Add support for HS (High Speed) mode tranfers, which is supported by Tegra194 onwards. Signed-off-by: Akhil R Signed-off-by: Kartik Rajput --- drivers/i2c/busses/i2c-tegra.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 87976e99e6d0..7b97c6d347ee 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -91,6 +91,7 @@ #define I2C_HEADER_IE_ENABLE BIT(17) #define I2C_HEADER_REPEAT_START BIT(16) #define I2C_HEADER_CONTINUE_XFER BIT(15) +#define I2C_HEADER_HS_MODE BIT(22) #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 #define I2C_BUS_CLEAR_CNFG 0x084 @@ -220,10 +221,13 @@ struct tegra_i2c_hw_feature { u32 thigh_std_mode; u32 tlow_fast_fastplus_mode; u32 thigh_fast_fastplus_mode; + u32 tlow_hs_mode; + u32 thigh_hs_mode; u32 setup_hold_time_std_mode; u32 setup_hold_time_fast_fast_plus_mode; u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; + bool has_hs_mode_support; }; /** @@ -681,6 +685,18 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); + /* Write HS mode registers. These will get used only for HS mode*/ + if (i2c_dev->hw->has_hs_mode_support) { + tlow = i2c_dev->hw->tlow_hs_mode; + thigh = i2c_dev->hw->thigh_hs_mode; + tsu_thd = i2c_dev->hw->setup_hold_time_hs_mode; + + val = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) | + FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow); + i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0); + i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1); + } + clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); err = clk_set_rate(i2c_dev->div_clk, @@ -1178,6 +1194,9 @@ static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev, if (msg->flags & I2C_M_RD) packet_header |= I2C_HEADER_READ; + if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) + packet_header |= I2C_HEADER_HS_MODE; + if (i2c_dev->dma_mode && !i2c_dev->msg_read) *dma_buf++ = packet_header; else @@ -1618,10 +1637,13 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .thigh_std_mode = 0x7, .tlow_fast_fastplus_mode = 0x2, .thigh_fast_fastplus_mode = 0x2, + .tlow_hs_mode = 0x8, + .thigh_hs_mode = 0x3, .setup_hold_time_std_mode = 0x08080808, .setup_hold_time_fast_fast_plus_mode = 0x02020202, .setup_hold_time_hs_mode = 0x090909, .has_interface_timing_reg = true, + .has_hs_mode_support = true, }; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(376014)(7416014)(1800799024)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jan 2025 11:06:55.6291 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dab58ac4-73ca-40a8-c7b4-08dd2fd49059 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8602 On Tegra264, not all I2C controllers support DMA, this causes failures when function tegra_i2c_init_dma() is called. Ensure that "dmas" device-tree property is present before initializing DMA in function tegra_i2c_init_dma(). Signed-off-by: Kartik Rajput --- drivers/i2c/busses/i2c-tegra.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index a5974af5b1af..9957802fa4ed 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -546,6 +546,9 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) if (IS_VI(i2c_dev)) return 0; + if (!device_property_present(i2c_dev->dev, "dmas")) + return 0; + if (i2c_dev->hw->has_apb_dma) { if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n");