From patchwork Tue Jan 7 16:07:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 855652 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D52C11F2C25; Tue, 7 Jan 2025 16:08:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736266120; cv=none; b=rwSgCziiTKBtGy89kf0MXzRXViAjVPptEfH3faFJqtWNF9eciyacUWHUcuXRu/b0vtm65RNT3vZq/4YI1oNRRf/ZU9rCoxxg1cd175qpEBE3/kJPGVafxTjh4tCOQsUs028ut7QgijNqIOFwcu9bsGZhBLK/pXQHHOFvFI1F8eA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736266120; c=relaxed/simple; bh=VUT45XGlDSMQNHusgz0mY/5e3jHIdDXBnlb8O2girPc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qSHdpW4ur92q2AIGSB9AamHe8XH+TAZ1as0z2sEerfEXVmJoQdm1QNPt9Y0Jq7Hhz9vKY5lMrgktmpaIHBD6i4vhFLUE402W7U+P6/LMsiyBT1E7/souN6u69GK1wtz+Fu/VxQrGmnc0U3fX9ZtK4y6ZpPPpQo4Yug5OiVVjwIo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=nEUN+74p; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="nEUN+74p" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1736266116; x=1767802116; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VUT45XGlDSMQNHusgz0mY/5e3jHIdDXBnlb8O2girPc=; b=nEUN+74pvOXonDQfXpNQf4/Emp04hsHpm1RVa9ci+77C8THylixBfkHE QsrPT/lC/qn/QIhesy0o/CJ6SBR4E7EHnx4KVjCS3gjrPEx6+1uCB9XCa AcHyVtu5pO13UdK9YKtR0zN/B3//iR4GMLGEkzrfMBhjJNbhffZ8ao6pP TByFby3REkZCg6v5AGjlhcHoA5hYqwgqAhqRjeATu141X59du3pouSFdC Pb1Q0T0p79gRI67/1IUn9MGRLMwvAAMVojApmJLR8dQaya2IY2bybGdIx jv33Le3CI28HAMPZyrgO2Ub7CP8Sli75CFTvlqleEPeTql2ZunNVaO4Hm g==; X-CSE-ConnectionGUID: lqpfnJzJQpCXzb9QKpQeRA== X-CSE-MsgGUID: qZ8ajRtFTXKuCSFks2gq8Q== X-IronPort-AV: E=Sophos;i="6.12,296,1728975600"; d="scan'208";a="40091248" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 07 Jan 2025 09:08:24 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 7 Jan 2025 09:08:17 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 7 Jan 2025 09:08:17 -0700 From: To: , , , , , , , , CC: , , , , , , , , , , , , Conor Dooley Subject: [PATCH v5 1/5] dt-bindings: ARM: at91: Document Microchip SAMA7D65 Curiosity Date: Tue, 7 Jan 2025 09:07:23 -0700 Message-ID: <20250107160850.120537-2-Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250107160850.120537-1-Ryan.Wanner@microchip.com> References: <20250107160850.120537-1-Ryan.Wanner@microchip.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Romain Sioen Document device tree binding of the Microchip SAMA7D65 Curiosity board. Signed-off-by: Romain Sioen Acked-by: Nicolas Ferre Signed-off-by: Dharma Balasubiramani Signed-off-by: Ryan Wanner Acked-by: Conor Dooley Reviewed-by: Claudiu Beznea --- Documentation/devicetree/bindings/arm/atmel-at91.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index 7160ec80ac1b..0ec29366e6c2 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -180,6 +180,13 @@ properties: - const: atmel,sama5d4 - const: atmel,sama5 + - description: Microchip SAMA7D65 Curiosity Board + items: + - const: microchip,sama7d65-curiosity + - const: microchip,sama7d65 + - const: microchip,sama7d6 + - const: microchip,sama7 + - items: - const: microchip,sama7g5ek # SAMA7G5 Evaluation Kit - const: microchip,sama7g5 From patchwork Tue Jan 7 16:07:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 855917 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43C951F37B1; Tue, 7 Jan 2025 16:08:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736266119; cv=none; b=Rp2qoEKG/OiHTmSQCcLlZwixJ15iVLSi2PUXP13JNeFthVG4VGvYGigvD8aAJjCH37eJwC7/Q2/qKq8jli0CbMkdr0jVL7wcW0zCxK+/SmJpSeFtItcHeC8z/xECm0C9nPIC0qGSoG20LSd+ciczlFcGTON7//9PcpVu6qtPh10= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736266119; c=relaxed/simple; bh=T+l6OVVT45tzMYV8TY6DeZg93MwIQ0gaakx3sxA0rT0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cja4QyTOB4+EZO3G3f76T50Dj9nzEjbJll/WmRUpGx3DbmrwKFbNMnJKlPB1/TrqJ7R7mk/peetj7ZtUdUAVeDbl4yOOcJoXPyeS1OsU/Y0IbuqVV7Yb2t9s1qmbf3z8R/Th3OydMMJZjPkm2mx/hGqUt8Hnf6oEMna66bmnGfs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=2d8wH3vc; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="2d8wH3vc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1736266116; x=1767802116; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=T+l6OVVT45tzMYV8TY6DeZg93MwIQ0gaakx3sxA0rT0=; b=2d8wH3vcoOELDLJCjBndVfPwQ1AGUGh7gy+a3+IhY5UzTT/TfxrngBi1 H1bSXlQx0/bwTBezRpOFBp5Gtj9ne1FcOeHM2OaZzHB7DWDb+EmuTSgnn 9DBmlyprZgh9mkKzM4WRqhqO/0BMBfn3s+gIJWAwIs/PUjHENfv3fCVyO aOvDI+BpDcPTIBT1scsBOhWb1VKhpMNEYptRow9PIx1vBr6r6AhWrsxFE N9EychGC9suJx8MjEePUFfmc+bKWgwlphAuIJtza8UTSIRSOl6FWTlYAt 0urkMO13nE5+89+rsOOuH98xXSCnd1Sw3JZFjZfYGBGdqhLztSPB0UYwS g==; X-CSE-ConnectionGUID: lqpfnJzJQpCXzb9QKpQeRA== X-CSE-MsgGUID: HApmCmBKQ7WE/cZfewCh/w== X-IronPort-AV: E=Sophos;i="6.12,296,1728975600"; d="scan'208";a="40091250" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 07 Jan 2025 09:08:25 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 7 Jan 2025 09:08:18 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 7 Jan 2025 09:08:18 -0700 From: To: , , , , , , , , CC: , , , , , , , , , , , Subject: [PATCH v5 2/5] dt-bindings: serial: atmel,at91-usart: add microchip,sama7d65-usart Date: Tue, 7 Jan 2025 09:07:24 -0700 Message-ID: <20250107160850.120537-3-Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250107160850.120537-1-Ryan.Wanner@microchip.com> References: <20250107160850.120537-1-Ryan.Wanner@microchip.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Dharma Balasubiramani Add SAMA7D65 USART compatible to DT bindings documentation. Signed-off-by: Dharma Balasubiramani Signed-off-by: Ryan Wanner Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index f466c38518c4..087a8926f8b4 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -26,6 +26,7 @@ properties: - enum: - microchip,sam9x60-usart - microchip,sam9x7-usart + - microchip,sama7d65-usart - const: atmel,at91sam9260-usart - items: - const: microchip,sam9x60-dbgu From patchwork Tue Jan 7 16:07:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 855916 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92F771D8A16; Tue, 7 Jan 2025 16:08:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736266123; cv=none; b=cJ/gnvuVVg7mxb8yNgYry6bD85xEiky8aiy7o2sPPdMNotE56dnaXMBbAO30J7yj6/VVKhGwNjvMK2knNet8P0babGOLFvJ3I+pLvFVu7t2SN9aWNzftUJuHz0CPGIclWPps+C5jpZfeaVix397Ea0vraNSyHkE23+K+3Vw43z8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736266123; c=relaxed/simple; bh=PH4rUN/rnjax/mDGGIYBtSheO/61fSdwRtwLQU4elCQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=UhdrRqC9ZvFwcLetHirDpvTFXVBYQEX+ZmdboCYsSEDaF31xbQqdUBbFAjPzu8BMxFrQnYwg3iWswLiAJyKLAH5snEYhfKzpi6UwstaxEr0CpxBnXVFs8+aYLbrN48PllxNms7O3inLBnA/wmGM+DvN+x+anLpwh4GpfIHYj0MU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=nFIbfIMa; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="nFIbfIMa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1736266119; x=1767802119; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PH4rUN/rnjax/mDGGIYBtSheO/61fSdwRtwLQU4elCQ=; b=nFIbfIMadkmcj/nc1iHvqv390MSRguhbR1CpfbOgwvRzER3Hui1IAYUt BX2MkgXYBsv0iQ+gwUG41auBJC8bPZgwJM8xYDATQpT+5VKfWEpxQStCn LDeRA3ZQ4aAYeJs47qa4x0WlPNkBS7WWELkZYpgGqFV9mUES6uQLYgaF9 wMpb5/Asv/MZhrb+thX5dzIK1PuSdqYJ7eQa08rO9VpQLBNGp9lmU2Gkj yE59IqV8fiEvJ9NZ1cEUT3edpqOlE405Vy1sCqs5oUPcsy23vhECaotBJ 2mfCEH69NCzeK35Z2kib8CYc0RKDqwpotdwJmukmQBQsokUOoK9aE+Ck2 Q==; X-CSE-ConnectionGUID: lqpfnJzJQpCXzb9QKpQeRA== X-CSE-MsgGUID: K4H+nriUSkCBJNw9ScA8Kg== X-IronPort-AV: E=Sophos;i="6.12,296,1728975600"; d="scan'208";a="40091253" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 07 Jan 2025 09:08:26 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 7 Jan 2025 09:08:18 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 7 Jan 2025 09:08:18 -0700 From: To: , , , , , , , , CC: , , , , , , , , , , , Subject: [PATCH v5 3/5] dt-bindings: pinctrl: at91-pio4: add microchip,sama7d65-pinctrl Date: Tue, 7 Jan 2025 09:07:25 -0700 Message-ID: <20250107160850.120537-4-Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250107160850.120537-1-Ryan.Wanner@microchip.com> References: <20250107160850.120537-1-Ryan.Wanner@microchip.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Dharma Balasubiramani Add pinctrl bindings for microchip sama7d65 SoC. Signed-off-by: Dharma Balasubiramani Signed-off-by: Ryan Wanner Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt index 774c3c269c40..4b9f3373503d 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt @@ -6,7 +6,8 @@ configure it. Required properties: - compatible: "atmel,sama5d2-pinctrl" - "microchip,sama7g5-pinctrl" + "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl" + "microchip,sama7g5-pinctrl" - reg: base address and length of the PIO controller. - interrupts: interrupt outputs from the controller, one for each bank. - interrupt-controller: mark the device node as an interrupt controller. From patchwork Tue Jan 7 16:07:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 855915 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECFB11F4293; Tue, 7 Jan 2025 16:08:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736266124; cv=none; b=gyEvWrlhSvmv7t02M6vV0W7evMIkpc6hCFo/hH/lDkQFGnBDIK6Wx7MQjbzbCtKGIXbQziX+HiXHYWqjxBSmVeYysed+pZ++LhoNtMcCv2MBWkrT3hXXpMh/uCm+UW5bTT7SS32Pr2iFz2RAmxvS7vLCRFkhJp+Oq64eHpzSL2s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736266124; c=relaxed/simple; bh=urfNn5rVdf7gcjV7bg+HRVF6ewJXcTZT7wfn3zRvj2Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kGahENe5szOW1dY88x9pHW0LnUAa/CK3b61wWcVCku71KQ3eC0hBLn9pE2t0T+NmHkvPaYl5v6vOxmlDT89TimhjAWdcdd5mRaiuhr9fI6rFURhR9m6iYowgCPcqH8eqAtOS5/TIq8+ybPQ7TLsylJeofcjlQpLmSOkT7Q4lbv4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=atprrP7z; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="atprrP7z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1736266120; x=1767802120; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=urfNn5rVdf7gcjV7bg+HRVF6ewJXcTZT7wfn3zRvj2Y=; b=atprrP7zlcuWu6TVeNy7PAzs3VOEsbaZ78GsSoC8qyYi3lE8oPnuc9Pp nOGM6Jh1pqQuq7Jzz7gZMhPgjIF7leWCPFGAHvm/loTq7PF1IxZvxdGg7 3zkRkERf0AJa+uHbAPjSCKZ88j0i1jEB58epSnBQSFAWctN7mWYfF5j1g ShnkrD8WU/JhKPG0+rWKXNNpTIIFXr3l697kIbzN7jCz7c1NU1BYLUsrZ 15+dlQAnLBDa+WvfE471KilBAnrTGi8lUI2kU/K9KtkinRFs6vuUA5+mk 9KNtvXChdYGaY8IyJMZURW5WObjCQP0RUCX2gerSPeIjjpAJdZPJDC6jC A==; X-CSE-ConnectionGUID: lqpfnJzJQpCXzb9QKpQeRA== X-CSE-MsgGUID: dNICsMlrT3qhDCy3ycLAog== X-IronPort-AV: E=Sophos;i="6.12,296,1728975600"; d="scan'208";a="40091254" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 07 Jan 2025 09:08:26 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 7 Jan 2025 09:08:18 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 7 Jan 2025 09:08:18 -0700 From: To: , , , , , , , , CC: , , , , , , , , , , , , Ryan Wanner Subject: [PATCH v5 4/5] ARM: dts: microchip: add sama7d65 SoC DT Date: Tue, 7 Jan 2025 09:07:26 -0700 Message-ID: <20250107160850.120537-5-Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250107160850.120537-1-Ryan.Wanner@microchip.com> References: <20250107160850.120537-1-Ryan.Wanner@microchip.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add Device Tree for sama7d65 SoC. Co-developed-by: Dharma Balasubiramani Signed-off-by: Dharma Balasubiramani Co-developed-by: Romain Sioen Signed-off-by: Romain Sioen Co-developed-by: Varshini Rajendran Signed-off-by: Varshini Rajendran Signed-off-by: Ryan Wanner Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 145 ++++++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 arch/arm/boot/dts/microchip/sama7d65.dtsi diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi new file mode 100644 index 000000000000..03e1adfdcd34 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sama7d65.dtsi - Device Tree Include file for SAMA7D65 SoC + * + * Copyright (C) 2024 Microchip Technology, Inc. and its subsidiaries + * + * Author: Ryan Wanner + * + */ + +#include +#include +#include +#include +#include + +/ { + model = "Microchip SAMA7D65 family SoC"; + compatible = "microchip,sama7d65"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + reg = <0x0>; + device_type = "cpu"; + clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; + clock-names = "cpu"; + }; + }; + + clocks { + main_xtal: clock-mainxtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + slow_xtal: clock-slowxtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + pioa: pinctrl@e0014000 { + compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"; + reg = <0xe0014000 0x800>; + interrupts = , + , + , + , + ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + pmc: clock-controller@e0018000 { + compatible = "microchip,sama7d65-pmc", "syscon"; + reg = <0xe0018000 0x200>; + interrupts = ; + #clock-cells = <2>; + clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clock-names = "td_slck", "md_slck", "main_xtal"; + }; + + clk32k: clock-controller@e001d500 { + compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; + reg = <0xe001d500 0x4>; + clocks = <&slow_xtal>; + #clock-cells = <1>; + }; + + sdmmc1: mmc@e1208000 { + compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci"; + reg = <0xe1208000 0x400>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 76>, <&pmc PMC_TYPE_GCK 76>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 76>; + assigned-clock-rates = <200000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>; + status = "disabled"; + }; + + pit64b0: timer@e1800000 { + compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xe1800000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; + clock-names = "pclk", "gclk"; + }; + + pit64b1: timer@e1804000 { + compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xe1804000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 67>, <&pmc PMC_TYPE_GCK 67>; + clock-names = "pclk", "gclk"; + }; + + flx6: flexcom@e2020000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe2020000 0x200>; + ranges = <0x0 0xe2020000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + status = "disabled"; + + uart6: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names = "usart"; + atmel,usart-mode = ; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@e8c11000 { + compatible = "arm,cortex-a7-gic"; + reg = <0xe8c11000 0x1000>, + <0xe8c12000 0x2000>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + }; + }; +}; From patchwork Tue Jan 7 16:07:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 855651 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FEA11F4712; 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X-CSE-ConnectionGUID: lqpfnJzJQpCXzb9QKpQeRA== X-CSE-MsgGUID: lkEXHdiKQIKQ2alr2emajQ== X-IronPort-AV: E=Sophos;i="6.12,296,1728975600"; d="scan'208";a="40091256" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 07 Jan 2025 09:08:27 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 7 Jan 2025 09:08:18 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 7 Jan 2025 09:08:18 -0700 From: To: , , , , , , , , CC: , , , , , , , , , , , Subject: [PATCH v5 5/5] ARM: dts: microchip: add support for sama7d65_curiosity board Date: Tue, 7 Jan 2025 09:07:27 -0700 Message-ID: <20250107160850.120537-6-Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250107160850.120537-1-Ryan.Wanner@microchip.com> References: <20250107160850.120537-1-Ryan.Wanner@microchip.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Romain Sioen Add device tree support for the SAMA7D65 Curiosity board. Update the Makefile to include the new device tree file. uart6 is related to flexcom6, hence not sorted in alphabetical order. Signed-off-by: Romain Sioen Signed-off-by: Varshini Rajendran Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/Makefile | 3 + .../dts/microchip/at91-sama7d65_curiosity.dts | 89 +++++++++++++++++++ 2 files changed, 92 insertions(+) create mode 100644 arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile index 470fe46433a9..79cd38fdc7da 100644 --- a/arch/arm/boot/dts/microchip/Makefile +++ b/arch/arm/boot/dts/microchip/Makefile @@ -12,6 +12,7 @@ DTC_FLAGS_at91-sama5d2_xplained := -@ DTC_FLAGS_at91-sama5d3_eds := -@ DTC_FLAGS_at91-sama5d3_xplained := -@ DTC_FLAGS_at91-sama5d4_xplained := -@ +DTC_FLAGS_at91-sama7d65_curiosity := -@ DTC_FLAGS_at91-sama7g54_curiosity := -@ DTC_FLAGS_at91-sama7g5ek := -@ dtb-$(CONFIG_SOC_AT91RM9200) += \ @@ -90,6 +91,8 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d4_xplained.dtb \ at91-sama5d4ek.dtb \ at91-vinco.dtb +dtb-$(CONFIG_SOC_SAMA7D65) += \ + at91-sama7d65_curiosity.dtb dtb-$(CONFIG_SOC_SAMA7G5) += \ at91-sama7g54_curiosity.dtb \ at91-sama7g5ek.dtb diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts new file mode 100644 index 000000000000..ef6a56db8acb --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama7d65_curiosity.dts - Device Tree file for SAMA7D65 Curiosity board + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Romain Sioen + * + */ +/dts-v1/; +#include "sama7d65-pinfunc.h" +#include "sama7d65.dtsi" +#include +#include + +/ { + model = "Microchip SAMA7D65 Curiosity"; + compatible = "microchip,sama7d65-curiosity", "microchip,sama7d65", + "microchip,sama7d6", "microchip,sama7"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart6; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; +}; + +&flx6 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6_default>; + status = "okay"; +}; + +&main_xtal { + clock-frequency = <24000000>; +}; + +&pioa { + pinctrl_sdmmc1_default: sdmmc1-default { + cmd-data { + pinmux = , + , + , + , + ; + slew-rate = <0>; + bias-disable; + }; + + ck-cd-rstn-vddsel { + pinmux = , + , + , + , + ; + slew-rate = <0>; + bias-disable; + }; + }; + + pinctrl_uart6_default: uart6-default { + pinmux = , + ; + bias-disable; + }; +}; + +&sdmmc1 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + status = "okay"; +}; + +&slow_xtal { + clock-frequency = <32768>; +};